diff options
Diffstat (limited to 'drivers/sh/clk/cpg.c')
| -rw-r--r-- | drivers/sh/clk/cpg.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c index 3aea5f0ceb09..6172335ae323 100644 --- a/drivers/sh/clk/cpg.c +++ b/drivers/sh/clk/cpg.c | |||
| @@ -110,8 +110,7 @@ static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent) | |||
| 110 | return 0; | 110 | return 0; |
| 111 | } | 111 | } |
| 112 | 112 | ||
| 113 | static int sh_clk_div6_set_rate(struct clk *clk, | 113 | static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate) |
| 114 | unsigned long rate, int algo_id) | ||
| 115 | { | 114 | { |
| 116 | unsigned long value; | 115 | unsigned long value; |
| 117 | int idx; | 116 | int idx; |
| @@ -132,7 +131,7 @@ static int sh_clk_div6_enable(struct clk *clk) | |||
| 132 | unsigned long value; | 131 | unsigned long value; |
| 133 | int ret; | 132 | int ret; |
| 134 | 133 | ||
| 135 | ret = sh_clk_div6_set_rate(clk, clk->rate, 0); | 134 | ret = sh_clk_div6_set_rate(clk, clk->rate); |
| 136 | if (ret == 0) { | 135 | if (ret == 0) { |
| 137 | value = __raw_readl(clk->enable_reg); | 136 | value = __raw_readl(clk->enable_reg); |
| 138 | value &= ~0x100; /* clear stop bit to enable clock */ | 137 | value &= ~0x100; /* clear stop bit to enable clock */ |
| @@ -253,7 +252,7 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) | |||
| 253 | return 0; | 252 | return 0; |
| 254 | } | 253 | } |
| 255 | 254 | ||
| 256 | static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id) | 255 | static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate) |
| 257 | { | 256 | { |
| 258 | struct clk_div4_table *d4t = clk->priv; | 257 | struct clk_div4_table *d4t = clk->priv; |
| 259 | unsigned long value; | 258 | unsigned long value; |
