diff options
Diffstat (limited to 'drivers/serial')
| -rw-r--r-- | drivers/serial/imx.c | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c index 9f460b175c50..3f5d5a200481 100644 --- a/drivers/serial/imx.c +++ b/drivers/serial/imx.c | |||
| @@ -66,7 +66,7 @@ | |||
| 66 | #define ONEMS 0xb0 /* One Millisecond register */ | 66 | #define ONEMS 0xb0 /* One Millisecond register */ |
| 67 | #define UTS 0xb4 /* UART Test Register */ | 67 | #define UTS 0xb4 /* UART Test Register */ |
| 68 | #endif | 68 | #endif |
| 69 | #if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1) | 69 | #ifdef CONFIG_ARCH_MX1 |
| 70 | #define BIPR1 0xb0 /* Incremental Preset Register 1 */ | 70 | #define BIPR1 0xb0 /* Incremental Preset Register 1 */ |
| 71 | #define BIPR2 0xb4 /* Incremental Preset Register 2 */ | 71 | #define BIPR2 0xb4 /* Incremental Preset Register 2 */ |
| 72 | #define BIPR3 0xb8 /* Incremental Preset Register 3 */ | 72 | #define BIPR3 0xb8 /* Incremental Preset Register 3 */ |
| @@ -96,7 +96,7 @@ | |||
| 96 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ | 96 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ |
| 97 | #define UCR1_SNDBRK (1<<4) /* Send break */ | 97 | #define UCR1_SNDBRK (1<<4) /* Send break */ |
| 98 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ | 98 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ |
| 99 | #if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1) | 99 | #ifdef CONFIG_ARCH_MX1 |
| 100 | #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ | 100 | #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ |
| 101 | #endif | 101 | #endif |
| 102 | #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 | 102 | #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 |
| @@ -127,7 +127,7 @@ | |||
| 127 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ | 127 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ |
| 128 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ | 128 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ |
| 129 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ | 129 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ |
| 130 | #ifdef CONFIG_ARCH_IMX | 130 | #ifdef CONFIG_ARCH_MX1 |
| 131 | #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */ | 131 | #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */ |
| 132 | #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */ | 132 | #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */ |
| 133 | #endif | 133 | #endif |
| @@ -180,13 +180,6 @@ | |||
| 180 | #define UTS_SOFTRST (1<<0) /* Software reset */ | 180 | #define UTS_SOFTRST (1<<0) /* Software reset */ |
| 181 | 181 | ||
| 182 | /* We've been assigned a range on the "Low-density serial ports" major */ | 182 | /* We've been assigned a range on the "Low-density serial ports" major */ |
| 183 | #ifdef CONFIG_ARCH_IMX | ||
| 184 | #define SERIAL_IMX_MAJOR 204 | ||
| 185 | #define MINOR_START 41 | ||
| 186 | #define DEV_NAME "ttySMX" | ||
| 187 | #define MAX_INTERNAL_IRQ IMX_IRQS | ||
| 188 | #endif | ||
| 189 | |||
| 190 | #ifdef CONFIG_ARCH_MXC | 183 | #ifdef CONFIG_ARCH_MXC |
| 191 | #define SERIAL_IMX_MAJOR 207 | 184 | #define SERIAL_IMX_MAJOR 207 |
| 192 | #define MINOR_START 16 | 185 | #define MINOR_START 16 |