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-rw-r--r--drivers/serial/Kconfig30
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/zs.c1287
-rw-r--r--drivers/serial/zs.h284
4 files changed, 1602 insertions, 0 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 7fa413ddccf5..18f629706448 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -486,6 +486,36 @@ config SERIAL_DZ_CONSOLE
486 486
487 If unsure, say Y. 487 If unsure, say Y.
488 488
489config SERIAL_ZS
490 tristate "DECstation Z85C30 serial support"
491 depends on MACH_DECSTATION
492 select SERIAL_CORE
493 default y
494 ---help---
495 Support for the Zilog 85C350 serial communications controller used
496 for serial ports in newer DECstation systems. These include the
497 DECsystem 5900 and all models of the DECstation and DECsystem 5000
498 systems except from model 200.
499
500 If unsure, say Y. To compile this driver as a module, choose M here:
501 the module will be called zs.
502
503config SERIAL_ZS_CONSOLE
504 bool "Support for console on a DECstation Z85C30 serial port"
505 depends on SERIAL_ZS=y
506 select SERIAL_CORE_CONSOLE
507 default y
508 ---help---
509 If you say Y here, it will be possible to use a serial port as the
510 system console (the system console is the device which receives all
511 kernel messages and warnings and which allows logins in single user
512 mode).
513
514 Note that the firmware uses ttyS1 as the serial console on the
515 Maxine and ttyS3 on the others using this driver.
516
517 If unsure, say Y.
518
489config SERIAL_21285 519config SERIAL_21285
490 tristate "DC21285 serial port support" 520 tristate "DC21285 serial port support"
491 depends on ARM && FOOTBRIDGE 521 depends on ARM && FOOTBRIDGE
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index c48cdd61b736..af6377d480d7 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_V850E_UART) += v850e_uart.o
43obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o 43obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o
44obj-$(CONFIG_SERIAL_LH7A40X) += serial_lh7a40x.o 44obj-$(CONFIG_SERIAL_LH7A40X) += serial_lh7a40x.o
45obj-$(CONFIG_SERIAL_DZ) += dz.o 45obj-$(CONFIG_SERIAL_DZ) += dz.o
46obj-$(CONFIG_SERIAL_ZS) += zs.o
46obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o 47obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
47obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o 48obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o
48obj-$(CONFIG_SERIAL_CPM) += cpm_uart/ 49obj-$(CONFIG_SERIAL_CPM) += cpm_uart/
diff --git a/drivers/serial/zs.c b/drivers/serial/zs.c
new file mode 100644
index 000000000000..65f1294fd27b
--- /dev/null
+++ b/drivers/serial/zs.c
@@ -0,0 +1,1287 @@
1/*
2 * zs.c: Serial port driver for IOASIC DECstations.
3 *
4 * Derived from drivers/sbus/char/sunserial.c by Paul Mackerras.
5 * Derived from drivers/macintosh/macserial.c by Harald Koerfgen.
6 *
7 * DECstation changes
8 * Copyright (C) 1998-2000 Harald Koerfgen
9 * Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
10 *
11 * For the rest of the code the original Copyright applies:
12 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
13 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
14 *
15 *
16 * Note: for IOASIC systems the wiring is as follows:
17 *
18 * mouse/keyboard:
19 * DIN-7 MJ-4 signal SCC
20 * 2 1 TxD <- A.TxD
21 * 3 4 RxD -> A.RxD
22 *
23 * EIA-232/EIA-423:
24 * DB-25 MMJ-6 signal SCC
25 * 2 2 TxD <- B.TxD
26 * 3 5 RxD -> B.RxD
27 * 4 RTS <- ~A.RTS
28 * 5 CTS -> ~B.CTS
29 * 6 6 DSR -> ~A.SYNC
30 * 8 CD -> ~B.DCD
31 * 12 DSRS(DCE) -> ~A.CTS (*)
32 * 15 TxC -> B.TxC
33 * 17 RxC -> B.RxC
34 * 20 1 DTR <- ~A.DTR
35 * 22 RI -> ~A.DCD
36 * 23 DSRS(DTE) <- ~B.RTS
37 *
38 * (*) EIA-232 defines the signal at this pin to be SCD, while DSRS(DCE)
39 * is shared with DSRS(DTE) at pin 23.
40 *
41 * As you can immediately notice the wiring of the RTS, DTR and DSR signals
42 * is a bit odd. This makes the handling of port B unnecessarily
43 * complicated and prevents the use of some automatic modes of operation.
44 */
45
46#if defined(CONFIG_SERIAL_ZS_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
47#define SUPPORT_SYSRQ
48#endif
49
50#include <linux/bug.h>
51#include <linux/console.h>
52#include <linux/delay.h>
53#include <linux/errno.h>
54#include <linux/init.h>
55#include <linux/interrupt.h>
56#include <linux/io.h>
57#include <linux/ioport.h>
58#include <linux/irqflags.h>
59#include <linux/kernel.h>
60#include <linux/major.h>
61#include <linux/serial.h>
62#include <linux/serial_core.h>
63#include <linux/spinlock.h>
64#include <linux/sysrq.h>
65#include <linux/tty.h>
66#include <linux/types.h>
67
68#include <asm/atomic.h>
69#include <asm/system.h>
70
71#include <asm/dec/interrupts.h>
72#include <asm/dec/ioasic_addrs.h>
73#include <asm/dec/system.h>
74
75#include "zs.h"
76
77
78MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
79MODULE_DESCRIPTION("DECstation Z85C30 serial driver");
80MODULE_LICENSE("GPL");
81
82
83static char zs_name[] __initdata = "DECstation Z85C30 serial driver version ";
84static char zs_version[] __initdata = "0.10";
85
86/*
87 * It would be nice to dynamically allocate everything that
88 * depends on ZS_NUM_SCCS, so we could support any number of
89 * Z85C30s, but for now...
90 */
91#define ZS_NUM_SCCS 2 /* Max # of ZS chips supported. */
92#define ZS_NUM_CHAN 2 /* 2 channels per chip. */
93#define ZS_CHAN_A 0 /* Index of the channel A. */
94#define ZS_CHAN_B 1 /* Index of the channel B. */
95#define ZS_CHAN_IO_SIZE 8 /* IOMEM space size. */
96#define ZS_CHAN_IO_STRIDE 4 /* Register alignment. */
97#define ZS_CHAN_IO_OFFSET 1 /* The SCC resides on the high byte
98 of the 16-bit IOBUS. */
99#define ZS_CLOCK 7372800 /* Z85C30 PCLK input clock rate. */
100
101#define to_zport(uport) container_of(uport, struct zs_port, port)
102
103struct zs_parms {
104 resource_size_t scc[ZS_NUM_SCCS];
105 int irq[ZS_NUM_SCCS];
106};
107
108static struct zs_scc zs_sccs[ZS_NUM_SCCS];
109
110static u8 zs_init_regs[ZS_NUM_REGS] __initdata = {
111 0, /* write 0 */
112 PAR_SPEC, /* write 1 */
113 0, /* write 2 */
114 0, /* write 3 */
115 X16CLK | SB1, /* write 4 */
116 0, /* write 5 */
117 0, 0, 0, /* write 6, 7, 8 */
118 MIE | DLC | NV, /* write 9 */
119 NRZ, /* write 10 */
120 TCBR | RCBR, /* write 11 */
121 0, 0, /* BRG time constant, write 12 + 13 */
122 BRSRC | BRENABL, /* write 14 */
123 0, /* write 15 */
124};
125
126/*
127 * Debugging.
128 */
129#undef ZS_DEBUG_REGS
130
131
132/*
133 * Reading and writing Z85C30 registers.
134 */
135static void recovery_delay(void)
136{
137 udelay(2);
138}
139
140static u8 read_zsreg(struct zs_port *zport, int reg)
141{
142 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
143 u8 retval;
144
145 if (reg != 0) {
146 writeb(reg & 0xf, control);
147 fast_iob();
148 recovery_delay();
149 }
150 retval = readb(control);
151 recovery_delay();
152 return retval;
153}
154
155static void write_zsreg(struct zs_port *zport, int reg, u8 value)
156{
157 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
158
159 if (reg != 0) {
160 writeb(reg & 0xf, control);
161 fast_iob(); recovery_delay();
162 }
163 writeb(value, control);
164 fast_iob();
165 recovery_delay();
166 return;
167}
168
169static u8 read_zsdata(struct zs_port *zport)
170{
171 void __iomem *data = zport->port.membase +
172 ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
173 u8 retval;
174
175 retval = readb(data);
176 recovery_delay();
177 return retval;
178}
179
180static void write_zsdata(struct zs_port *zport, u8 value)
181{
182 void __iomem *data = zport->port.membase +
183 ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
184
185 writeb(value, data);
186 fast_iob();
187 recovery_delay();
188 return;
189}
190
191#ifdef ZS_DEBUG_REGS
192void zs_dump(void)
193{
194 struct zs_port *zport;
195 int i, j;
196
197 for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
198 zport = &zs_sccs[i / ZS_NUM_CHAN].zport[i % ZS_NUM_CHAN];
199
200 if (!zport->scc)
201 continue;
202
203 for (j = 0; j < 16; j++)
204 printk("W%-2d = 0x%02x\t", j, zport->regs[j]);
205 printk("\n");
206 for (j = 0; j < 16; j++)
207 printk("R%-2d = 0x%02x\t", j, read_zsreg(zport, j));
208 printk("\n\n");
209 }
210}
211#endif
212
213
214static void zs_spin_lock_cond_irq(spinlock_t *lock, int irq)
215{
216 if (irq)
217 spin_lock_irq(lock);
218 else
219 spin_lock(lock);
220}
221
222static void zs_spin_unlock_cond_irq(spinlock_t *lock, int irq)
223{
224 if (irq)
225 spin_unlock_irq(lock);
226 else
227 spin_unlock(lock);
228}
229
230static int zs_receive_drain(struct zs_port *zport)
231{
232 int loops = 10000;
233
234 while ((read_zsreg(zport, R0) & Rx_CH_AV) && loops--)
235 read_zsdata(zport);
236 return loops;
237}
238
239static int zs_transmit_drain(struct zs_port *zport, int irq)
240{
241 struct zs_scc *scc = zport->scc;
242 int loops = 10000;
243
244 while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && loops--) {
245 zs_spin_unlock_cond_irq(&scc->zlock, irq);
246 udelay(2);
247 zs_spin_lock_cond_irq(&scc->zlock, irq);
248 }
249 return loops;
250}
251
252static int zs_line_drain(struct zs_port *zport, int irq)
253{
254 struct zs_scc *scc = zport->scc;
255 int loops = 10000;
256
257 while (!(read_zsreg(zport, R1) & ALL_SNT) && loops--) {
258 zs_spin_unlock_cond_irq(&scc->zlock, irq);
259 udelay(2);
260 zs_spin_lock_cond_irq(&scc->zlock, irq);
261 }
262 return loops;
263}
264
265
266static void load_zsregs(struct zs_port *zport, u8 *regs, int irq)
267{
268 /* Let the current transmission finish. */
269 zs_line_drain(zport, irq);
270 /* Load 'em up. */
271 write_zsreg(zport, R3, regs[3] & ~RxENABLE);
272 write_zsreg(zport, R5, regs[5] & ~TxENAB);
273 write_zsreg(zport, R4, regs[4]);
274 write_zsreg(zport, R9, regs[9]);
275 write_zsreg(zport, R1, regs[1]);
276 write_zsreg(zport, R2, regs[2]);
277 write_zsreg(zport, R10, regs[10]);
278 write_zsreg(zport, R14, regs[14] & ~BRENABL);
279 write_zsreg(zport, R11, regs[11]);
280 write_zsreg(zport, R12, regs[12]);
281 write_zsreg(zport, R13, regs[13]);
282 write_zsreg(zport, R14, regs[14]);
283 write_zsreg(zport, R15, regs[15]);
284 if (regs[3] & RxENABLE)
285 write_zsreg(zport, R3, regs[3]);
286 if (regs[5] & TxENAB)
287 write_zsreg(zport, R5, regs[5]);
288 return;
289}
290
291
292/*
293 * Status handling routines.
294 */
295
296/*
297 * zs_tx_empty() -- get the transmitter empty status
298 *
299 * Purpose: Let user call ioctl() to get info when the UART physically
300 * is emptied. On bus types like RS485, the transmitter must
301 * release the bus after transmitting. This must be done when
302 * the transmit shift register is empty, not be done when the
303 * transmit holding register is empty. This functionality
304 * allows an RS485 driver to be written in user space.
305 */
306static unsigned int zs_tx_empty(struct uart_port *uport)
307{
308 struct zs_port *zport = to_zport(uport);
309 struct zs_scc *scc = zport->scc;
310 unsigned long flags;
311 u8 status;
312
313 spin_lock_irqsave(&scc->zlock, flags);
314 status = read_zsreg(zport, R1);
315 spin_unlock_irqrestore(&scc->zlock, flags);
316
317 return status & ALL_SNT ? TIOCSER_TEMT : 0;
318}
319
320static unsigned int zs_raw_get_ab_mctrl(struct zs_port *zport_a,
321 struct zs_port *zport_b)
322{
323 u8 status_a, status_b;
324 unsigned int mctrl;
325
326 status_a = read_zsreg(zport_a, R0);
327 status_b = read_zsreg(zport_b, R0);
328
329 mctrl = ((status_b & CTS) ? TIOCM_CTS : 0) |
330 ((status_b & DCD) ? TIOCM_CAR : 0) |
331 ((status_a & DCD) ? TIOCM_RNG : 0) |
332 ((status_a & SYNC_HUNT) ? TIOCM_DSR : 0);
333
334 return mctrl;
335}
336
337static unsigned int zs_raw_get_mctrl(struct zs_port *zport)
338{
339 struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
340
341 return zport != zport_a ? zs_raw_get_ab_mctrl(zport_a, zport) : 0;
342}
343
344static unsigned int zs_raw_xor_mctrl(struct zs_port *zport)
345{
346 struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
347 unsigned int mmask, mctrl, delta;
348 u8 mask_a, mask_b;
349
350 if (zport == zport_a)
351 return 0;
352
353 mask_a = zport_a->regs[15];
354 mask_b = zport->regs[15];
355
356 mmask = ((mask_b & CTSIE) ? TIOCM_CTS : 0) |
357 ((mask_b & DCDIE) ? TIOCM_CAR : 0) |
358 ((mask_a & DCDIE) ? TIOCM_RNG : 0) |
359 ((mask_a & SYNCIE) ? TIOCM_DSR : 0);
360
361 mctrl = zport->mctrl;
362 if (mmask) {
363 mctrl &= ~mmask;
364 mctrl |= zs_raw_get_ab_mctrl(zport_a, zport) & mmask;
365 }
366
367 delta = mctrl ^ zport->mctrl;
368 if (delta)
369 zport->mctrl = mctrl;
370
371 return delta;
372}
373
374static unsigned int zs_get_mctrl(struct uart_port *uport)
375{
376 struct zs_port *zport = to_zport(uport);
377 struct zs_scc *scc = zport->scc;
378 unsigned int mctrl;
379
380 spin_lock(&scc->zlock);
381 mctrl = zs_raw_get_mctrl(zport);
382 spin_unlock(&scc->zlock);
383
384 return mctrl;
385}
386
387static void zs_set_mctrl(struct uart_port *uport, unsigned int mctrl)
388{
389 struct zs_port *zport = to_zport(uport);
390 struct zs_scc *scc = zport->scc;
391 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
392 u8 oldloop, newloop;
393
394 spin_lock(&scc->zlock);
395 if (zport != zport_a) {
396 if (mctrl & TIOCM_DTR)
397 zport_a->regs[5] |= DTR;
398 else
399 zport_a->regs[5] &= ~DTR;
400 if (mctrl & TIOCM_RTS)
401 zport_a->regs[5] |= RTS;
402 else
403 zport_a->regs[5] &= ~RTS;
404 write_zsreg(zport_a, R5, zport_a->regs[5]);
405 }
406
407 /* Rarely modified, so don't poke at hardware unless necessary. */
408 oldloop = zport->regs[14];
409 newloop = oldloop;
410 if (mctrl & TIOCM_LOOP)
411 newloop |= LOOPBAK;
412 else
413 newloop &= ~LOOPBAK;
414 if (newloop != oldloop) {
415 zport->regs[14] = newloop;
416 write_zsreg(zport, R14, zport->regs[14]);
417 }
418 spin_unlock(&scc->zlock);
419}
420
421static void zs_raw_stop_tx(struct zs_port *zport)
422{
423 write_zsreg(zport, R0, RES_Tx_P);
424 zport->tx_stopped = 1;
425}
426
427static void zs_stop_tx(struct uart_port *uport)
428{
429 struct zs_port *zport = to_zport(uport);
430 struct zs_scc *scc = zport->scc;
431
432 spin_lock(&scc->zlock);
433 zs_raw_stop_tx(zport);
434 spin_unlock(&scc->zlock);
435}
436
437static void zs_raw_transmit_chars(struct zs_port *);
438
439static void zs_start_tx(struct uart_port *uport)
440{
441 struct zs_port *zport = to_zport(uport);
442 struct zs_scc *scc = zport->scc;
443
444 spin_lock(&scc->zlock);
445 if (zport->tx_stopped) {
446 zs_transmit_drain(zport, 0);
447 zport->tx_stopped = 0;
448 zs_raw_transmit_chars(zport);
449 }
450 spin_unlock(&scc->zlock);
451}
452
453static void zs_stop_rx(struct uart_port *uport)
454{
455 struct zs_port *zport = to_zport(uport);
456 struct zs_scc *scc = zport->scc;
457 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
458
459 spin_lock(&scc->zlock);
460 zport->regs[15] &= ~BRKIE;
461 zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB);
462 zport->regs[1] |= RxINT_DISAB;
463
464 if (zport != zport_a) {
465 /* A-side DCD tracks RI and SYNC tracks DSR. */
466 zport_a->regs[15] &= ~(DCDIE | SYNCIE);
467 write_zsreg(zport_a, R15, zport_a->regs[15]);
468 if (!(zport_a->regs[15] & BRKIE)) {
469 zport_a->regs[1] &= ~EXT_INT_ENAB;
470 write_zsreg(zport_a, R1, zport_a->regs[1]);
471 }
472
473 /* This-side DCD tracks DCD and CTS tracks CTS. */
474 zport->regs[15] &= ~(DCDIE | CTSIE);
475 zport->regs[1] &= ~EXT_INT_ENAB;
476 } else {
477 /* DCD tracks RI and SYNC tracks DSR for the B side. */
478 if (!(zport->regs[15] & (DCDIE | SYNCIE)))
479 zport->regs[1] &= ~EXT_INT_ENAB;
480 }
481
482 write_zsreg(zport, R15, zport->regs[15]);
483 write_zsreg(zport, R1, zport->regs[1]);
484 spin_unlock(&scc->zlock);
485}
486
487static void zs_enable_ms(struct uart_port *uport)
488{
489 struct zs_port *zport = to_zport(uport);
490 struct zs_scc *scc = zport->scc;
491 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
492
493 if (zport == zport_a)
494 return;
495
496 spin_lock(&scc->zlock);
497
498 /* Clear Ext interrupts if not being handled already. */
499 if (!(zport_a->regs[1] & EXT_INT_ENAB))
500 write_zsreg(zport_a, R0, RES_EXT_INT);
501
502 /* A-side DCD tracks RI and SYNC tracks DSR. */
503 zport_a->regs[1] |= EXT_INT_ENAB;
504 zport_a->regs[15] |= DCDIE | SYNCIE;
505
506 /* This-side DCD tracks DCD and CTS tracks CTS. */
507 zport->regs[15] |= DCDIE | CTSIE;
508
509 zs_raw_xor_mctrl(zport);
510
511 write_zsreg(zport_a, R1, zport_a->regs[1]);
512 write_zsreg(zport_a, R15, zport_a->regs[15]);
513 write_zsreg(zport, R15, zport->regs[15]);
514 spin_unlock(&scc->zlock);
515}
516
517static void zs_break_ctl(struct uart_port *uport, int break_state)
518{
519 struct zs_port *zport = to_zport(uport);
520 struct zs_scc *scc = zport->scc;
521 unsigned long flags;
522
523 spin_lock_irqsave(&scc->zlock, flags);
524 if (break_state == -1)
525 zport->regs[5] |= SND_BRK;
526 else
527 zport->regs[5] &= ~SND_BRK;
528 write_zsreg(zport, R5, zport->regs[5]);
529 spin_unlock_irqrestore(&scc->zlock, flags);
530}
531
532
533/*
534 * Interrupt handling routines.
535 */
536#define Rx_BRK 0x0100 /* BREAK event software flag. */
537#define Rx_SYS 0x0200 /* SysRq event software flag. */
538
539static void zs_receive_chars(struct zs_port *zport)
540{
541 struct uart_port *uport = &zport->port;
542 struct zs_scc *scc = zport->scc;
543 struct uart_icount *icount;
544 unsigned int avail, status, ch, flag;
545 int count;
546
547 for (count = 16; count; count--) {
548 spin_lock(&scc->zlock);
549 avail = read_zsreg(zport, R0) & Rx_CH_AV;
550 spin_unlock(&scc->zlock);
551 if (!avail)
552 break;
553
554 spin_lock(&scc->zlock);
555 status = read_zsreg(zport, R1) & (Rx_OVR | FRM_ERR | PAR_ERR);
556 ch = read_zsdata(zport);
557 spin_unlock(&scc->zlock);
558
559 flag = TTY_NORMAL;
560
561 icount = &uport->icount;
562 icount->rx++;
563
564 /* Handle the null char got when BREAK is removed. */
565 if (!ch)
566 status |= zport->tty_break;
567 if (unlikely(status &
568 (Rx_OVR | FRM_ERR | PAR_ERR | Rx_SYS | Rx_BRK))) {
569 zport->tty_break = 0;
570
571 /* Reset the error indication. */
572 if (status & (Rx_OVR | FRM_ERR | PAR_ERR)) {
573 spin_lock(&scc->zlock);
574 write_zsreg(zport, R0, ERR_RES);
575 spin_unlock(&scc->zlock);
576 }
577
578 if (status & (Rx_SYS | Rx_BRK)) {
579 icount->brk++;
580 /* SysRq discards the null char. */
581 if (status & Rx_SYS)
582 continue;
583 } else if (status & FRM_ERR)
584 icount->frame++;
585 else if (status & PAR_ERR)
586 icount->parity++;
587 if (status & Rx_OVR)
588 icount->overrun++;
589
590 status &= uport->read_status_mask;
591 if (status & Rx_BRK)
592 flag = TTY_BREAK;
593 else if (status & FRM_ERR)
594 flag = TTY_FRAME;
595 else if (status & PAR_ERR)
596 flag = TTY_PARITY;
597 }
598
599 if (uart_handle_sysrq_char(uport, ch))
600 continue;
601
602 uart_insert_char(uport, status, Rx_OVR, ch, flag);
603 }
604
605 tty_flip_buffer_push(uport->info->tty);
606}
607
608static void zs_raw_transmit_chars(struct zs_port *zport)
609{
610 struct circ_buf *xmit = &zport->port.info->xmit;
611
612 /* XON/XOFF chars. */
613 if (zport->port.x_char) {
614 write_zsdata(zport, zport->port.x_char);
615 zport->port.icount.tx++;
616 zport->port.x_char = 0;
617 return;
618 }
619
620 /* If nothing to do or stopped or hardware stopped. */
621 if (uart_circ_empty(xmit) || uart_tx_stopped(&zport->port)) {
622 zs_raw_stop_tx(zport);
623 return;
624 }
625
626 /* Send char. */
627 write_zsdata(zport, xmit->buf[xmit->tail]);
628 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
629 zport->port.icount.tx++;
630
631 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
632 uart_write_wakeup(&zport->port);
633
634 /* Are we are done? */
635 if (uart_circ_empty(xmit))
636 zs_raw_stop_tx(zport);
637}
638
639static void zs_transmit_chars(struct zs_port *zport)
640{
641 struct zs_scc *scc = zport->scc;
642
643 spin_lock(&scc->zlock);
644 zs_raw_transmit_chars(zport);
645 spin_unlock(&scc->zlock);
646}
647
648static void zs_status_handle(struct zs_port *zport, struct zs_port *zport_a)
649{
650 struct uart_port *uport = &zport->port;
651 struct zs_scc *scc = zport->scc;
652 unsigned int delta;
653 u8 status, brk;
654
655 spin_lock(&scc->zlock);
656
657 /* Get status from Read Register 0. */
658 status = read_zsreg(zport, R0);
659
660 if (zport->regs[15] & BRKIE) {
661 brk = status & BRK_ABRT;
662 if (brk && !zport->brk) {
663 spin_unlock(&scc->zlock);
664 if (uart_handle_break(uport))
665 zport->tty_break = Rx_SYS;
666 else
667 zport->tty_break = Rx_BRK;
668 spin_lock(&scc->zlock);
669 }
670 zport->brk = brk;
671 }
672
673 if (zport != zport_a) {
674 delta = zs_raw_xor_mctrl(zport);
675 spin_unlock(&scc->zlock);
676
677 if (delta & TIOCM_CTS)
678 uart_handle_cts_change(uport,
679 zport->mctrl & TIOCM_CTS);
680 if (delta & TIOCM_CAR)
681 uart_handle_dcd_change(uport,
682 zport->mctrl & TIOCM_CAR);
683 if (delta & TIOCM_RNG)
684 uport->icount.dsr++;
685 if (delta & TIOCM_DSR)
686 uport->icount.rng++;
687
688 if (delta)
689 wake_up_interruptible(&uport->info->delta_msr_wait);
690
691 spin_lock(&scc->zlock);
692 }
693
694 /* Clear the status condition... */
695 write_zsreg(zport, R0, RES_EXT_INT);
696
697 spin_unlock(&scc->zlock);
698}
699
700/*
701 * This is the Z85C30 driver's generic interrupt routine.
702 */
703static irqreturn_t zs_interrupt(int irq, void *dev_id)
704{
705 struct zs_scc *scc = dev_id;
706 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
707 struct zs_port *zport_b = &scc->zport[ZS_CHAN_B];
708 irqreturn_t status = IRQ_NONE;
709 u8 zs_intreg;
710 int count;
711
712 /*
713 * NOTE: The read register 3, which holds the irq status,
714 * does so for both channels on each chip. Although
715 * the status value itself must be read from the A
716 * channel and is only valid when read from channel A.
717 * Yes... broken hardware...
718 */
719 for (count = 16; count; count--) {
720 spin_lock(&scc->zlock);
721 zs_intreg = read_zsreg(zport_a, R3);
722 spin_unlock(&scc->zlock);
723 if (!zs_intreg)
724 break;
725
726 /*
727 * We do not like losing characters, so we prioritise
728 * interrupt sources a little bit differently than
729 * the SCC would, was it allowed to.
730 */
731 if (zs_intreg & CHBRxIP)
732 zs_receive_chars(zport_b);
733 if (zs_intreg & CHARxIP)
734 zs_receive_chars(zport_a);
735 if (zs_intreg & CHBEXT)
736 zs_status_handle(zport_b, zport_a);
737 if (zs_intreg & CHAEXT)
738 zs_status_handle(zport_a, zport_a);
739 if (zs_intreg & CHBTxIP)
740 zs_transmit_chars(zport_b);
741 if (zs_intreg & CHATxIP)
742 zs_transmit_chars(zport_a);
743
744 status = IRQ_HANDLED;
745 }
746
747 return status;
748}
749
750
751/*
752 * Finally, routines used to initialize the serial port.
753 */
754static int zs_startup(struct uart_port *uport)
755{
756 struct zs_port *zport = to_zport(uport);
757 struct zs_scc *scc = zport->scc;
758 unsigned long flags;
759 int irq_guard;
760 int ret;
761
762 irq_guard = atomic_add_return(1, &scc->irq_guard);
763 if (irq_guard == 1) {
764 ret = request_irq(zport->port.irq, zs_interrupt,
765 IRQF_SHARED, "scc", scc);
766 if (ret) {
767 atomic_add(-1, &scc->irq_guard);
768 printk(KERN_ERR "zs: can't get irq %d\n",
769 zport->port.irq);
770 return ret;
771 }
772 }
773
774 spin_lock_irqsave(&scc->zlock, flags);
775
776 /* Clear the receive FIFO. */
777 zs_receive_drain(zport);
778
779 /* Clear the interrupt registers. */
780 write_zsreg(zport, R0, ERR_RES);
781 write_zsreg(zport, R0, RES_Tx_P);
782 /* But Ext only if not being handled already. */
783 if (!(zport->regs[1] & EXT_INT_ENAB))
784 write_zsreg(zport, R0, RES_EXT_INT);
785
786 /* Finally, enable sequencing and interrupts. */
787 zport->regs[1] &= ~RxINT_MASK;
788 zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB;
789 zport->regs[3] |= RxENABLE;
790 zport->regs[5] |= TxENAB;
791 zport->regs[15] |= BRKIE;
792 write_zsreg(zport, R1, zport->regs[1]);
793 write_zsreg(zport, R3, zport->regs[3]);
794 write_zsreg(zport, R5, zport->regs[5]);
795 write_zsreg(zport, R15, zport->regs[15]);
796
797 /* Record the current state of RR0. */
798 zport->mctrl = zs_raw_get_mctrl(zport);
799 zport->brk = read_zsreg(zport, R0) & BRK_ABRT;
800
801 zport->tx_stopped = 1;
802
803 spin_unlock_irqrestore(&scc->zlock, flags);
804
805 return 0;
806}
807
808static void zs_shutdown(struct uart_port *uport)
809{
810 struct zs_port *zport = to_zport(uport);
811 struct zs_scc *scc = zport->scc;
812 unsigned long flags;
813 int irq_guard;
814
815 spin_lock_irqsave(&scc->zlock, flags);
816
817 zport->regs[5] &= ~TxENAB;
818 zport->regs[3] &= ~RxENABLE;
819 write_zsreg(zport, R5, zport->regs[5]);
820 write_zsreg(zport, R3, zport->regs[3]);
821
822 spin_unlock_irqrestore(&scc->zlock, flags);
823
824 irq_guard = atomic_add_return(-1, &scc->irq_guard);
825 if (!irq_guard)
826 free_irq(zport->port.irq, scc);
827}
828
829
830static void zs_reset(struct zs_port *zport)
831{
832 struct zs_scc *scc = zport->scc;
833 int irq;
834 unsigned long flags;
835
836 spin_lock_irqsave(&scc->zlock, flags);
837 irq = !irqs_disabled_flags(flags);
838 if (!scc->initialised) {
839 /* Reset the pointer first, just in case... */
840 read_zsreg(zport, R0);
841 /* And let the current transmission finish. */
842 zs_line_drain(zport, irq);
843 write_zsreg(zport, R9, FHWRES);
844 udelay(10);
845 write_zsreg(zport, R9, 0);
846 scc->initialised = 1;
847 }
848 load_zsregs(zport, zport->regs, irq);
849 spin_unlock_irqrestore(&scc->zlock, flags);
850}
851
852static void zs_set_termios(struct uart_port *uport, struct ktermios *termios,
853 struct ktermios *old_termios)
854{
855 struct zs_port *zport = to_zport(uport);
856 struct zs_scc *scc = zport->scc;
857 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
858 int irq;
859 unsigned int baud, brg;
860 unsigned long flags;
861
862 spin_lock_irqsave(&scc->zlock, flags);
863 irq = !irqs_disabled_flags(flags);
864
865 /* Byte size. */
866 zport->regs[3] &= ~RxNBITS_MASK;
867 zport->regs[5] &= ~TxNBITS_MASK;
868 switch (termios->c_cflag & CSIZE) {
869 case CS5:
870 zport->regs[3] |= Rx5;
871 zport->regs[5] |= Tx5;
872 break;
873 case CS6:
874 zport->regs[3] |= Rx6;
875 zport->regs[5] |= Tx6;
876 break;
877 case CS7:
878 zport->regs[3] |= Rx7;
879 zport->regs[5] |= Tx7;
880 break;
881 case CS8:
882 default:
883 zport->regs[3] |= Rx8;
884 zport->regs[5] |= Tx8;
885 break;
886 }
887
888 /* Parity and stop bits. */
889 zport->regs[4] &= ~(XCLK_MASK | SB_MASK | PAR_ENA | PAR_EVEN);
890 if (termios->c_cflag & CSTOPB)
891 zport->regs[4] |= SB2;
892 else
893 zport->regs[4] |= SB1;
894 if (termios->c_cflag & PARENB)
895 zport->regs[4] |= PAR_ENA;
896 if (!(termios->c_cflag & PARODD))
897 zport->regs[4] |= PAR_EVEN;
898 switch (zport->clk_mode) {
899 case 64:
900 zport->regs[4] |= X64CLK;
901 break;
902 case 32:
903 zport->regs[4] |= X32CLK;
904 break;
905 case 16:
906 zport->regs[4] |= X16CLK;
907 break;
908 case 1:
909 zport->regs[4] |= X1CLK;
910 break;
911 default:
912 BUG();
913 }
914
915 baud = uart_get_baud_rate(uport, termios, old_termios, 0,
916 uport->uartclk / zport->clk_mode / 4);
917
918 brg = ZS_BPS_TO_BRG(baud, uport->uartclk / zport->clk_mode);
919 zport->regs[12] = brg & 0xff;
920 zport->regs[13] = (brg >> 8) & 0xff;
921
922 uart_update_timeout(uport, termios->c_cflag, baud);
923
924 uport->read_status_mask = Rx_OVR;
925 if (termios->c_iflag & INPCK)
926 uport->read_status_mask |= FRM_ERR | PAR_ERR;
927 if (termios->c_iflag & (BRKINT | PARMRK))
928 uport->read_status_mask |= Rx_BRK;
929
930 uport->ignore_status_mask = 0;
931 if (termios->c_iflag & IGNPAR)
932 uport->ignore_status_mask |= FRM_ERR | PAR_ERR;
933 if (termios->c_iflag & IGNBRK) {
934 uport->ignore_status_mask |= Rx_BRK;
935 if (termios->c_iflag & IGNPAR)
936 uport->ignore_status_mask |= Rx_OVR;
937 }
938
939 if (termios->c_cflag & CREAD)
940 zport->regs[3] |= RxENABLE;
941 else
942 zport->regs[3] &= ~RxENABLE;
943
944 if (zport != zport_a) {
945 if (!(termios->c_cflag & CLOCAL)) {
946 zport->regs[15] |= DCDIE;
947 } else
948 zport->regs[15] &= ~DCDIE;
949 if (termios->c_cflag & CRTSCTS) {
950 zport->regs[15] |= CTSIE;
951 } else
952 zport->regs[15] &= ~CTSIE;
953 zs_raw_xor_mctrl(zport);
954 }
955
956 /* Load up the new values. */
957 load_zsregs(zport, zport->regs, irq);
958
959 spin_unlock_irqrestore(&scc->zlock, flags);
960}
961
962
963static const char *zs_type(struct uart_port *uport)
964{
965 return "Z85C30 SCC";
966}
967
968static void zs_release_port(struct uart_port *uport)
969{
970 iounmap(uport->membase);
971 uport->membase = 0;
972 release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
973}
974
975static int zs_map_port(struct uart_port *uport)
976{
977 if (!uport->membase)
978 uport->membase = ioremap_nocache(uport->mapbase,
979 ZS_CHAN_IO_SIZE);
980 if (!uport->membase) {
981 printk(KERN_ERR "zs: Cannot map MMIO\n");
982 return -ENOMEM;
983 }
984 return 0;
985}
986
987static int zs_request_port(struct uart_port *uport)
988{
989 int ret;
990
991 if (!request_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE, "scc")) {
992 printk(KERN_ERR "zs: Unable to reserve MMIO resource\n");
993 return -EBUSY;
994 }
995 ret = zs_map_port(uport);
996 if (ret) {
997 release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
998 return ret;
999 }
1000 return 0;
1001}
1002
1003static void zs_config_port(struct uart_port *uport, int flags)
1004{
1005 struct zs_port *zport = to_zport(uport);
1006
1007 if (flags & UART_CONFIG_TYPE) {
1008 if (zs_request_port(uport))
1009 return;
1010
1011 uport->type = PORT_ZS;
1012
1013 zs_reset(zport);
1014 }
1015}
1016
1017static int zs_verify_port(struct uart_port *uport, struct serial_struct *ser)
1018{
1019 struct zs_port *zport = to_zport(uport);
1020 int ret = 0;
1021
1022 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ZS)
1023 ret = -EINVAL;
1024 if (ser->irq != uport->irq)
1025 ret = -EINVAL;
1026 if (ser->baud_base != uport->uartclk / zport->clk_mode / 4)
1027 ret = -EINVAL;
1028 return ret;
1029}
1030
1031
1032static struct uart_ops zs_ops = {
1033 .tx_empty = zs_tx_empty,
1034 .set_mctrl = zs_set_mctrl,
1035 .get_mctrl = zs_get_mctrl,
1036 .stop_tx = zs_stop_tx,
1037 .start_tx = zs_start_tx,
1038 .stop_rx = zs_stop_rx,
1039 .enable_ms = zs_enable_ms,
1040 .break_ctl = zs_break_ctl,
1041 .startup = zs_startup,
1042 .shutdown = zs_shutdown,
1043 .set_termios = zs_set_termios,
1044 .type = zs_type,
1045 .release_port = zs_release_port,
1046 .request_port = zs_request_port,
1047 .config_port = zs_config_port,
1048 .verify_port = zs_verify_port,
1049};
1050
1051/*
1052 * Initialize Z85C30 port structures.
1053 */
1054static int __init zs_probe_sccs(void)
1055{
1056 static int probed;
1057 struct zs_parms zs_parms;
1058 int chip, side, irq;
1059 int n_chips = 0;
1060 int i;
1061
1062 if (probed)
1063 return 0;
1064
1065 irq = dec_interrupt[DEC_IRQ_SCC0];
1066 if (irq >= 0) {
1067 zs_parms.scc[n_chips] = IOASIC_SCC0;
1068 zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC0];
1069 n_chips++;
1070 }
1071 irq = dec_interrupt[DEC_IRQ_SCC1];
1072 if (irq >= 0) {
1073 zs_parms.scc[n_chips] = IOASIC_SCC1;
1074 zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC1];
1075 n_chips++;
1076 }
1077 if (!n_chips)
1078 return -ENXIO;
1079
1080 probed = 1;
1081
1082 for (chip = 0; chip < n_chips; chip++) {
1083 spin_lock_init(&zs_sccs[chip].zlock);
1084 for (side = 0; side < ZS_NUM_CHAN; side++) {
1085 struct zs_port *zport = &zs_sccs[chip].zport[side];
1086 struct uart_port *uport = &zport->port;
1087
1088 zport->scc = &zs_sccs[chip];
1089 zport->clk_mode = 16;
1090
1091 uport->irq = zs_parms.irq[chip];
1092 uport->uartclk = ZS_CLOCK;
1093 uport->fifosize = 1;
1094 uport->iotype = UPIO_MEM;
1095 uport->flags = UPF_BOOT_AUTOCONF;
1096 uport->ops = &zs_ops;
1097 uport->line = chip * ZS_NUM_CHAN + side;
1098 uport->mapbase = dec_kn_slot_base +
1099 zs_parms.scc[chip] +
1100 (side ^ ZS_CHAN_B) * ZS_CHAN_IO_SIZE;
1101
1102 for (i = 0; i < ZS_NUM_REGS; i++)
1103 zport->regs[i] = zs_init_regs[i];
1104 }
1105 }
1106
1107 return 0;
1108}
1109
1110
1111#ifdef CONFIG_SERIAL_ZS_CONSOLE
1112static void zs_console_putchar(struct uart_port *uport, int ch)
1113{
1114 struct zs_port *zport = to_zport(uport);
1115 struct zs_scc *scc = zport->scc;
1116 int irq;
1117 unsigned long flags;
1118
1119 spin_lock_irqsave(&scc->zlock, flags);
1120 irq = !irqs_disabled_flags(flags);
1121 if (zs_transmit_drain(zport, irq))
1122 write_zsdata(zport, ch);
1123 spin_unlock_irqrestore(&scc->zlock, flags);
1124}
1125
1126/*
1127 * Print a string to the serial port trying not to disturb
1128 * any possible real use of the port...
1129 */
1130static void zs_console_write(struct console *co, const char *s,
1131 unsigned int count)
1132{
1133 int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
1134 struct zs_port *zport = &zs_sccs[chip].zport[side];
1135 struct zs_scc *scc = zport->scc;
1136 unsigned long flags;
1137 u8 txint, txenb;
1138 int irq;
1139
1140 /* Disable transmit interrupts and enable the transmitter. */
1141 spin_lock_irqsave(&scc->zlock, flags);
1142 txint = zport->regs[1];
1143 txenb = zport->regs[5];
1144 if (txint & TxINT_ENAB) {
1145 zport->regs[1] = txint & ~TxINT_ENAB;
1146 write_zsreg(zport, R1, zport->regs[1]);
1147 }
1148 if (!(txenb & TxENAB)) {
1149 zport->regs[5] = txenb | TxENAB;
1150 write_zsreg(zport, R5, zport->regs[5]);
1151 }
1152 spin_unlock_irqrestore(&scc->zlock, flags);
1153
1154 uart_console_write(&zport->port, s, count, zs_console_putchar);
1155
1156 /* Restore transmit interrupts and the transmitter enable. */
1157 spin_lock_irqsave(&scc->zlock, flags);
1158 irq = !irqs_disabled_flags(flags);
1159 zs_line_drain(zport, irq);
1160 if (!(txenb & TxENAB)) {
1161 zport->regs[5] &= ~TxENAB;
1162 write_zsreg(zport, R5, zport->regs[5]);
1163 }
1164 if (txint & TxINT_ENAB) {
1165 zport->regs[1] |= TxINT_ENAB;
1166 write_zsreg(zport, R1, zport->regs[1]);
1167 }
1168 spin_unlock_irqrestore(&scc->zlock, flags);
1169}
1170
1171/*
1172 * Setup serial console baud/bits/parity. We do two things here:
1173 * - construct a cflag setting for the first uart_open()
1174 * - initialise the serial port
1175 * Return non-zero if we didn't find a serial port.
1176 */
1177static int __init zs_console_setup(struct console *co, char *options)
1178{
1179 int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
1180 struct zs_port *zport = &zs_sccs[chip].zport[side];
1181 struct uart_port *uport = &zport->port;
1182 int baud = 9600;
1183 int bits = 8;
1184 int parity = 'n';
1185 int flow = 'n';
1186 int ret;
1187
1188 ret = zs_map_port(uport);
1189 if (ret)
1190 return ret;
1191
1192 zs_reset(zport);
1193
1194 if (options)
1195 uart_parse_options(options, &baud, &parity, &bits, &flow);
1196 return uart_set_options(uport, co, baud, parity, bits, flow);
1197}
1198
1199static struct uart_driver zs_reg;
1200static struct console zs_console = {
1201 .name = "ttyS",
1202 .write = zs_console_write,
1203 .device = uart_console_device,
1204 .setup = zs_console_setup,
1205 .flags = CON_PRINTBUFFER,
1206 .index = -1,
1207 .data = &zs_reg,
1208};
1209
1210/*
1211 * Register console.
1212 */
1213static int __init zs_serial_console_init(void)
1214{
1215 int ret;
1216
1217 ret = zs_probe_sccs();
1218 if (ret)
1219 return ret;
1220 register_console(&zs_console);
1221
1222 return 0;
1223}
1224
1225console_initcall(zs_serial_console_init);
1226
1227#define SERIAL_ZS_CONSOLE &zs_console
1228#else
1229#define SERIAL_ZS_CONSOLE NULL
1230#endif /* CONFIG_SERIAL_ZS_CONSOLE */
1231
1232static struct uart_driver zs_reg = {
1233 .owner = THIS_MODULE,
1234 .driver_name = "serial",
1235 .dev_name = "ttyS",
1236 .major = TTY_MAJOR,
1237 .minor = 64,
1238 .nr = ZS_NUM_SCCS * ZS_NUM_CHAN,
1239 .cons = SERIAL_ZS_CONSOLE,
1240};
1241
1242/* zs_init inits the driver. */
1243static int __init zs_init(void)
1244{
1245 int i, ret;
1246
1247 pr_info("%s%s\n", zs_name, zs_version);
1248
1249 /* Find out how many Z85C30 SCCs we have. */
1250 ret = zs_probe_sccs();
1251 if (ret)
1252 return ret;
1253
1254 ret = uart_register_driver(&zs_reg);
1255 if (ret)
1256 return ret;
1257
1258 for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
1259 struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
1260 struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
1261 struct uart_port *uport = &zport->port;
1262
1263 if (zport->scc)
1264 uart_add_one_port(&zs_reg, uport);
1265 }
1266
1267 return 0;
1268}
1269
1270static void __exit zs_exit(void)
1271{
1272 int i;
1273
1274 for (i = ZS_NUM_SCCS * ZS_NUM_CHAN - 1; i >= 0; i--) {
1275 struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
1276 struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
1277 struct uart_port *uport = &zport->port;
1278
1279 if (zport->scc)
1280 uart_remove_one_port(&zs_reg, uport);
1281 }
1282
1283 uart_unregister_driver(&zs_reg);
1284}
1285
1286module_init(zs_init);
1287module_exit(zs_exit);
diff --git a/drivers/serial/zs.h b/drivers/serial/zs.h
new file mode 100644
index 000000000000..aa921b57d827
--- /dev/null
+++ b/drivers/serial/zs.h
@@ -0,0 +1,284 @@
1/*
2 * zs.h: Definitions for the DECstation Z85C30 serial driver.
3 *
4 * Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras.
5 * Adapted from drivers/macintosh/macserial.h by Harald Koerfgen.
6 *
7 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
8 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
9 * Copyright (C) 2004, 2005, 2007 Maciej W. Rozycki
10 */
11#ifndef _SERIAL_ZS_H
12#define _SERIAL_ZS_H
13
14#ifdef __KERNEL__
15
16#define ZS_NUM_REGS 16
17
18/*
19 * This is our internal structure for each serial port's state.
20 */
21struct zs_port {
22 struct zs_scc *scc; /* Containing SCC. */
23 struct uart_port port; /* Underlying UART. */
24
25 int clk_mode; /* May be 1, 16, 32, or 64. */
26
27 unsigned int tty_break; /* Set on BREAK condition. */
28 int tx_stopped; /* Output is suspended. */
29
30 unsigned int mctrl; /* State of modem lines. */
31 u8 brk; /* BREAK state from RR0. */
32
33 u8 regs[ZS_NUM_REGS]; /* Channel write registers. */
34};
35
36/*
37 * Per-SCC state for locking and the interrupt handler.
38 */
39struct zs_scc {
40 struct zs_port zport[2];
41 spinlock_t zlock;
42 atomic_t irq_guard;
43 int initialised;
44};
45
46#endif /* __KERNEL__ */
47
48/*
49 * Conversion routines to/from brg time constants from/to bits per second.
50 */
51#define ZS_BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
52#define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
53
54/*
55 * The Zilog register set.
56 */
57
58/* Write Register 0 (Command) */
59#define R0 0 /* Register selects */
60#define R1 1
61#define R2 2
62#define R3 3
63#define R4 4
64#define R5 5
65#define R6 6
66#define R7 7
67#define R8 8
68#define R9 9
69#define R10 10
70#define R11 11
71#define R12 12
72#define R13 13
73#define R14 14
74#define R15 15
75
76#define NULLCODE 0 /* Null Code */
77#define POINT_HIGH 0x8 /* Select upper half of registers */
78#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
79#define SEND_ABORT 0x18 /* HDLC Abort */
80#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
81#define RES_Tx_P 0x28 /* Reset TxINT Pending */
82#define ERR_RES 0x30 /* Error Reset */
83#define RES_H_IUS 0x38 /* Reset highest IUS */
84
85#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
86#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
87#define RES_EOM_L 0xC0 /* Reset EOM latch */
88
89/* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
90#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
91#define TxINT_ENAB 0x2 /* Tx Int Enable */
92#define PAR_SPEC 0x4 /* Parity is special condition */
93
94#define RxINT_DISAB 0 /* Rx Int Disable */
95#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
96#define RxINT_ALL 0x10 /* Int on all Rx Characters or error */
97#define RxINT_ERR 0x18 /* Int on error only */
98#define RxINT_MASK 0x18
99
100#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
101#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
102#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
103
104/* Write Register 2 (Interrupt Vector) */
105
106/* Write Register 3 (Receive Parameters and Control) */
107#define RxENABLE 0x1 /* Rx Enable */
108#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
109#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
110#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
111#define ENT_HM 0x10 /* Enter Hunt Mode */
112#define AUTO_ENAB 0x20 /* Auto Enables */
113#define Rx5 0x0 /* Rx 5 Bits/Character */
114#define Rx7 0x40 /* Rx 7 Bits/Character */
115#define Rx6 0x80 /* Rx 6 Bits/Character */
116#define Rx8 0xc0 /* Rx 8 Bits/Character */
117#define RxNBITS_MASK 0xc0
118
119/* Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) */
120#define PAR_ENA 0x1 /* Parity Enable */
121#define PAR_EVEN 0x2 /* Parity Even/Odd* */
122
123#define SYNC_ENAB 0 /* Sync Modes Enable */
124#define SB1 0x4 /* 1 stop bit/char */
125#define SB15 0x8 /* 1.5 stop bits/char */
126#define SB2 0xc /* 2 stop bits/char */
127#define SB_MASK 0xc
128
129#define MONSYNC 0 /* 8 Bit Sync character */
130#define BISYNC 0x10 /* 16 bit sync character */
131#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
132#define EXTSYNC 0x30 /* External Sync Mode */
133
134#define X1CLK 0x0 /* x1 clock mode */
135#define X16CLK 0x40 /* x16 clock mode */
136#define X32CLK 0x80 /* x32 clock mode */
137#define X64CLK 0xc0 /* x64 clock mode */
138#define XCLK_MASK 0xc0
139
140/* Write Register 5 (Transmit Parameters and Controls) */
141#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
142#define RTS 0x2 /* RTS */
143#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
144#define TxENAB 0x8 /* Tx Enable */
145#define SND_BRK 0x10 /* Send Break */
146#define Tx5 0x0 /* Tx 5 bits (or less)/character */
147#define Tx7 0x20 /* Tx 7 bits/character */
148#define Tx6 0x40 /* Tx 6 bits/character */
149#define Tx8 0x60 /* Tx 8 bits/character */
150#define TxNBITS_MASK 0x60
151#define DTR 0x80 /* DTR */
152
153/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
154
155/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
156
157/* Write Register 8 (Transmit Buffer) */
158
159/* Write Register 9 (Master Interrupt Control) */
160#define VIS 1 /* Vector Includes Status */
161#define NV 2 /* No Vector */
162#define DLC 4 /* Disable Lower Chain */
163#define MIE 8 /* Master Interrupt Enable */
164#define STATHI 0x10 /* Status high */
165#define SOFTACK 0x20 /* Software Interrupt Acknowledge */
166#define NORESET 0 /* No reset on write to R9 */
167#define CHRB 0x40 /* Reset channel B */
168#define CHRA 0x80 /* Reset channel A */
169#define FHWRES 0xc0 /* Force hardware reset */
170
171/* Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) */
172#define BIT6 1 /* 6 bit/8bit sync */
173#define LOOPMODE 2 /* SDLC Loop mode */
174#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
175#define MARKIDLE 8 /* Mark/flag on idle */
176#define GAOP 0x10 /* Go active on poll */
177#define NRZ 0 /* NRZ mode */
178#define NRZI 0x20 /* NRZI mode */
179#define FM1 0x40 /* FM1 (transition = 1) */
180#define FM0 0x60 /* FM0 (transition = 0) */
181#define CRCPS 0x80 /* CRC Preset I/O */
182
183/* Write Register 11 (Clock Mode Control) */
184#define TRxCXT 0 /* TRxC = Xtal output */
185#define TRxCTC 1 /* TRxC = Transmit clock */
186#define TRxCBR 2 /* TRxC = BR Generator Output */
187#define TRxCDP 3 /* TRxC = DPLL output */
188#define TRxCOI 4 /* TRxC O/I */
189#define TCRTxCP 0 /* Transmit clock = RTxC pin */
190#define TCTRxCP 8 /* Transmit clock = TRxC pin */
191#define TCBR 0x10 /* Transmit clock = BR Generator output */
192#define TCDPLL 0x18 /* Transmit clock = DPLL output */
193#define RCRTxCP 0 /* Receive clock = RTxC pin */
194#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
195#define RCBR 0x40 /* Receive clock = BR Generator output */
196#define RCDPLL 0x60 /* Receive clock = DPLL output */
197#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
198
199/* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */
200
201/* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */
202
203/* Write Register 14 (Miscellaneous Control Bits) */
204#define BRENABL 1 /* Baud rate generator enable */
205#define BRSRC 2 /* Baud rate generator source */
206#define DTRREQ 4 /* DTR/Request function */
207#define AUTOECHO 8 /* Auto Echo */
208#define LOOPBAK 0x10 /* Local loopback */
209#define SEARCH 0x20 /* Enter search mode */
210#define RMC 0x40 /* Reset missing clock */
211#define DISDPLL 0x60 /* Disable DPLL */
212#define SSBR 0x80 /* Set DPLL source = BR generator */
213#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
214#define SFMM 0xc0 /* Set FM mode */
215#define SNRZI 0xe0 /* Set NRZI mode */
216
217/* Write Register 15 (External/Status Interrupt Control) */
218#define WR7P_EN 1 /* WR7 Prime SDLC Feature Enable */
219#define ZCIE 2 /* Zero count IE */
220#define DCDIE 8 /* DCD IE */
221#define SYNCIE 0x10 /* Sync/hunt IE */
222#define CTSIE 0x20 /* CTS IE */
223#define TxUIE 0x40 /* Tx Underrun/EOM IE */
224#define BRKIE 0x80 /* Break/Abort IE */
225
226
227/* Read Register 0 (Transmit/Receive Buffer Status and External Status) */
228#define Rx_CH_AV 0x1 /* Rx Character Available */
229#define ZCOUNT 0x2 /* Zero count */
230#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
231#define DCD 0x8 /* DCD */
232#define SYNC_HUNT 0x10 /* Sync/hunt */
233#define CTS 0x20 /* CTS */
234#define TxEOM 0x40 /* Tx underrun */
235#define BRK_ABRT 0x80 /* Break/Abort */
236
237/* Read Register 1 (Special Receive Condition Status) */
238#define ALL_SNT 0x1 /* All sent */
239/* Residue Data for 8 Rx bits/char programmed */
240#define RES3 0x8 /* 0/3 */
241#define RES4 0x4 /* 0/4 */
242#define RES5 0xc /* 0/5 */
243#define RES6 0x2 /* 0/6 */
244#define RES7 0xa /* 0/7 */
245#define RES8 0x6 /* 0/8 */
246#define RES18 0xe /* 1/8 */
247#define RES28 0x0 /* 2/8 */
248/* Special Rx Condition Interrupts */
249#define PAR_ERR 0x10 /* Parity Error */
250#define Rx_OVR 0x20 /* Rx Overrun Error */
251#define FRM_ERR 0x40 /* CRC/Framing Error */
252#define END_FR 0x80 /* End of Frame (SDLC) */
253
254/* Read Register 2 (Interrupt Vector (WR2) -- channel A). */
255
256/* Read Register 2 (Modified Interrupt Vector -- channel B). */
257
258/* Read Register 3 (Interrupt Pending Bits -- channel A only). */
259#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
260#define CHBTxIP 0x2 /* Channel B Tx IP */
261#define CHBRxIP 0x4 /* Channel B Rx IP */
262#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
263#define CHATxIP 0x10 /* Channel A Tx IP */
264#define CHARxIP 0x20 /* Channel A Rx IP */
265
266/* Read Register 6 (SDLC FIFO Status and Byte Count LSB) */
267
268/* Read Register 7 (SDLC FIFO Status and Byte Count MSB) */
269
270/* Read Register 8 (Receive Data) */
271
272/* Read Register 10 (Miscellaneous Status Bits) */
273#define ONLOOP 2 /* On loop */
274#define LOOPSEND 0x10 /* Loop sending */
275#define CLK2MIS 0x40 /* Two clocks missing */
276#define CLK1MIS 0x80 /* One clock missing */
277
278/* Read Register 12 (Lower Byte of Baud Rate Generator Constant (WR12)) */
279
280/* Read Register 13 (Upper Byte of Baud Rate Generator Constant (WR13) */
281
282/* Read Register 15 (External/Status Interrupt Control (WR15)) */
283
284#endif /* _SERIAL_ZS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 16:30:51 -0500