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-rw-r--r--drivers/serial/8250_pci.c412
-rw-r--r--drivers/serial/8250_pnp.c7
-rw-r--r--drivers/serial/Kconfig53
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/bfin_5xx.c297
-rw-r--r--drivers/serial/cpm_uart/cpm_uart_core.c14
-rw-r--r--drivers/serial/crisv10.c79
-rw-r--r--drivers/serial/crisv10.h2
-rw-r--r--drivers/serial/icom.c14
-rw-r--r--drivers/serial/jsm/jsm_driver.c9
-rw-r--r--drivers/serial/jsm/jsm_neo.c14
-rw-r--r--drivers/serial/jsm/jsm_tty.c23
-rw-r--r--drivers/serial/max3100.c927
-rw-r--r--drivers/serial/pmac_zilog.c15
-rw-r--r--drivers/serial/sunsu.c2
-rw-r--r--drivers/serial/ucc_uart.c1
16 files changed, 1685 insertions, 185 deletions
diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
index 533f82025adf..7ddff3f55087 100644
--- a/drivers/serial/8250_pci.c
+++ b/drivers/serial/8250_pci.c
@@ -306,6 +306,63 @@ static void __devexit pci_plx9050_exit(struct pci_dev *dev)
306 } 306 }
307} 307}
308 308
309#define NI8420_INT_ENABLE_REG 0x38
310#define NI8420_INT_ENABLE_BIT 0x2000
311
312static void __devexit pci_ni8420_exit(struct pci_dev *dev)
313{
314 void __iomem *p;
315 unsigned long base, len;
316 unsigned int bar = 0;
317
318 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
319 moan_device("no memory in bar", dev);
320 return;
321 }
322
323 base = pci_resource_start(dev, bar);
324 len = pci_resource_len(dev, bar);
325 p = ioremap_nocache(base, len);
326 if (p == NULL)
327 return;
328
329 /* Disable the CPU Interrupt */
330 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
331 p + NI8420_INT_ENABLE_REG);
332 iounmap(p);
333}
334
335
336/* MITE registers */
337#define MITE_IOWBSR1 0xc4
338#define MITE_IOWCR1 0xf4
339#define MITE_LCIMR1 0x08
340#define MITE_LCIMR2 0x10
341
342#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
343
344static void __devexit pci_ni8430_exit(struct pci_dev *dev)
345{
346 void __iomem *p;
347 unsigned long base, len;
348 unsigned int bar = 0;
349
350 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
351 moan_device("no memory in bar", dev);
352 return;
353 }
354
355 base = pci_resource_start(dev, bar);
356 len = pci_resource_len(dev, bar);
357 p = ioremap_nocache(base, len);
358 if (p == NULL)
359 return;
360
361 /* Disable the CPU Interrupt */
362 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
363 iounmap(p);
364}
365
309/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 366/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
310static int 367static int
311sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 368sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
@@ -597,6 +654,108 @@ static int pci_xircom_init(struct pci_dev *dev)
597 return 0; 654 return 0;
598} 655}
599 656
657static int pci_ni8420_init(struct pci_dev *dev)
658{
659 void __iomem *p;
660 unsigned long base, len;
661 unsigned int bar = 0;
662
663 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
664 moan_device("no memory in bar", dev);
665 return 0;
666 }
667
668 base = pci_resource_start(dev, bar);
669 len = pci_resource_len(dev, bar);
670 p = ioremap_nocache(base, len);
671 if (p == NULL)
672 return -ENOMEM;
673
674 /* Enable CPU Interrupt */
675 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
676 p + NI8420_INT_ENABLE_REG);
677
678 iounmap(p);
679 return 0;
680}
681
682#define MITE_IOWBSR1_WSIZE 0xa
683#define MITE_IOWBSR1_WIN_OFFSET 0x800
684#define MITE_IOWBSR1_WENAB (1 << 7)
685#define MITE_LCIMR1_IO_IE_0 (1 << 24)
686#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
687#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
688
689static int pci_ni8430_init(struct pci_dev *dev)
690{
691 void __iomem *p;
692 unsigned long base, len;
693 u32 device_window;
694 unsigned int bar = 0;
695
696 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
697 moan_device("no memory in bar", dev);
698 return 0;
699 }
700
701 base = pci_resource_start(dev, bar);
702 len = pci_resource_len(dev, bar);
703 p = ioremap_nocache(base, len);
704 if (p == NULL)
705 return -ENOMEM;
706
707 /* Set device window address and size in BAR0 */
708 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
709 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
710 writel(device_window, p + MITE_IOWBSR1);
711
712 /* Set window access to go to RAMSEL IO address space */
713 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
714 p + MITE_IOWCR1);
715
716 /* Enable IO Bus Interrupt 0 */
717 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
718
719 /* Enable CPU Interrupt */
720 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
721
722 iounmap(p);
723 return 0;
724}
725
726/* UART Port Control Register */
727#define NI8430_PORTCON 0x0f
728#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
729
730static int
731pci_ni8430_setup(struct serial_private *priv,
732 const struct pciserial_board *board,
733 struct uart_port *port, int idx)
734{
735 void __iomem *p;
736 unsigned long base, len;
737 unsigned int bar, offset = board->first_offset;
738
739 if (idx >= board->num_ports)
740 return 1;
741
742 bar = FL_GET_BASE(board->flags);
743 offset += idx * board->uart_offset;
744
745 base = pci_resource_start(priv->dev, bar);
746 len = pci_resource_len(priv->dev, bar);
747 p = ioremap_nocache(base, len);
748
749 /* enable the transciever */
750 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
751 p + offset + NI8430_PORTCON);
752
753 iounmap(p);
754
755 return setup_port(priv, port, bar, offset, board->reg_shift);
756}
757
758
600static int pci_netmos_init(struct pci_dev *dev) 759static int pci_netmos_init(struct pci_dev *dev)
601{ 760{
602 /* subdevice 0x00PS means <P> parallel, <S> serial */ 761 /* subdevice 0x00PS means <P> parallel, <S> serial */
@@ -913,6 +1072,126 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
913 .exit = __devexit_p(pci_ite887x_exit), 1072 .exit = __devexit_p(pci_ite887x_exit),
914 }, 1073 },
915 /* 1074 /*
1075 * National Instruments
1076 */
1077 {
1078 .vendor = PCI_VENDOR_ID_NI,
1079 .device = PCI_DEVICE_ID_NI_PCI23216,
1080 .subvendor = PCI_ANY_ID,
1081 .subdevice = PCI_ANY_ID,
1082 .init = pci_ni8420_init,
1083 .setup = pci_default_setup,
1084 .exit = __devexit_p(pci_ni8420_exit),
1085 },
1086 {
1087 .vendor = PCI_VENDOR_ID_NI,
1088 .device = PCI_DEVICE_ID_NI_PCI2328,
1089 .subvendor = PCI_ANY_ID,
1090 .subdevice = PCI_ANY_ID,
1091 .init = pci_ni8420_init,
1092 .setup = pci_default_setup,
1093 .exit = __devexit_p(pci_ni8420_exit),
1094 },
1095 {
1096 .vendor = PCI_VENDOR_ID_NI,
1097 .device = PCI_DEVICE_ID_NI_PCI2324,
1098 .subvendor = PCI_ANY_ID,
1099 .subdevice = PCI_ANY_ID,
1100 .init = pci_ni8420_init,
1101 .setup = pci_default_setup,
1102 .exit = __devexit_p(pci_ni8420_exit),
1103 },
1104 {
1105 .vendor = PCI_VENDOR_ID_NI,
1106 .device = PCI_DEVICE_ID_NI_PCI2322,
1107 .subvendor = PCI_ANY_ID,
1108 .subdevice = PCI_ANY_ID,
1109 .init = pci_ni8420_init,
1110 .setup = pci_default_setup,
1111 .exit = __devexit_p(pci_ni8420_exit),
1112 },
1113 {
1114 .vendor = PCI_VENDOR_ID_NI,
1115 .device = PCI_DEVICE_ID_NI_PCI2324I,
1116 .subvendor = PCI_ANY_ID,
1117 .subdevice = PCI_ANY_ID,
1118 .init = pci_ni8420_init,
1119 .setup = pci_default_setup,
1120 .exit = __devexit_p(pci_ni8420_exit),
1121 },
1122 {
1123 .vendor = PCI_VENDOR_ID_NI,
1124 .device = PCI_DEVICE_ID_NI_PCI2322I,
1125 .subvendor = PCI_ANY_ID,
1126 .subdevice = PCI_ANY_ID,
1127 .init = pci_ni8420_init,
1128 .setup = pci_default_setup,
1129 .exit = __devexit_p(pci_ni8420_exit),
1130 },
1131 {
1132 .vendor = PCI_VENDOR_ID_NI,
1133 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1134 .subvendor = PCI_ANY_ID,
1135 .subdevice = PCI_ANY_ID,
1136 .init = pci_ni8420_init,
1137 .setup = pci_default_setup,
1138 .exit = __devexit_p(pci_ni8420_exit),
1139 },
1140 {
1141 .vendor = PCI_VENDOR_ID_NI,
1142 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1143 .subvendor = PCI_ANY_ID,
1144 .subdevice = PCI_ANY_ID,
1145 .init = pci_ni8420_init,
1146 .setup = pci_default_setup,
1147 .exit = __devexit_p(pci_ni8420_exit),
1148 },
1149 {
1150 .vendor = PCI_VENDOR_ID_NI,
1151 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1152 .subvendor = PCI_ANY_ID,
1153 .subdevice = PCI_ANY_ID,
1154 .init = pci_ni8420_init,
1155 .setup = pci_default_setup,
1156 .exit = __devexit_p(pci_ni8420_exit),
1157 },
1158 {
1159 .vendor = PCI_VENDOR_ID_NI,
1160 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1161 .subvendor = PCI_ANY_ID,
1162 .subdevice = PCI_ANY_ID,
1163 .init = pci_ni8420_init,
1164 .setup = pci_default_setup,
1165 .exit = __devexit_p(pci_ni8420_exit),
1166 },
1167 {
1168 .vendor = PCI_VENDOR_ID_NI,
1169 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1170 .subvendor = PCI_ANY_ID,
1171 .subdevice = PCI_ANY_ID,
1172 .init = pci_ni8420_init,
1173 .setup = pci_default_setup,
1174 .exit = __devexit_p(pci_ni8420_exit),
1175 },
1176 {
1177 .vendor = PCI_VENDOR_ID_NI,
1178 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1179 .subvendor = PCI_ANY_ID,
1180 .subdevice = PCI_ANY_ID,
1181 .init = pci_ni8420_init,
1182 .setup = pci_default_setup,
1183 .exit = __devexit_p(pci_ni8420_exit),
1184 },
1185 {
1186 .vendor = PCI_VENDOR_ID_NI,
1187 .device = PCI_ANY_ID,
1188 .subvendor = PCI_ANY_ID,
1189 .subdevice = PCI_ANY_ID,
1190 .init = pci_ni8430_init,
1191 .setup = pci_ni8430_setup,
1192 .exit = __devexit_p(pci_ni8430_exit),
1193 },
1194 /*
916 * Panacom 1195 * Panacom
917 */ 1196 */
918 { 1197 {
@@ -1216,6 +1495,7 @@ enum pci_board_num_t {
1216 pbn_b1_2_115200, 1495 pbn_b1_2_115200,
1217 pbn_b1_4_115200, 1496 pbn_b1_4_115200,
1218 pbn_b1_8_115200, 1497 pbn_b1_8_115200,
1498 pbn_b1_16_115200,
1219 1499
1220 pbn_b1_1_921600, 1500 pbn_b1_1_921600,
1221 pbn_b1_2_921600, 1501 pbn_b1_2_921600,
@@ -1225,6 +1505,9 @@ enum pci_board_num_t {
1225 pbn_b1_2_1250000, 1505 pbn_b1_2_1250000,
1226 1506
1227 pbn_b1_bt_1_115200, 1507 pbn_b1_bt_1_115200,
1508 pbn_b1_bt_2_115200,
1509 pbn_b1_bt_4_115200,
1510
1228 pbn_b1_bt_2_921600, 1511 pbn_b1_bt_2_921600,
1229 1512
1230 pbn_b1_1_1382400, 1513 pbn_b1_1_1382400,
@@ -1280,6 +1563,10 @@ enum pci_board_num_t {
1280 pbn_exar_XR17C154, 1563 pbn_exar_XR17C154,
1281 pbn_exar_XR17C158, 1564 pbn_exar_XR17C158,
1282 pbn_pasemi_1682M, 1565 pbn_pasemi_1682M,
1566 pbn_ni8430_2,
1567 pbn_ni8430_4,
1568 pbn_ni8430_8,
1569 pbn_ni8430_16,
1283}; 1570};
1284 1571
1285/* 1572/*
@@ -1487,6 +1774,12 @@ static struct pciserial_board pci_boards[] __devinitdata = {
1487 .base_baud = 115200, 1774 .base_baud = 115200,
1488 .uart_offset = 8, 1775 .uart_offset = 8,
1489 }, 1776 },
1777 [pbn_b1_16_115200] = {
1778 .flags = FL_BASE1,
1779 .num_ports = 16,
1780 .base_baud = 115200,
1781 .uart_offset = 8,
1782 },
1490 1783
1491 [pbn_b1_1_921600] = { 1784 [pbn_b1_1_921600] = {
1492 .flags = FL_BASE1, 1785 .flags = FL_BASE1,
@@ -1525,6 +1818,18 @@ static struct pciserial_board pci_boards[] __devinitdata = {
1525 .base_baud = 115200, 1818 .base_baud = 115200,
1526 .uart_offset = 8, 1819 .uart_offset = 8,
1527 }, 1820 },
1821 [pbn_b1_bt_2_115200] = {
1822 .flags = FL_BASE1|FL_BASE_BARS,
1823 .num_ports = 2,
1824 .base_baud = 115200,
1825 .uart_offset = 8,
1826 },
1827 [pbn_b1_bt_4_115200] = {
1828 .flags = FL_BASE1|FL_BASE_BARS,
1829 .num_ports = 4,
1830 .base_baud = 115200,
1831 .uart_offset = 8,
1832 },
1528 1833
1529 [pbn_b1_bt_2_921600] = { 1834 [pbn_b1_bt_2_921600] = {
1530 .flags = FL_BASE1|FL_BASE_BARS, 1835 .flags = FL_BASE1|FL_BASE_BARS,
@@ -1850,6 +2155,37 @@ static struct pciserial_board pci_boards[] __devinitdata = {
1850 .num_ports = 1, 2155 .num_ports = 1,
1851 .base_baud = 8333333, 2156 .base_baud = 8333333,
1852 }, 2157 },
2158 /*
2159 * National Instruments 843x
2160 */
2161 [pbn_ni8430_16] = {
2162 .flags = FL_BASE0,
2163 .num_ports = 16,
2164 .base_baud = 3686400,
2165 .uart_offset = 0x10,
2166 .first_offset = 0x800,
2167 },
2168 [pbn_ni8430_8] = {
2169 .flags = FL_BASE0,
2170 .num_ports = 8,
2171 .base_baud = 3686400,
2172 .uart_offset = 0x10,
2173 .first_offset = 0x800,
2174 },
2175 [pbn_ni8430_4] = {
2176 .flags = FL_BASE0,
2177 .num_ports = 4,
2178 .base_baud = 3686400,
2179 .uart_offset = 0x10,
2180 .first_offset = 0x800,
2181 },
2182 [pbn_ni8430_2] = {
2183 .flags = FL_BASE0,
2184 .num_ports = 2,
2185 .base_baud = 3686400,
2186 .uart_offset = 0x10,
2187 .first_offset = 0x800,
2188 },
1853}; 2189};
1854 2190
1855static const struct pci_device_id softmodem_blacklist[] = { 2191static const struct pci_device_id softmodem_blacklist[] = {
@@ -3052,6 +3388,82 @@ static struct pci_device_id serial_pci_tbl[] = {
3052 pbn_pasemi_1682M }, 3388 pbn_pasemi_1682M },
3053 3389
3054 /* 3390 /*
3391 * National Instruments
3392 */
3393 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3395 pbn_b1_16_115200 },
3396 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3398 pbn_b1_8_115200 },
3399 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3401 pbn_b1_bt_4_115200 },
3402 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3404 pbn_b1_bt_2_115200 },
3405 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3407 pbn_b1_bt_4_115200 },
3408 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3410 pbn_b1_bt_2_115200 },
3411 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3413 pbn_b1_16_115200 },
3414 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3416 pbn_b1_8_115200 },
3417 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3419 pbn_b1_bt_4_115200 },
3420 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3422 pbn_b1_bt_2_115200 },
3423 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3425 pbn_b1_bt_4_115200 },
3426 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3428 pbn_b1_bt_2_115200 },
3429 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3431 pbn_ni8430_2 },
3432 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3434 pbn_ni8430_2 },
3435 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3437 pbn_ni8430_4 },
3438 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3440 pbn_ni8430_4 },
3441 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3443 pbn_ni8430_8 },
3444 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3446 pbn_ni8430_8 },
3447 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3449 pbn_ni8430_16 },
3450 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3452 pbn_ni8430_16 },
3453 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3455 pbn_ni8430_2 },
3456 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3458 pbn_ni8430_2 },
3459 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3461 pbn_ni8430_4 },
3462 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3464 pbn_ni8430_4 },
3465
3466 /*
3055 * ADDI-DATA GmbH communication cards <info@addi-data.com> 3467 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3056 */ 3468 */
3057 { PCI_VENDOR_ID_ADDIDATA, 3469 { PCI_VENDOR_ID_ADDIDATA,
diff --git a/drivers/serial/8250_pnp.c b/drivers/serial/8250_pnp.c
index bbcfc26a3b6d..d71dfe398940 100644
--- a/drivers/serial/8250_pnp.c
+++ b/drivers/serial/8250_pnp.c
@@ -333,6 +333,10 @@ static const struct pnp_device_id pnp_dev_table[] = {
333 { "WACF006", 0 }, 333 { "WACF006", 0 },
334 { "WACF007", 0 }, 334 { "WACF007", 0 },
335 { "WACF008", 0 }, 335 { "WACF008", 0 },
336 { "WACF009", 0 },
337 { "WACF00A", 0 },
338 { "WACF00B", 0 },
339 { "WACF00C", 0 },
336 /* Compaq touchscreen */ 340 /* Compaq touchscreen */
337 { "FPI2002", 0 }, 341 { "FPI2002", 0 },
338 /* Fujitsu Stylistic touchscreens */ 342 /* Fujitsu Stylistic touchscreens */
@@ -346,8 +350,9 @@ static const struct pnp_device_id pnp_dev_table[] = {
346 { "FUJ02B8", 0 }, 350 { "FUJ02B8", 0 },
347 { "FUJ02B9", 0 }, 351 { "FUJ02B9", 0 },
348 { "FUJ02BC", 0 }, 352 { "FUJ02BC", 0 },
349 /* Fujitsu Wacom Tablet PC devices */ 353 /* Fujitsu Wacom Tablet PC device */
350 { "FUJ02E5", 0 }, 354 { "FUJ02E5", 0 },
355 /* Fujitsu P-series tablet PC device */
351 { "FUJ02E6", 0 }, 356 { "FUJ02E6", 0 },
352 /* 357 /*
353 * LG C1 EXPRESS DUAL (C1-PB11A3) touch screen (actually a FUJ02E6 in 358 * LG C1 EXPRESS DUAL (C1-PB11A3) touch screen (actually a FUJ02E6 in
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index aa9d3a4c2d50..343e3a35b6a3 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -533,6 +533,13 @@ config SERIAL_S3C6400
533 Serial port support for the Samsung S3C6400 and S3C6410 533 Serial port support for the Samsung S3C6400 and S3C6410
534 SoCs 534 SoCs
535 535
536config SERIAL_MAX3100
537 tristate "MAX3100 support"
538 depends on SPI
539 select SERIAL_CORE
540 help
541 MAX3100 chip support
542
536config SERIAL_DZ 543config SERIAL_DZ
537 bool "DECstation DZ serial driver" 544 bool "DECstation DZ serial driver"
538 depends on MACH_DECSTATION && 32BIT 545 depends on MACH_DECSTATION && 32BIT
@@ -700,7 +707,7 @@ choice
700 707
701config SERIAL_BFIN_DMA 708config SERIAL_BFIN_DMA
702 bool "DMA mode" 709 bool "DMA mode"
703 depends on !DMA_UNCACHED_NONE && !KGDB_UART 710 depends on !DMA_UNCACHED_NONE && KGDB_SERIAL_CONSOLE=n
704 help 711 help
705 This driver works under DMA mode. If this option is selected, the 712 This driver works under DMA mode. If this option is selected, the
706 blackfin simple dma driver is also enabled. 713 blackfin simple dma driver is also enabled.
@@ -727,19 +734,19 @@ config BFIN_UART0_CTSRTS
727 734
728config UART0_CTS_PIN 735config UART0_CTS_PIN
729 int "UART0 CTS pin" 736 int "UART0 CTS pin"
730 depends on BFIN_UART0_CTSRTS 737 depends on BFIN_UART0_CTSRTS && !BF548
731 default 23 738 default 23
732 help 739 help
733 The default pin is GPIO_GP7. 740 The default pin is GPIO_GP7.
734 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. 741 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
735 742
736config UART0_RTS_PIN 743config UART0_RTS_PIN
737 int "UART0 RTS pin" 744 int "UART0 RTS pin"
738 depends on BFIN_UART0_CTSRTS 745 depends on BFIN_UART0_CTSRTS && !BF548
739 default 22 746 default 22
740 help 747 help
741 The default pin is GPIO_GP6. 748 The default pin is GPIO_GP6.
742 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. 749 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
743 750
744config SERIAL_BFIN_UART1 751config SERIAL_BFIN_UART1
745 bool "Enable UART1" 752 bool "Enable UART1"
@@ -756,21 +763,21 @@ config BFIN_UART1_CTSRTS
756 763
757config UART1_CTS_PIN 764config UART1_CTS_PIN
758 int "UART1 CTS pin" 765 int "UART1 CTS pin"
759 depends on BFIN_UART1_CTSRTS && !BF54x 766 depends on BFIN_UART1_CTSRTS && !BF548
760 default -1 767 default -1
761 help 768 help
762 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. 769 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
763 770
764config UART1_RTS_PIN 771config UART1_RTS_PIN
765 int "UART1 RTS pin" 772 int "UART1 RTS pin"
766 depends on BFIN_UART1_CTSRTS && !BF54x 773 depends on BFIN_UART1_CTSRTS && !BF548
767 default -1 774 default -1
768 help 775 help
769 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. 776 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
770 777
771config SERIAL_BFIN_UART2 778config SERIAL_BFIN_UART2
772 bool "Enable UART2" 779 bool "Enable UART2"
773 depends on SERIAL_BFIN && (BF54x) 780 depends on SERIAL_BFIN && (BF54x || BF538 || BF539)
774 help 781 help
775 Enable UART2 782 Enable UART2
776 783
@@ -783,17 +790,17 @@ config BFIN_UART2_CTSRTS
783 790
784config UART2_CTS_PIN 791config UART2_CTS_PIN
785 int "UART2 CTS pin" 792 int "UART2 CTS pin"
786 depends on BFIN_UART2_CTSRTS 793 depends on BFIN_UART2_CTSRTS && !BF548
787 default -1 794 default -1
788 help 795 help
789 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. 796 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
790 797
791config UART2_RTS_PIN 798config UART2_RTS_PIN
792 int "UART2 RTS pin" 799 int "UART2 RTS pin"
793 depends on BFIN_UART2_CTSRTS 800 depends on BFIN_UART2_CTSRTS && !BF548
794 default -1 801 default -1
795 help 802 help
796 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. 803 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
797 804
798config SERIAL_BFIN_UART3 805config SERIAL_BFIN_UART3
799 bool "Enable UART3" 806 bool "Enable UART3"
@@ -808,6 +815,20 @@ config BFIN_UART3_CTSRTS
808 Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS 815 Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
809 signal. 816 signal.
810 817
818config UART3_CTS_PIN
819 int "UART3 CTS pin"
820 depends on BFIN_UART3_CTSRTS && !BF548
821 default -1
822 help
823 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
824
825config UART3_RTS_PIN
826 int "UART3 RTS pin"
827 depends on BFIN_UART3_CTSRTS && !BF548
828 default -1
829 help
830 Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
831
811config SERIAL_IMX 832config SERIAL_IMX
812 bool "IMX serial port support" 833 bool "IMX serial port support"
813 depends on ARM && (ARCH_IMX || ARCH_MXC) 834 depends on ARM && (ARCH_IMX || ARCH_MXC)
@@ -833,7 +854,7 @@ config SERIAL_IMX_CONSOLE
833 854
834config SERIAL_UARTLITE 855config SERIAL_UARTLITE
835 tristate "Xilinx uartlite serial port support" 856 tristate "Xilinx uartlite serial port support"
836 depends on PPC32 857 depends on PPC32 || MICROBLAZE
837 select SERIAL_CORE 858 select SERIAL_CORE
838 help 859 help
839 Say Y here if you want to use the Xilinx uartlite serial controller. 860 Say Y here if you want to use the Xilinx uartlite serial controller.
@@ -1319,7 +1340,7 @@ config SERIAL_NETX_CONSOLE
1319 1340
1320config SERIAL_OF_PLATFORM 1341config SERIAL_OF_PLATFORM
1321 tristate "Serial port on Open Firmware platform bus" 1342 tristate "Serial port on Open Firmware platform bus"
1322 depends on PPC_OF 1343 depends on PPC_OF || MICROBLAZE
1323 depends on SERIAL_8250 || SERIAL_OF_PLATFORM_NWPSERIAL 1344 depends on SERIAL_8250 || SERIAL_OF_PLATFORM_NWPSERIAL
1324 help 1345 help
1325 If you have a PowerPC based system that has serial ports 1346 If you have a PowerPC based system that has serial ports
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 8844c0a03929..d438eb2a73de 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o
43obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o 43obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
44obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o 44obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
45obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o 45obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
46obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
46obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o 47obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
47obj-$(CONFIG_SERIAL_MUX) += mux.o 48obj-$(CONFIG_SERIAL_MUX) += mux.o
48obj-$(CONFIG_SERIAL_68328) += 68328serial.o 49obj-$(CONFIG_SERIAL_68328) += 68328serial.o
diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c
index 318d69dce8e1..18ba812a4f84 100644
--- a/drivers/serial/bfin_5xx.c
+++ b/drivers/serial/bfin_5xx.c
@@ -63,7 +63,6 @@ static int kgdboc_break_enabled;
63#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) 63#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
64 64
65#define DMA_RX_FLUSH_JIFFIES (HZ / 50) 65#define DMA_RX_FLUSH_JIFFIES (HZ / 50)
66#define CTS_CHECK_JIFFIES (HZ / 50)
67 66
68#ifdef CONFIG_SERIAL_BFIN_DMA 67#ifdef CONFIG_SERIAL_BFIN_DMA
69static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); 68static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
@@ -71,10 +70,65 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
71static void bfin_serial_tx_chars(struct bfin_serial_port *uart); 70static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
72#endif 71#endif
73 72
74static void bfin_serial_mctrl_check(struct bfin_serial_port *uart);
75
76static void bfin_serial_reset_irda(struct uart_port *port); 73static void bfin_serial_reset_irda(struct uart_port *port);
77 74
75#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
76 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
77static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
78{
79 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
80 if (uart->cts_pin < 0)
81 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
82
83 /* CTS PIN is negative assertive. */
84 if (UART_GET_CTS(uart))
85 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
86 else
87 return TIOCM_DSR | TIOCM_CAR;
88}
89
90static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
91{
92 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
93 if (uart->rts_pin < 0)
94 return;
95
96 /* RTS PIN is negative assertive. */
97 if (mctrl & TIOCM_RTS)
98 UART_ENABLE_RTS(uart);
99 else
100 UART_DISABLE_RTS(uart);
101}
102
103/*
104 * Handle any change of modem status signal.
105 */
106static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
107{
108 struct bfin_serial_port *uart = dev_id;
109 unsigned int status;
110
111 status = bfin_serial_get_mctrl(&uart->port);
112 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
113#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
114 uart->scts = 1;
115 UART_CLEAR_SCTS(uart);
116 UART_CLEAR_IER(uart, EDSSI);
117#endif
118
119 return IRQ_HANDLED;
120}
121#else
122static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
123{
124 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
125}
126
127static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
128{
129}
130#endif
131
78/* 132/*
79 * interrupts are disabled on entry 133 * interrupts are disabled on entry
80 */ 134 */
@@ -111,6 +165,13 @@ static void bfin_serial_start_tx(struct uart_port *port)
111 struct bfin_serial_port *uart = (struct bfin_serial_port *)port; 165 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
112 struct tty_struct *tty = uart->port.info->port.tty; 166 struct tty_struct *tty = uart->port.info->port.tty;
113 167
168#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
169 if (uart->scts && (!bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
170 uart->scts = 0;
171 uart_handle_cts_change(&uart->port, uart->scts);
172 }
173#endif
174
114 /* 175 /*
115 * To avoid losting RX interrupt, we reset IR function 176 * To avoid losting RX interrupt, we reset IR function
116 * before sending data. 177 * before sending data.
@@ -174,10 +235,10 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
174 return; 235 return;
175 } 236 }
176 237
177 if (!uart->port.info || !uart->port.info->tty) 238 if (!uart->port.info || !uart->port.info->port.tty)
178 return; 239 return;
179#endif 240#endif
180 tty = uart->port.info->tty; 241 tty = uart->port.info->port.tty;
181 242
182 if (ANOMALY_05000363) { 243 if (ANOMALY_05000363) {
183 /* The BF533 (and BF561) family of processors have a nice anomaly 244 /* The BF533 (and BF561) family of processors have a nice anomaly
@@ -264,12 +325,6 @@ static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
264{ 325{
265 struct circ_buf *xmit = &uart->port.info->xmit; 326 struct circ_buf *xmit = &uart->port.info->xmit;
266 327
267 /*
268 * Check the modem control lines before
269 * transmitting anything.
270 */
271 bfin_serial_mctrl_check(uart);
272
273 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { 328 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
274#ifdef CONFIG_BF54x 329#ifdef CONFIG_BF54x
275 /* Clear TFI bit */ 330 /* Clear TFI bit */
@@ -312,6 +367,12 @@ static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
312{ 367{
313 struct bfin_serial_port *uart = dev_id; 368 struct bfin_serial_port *uart = dev_id;
314 369
370#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
371 if (uart->scts && (!bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
372 uart->scts = 0;
373 uart_handle_cts_change(&uart->port, uart->scts);
374 }
375#endif
315 spin_lock(&uart->port.lock); 376 spin_lock(&uart->port.lock);
316 if (UART_GET_LSR(uart) & THRE) 377 if (UART_GET_LSR(uart) & THRE)
317 bfin_serial_tx_chars(uart); 378 bfin_serial_tx_chars(uart);
@@ -328,12 +389,6 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
328 389
329 uart->tx_done = 0; 390 uart->tx_done = 0;
330 391
331 /*
332 * Check the modem control lines before
333 * transmitting anything.
334 */
335 bfin_serial_mctrl_check(uart);
336
337 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { 392 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
338 uart->tx_count = 0; 393 uart->tx_count = 0;
339 uart->tx_done = 1; 394 uart->tx_done = 1;
@@ -401,9 +456,11 @@ static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
401 else 456 else
402 flg = TTY_NORMAL; 457 flg = TTY_NORMAL;
403 458
404 for (i = uart->rx_dma_buf.tail; i != uart->rx_dma_buf.head; i++) { 459 for (i = uart->rx_dma_buf.tail; ; i++) {
405 if (i >= UART_XMIT_SIZE) 460 if (i >= UART_XMIT_SIZE)
406 i = 0; 461 i = 0;
462 if (i == uart->rx_dma_buf.head)
463 break;
407 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i])) 464 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
408 uart_insert_char(&uart->port, status, OE, 465 uart_insert_char(&uart->port, status, OE,
409 uart->rx_dma_buf.buf[i], flg); 466 uart->rx_dma_buf.buf[i], flg);
@@ -415,7 +472,8 @@ static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
415 472
416void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) 473void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
417{ 474{
418 int x_pos, pos, flags; 475 int x_pos, pos;
476 unsigned long flags;
419 477
420 spin_lock_irqsave(&uart->port.lock, flags); 478 spin_lock_irqsave(&uart->port.lock, flags);
421 479
@@ -445,6 +503,13 @@ static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
445 struct bfin_serial_port *uart = dev_id; 503 struct bfin_serial_port *uart = dev_id;
446 struct circ_buf *xmit = &uart->port.info->xmit; 504 struct circ_buf *xmit = &uart->port.info->xmit;
447 505
506#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
507 if (uart->scts && (!bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
508 uart->scts = 0;
509 uart_handle_cts_change(&uart->port, uart->scts);
510 }
511#endif
512
448 spin_lock(&uart->port.lock); 513 spin_lock(&uart->port.lock);
449 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { 514 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
450 disable_dma(uart->tx_dma_channel); 515 disable_dma(uart->tx_dma_channel);
@@ -493,61 +558,6 @@ static unsigned int bfin_serial_tx_empty(struct uart_port *port)
493 return 0; 558 return 0;
494} 559}
495 560
496static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
497{
498#ifdef CONFIG_SERIAL_BFIN_CTSRTS
499 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
500 if (uart->cts_pin < 0)
501 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
502
503 if (UART_GET_CTS(uart))
504 return TIOCM_DSR | TIOCM_CAR;
505 else
506#endif
507 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
508}
509
510static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
511{
512#ifdef CONFIG_SERIAL_BFIN_CTSRTS
513 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
514 if (uart->rts_pin < 0)
515 return;
516
517 if (mctrl & TIOCM_RTS)
518 UART_CLEAR_RTS(uart);
519 else
520 UART_SET_RTS(uart);
521#endif
522}
523
524/*
525 * Handle any change of modem status signal since we were last called.
526 */
527static void bfin_serial_mctrl_check(struct bfin_serial_port *uart)
528{
529#ifdef CONFIG_SERIAL_BFIN_CTSRTS
530 unsigned int status;
531 struct uart_info *info = uart->port.info;
532 struct tty_struct *tty = info->port.tty;
533
534 status = bfin_serial_get_mctrl(&uart->port);
535 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
536 if (!(status & TIOCM_CTS)) {
537 tty->hw_stopped = 1;
538 uart->cts_timer.data = (unsigned long)(uart);
539 uart->cts_timer.function = (void *)bfin_serial_mctrl_check;
540 uart->cts_timer.expires = jiffies + CTS_CHECK_JIFFIES;
541 add_timer(&(uart->cts_timer));
542 } else {
543 tty->hw_stopped = 0;
544 }
545#endif
546}
547
548/*
549 * Interrupts are always disabled.
550 */
551static void bfin_serial_break_ctl(struct uart_port *port, int break_state) 561static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
552{ 562{
553 struct bfin_serial_port *uart = (struct bfin_serial_port *)port; 563 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
@@ -603,7 +613,7 @@ static int bfin_serial_startup(struct uart_port *port)
603 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; 613 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
604 add_timer(&(uart->rx_dma_timer)); 614 add_timer(&(uart->rx_dma_timer));
605#else 615#else
606#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ 616# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
607 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) 617 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
608 if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled) 618 if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
609 kgdboc_break_enabled = 0; 619 kgdboc_break_enabled = 0;
@@ -658,11 +668,50 @@ static int bfin_serial_startup(struct uart_port *port)
658 } 668 }
659 } 669 }
660# endif 670# endif
661#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ 671# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
662 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) 672 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
663 } 673 }
664# endif 674# endif
665#endif 675#endif
676
677#ifdef CONFIG_SERIAL_BFIN_CTSRTS
678 if (uart->cts_pin >= 0) {
679 if (request_irq(gpio_to_irq(uart->cts_pin),
680 bfin_serial_mctrl_cts_int,
681 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
682 IRQF_DISABLED, "BFIN_UART_CTS", uart)) {
683 uart->cts_pin = -1;
684 pr_info("Unable to attach BlackFin UART CTS interrupt.\
685 So, disable it.\n");
686 }
687 }
688 if (uart->rts_pin >= 0) {
689 gpio_request(uart->rts_pin, DRIVER_NAME);
690 gpio_direction_output(uart->rts_pin, 0);
691 }
692#endif
693#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
694 if (request_irq(uart->status_irq,
695 bfin_serial_mctrl_cts_int,
696 IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) {
697 pr_info("Unable to attach BlackFin UART Modem \
698 Status interrupt.\n");
699 }
700
701 if (uart->cts_pin >= 0) {
702 gpio_request(uart->cts_pin, DRIVER_NAME);
703 gpio_direction_output(uart->cts_pin, 1);
704 }
705 if (uart->rts_pin >= 0) {
706 gpio_request(uart->rts_pin, DRIVER_NAME);
707 gpio_direction_output(uart->rts_pin, 0);
708 }
709
710 /* CTS RTS PINs are negative assertive. */
711 UART_PUT_MCR(uart, ACTS);
712 UART_SET_IER(uart, EDSSI);
713#endif
714
666 UART_SET_IER(uart, ERBFI); 715 UART_SET_IER(uart, ERBFI);
667 return 0; 716 return 0;
668} 717}
@@ -696,6 +745,21 @@ static void bfin_serial_shutdown(struct uart_port *port)
696 free_irq(uart->port.irq, uart); 745 free_irq(uart->port.irq, uart);
697 free_irq(uart->port.irq+1, uart); 746 free_irq(uart->port.irq+1, uart);
698#endif 747#endif
748
749#ifdef CONFIG_SERIAL_BFIN_CTSRTS
750 if (uart->cts_pin >= 0)
751 free_irq(gpio_to_irq(uart->cts_pin), uart);
752 if (uart->rts_pin >= 0)
753 gpio_free(uart->rts_pin);
754#endif
755#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
756 if (uart->cts_pin >= 0)
757 gpio_free(uart->cts_pin);
758 if (uart->rts_pin >= 0)
759 gpio_free(uart->rts_pin);
760 if (UART_GET_IER(uart) && EDSSI)
761 free_irq(uart->status_irq, uart);
762#endif
699} 763}
700 764
701static void 765static void
@@ -757,7 +821,7 @@ bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
757 } 821 }
758 822
759 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 823 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
760 quot = uart_get_divisor(port, baud); 824 quot = uart_get_divisor(port, baud) - ANOMALY_05000230;
761 spin_lock_irqsave(&uart->port.lock, flags); 825 spin_lock_irqsave(&uart->port.lock, flags);
762 826
763 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15); 827 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
@@ -861,6 +925,20 @@ static void bfin_serial_set_ldisc(struct uart_port *port)
861 } 925 }
862} 926}
863 927
928static void bfin_serial_reset_irda(struct uart_port *port)
929{
930 int line = port->line;
931 unsigned short val;
932
933 val = UART_GET_GCTL(&bfin_serial_ports[line]);
934 val &= ~(IREN | RPOLC);
935 UART_PUT_GCTL(&bfin_serial_ports[line], val);
936 SSYNC();
937 val |= (IREN | RPOLC);
938 UART_PUT_GCTL(&bfin_serial_ports[line], val);
939 SSYNC();
940}
941
864#ifdef CONFIG_CONSOLE_POLL 942#ifdef CONFIG_CONSOLE_POLL
865static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr) 943static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
866{ 944{
@@ -906,20 +984,6 @@ static int bfin_kgdboc_port_startup(struct uart_port *port)
906} 984}
907#endif 985#endif
908 986
909static void bfin_serial_reset_irda(struct uart_port *port)
910{
911 int line = port->line;
912 unsigned short val;
913
914 val = UART_GET_GCTL(&bfin_serial_ports[line]);
915 val &= ~(IREN | RPOLC);
916 UART_PUT_GCTL(&bfin_serial_ports[line], val);
917 SSYNC();
918 val |= (IREN | RPOLC);
919 UART_PUT_GCTL(&bfin_serial_ports[line], val);
920 SSYNC();
921}
922
923static struct uart_ops bfin_serial_pops = { 987static struct uart_ops bfin_serial_pops = {
924 .tx_empty = bfin_serial_tx_empty, 988 .tx_empty = bfin_serial_tx_empty,
925 .set_mctrl = bfin_serial_set_mctrl, 989 .set_mctrl = bfin_serial_set_mctrl,
@@ -949,6 +1013,39 @@ static struct uart_ops bfin_serial_pops = {
949#endif 1013#endif
950}; 1014};
951 1015
1016static void __init bfin_serial_hw_init(void)
1017{
1018#ifdef CONFIG_SERIAL_BFIN_UART0
1019 peripheral_request(P_UART0_TX, DRIVER_NAME);
1020 peripheral_request(P_UART0_RX, DRIVER_NAME);
1021#endif
1022
1023#ifdef CONFIG_SERIAL_BFIN_UART1
1024 peripheral_request(P_UART1_TX, DRIVER_NAME);
1025 peripheral_request(P_UART1_RX, DRIVER_NAME);
1026
1027# if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x)
1028 peripheral_request(P_UART1_RTS, DRIVER_NAME);
1029 peripheral_request(P_UART1_CTS, DRIVER_NAME);
1030# endif
1031#endif
1032
1033#ifdef CONFIG_SERIAL_BFIN_UART2
1034 peripheral_request(P_UART2_TX, DRIVER_NAME);
1035 peripheral_request(P_UART2_RX, DRIVER_NAME);
1036#endif
1037
1038#ifdef CONFIG_SERIAL_BFIN_UART3
1039 peripheral_request(P_UART3_TX, DRIVER_NAME);
1040 peripheral_request(P_UART3_RX, DRIVER_NAME);
1041
1042# if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x)
1043 peripheral_request(P_UART3_RTS, DRIVER_NAME);
1044 peripheral_request(P_UART3_CTS, DRIVER_NAME);
1045# endif
1046#endif
1047}
1048
952static void __init bfin_serial_init_ports(void) 1049static void __init bfin_serial_init_ports(void)
953{ 1050{
954 static int first = 1; 1051 static int first = 1;
@@ -958,6 +1055,8 @@ static void __init bfin_serial_init_ports(void)
958 return; 1055 return;
959 first = 0; 1056 first = 0;
960 1057
1058 bfin_serial_hw_init();
1059
961 for (i = 0; i < nr_active_ports; i++) { 1060 for (i = 0; i < nr_active_ports; i++) {
962 bfin_serial_ports[i].port.uartclk = get_sclk(); 1061 bfin_serial_ports[i].port.uartclk = get_sclk();
963 bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE; 1062 bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE;
@@ -970,6 +1069,8 @@ static void __init bfin_serial_init_ports(void)
970 bfin_serial_resource[i].uart_base_addr; 1069 bfin_serial_resource[i].uart_base_addr;
971 bfin_serial_ports[i].port.irq = 1070 bfin_serial_ports[i].port.irq =
972 bfin_serial_resource[i].uart_irq; 1071 bfin_serial_resource[i].uart_irq;
1072 bfin_serial_ports[i].status_irq =
1073 bfin_serial_resource[i].uart_status_irq;
973 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF; 1074 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
974#ifdef CONFIG_SERIAL_BFIN_DMA 1075#ifdef CONFIG_SERIAL_BFIN_DMA
975 bfin_serial_ports[i].tx_done = 1; 1076 bfin_serial_ports[i].tx_done = 1;
@@ -980,16 +1081,14 @@ static void __init bfin_serial_init_ports(void)
980 bfin_serial_resource[i].uart_rx_dma_channel; 1081 bfin_serial_resource[i].uart_rx_dma_channel;
981 init_timer(&(bfin_serial_ports[i].rx_dma_timer)); 1082 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
982#endif 1083#endif
983#ifdef CONFIG_SERIAL_BFIN_CTSRTS 1084#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
984 init_timer(&(bfin_serial_ports[i].cts_timer)); 1085 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
985 bfin_serial_ports[i].cts_pin = 1086 bfin_serial_ports[i].cts_pin =
986 bfin_serial_resource[i].uart_cts_pin; 1087 bfin_serial_resource[i].uart_cts_pin;
987 bfin_serial_ports[i].rts_pin = 1088 bfin_serial_ports[i].rts_pin =
988 bfin_serial_resource[i].uart_rts_pin; 1089 bfin_serial_resource[i].uart_rts_pin;
989#endif 1090#endif
990 bfin_serial_hw_init(&bfin_serial_ports[i]);
991 } 1091 }
992
993} 1092}
994 1093
995#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) 1094#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
@@ -1046,7 +1145,8 @@ bfin_serial_console_setup(struct console *co, char *options)
1046 int baud = 57600; 1145 int baud = 57600;
1047 int bits = 8; 1146 int bits = 8;
1048 int parity = 'n'; 1147 int parity = 'n';
1049# ifdef CONFIG_SERIAL_BFIN_CTSRTS 1148# if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1149 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1050 int flow = 'r'; 1150 int flow = 'r';
1051# else 1151# else
1052 int flow = 'n'; 1152 int flow = 'n';
@@ -1088,7 +1188,7 @@ static void
1088bfin_serial_console_write(struct console *co, const char *s, unsigned int count) 1188bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1089{ 1189{
1090 struct bfin_serial_port *uart = &bfin_serial_ports[co->index]; 1190 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
1091 int flags = 0; 1191 unsigned long flags;
1092 1192
1093 spin_lock_irqsave(&uart->port.lock, flags); 1193 spin_lock_irqsave(&uart->port.lock, flags);
1094 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar); 1194 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
@@ -1243,7 +1343,8 @@ static int bfin_serial_remove(struct platform_device *dev)
1243 continue; 1343 continue;
1244 uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); 1344 uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1245 bfin_serial_ports[i].port.dev = NULL; 1345 bfin_serial_ports[i].port.dev = NULL;
1246#ifdef CONFIG_SERIAL_BFIN_CTSRTS 1346#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1347 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1247 gpio_free(bfin_serial_ports[i].cts_pin); 1348 gpio_free(bfin_serial_ports[i].cts_pin);
1248 gpio_free(bfin_serial_ports[i].rts_pin); 1349 gpio_free(bfin_serial_ports[i].rts_pin);
1249#endif 1350#endif
diff --git a/drivers/serial/cpm_uart/cpm_uart_core.c b/drivers/serial/cpm_uart/cpm_uart_core.c
index 5c6ef51da274..f8df0681e160 100644
--- a/drivers/serial/cpm_uart/cpm_uart_core.c
+++ b/drivers/serial/cpm_uart/cpm_uart_core.c
@@ -1106,6 +1106,10 @@ static int cpm_uart_init_port(struct device_node *np,
1106 for (i = 0; i < NUM_GPIOS; i++) 1106 for (i = 0; i < NUM_GPIOS; i++)
1107 pinfo->gpios[i] = of_get_gpio(np, i); 1107 pinfo->gpios[i] = of_get_gpio(np, i);
1108 1108
1109#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1110 udbg_putc = NULL;
1111#endif
1112
1109 return cpm_uart_request_port(&pinfo->port); 1113 return cpm_uart_request_port(&pinfo->port);
1110 1114
1111out_pram: 1115out_pram:
@@ -1255,10 +1259,6 @@ static int __init cpm_uart_console_setup(struct console *co, char *options)
1255 baud = 9600; 1259 baud = 9600;
1256 } 1260 }
1257 1261
1258#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1259 udbg_putc = NULL;
1260#endif
1261
1262 if (IS_SMC(pinfo)) { 1262 if (IS_SMC(pinfo)) {
1263 out_be16(&pinfo->smcup->smc_brkcr, 0); 1263 out_be16(&pinfo->smcup->smc_brkcr, 0);
1264 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 1264 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
@@ -1339,13 +1339,13 @@ static int __devinit cpm_uart_probe(struct of_device *ofdev,
1339 1339
1340 dev_set_drvdata(&ofdev->dev, pinfo); 1340 dev_set_drvdata(&ofdev->dev, pinfo);
1341 1341
1342 /* initialize the device pointer for the port */
1343 pinfo->port.dev = &ofdev->dev;
1344
1342 ret = cpm_uart_init_port(ofdev->node, pinfo); 1345 ret = cpm_uart_init_port(ofdev->node, pinfo);
1343 if (ret) 1346 if (ret)
1344 return ret; 1347 return ret;
1345 1348
1346 /* initialize the device pointer for the port */
1347 pinfo->port.dev = &ofdev->dev;
1348
1349 return uart_add_one_port(&cpm_reg, &pinfo->port); 1349 return uart_add_one_port(&cpm_reg, &pinfo->port);
1350} 1350}
1351 1351
diff --git a/drivers/serial/crisv10.c b/drivers/serial/crisv10.c
index e642c22c80e2..7ba7d70f04d6 100644
--- a/drivers/serial/crisv10.c
+++ b/drivers/serial/crisv10.c
@@ -1391,7 +1391,7 @@ static inline void e100_disable_rx_irq(struct e100_serial *info)
1391#if defined(CONFIG_ETRAX_RS485) 1391#if defined(CONFIG_ETRAX_RS485)
1392/* Enable RS-485 mode on selected port. This is UGLY. */ 1392/* Enable RS-485 mode on selected port. This is UGLY. */
1393static int 1393static int
1394e100_enable_rs485(struct tty_struct *tty,struct rs485_control *r) 1394e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r)
1395{ 1395{
1396 struct e100_serial * info = (struct e100_serial *)tty->driver_data; 1396 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1397 1397
@@ -1409,13 +1409,11 @@ e100_enable_rs485(struct tty_struct *tty,struct rs485_control *r)
1409 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1); 1409 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1);
1410#endif 1410#endif
1411 1411
1412 info->rs485.rts_on_send = 0x01 & r->rts_on_send; 1412 info->rs485.flags = r->flags;
1413 info->rs485.rts_after_sent = 0x01 & r->rts_after_sent;
1414 if (r->delay_rts_before_send >= 1000) 1413 if (r->delay_rts_before_send >= 1000)
1415 info->rs485.delay_rts_before_send = 1000; 1414 info->rs485.delay_rts_before_send = 1000;
1416 else 1415 else
1417 info->rs485.delay_rts_before_send = r->delay_rts_before_send; 1416 info->rs485.delay_rts_before_send = r->delay_rts_before_send;
1418 info->rs485.enabled = r->enabled;
1419/* printk("rts: on send = %i, after = %i, enabled = %i", 1417/* printk("rts: on send = %i, after = %i, enabled = %i",
1420 info->rs485.rts_on_send, 1418 info->rs485.rts_on_send,
1421 info->rs485.rts_after_sent, 1419 info->rs485.rts_after_sent,
@@ -1430,17 +1428,18 @@ e100_write_rs485(struct tty_struct *tty,
1430 const unsigned char *buf, int count) 1428 const unsigned char *buf, int count)
1431{ 1429{
1432 struct e100_serial * info = (struct e100_serial *)tty->driver_data; 1430 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1433 int old_enabled = info->rs485.enabled; 1431 int old_value = (info->rs485.flags) & SER_RS485_ENABLED;
1434 1432
1435 /* rs485 is always implicitly enabled if we're using the ioctl() 1433 /* rs485 is always implicitly enabled if we're using the ioctl()
1436 * but it doesn't have to be set in the rs485_control 1434 * but it doesn't have to be set in the serial_rs485
1437 * (to be backward compatible with old apps) 1435 * (to be backward compatible with old apps)
1438 * So we store, set and restore it. 1436 * So we store, set and restore it.
1439 */ 1437 */
1440 info->rs485.enabled = 1; 1438 info->rs485.flags |= SER_RS485_ENABLED;
1441 /* rs_write now deals with RS485 if enabled */ 1439 /* rs_write now deals with RS485 if enabled */
1442 count = rs_write(tty, buf, count); 1440 count = rs_write(tty, buf, count);
1443 info->rs485.enabled = old_enabled; 1441 if (!old_value)
1442 info->rs485.flags &= ~(SER_RS485_ENABLED);
1444 return count; 1443 return count;
1445} 1444}
1446 1445
@@ -1451,7 +1450,7 @@ static void rs485_toggle_rts_timer_function(unsigned long data)
1451 struct e100_serial *info = (struct e100_serial *)data; 1450 struct e100_serial *info = (struct e100_serial *)data;
1452 1451
1453 fast_timers_rs485[info->line].function = NULL; 1452 fast_timers_rs485[info->line].function = NULL;
1454 e100_rts(info, info->rs485.rts_after_sent); 1453 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1455#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER) 1454#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1456 e100_enable_rx(info); 1455 e100_enable_rx(info);
1457 e100_enable_rx_irq(info); 1456 e100_enable_rx_irq(info);
@@ -1647,7 +1646,7 @@ transmit_chars_dma(struct e100_serial *info)
1647 info->tr_running = 0; 1646 info->tr_running = 0;
1648 1647
1649#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER) 1648#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
1650 if (info->rs485.enabled) { 1649 if (info->rs485.flags & SER_RS485_ENABLED) {
1651 /* Set a short timer to toggle RTS */ 1650 /* Set a short timer to toggle RTS */
1652 start_one_shot_timer(&fast_timers_rs485[info->line], 1651 start_one_shot_timer(&fast_timers_rs485[info->line],
1653 rs485_toggle_rts_timer_function, 1652 rs485_toggle_rts_timer_function,
@@ -2577,7 +2576,7 @@ static void handle_ser_tx_interrupt(struct e100_serial *info)
2577 info->icount.tx++; 2576 info->icount.tx++;
2578 if (info->xmit.head == info->xmit.tail) { 2577 if (info->xmit.head == info->xmit.tail) {
2579#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER) 2578#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
2580 if (info->rs485.enabled) { 2579 if (info->rs485.flags & SER_RS485_ENABLED) {
2581 /* Set a short timer to toggle RTS */ 2580 /* Set a short timer to toggle RTS */
2582 start_one_shot_timer(&fast_timers_rs485[info->line], 2581 start_one_shot_timer(&fast_timers_rs485[info->line],
2583 rs485_toggle_rts_timer_function, 2582 rs485_toggle_rts_timer_function,
@@ -3218,7 +3217,7 @@ rs_write(struct tty_struct *tty,
3218#if defined(CONFIG_ETRAX_RS485) 3217#if defined(CONFIG_ETRAX_RS485)
3219 struct e100_serial *info = (struct e100_serial *)tty->driver_data; 3218 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3220 3219
3221 if (info->rs485.enabled) 3220 if (info->rs485.flags & SER_RS485_ENABLED)
3222 { 3221 {
3223 /* If we are in RS-485 mode, we need to toggle RTS and disable 3222 /* If we are in RS-485 mode, we need to toggle RTS and disable
3224 * the receiver before initiating a DMA transfer 3223 * the receiver before initiating a DMA transfer
@@ -3228,7 +3227,7 @@ rs_write(struct tty_struct *tty,
3228 fast_timers_rs485[info->line].function = NULL; 3227 fast_timers_rs485[info->line].function = NULL;
3229 del_fast_timer(&fast_timers_rs485[info->line]); 3228 del_fast_timer(&fast_timers_rs485[info->line]);
3230#endif 3229#endif
3231 e100_rts(info, info->rs485.rts_on_send); 3230 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND));
3232#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER) 3231#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3233 e100_disable_rx(info); 3232 e100_disable_rx(info);
3234 e100_enable_rx_irq(info); 3233 e100_enable_rx_irq(info);
@@ -3242,7 +3241,7 @@ rs_write(struct tty_struct *tty,
3242 count = rs_raw_write(tty, buf, count); 3241 count = rs_raw_write(tty, buf, count);
3243 3242
3244#if defined(CONFIG_ETRAX_RS485) 3243#if defined(CONFIG_ETRAX_RS485)
3245 if (info->rs485.enabled) 3244 if (info->rs485.flags & SER_RS485_ENABLED)
3246 { 3245 {
3247 unsigned int val; 3246 unsigned int val;
3248 /* If we are in RS-485 mode the following has to be done: 3247 /* If we are in RS-485 mode the following has to be done:
@@ -3263,7 +3262,7 @@ rs_write(struct tty_struct *tty,
3263 get_lsr_info(info, &val); 3262 get_lsr_info(info, &val);
3264 }while (!(val & TIOCSER_TEMT)); 3263 }while (!(val & TIOCSER_TEMT));
3265 3264
3266 e100_rts(info, info->rs485.rts_after_sent); 3265 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
3267 3266
3268#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER) 3267#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3269 e100_enable_rx(info); 3268 e100_enable_rx(info);
@@ -3678,14 +3677,52 @@ rs_ioctl(struct tty_struct *tty, struct file * file,
3678#if defined(CONFIG_ETRAX_RS485) 3677#if defined(CONFIG_ETRAX_RS485)
3679 case TIOCSERSETRS485: 3678 case TIOCSERSETRS485:
3680 { 3679 {
3680 /* In this ioctl we still use the old structure
3681 * rs485_control for backward compatibility
3682 * (if we use serial_rs485, then old user-level code
3683 * wouldn't work anymore...).
3684 * The use of this ioctl is deprecated: use TIOCSRS485
3685 * instead.*/
3681 struct rs485_control rs485ctrl; 3686 struct rs485_control rs485ctrl;
3687 struct serial_rs485 rs485data;
3688 printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n");
3682 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg, 3689 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3683 sizeof(rs485ctrl))) 3690 sizeof(rs485ctrl)))
3684 return -EFAULT; 3691 return -EFAULT;
3685 3692
3686 return e100_enable_rs485(tty, &rs485ctrl); 3693 rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send;
3694 rs485data.flags = 0;
3695 if (rs485ctrl.enabled)
3696 rs485data.flags |= SER_RS485_ENABLED;
3697 else
3698 rs485data.flags &= ~(SER_RS485_ENABLED);
3699
3700 if (rs485ctrl.rts_on_send)
3701 rs485data.flags |= SER_RS485_RTS_ON_SEND;
3702 else
3703 rs485data.flags &= ~(SER_RS485_RTS_ON_SEND);
3704
3705 if (rs485ctrl.rts_after_sent)
3706 rs485data.flags |= SER_RS485_RTS_AFTER_SEND;
3707 else
3708 rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND);
3709
3710 return e100_enable_rs485(tty, &rs485data);
3687 } 3711 }
3688 3712
3713 case TIOCSRS485:
3714 {
3715 /* This is the new version of TIOCSRS485, with new
3716 * data structure serial_rs485 */
3717 struct serial_rs485 rs485data;
3718 if (copy_from_user(&rs485data, (struct rs485_control *)arg,
3719 sizeof(rs485data)))
3720 return -EFAULT;
3721
3722 return e100_enable_rs485(tty, &rs485data);
3723 }
3724
3725
3689 case TIOCSERWRRS485: 3726 case TIOCSERWRRS485:
3690 { 3727 {
3691 struct rs485_write rs485wr; 3728 struct rs485_write rs485wr;
@@ -3827,8 +3864,8 @@ rs_close(struct tty_struct *tty, struct file * filp)
3827 /* port closed */ 3864 /* port closed */
3828 3865
3829#if defined(CONFIG_ETRAX_RS485) 3866#if defined(CONFIG_ETRAX_RS485)
3830 if (info->rs485.enabled) { 3867 if (info->rs485.flags & SER_RS485_ENABLED) {
3831 info->rs485.enabled = 0; 3868 info->rs485.flags &= ~(SER_RS485_ENABLED);
3832#if defined(CONFIG_ETRAX_RS485_ON_PA) 3869#if defined(CONFIG_ETRAX_RS485_ON_PA)
3833 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit); 3870 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
3834#endif 3871#endif
@@ -4493,10 +4530,10 @@ rs_init(void)
4493 4530
4494#if defined(CONFIG_ETRAX_RS485) 4531#if defined(CONFIG_ETRAX_RS485)
4495 /* Set sane defaults */ 4532 /* Set sane defaults */
4496 info->rs485.rts_on_send = 0; 4533 info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND);
4497 info->rs485.rts_after_sent = 1; 4534 info->rs485.flags |= SER_RS485_RTS_AFTER_SEND;
4498 info->rs485.delay_rts_before_send = 0; 4535 info->rs485.delay_rts_before_send = 0;
4499 info->rs485.enabled = 0; 4536 info->rs485.flags &= ~(SER_RS485_ENABLED);
4500#endif 4537#endif
4501 INIT_WORK(&info->work, do_softint); 4538 INIT_WORK(&info->work, do_softint);
4502 4539
diff --git a/drivers/serial/crisv10.h b/drivers/serial/crisv10.h
index f36a729280bc..ea0beb46a10d 100644
--- a/drivers/serial/crisv10.h
+++ b/drivers/serial/crisv10.h
@@ -125,7 +125,7 @@ struct e100_serial {
125 int errorcode; 125 int errorcode;
126 126
127#ifdef CONFIG_ETRAX_RS485 127#ifdef CONFIG_ETRAX_RS485
128 struct rs485_control rs485; /* RS-485 support */ 128 struct serial_rs485 rs485; /* RS-485 support */
129#endif 129#endif
130}; 130};
131 131
diff --git a/drivers/serial/icom.c b/drivers/serial/icom.c
index 2b7531d9f6ab..6579e2be1dd1 100644
--- a/drivers/serial/icom.c
+++ b/drivers/serial/icom.c
@@ -1098,7 +1098,6 @@ static void icom_set_termios(struct uart_port *port,
1098{ 1098{
1099 int baud; 1099 int baud;
1100 unsigned cflag, iflag; 1100 unsigned cflag, iflag;
1101 int bits;
1102 char new_config2; 1101 char new_config2;
1103 char new_config3 = 0; 1102 char new_config3 = 0;
1104 char tmp_byte; 1103 char tmp_byte;
@@ -1119,34 +1118,27 @@ static void icom_set_termios(struct uart_port *port,
1119 switch (cflag & CSIZE) { 1118 switch (cflag & CSIZE) {
1120 case CS5: /* 5 bits/char */ 1119 case CS5: /* 5 bits/char */
1121 new_config2 |= ICOM_ACFG_5BPC; 1120 new_config2 |= ICOM_ACFG_5BPC;
1122 bits = 7;
1123 break; 1121 break;
1124 case CS6: /* 6 bits/char */ 1122 case CS6: /* 6 bits/char */
1125 new_config2 |= ICOM_ACFG_6BPC; 1123 new_config2 |= ICOM_ACFG_6BPC;
1126 bits = 8;
1127 break; 1124 break;
1128 case CS7: /* 7 bits/char */ 1125 case CS7: /* 7 bits/char */
1129 new_config2 |= ICOM_ACFG_7BPC; 1126 new_config2 |= ICOM_ACFG_7BPC;
1130 bits = 9;
1131 break; 1127 break;
1132 case CS8: /* 8 bits/char */ 1128 case CS8: /* 8 bits/char */
1133 new_config2 |= ICOM_ACFG_8BPC; 1129 new_config2 |= ICOM_ACFG_8BPC;
1134 bits = 10;
1135 break; 1130 break;
1136 default: 1131 default:
1137 bits = 10;
1138 break; 1132 break;
1139 } 1133 }
1140 if (cflag & CSTOPB) { 1134 if (cflag & CSTOPB) {
1141 /* 2 stop bits */ 1135 /* 2 stop bits */
1142 new_config2 |= ICOM_ACFG_2STOP_BIT; 1136 new_config2 |= ICOM_ACFG_2STOP_BIT;
1143 bits++;
1144 } 1137 }
1145 if (cflag & PARENB) { 1138 if (cflag & PARENB) {
1146 /* parity bit enabled */ 1139 /* parity bit enabled */
1147 new_config2 |= ICOM_ACFG_PARITY_ENAB; 1140 new_config2 |= ICOM_ACFG_PARITY_ENAB;
1148 trace(ICOM_PORT, "PARENB", 0); 1141 trace(ICOM_PORT, "PARENB", 0);
1149 bits++;
1150 } 1142 }
1151 if (cflag & PARODD) { 1143 if (cflag & PARODD) {
1152 /* odd parity */ 1144 /* odd parity */
@@ -1322,7 +1314,6 @@ static struct uart_driver icom_uart_driver = {
1322static int __devinit icom_init_ports(struct icom_adapter *icom_adapter) 1314static int __devinit icom_init_ports(struct icom_adapter *icom_adapter)
1323{ 1315{
1324 u32 subsystem_id = icom_adapter->subsystem_id; 1316 u32 subsystem_id = icom_adapter->subsystem_id;
1325 int retval = 0;
1326 int i; 1317 int i;
1327 struct icom_port *icom_port; 1318 struct icom_port *icom_port;
1328 1319
@@ -1368,7 +1359,7 @@ static int __devinit icom_init_ports(struct icom_adapter *icom_adapter)
1368 } 1359 }
1369 } 1360 }
1370 1361
1371 return retval; 1362 return 0;
1372} 1363}
1373 1364
1374static void icom_port_active(struct icom_port *icom_port, struct icom_adapter *icom_adapter, int port_num) 1365static void icom_port_active(struct icom_port *icom_port, struct icom_adapter *icom_adapter, int port_num)
@@ -1391,7 +1382,6 @@ static int __devinit icom_load_ports(struct icom_adapter *icom_adapter)
1391{ 1382{
1392 struct icom_port *icom_port; 1383 struct icom_port *icom_port;
1393 int port_num; 1384 int port_num;
1394 int retval;
1395 1385
1396 for (port_num = 0; port_num < icom_adapter->numb_ports; port_num++) { 1386 for (port_num = 0; port_num < icom_adapter->numb_ports; port_num++) {
1397 1387
@@ -1405,7 +1395,7 @@ static int __devinit icom_load_ports(struct icom_adapter *icom_adapter)
1405 icom_port->adapter = icom_adapter; 1395 icom_port->adapter = icom_adapter;
1406 1396
1407 /* get port memory */ 1397 /* get port memory */
1408 if ((retval = get_port_memory(icom_port)) != 0) { 1398 if (get_port_memory(icom_port) != 0) {
1409 dev_err(&icom_port->adapter->pci_dev->dev, 1399 dev_err(&icom_port->adapter->pci_dev->dev,
1410 "Memory allocation for port FAILED\n"); 1400 "Memory allocation for port FAILED\n");
1411 } 1401 }
diff --git a/drivers/serial/jsm/jsm_driver.c b/drivers/serial/jsm/jsm_driver.c
index ac79cbe4c2cf..d2d32a198629 100644
--- a/drivers/serial/jsm/jsm_driver.c
+++ b/drivers/serial/jsm/jsm_driver.c
@@ -52,12 +52,11 @@ int jsm_debug;
52module_param(jsm_debug, int, 0); 52module_param(jsm_debug, int, 0);
53MODULE_PARM_DESC(jsm_debug, "Driver debugging level"); 53MODULE_PARM_DESC(jsm_debug, "Driver debugging level");
54 54
55static int jsm_probe_one(struct pci_dev *pdev, const struct pci_device_id *ent) 55static int __devinit jsm_probe_one(struct pci_dev *pdev, const struct pci_device_id *ent)
56{ 56{
57 int rc = 0; 57 int rc = 0;
58 struct jsm_board *brd; 58 struct jsm_board *brd;
59 static int adapter_count = 0; 59 static int adapter_count = 0;
60 int retval;
61 60
62 rc = pci_enable_device(pdev); 61 rc = pci_enable_device(pdev);
63 if (rc) { 62 if (rc) {
@@ -134,7 +133,7 @@ static int jsm_probe_one(struct pci_dev *pdev, const struct pci_device_id *ent)
134 rc = jsm_tty_init(brd); 133 rc = jsm_tty_init(brd);
135 if (rc < 0) { 134 if (rc < 0) {
136 dev_err(&pdev->dev, "Can't init tty devices (%d)\n", rc); 135 dev_err(&pdev->dev, "Can't init tty devices (%d)\n", rc);
137 retval = -ENXIO; 136 rc = -ENXIO;
138 goto out_free_irq; 137 goto out_free_irq;
139 } 138 }
140 139
@@ -142,7 +141,7 @@ static int jsm_probe_one(struct pci_dev *pdev, const struct pci_device_id *ent)
142 if (rc < 0) { 141 if (rc < 0) {
143 /* XXX: leaking all resources from jsm_tty_init here! */ 142 /* XXX: leaking all resources from jsm_tty_init here! */
144 dev_err(&pdev->dev, "Can't init uart port (%d)\n", rc); 143 dev_err(&pdev->dev, "Can't init uart port (%d)\n", rc);
145 retval = -ENXIO; 144 rc = -ENXIO;
146 goto out_free_irq; 145 goto out_free_irq;
147 } 146 }
148 147
@@ -161,7 +160,7 @@ static int jsm_probe_one(struct pci_dev *pdev, const struct pci_device_id *ent)
161 /* XXX: leaking all resources from jsm_tty_init and 160 /* XXX: leaking all resources from jsm_tty_init and
162 jsm_uart_port_init here! */ 161 jsm_uart_port_init here! */
163 dev_err(&pdev->dev, "memory allocation for flipbuf failed\n"); 162 dev_err(&pdev->dev, "memory allocation for flipbuf failed\n");
164 retval = -ENOMEM; 163 rc = -ENOMEM;
165 goto out_free_irq; 164 goto out_free_irq;
166 } 165 }
167 166
diff --git a/drivers/serial/jsm/jsm_neo.c b/drivers/serial/jsm/jsm_neo.c
index e6390d023634..9dadaa11d266 100644
--- a/drivers/serial/jsm/jsm_neo.c
+++ b/drivers/serial/jsm/jsm_neo.c
@@ -533,7 +533,6 @@ static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
533 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) 533 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
534 return; 534 return;
535 535
536 len_written = 0;
537 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel; 536 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
538 537
539 /* cache head and tail of queue */ 538 /* cache head and tail of queue */
@@ -619,14 +618,10 @@ static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
619/* Make the UART raise any of the output signals we want up */ 618/* Make the UART raise any of the output signals we want up */
620static void neo_assert_modem_signals(struct jsm_channel *ch) 619static void neo_assert_modem_signals(struct jsm_channel *ch)
621{ 620{
622 u8 out;
623
624 if (!ch) 621 if (!ch)
625 return; 622 return;
626 623
627 out = ch->ch_mostat; 624 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
628
629 writeb(out, &ch->ch_neo_uart->mcr);
630 625
631 /* flush write operation */ 626 /* flush write operation */
632 neo_pci_posting_flush(ch->ch_bd); 627 neo_pci_posting_flush(ch->ch_bd);
@@ -936,10 +931,9 @@ static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
936static void neo_param(struct jsm_channel *ch) 931static void neo_param(struct jsm_channel *ch)
937{ 932{
938 u8 lcr = 0; 933 u8 lcr = 0;
939 u8 uart_lcr = 0; 934 u8 uart_lcr, ier;
940 u8 ier = 0; 935 u32 baud;
941 u32 baud = 9600; 936 int quot;
942 int quot = 0;
943 struct jsm_board *bd; 937 struct jsm_board *bd;
944 938
945 bd = ch->ch_bd; 939 bd = ch->ch_bd;
diff --git a/drivers/serial/jsm/jsm_tty.c b/drivers/serial/jsm/jsm_tty.c
index 324c74d2f666..31496dc0a0d1 100644
--- a/drivers/serial/jsm/jsm_tty.c
+++ b/drivers/serial/jsm/jsm_tty.c
@@ -183,7 +183,6 @@ static void jsm_tty_break(struct uart_port *port, int break_state)
183static int jsm_tty_open(struct uart_port *port) 183static int jsm_tty_open(struct uart_port *port)
184{ 184{
185 struct jsm_board *brd; 185 struct jsm_board *brd;
186 int rc = 0;
187 struct jsm_channel *channel = (struct jsm_channel *)port; 186 struct jsm_channel *channel = (struct jsm_channel *)port;
188 struct ktermios *termios; 187 struct ktermios *termios;
189 188
@@ -265,7 +264,7 @@ static int jsm_tty_open(struct uart_port *port)
265 channel->ch_open_count++; 264 channel->ch_open_count++;
266 265
267 jsm_printk(OPEN, INFO, &channel->ch_bd->pci_dev, "finish\n"); 266 jsm_printk(OPEN, INFO, &channel->ch_bd->pci_dev, "finish\n");
268 return rc; 267 return 0;
269} 268}
270 269
271static void jsm_tty_close(struct uart_port *port) 270static void jsm_tty_close(struct uart_port *port)
@@ -367,7 +366,7 @@ static struct uart_ops jsm_ops = {
367 * Init the tty subsystem. Called once per board after board has been 366 * Init the tty subsystem. Called once per board after board has been
368 * downloaded and init'ed. 367 * downloaded and init'ed.
369 */ 368 */
370int jsm_tty_init(struct jsm_board *brd) 369int __devinit jsm_tty_init(struct jsm_board *brd)
371{ 370{
372 int i; 371 int i;
373 void __iomem *vaddr; 372 void __iomem *vaddr;
@@ -431,7 +430,7 @@ int jsm_tty_init(struct jsm_board *brd)
431 return 0; 430 return 0;
432} 431}
433 432
434int jsm_uart_port_init(struct jsm_board *brd) 433int __devinit jsm_uart_port_init(struct jsm_board *brd)
435{ 434{
436 int i; 435 int i;
437 struct jsm_channel *ch; 436 struct jsm_channel *ch;
@@ -748,7 +747,7 @@ static void jsm_carrier(struct jsm_channel *ch)
748void jsm_check_queue_flow_control(struct jsm_channel *ch) 747void jsm_check_queue_flow_control(struct jsm_channel *ch)
749{ 748{
750 struct board_ops *bd_ops = ch->ch_bd->bd_ops; 749 struct board_ops *bd_ops = ch->ch_bd->bd_ops;
751 int qleft = 0; 750 int qleft;
752 751
753 /* Store how much space we have left in the queue */ 752 /* Store how much space we have left in the queue */
754 if ((qleft = ch->ch_r_tail - ch->ch_r_head - 1) < 0) 753 if ((qleft = ch->ch_r_tail - ch->ch_r_head - 1) < 0)
@@ -834,7 +833,7 @@ void jsm_check_queue_flow_control(struct jsm_channel *ch)
834 */ 833 */
835int jsm_tty_write(struct uart_port *port) 834int jsm_tty_write(struct uart_port *port)
836{ 835{
837 int bufcount = 0, n = 0; 836 int bufcount;
838 int data_count = 0,data_count1 =0; 837 int data_count = 0,data_count1 =0;
839 u16 head; 838 u16 head;
840 u16 tail; 839 u16 tail;
@@ -850,14 +849,12 @@ int jsm_tty_write(struct uart_port *port)
850 if ((bufcount = tail - head - 1) < 0) 849 if ((bufcount = tail - head - 1) < 0)
851 bufcount += WQUEUESIZE; 850 bufcount += WQUEUESIZE;
852 851
853 n = bufcount; 852 bufcount = min(bufcount, 56);
854
855 n = min(n, 56);
856 remain = WQUEUESIZE - head; 853 remain = WQUEUESIZE - head;
857 854
858 data_count = 0; 855 data_count = 0;
859 if (n >= remain) { 856 if (bufcount >= remain) {
860 n -= remain; 857 bufcount -= remain;
861 while ((port->info->xmit.head != temp_tail) && 858 while ((port->info->xmit.head != temp_tail) &&
862 (data_count < remain)) { 859 (data_count < remain)) {
863 channel->ch_wqueue[head++] = 860 channel->ch_wqueue[head++] =
@@ -871,8 +868,8 @@ int jsm_tty_write(struct uart_port *port)
871 } 868 }
872 869
873 data_count1 = 0; 870 data_count1 = 0;
874 if (n > 0) { 871 if (bufcount > 0) {
875 remain = n; 872 remain = bufcount;
876 while ((port->info->xmit.head != temp_tail) && 873 while ((port->info->xmit.head != temp_tail) &&
877 (data_count1 < remain)) { 874 (data_count1 < remain)) {
878 channel->ch_wqueue[head++] = 875 channel->ch_wqueue[head++] =
diff --git a/drivers/serial/max3100.c b/drivers/serial/max3100.c
new file mode 100644
index 000000000000..9fd33e5622bd
--- /dev/null
+++ b/drivers/serial/max3100.c
@@ -0,0 +1,927 @@
1/*
2 *
3 * Copyright (C) 2008 Christian Pellegrin <chripell@evolware.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 *
11 * Notes: the MAX3100 doesn't provide an interrupt on CTS so we have
12 * to use polling for flow control. TX empty IRQ is unusable, since
13 * writing conf clears FIFO buffer and we cannot have this interrupt
14 * always asking us for attention.
15 *
16 * Example platform data:
17
18 static struct plat_max3100 max3100_plat_data = {
19 .loopback = 0,
20 .crystal = 0,
21 .poll_time = 100,
22 };
23
24 static struct spi_board_info spi_board_info[] = {
25 {
26 .modalias = "max3100",
27 .platform_data = &max3100_plat_data,
28 .irq = IRQ_EINT12,
29 .max_speed_hz = 5*1000*1000,
30 .chip_select = 0,
31 },
32 };
33
34 * The initial minor number is 209 in the low-density serial port:
35 * mknod /dev/ttyMAX0 c 204 209
36 */
37
38#define MAX3100_MAJOR 204
39#define MAX3100_MINOR 209
40/* 4 MAX3100s should be enough for everyone */
41#define MAX_MAX3100 4
42
43#include <linux/delay.h>
44#include <linux/device.h>
45#include <linux/serial_core.h>
46#include <linux/serial.h>
47#include <linux/spi/spi.h>
48#include <linux/freezer.h>
49
50#include <linux/serial_max3100.h>
51
52#define MAX3100_C (1<<14)
53#define MAX3100_D (0<<14)
54#define MAX3100_W (1<<15)
55#define MAX3100_RX (0<<15)
56
57#define MAX3100_WC (MAX3100_W | MAX3100_C)
58#define MAX3100_RC (MAX3100_RX | MAX3100_C)
59#define MAX3100_WD (MAX3100_W | MAX3100_D)
60#define MAX3100_RD (MAX3100_RX | MAX3100_D)
61#define MAX3100_CMD (3 << 14)
62
63#define MAX3100_T (1<<14)
64#define MAX3100_R (1<<15)
65
66#define MAX3100_FEN (1<<13)
67#define MAX3100_SHDN (1<<12)
68#define MAX3100_TM (1<<11)
69#define MAX3100_RM (1<<10)
70#define MAX3100_PM (1<<9)
71#define MAX3100_RAM (1<<8)
72#define MAX3100_IR (1<<7)
73#define MAX3100_ST (1<<6)
74#define MAX3100_PE (1<<5)
75#define MAX3100_L (1<<4)
76#define MAX3100_BAUD (0xf)
77
78#define MAX3100_TE (1<<10)
79#define MAX3100_RAFE (1<<10)
80#define MAX3100_RTS (1<<9)
81#define MAX3100_CTS (1<<9)
82#define MAX3100_PT (1<<8)
83#define MAX3100_DATA (0xff)
84
85#define MAX3100_RT (MAX3100_R | MAX3100_T)
86#define MAX3100_RTC (MAX3100_RT | MAX3100_CTS | MAX3100_RAFE)
87
88/* the following simulate a status reg for ignore_status_mask */
89#define MAX3100_STATUS_PE 1
90#define MAX3100_STATUS_FE 2
91#define MAX3100_STATUS_OE 4
92
93struct max3100_port {
94 struct uart_port port;
95 struct spi_device *spi;
96
97 int cts; /* last CTS received for flow ctrl */
98 int tx_empty; /* last TX empty bit */
99
100 spinlock_t conf_lock; /* shared data */
101 int conf_commit; /* need to make changes */
102 int conf; /* configuration for the MAX31000
103 * (bits 0-7, bits 8-11 are irqs) */
104 int rts_commit; /* need to change rts */
105 int rts; /* rts status */
106 int baud; /* current baud rate */
107
108 int parity; /* keeps track if we should send parity */
109#define MAX3100_PARITY_ON 1
110#define MAX3100_PARITY_ODD 2
111#define MAX3100_7BIT 4
112 int rx_enabled; /* if we should rx chars */
113
114 int irq; /* irq assigned to the max3100 */
115
116 int minor; /* minor number */
117 int crystal; /* 1 if 3.6864Mhz crystal 0 for 1.8432 */
118 int loopback; /* 1 if we are in loopback mode */
119
120 /* for handling irqs: need workqueue since we do spi_sync */
121 struct workqueue_struct *workqueue;
122 struct work_struct work;
123 /* set to 1 to make the workhandler exit as soon as possible */
124 int force_end_work;
125 /* need to know we are suspending to avoid deadlock on workqueue */
126 int suspending;
127
128 /* hook for suspending MAX3100 via dedicated pin */
129 void (*max3100_hw_suspend) (int suspend);
130
131 /* poll time (in ms) for ctrl lines */
132 int poll_time;
133 /* and its timer */
134 struct timer_list timer;
135};
136
137static struct max3100_port *max3100s[MAX_MAX3100]; /* the chips */
138static DEFINE_MUTEX(max3100s_lock); /* race on probe */
139
140static int max3100_do_parity(struct max3100_port *s, u16 c)
141{
142 int parity;
143
144 if (s->parity & MAX3100_PARITY_ODD)
145 parity = 1;
146 else
147 parity = 0;
148
149 if (s->parity & MAX3100_7BIT)
150 c &= 0x7f;
151 else
152 c &= 0xff;
153
154 parity = parity ^ (hweight8(c) & 1);
155 return parity;
156}
157
158static int max3100_check_parity(struct max3100_port *s, u16 c)
159{
160 return max3100_do_parity(s, c) == ((c >> 8) & 1);
161}
162
163static void max3100_calc_parity(struct max3100_port *s, u16 *c)
164{
165 if (s->parity & MAX3100_7BIT)
166 *c &= 0x7f;
167 else
168 *c &= 0xff;
169
170 if (s->parity & MAX3100_PARITY_ON)
171 *c |= max3100_do_parity(s, *c) << 8;
172}
173
174static void max3100_work(struct work_struct *w);
175
176static void max3100_dowork(struct max3100_port *s)
177{
178 if (!s->force_end_work && !work_pending(&s->work) &&
179 !freezing(current) && !s->suspending)
180 queue_work(s->workqueue, &s->work);
181}
182
183static void max3100_timeout(unsigned long data)
184{
185 struct max3100_port *s = (struct max3100_port *)data;
186
187 if (s->port.info) {
188 max3100_dowork(s);
189 mod_timer(&s->timer, jiffies + s->poll_time);
190 }
191}
192
193static int max3100_sr(struct max3100_port *s, u16 tx, u16 *rx)
194{
195 struct spi_message message;
196 u16 etx, erx;
197 int status;
198 struct spi_transfer tran = {
199 .tx_buf = &etx,
200 .rx_buf = &erx,
201 .len = 2,
202 };
203
204 etx = cpu_to_be16(tx);
205 spi_message_init(&message);
206 spi_message_add_tail(&tran, &message);
207 status = spi_sync(s->spi, &message);
208 if (status) {
209 dev_warn(&s->spi->dev, "error while calling spi_sync\n");
210 return -EIO;
211 }
212 *rx = be16_to_cpu(erx);
213 s->tx_empty = (*rx & MAX3100_T) > 0;
214 dev_dbg(&s->spi->dev, "%04x - %04x\n", tx, *rx);
215 return 0;
216}
217
218static int max3100_handlerx(struct max3100_port *s, u16 rx)
219{
220 unsigned int ch, flg, status = 0;
221 int ret = 0, cts;
222
223 if (rx & MAX3100_R && s->rx_enabled) {
224 dev_dbg(&s->spi->dev, "%s\n", __func__);
225 ch = rx & (s->parity & MAX3100_7BIT ? 0x7f : 0xff);
226 if (rx & MAX3100_RAFE) {
227 s->port.icount.frame++;
228 flg = TTY_FRAME;
229 status |= MAX3100_STATUS_FE;
230 } else {
231 if (s->parity & MAX3100_PARITY_ON) {
232 if (max3100_check_parity(s, rx)) {
233 s->port.icount.rx++;
234 flg = TTY_NORMAL;
235 } else {
236 s->port.icount.parity++;
237 flg = TTY_PARITY;
238 status |= MAX3100_STATUS_PE;
239 }
240 } else {
241 s->port.icount.rx++;
242 flg = TTY_NORMAL;
243 }
244 }
245 uart_insert_char(&s->port, status, MAX3100_STATUS_OE, ch, flg);
246 ret = 1;
247 }
248
249 cts = (rx & MAX3100_CTS) > 0;
250 if (s->cts != cts) {
251 s->cts = cts;
252 uart_handle_cts_change(&s->port, cts ? TIOCM_CTS : 0);
253 }
254
255 return ret;
256}
257
258static void max3100_work(struct work_struct *w)
259{
260 struct max3100_port *s = container_of(w, struct max3100_port, work);
261 int rxchars;
262 u16 tx, rx;
263 int conf, cconf, rts, crts;
264 struct circ_buf *xmit = &s->port.info->xmit;
265
266 dev_dbg(&s->spi->dev, "%s\n", __func__);
267
268 rxchars = 0;
269 do {
270 spin_lock(&s->conf_lock);
271 conf = s->conf;
272 cconf = s->conf_commit;
273 s->conf_commit = 0;
274 rts = s->rts;
275 crts = s->rts_commit;
276 s->rts_commit = 0;
277 spin_unlock(&s->conf_lock);
278 if (cconf)
279 max3100_sr(s, MAX3100_WC | conf, &rx);
280 if (crts) {
281 max3100_sr(s, MAX3100_WD | MAX3100_TE |
282 (s->rts ? MAX3100_RTS : 0), &rx);
283 rxchars += max3100_handlerx(s, rx);
284 }
285
286 max3100_sr(s, MAX3100_RD, &rx);
287 rxchars += max3100_handlerx(s, rx);
288
289 if (rx & MAX3100_T) {
290 tx = 0xffff;
291 if (s->port.x_char) {
292 tx = s->port.x_char;
293 s->port.icount.tx++;
294 s->port.x_char = 0;
295 } else if (!uart_circ_empty(xmit) &&
296 !uart_tx_stopped(&s->port)) {
297 tx = xmit->buf[xmit->tail];
298 xmit->tail = (xmit->tail + 1) &
299 (UART_XMIT_SIZE - 1);
300 s->port.icount.tx++;
301 }
302 if (tx != 0xffff) {
303 max3100_calc_parity(s, &tx);
304 tx |= MAX3100_WD | (s->rts ? MAX3100_RTS : 0);
305 max3100_sr(s, tx, &rx);
306 rxchars += max3100_handlerx(s, rx);
307 }
308 }
309
310 if (rxchars > 16 && s->port.info->port.tty != NULL) {
311 tty_flip_buffer_push(s->port.info->port.tty);
312 rxchars = 0;
313 }
314 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
315 uart_write_wakeup(&s->port);
316
317 } while (!s->force_end_work &&
318 !freezing(current) &&
319 ((rx & MAX3100_R) ||
320 (!uart_circ_empty(xmit) &&
321 !uart_tx_stopped(&s->port))));
322
323 if (rxchars > 0 && s->port.info->port.tty != NULL)
324 tty_flip_buffer_push(s->port.info->port.tty);
325}
326
327static irqreturn_t max3100_irq(int irqno, void *dev_id)
328{
329 struct max3100_port *s = dev_id;
330
331 dev_dbg(&s->spi->dev, "%s\n", __func__);
332
333 max3100_dowork(s);
334 return IRQ_HANDLED;
335}
336
337static void max3100_enable_ms(struct uart_port *port)
338{
339 struct max3100_port *s = container_of(port,
340 struct max3100_port,
341 port);
342
343 if (s->poll_time > 0)
344 mod_timer(&s->timer, jiffies);
345 dev_dbg(&s->spi->dev, "%s\n", __func__);
346}
347
348static void max3100_start_tx(struct uart_port *port)
349{
350 struct max3100_port *s = container_of(port,
351 struct max3100_port,
352 port);
353
354 dev_dbg(&s->spi->dev, "%s\n", __func__);
355
356 max3100_dowork(s);
357}
358
359static void max3100_stop_rx(struct uart_port *port)
360{
361 struct max3100_port *s = container_of(port,
362 struct max3100_port,
363 port);
364
365 dev_dbg(&s->spi->dev, "%s\n", __func__);
366
367 s->rx_enabled = 0;
368 spin_lock(&s->conf_lock);
369 s->conf &= ~MAX3100_RM;
370 s->conf_commit = 1;
371 spin_unlock(&s->conf_lock);
372 max3100_dowork(s);
373}
374
375static unsigned int max3100_tx_empty(struct uart_port *port)
376{
377 struct max3100_port *s = container_of(port,
378 struct max3100_port,
379 port);
380
381 dev_dbg(&s->spi->dev, "%s\n", __func__);
382
383 /* may not be truly up-to-date */
384 max3100_dowork(s);
385 return s->tx_empty;
386}
387
388static unsigned int max3100_get_mctrl(struct uart_port *port)
389{
390 struct max3100_port *s = container_of(port,
391 struct max3100_port,
392 port);
393
394 dev_dbg(&s->spi->dev, "%s\n", __func__);
395
396 /* may not be truly up-to-date */
397 max3100_dowork(s);
398 /* always assert DCD and DSR since these lines are not wired */
399 return (s->cts ? TIOCM_CTS : 0) | TIOCM_DSR | TIOCM_CAR;
400}
401
402static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl)
403{
404 struct max3100_port *s = container_of(port,
405 struct max3100_port,
406 port);
407 int rts;
408
409 dev_dbg(&s->spi->dev, "%s\n", __func__);
410
411 rts = (mctrl & TIOCM_RTS) > 0;
412
413 spin_lock(&s->conf_lock);
414 if (s->rts != rts) {
415 s->rts = rts;
416 s->rts_commit = 1;
417 max3100_dowork(s);
418 }
419 spin_unlock(&s->conf_lock);
420}
421
422static void
423max3100_set_termios(struct uart_port *port, struct ktermios *termios,
424 struct ktermios *old)
425{
426 struct max3100_port *s = container_of(port,
427 struct max3100_port,
428 port);
429 int baud = 0;
430 unsigned cflag;
431 u32 param_new, param_mask, parity = 0;
432 struct tty_struct *tty = s->port.info->port.tty;
433
434 dev_dbg(&s->spi->dev, "%s\n", __func__);
435 if (!tty)
436 return;
437
438 cflag = termios->c_cflag;
439 param_new = 0;
440 param_mask = 0;
441
442 baud = tty_get_baud_rate(tty);
443 param_new = s->conf & MAX3100_BAUD;
444 switch (baud) {
445 case 300:
446 if (s->crystal)
447 baud = s->baud;
448 else
449 param_new = 15;
450 break;
451 case 600:
452 param_new = 14 + s->crystal;
453 break;
454 case 1200:
455 param_new = 13 + s->crystal;
456 break;
457 case 2400:
458 param_new = 12 + s->crystal;
459 break;
460 case 4800:
461 param_new = 11 + s->crystal;
462 break;
463 case 9600:
464 param_new = 10 + s->crystal;
465 break;
466 case 19200:
467 param_new = 9 + s->crystal;
468 break;
469 case 38400:
470 param_new = 8 + s->crystal;
471 break;
472 case 57600:
473 param_new = 1 + s->crystal;
474 break;
475 case 115200:
476 param_new = 0 + s->crystal;
477 break;
478 case 230400:
479 if (s->crystal)
480 param_new = 0;
481 else
482 baud = s->baud;
483 break;
484 default:
485 baud = s->baud;
486 }
487 tty_encode_baud_rate(tty, baud, baud);
488 s->baud = baud;
489 param_mask |= MAX3100_BAUD;
490
491 if ((cflag & CSIZE) == CS8) {
492 param_new &= ~MAX3100_L;
493 parity &= ~MAX3100_7BIT;
494 } else {
495 param_new |= MAX3100_L;
496 parity |= MAX3100_7BIT;
497 cflag = (cflag & ~CSIZE) | CS7;
498 }
499 param_mask |= MAX3100_L;
500
501 if (cflag & CSTOPB)
502 param_new |= MAX3100_ST;
503 else
504 param_new &= ~MAX3100_ST;
505 param_mask |= MAX3100_ST;
506
507 if (cflag & PARENB) {
508 param_new |= MAX3100_PE;
509 parity |= MAX3100_PARITY_ON;
510 } else {
511 param_new &= ~MAX3100_PE;
512 parity &= ~MAX3100_PARITY_ON;
513 }
514 param_mask |= MAX3100_PE;
515
516 if (cflag & PARODD)
517 parity |= MAX3100_PARITY_ODD;
518 else
519 parity &= ~MAX3100_PARITY_ODD;
520
521 /* mask termios capabilities we don't support */
522 cflag &= ~CMSPAR;
523 termios->c_cflag = cflag;
524
525 s->port.ignore_status_mask = 0;
526 if (termios->c_iflag & IGNPAR)
527 s->port.ignore_status_mask |=
528 MAX3100_STATUS_PE | MAX3100_STATUS_FE |
529 MAX3100_STATUS_OE;
530
531 /* we are sending char from a workqueue so enable */
532 s->port.info->port.tty->low_latency = 1;
533
534 if (s->poll_time > 0)
535 del_timer_sync(&s->timer);
536
537 uart_update_timeout(port, termios->c_cflag, baud);
538
539 spin_lock(&s->conf_lock);
540 s->conf = (s->conf & ~param_mask) | (param_new & param_mask);
541 s->conf_commit = 1;
542 s->parity = parity;
543 spin_unlock(&s->conf_lock);
544 max3100_dowork(s);
545
546 if (UART_ENABLE_MS(&s->port, termios->c_cflag))
547 max3100_enable_ms(&s->port);
548}
549
550static void max3100_shutdown(struct uart_port *port)
551{
552 struct max3100_port *s = container_of(port,
553 struct max3100_port,
554 port);
555
556 dev_dbg(&s->spi->dev, "%s\n", __func__);
557
558 if (s->suspending)
559 return;
560
561 s->force_end_work = 1;
562
563 if (s->poll_time > 0)
564 del_timer_sync(&s->timer);
565
566 if (s->workqueue) {
567 flush_workqueue(s->workqueue);
568 destroy_workqueue(s->workqueue);
569 s->workqueue = NULL;
570 }
571 if (s->irq)
572 free_irq(s->irq, s);
573
574 /* set shutdown mode to save power */
575 if (s->max3100_hw_suspend)
576 s->max3100_hw_suspend(1);
577 else {
578 u16 tx, rx;
579
580 tx = MAX3100_WC | MAX3100_SHDN;
581 max3100_sr(s, tx, &rx);
582 }
583}
584
585static int max3100_startup(struct uart_port *port)
586{
587 struct max3100_port *s = container_of(port,
588 struct max3100_port,
589 port);
590 char b[12];
591
592 dev_dbg(&s->spi->dev, "%s\n", __func__);
593
594 s->conf = MAX3100_RM;
595 s->baud = s->crystal ? 230400 : 115200;
596 s->rx_enabled = 1;
597
598 if (s->suspending)
599 return 0;
600
601 s->force_end_work = 0;
602 s->parity = 0;
603 s->rts = 0;
604
605 sprintf(b, "max3100-%d", s->minor);
606 s->workqueue = create_freezeable_workqueue(b);
607 if (!s->workqueue) {
608 dev_warn(&s->spi->dev, "cannot create workqueue\n");
609 return -EBUSY;
610 }
611 INIT_WORK(&s->work, max3100_work);
612
613 if (request_irq(s->irq, max3100_irq,
614 IRQF_TRIGGER_FALLING, "max3100", s) < 0) {
615 dev_warn(&s->spi->dev, "cannot allocate irq %d\n", s->irq);
616 s->irq = 0;
617 destroy_workqueue(s->workqueue);
618 s->workqueue = NULL;
619 return -EBUSY;
620 }
621
622 if (s->loopback) {
623 u16 tx, rx;
624 tx = 0x4001;
625 max3100_sr(s, tx, &rx);
626 }
627
628 if (s->max3100_hw_suspend)
629 s->max3100_hw_suspend(0);
630 s->conf_commit = 1;
631 max3100_dowork(s);
632 /* wait for clock to settle */
633 msleep(50);
634
635 max3100_enable_ms(&s->port);
636
637 return 0;
638}
639
640static const char *max3100_type(struct uart_port *port)
641{
642 struct max3100_port *s = container_of(port,
643 struct max3100_port,
644 port);
645
646 dev_dbg(&s->spi->dev, "%s\n", __func__);
647
648 return s->port.type == PORT_MAX3100 ? "MAX3100" : NULL;
649}
650
651static void max3100_release_port(struct uart_port *port)
652{
653 struct max3100_port *s = container_of(port,
654 struct max3100_port,
655 port);
656
657 dev_dbg(&s->spi->dev, "%s\n", __func__);
658}
659
660static void max3100_config_port(struct uart_port *port, int flags)
661{
662 struct max3100_port *s = container_of(port,
663 struct max3100_port,
664 port);
665
666 dev_dbg(&s->spi->dev, "%s\n", __func__);
667
668 if (flags & UART_CONFIG_TYPE)
669 s->port.type = PORT_MAX3100;
670}
671
672static int max3100_verify_port(struct uart_port *port,
673 struct serial_struct *ser)
674{
675 struct max3100_port *s = container_of(port,
676 struct max3100_port,
677 port);
678 int ret = -EINVAL;
679
680 dev_dbg(&s->spi->dev, "%s\n", __func__);
681
682 if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3100)
683 ret = 0;
684 return ret;
685}
686
687static void max3100_stop_tx(struct uart_port *port)
688{
689 struct max3100_port *s = container_of(port,
690 struct max3100_port,
691 port);
692
693 dev_dbg(&s->spi->dev, "%s\n", __func__);
694}
695
696static int max3100_request_port(struct uart_port *port)
697{
698 struct max3100_port *s = container_of(port,
699 struct max3100_port,
700 port);
701
702 dev_dbg(&s->spi->dev, "%s\n", __func__);
703 return 0;
704}
705
706static void max3100_break_ctl(struct uart_port *port, int break_state)
707{
708 struct max3100_port *s = container_of(port,
709 struct max3100_port,
710 port);
711
712 dev_dbg(&s->spi->dev, "%s\n", __func__);
713}
714
715static struct uart_ops max3100_ops = {
716 .tx_empty = max3100_tx_empty,
717 .set_mctrl = max3100_set_mctrl,
718 .get_mctrl = max3100_get_mctrl,
719 .stop_tx = max3100_stop_tx,
720 .start_tx = max3100_start_tx,
721 .stop_rx = max3100_stop_rx,
722 .enable_ms = max3100_enable_ms,
723 .break_ctl = max3100_break_ctl,
724 .startup = max3100_startup,
725 .shutdown = max3100_shutdown,
726 .set_termios = max3100_set_termios,
727 .type = max3100_type,
728 .release_port = max3100_release_port,
729 .request_port = max3100_request_port,
730 .config_port = max3100_config_port,
731 .verify_port = max3100_verify_port,
732};
733
734static struct uart_driver max3100_uart_driver = {
735 .owner = THIS_MODULE,
736 .driver_name = "ttyMAX",
737 .dev_name = "ttyMAX",
738 .major = MAX3100_MAJOR,
739 .minor = MAX3100_MINOR,
740 .nr = MAX_MAX3100,
741};
742static int uart_driver_registered;
743
744static int __devinit max3100_probe(struct spi_device *spi)
745{
746 int i, retval;
747 struct plat_max3100 *pdata;
748 u16 tx, rx;
749
750 mutex_lock(&max3100s_lock);
751
752 if (!uart_driver_registered) {
753 uart_driver_registered = 1;
754 retval = uart_register_driver(&max3100_uart_driver);
755 if (retval) {
756 printk(KERN_ERR "Couldn't register max3100 uart driver\n");
757 mutex_unlock(&max3100s_lock);
758 return retval;
759 }
760 }
761
762 for (i = 0; i < MAX_MAX3100; i++)
763 if (!max3100s[i])
764 break;
765 if (i == MAX_MAX3100) {
766 dev_warn(&spi->dev, "too many MAX3100 chips\n");
767 mutex_unlock(&max3100s_lock);
768 return -ENOMEM;
769 }
770
771 max3100s[i] = kzalloc(sizeof(struct max3100_port), GFP_KERNEL);
772 if (!max3100s[i]) {
773 dev_warn(&spi->dev,
774 "kmalloc for max3100 structure %d failed!\n", i);
775 mutex_unlock(&max3100s_lock);
776 return -ENOMEM;
777 }
778 max3100s[i]->spi = spi;
779 max3100s[i]->irq = spi->irq;
780 spin_lock_init(&max3100s[i]->conf_lock);
781 dev_set_drvdata(&spi->dev, max3100s[i]);
782 pdata = spi->dev.platform_data;
783 max3100s[i]->crystal = pdata->crystal;
784 max3100s[i]->loopback = pdata->loopback;
785 max3100s[i]->poll_time = pdata->poll_time * HZ / 1000;
786 if (pdata->poll_time > 0 && max3100s[i]->poll_time == 0)
787 max3100s[i]->poll_time = 1;
788 max3100s[i]->max3100_hw_suspend = pdata->max3100_hw_suspend;
789 max3100s[i]->minor = i;
790 init_timer(&max3100s[i]->timer);
791 max3100s[i]->timer.function = max3100_timeout;
792 max3100s[i]->timer.data = (unsigned long) max3100s[i];
793
794 dev_dbg(&spi->dev, "%s: adding port %d\n", __func__, i);
795 max3100s[i]->port.irq = max3100s[i]->irq;
796 max3100s[i]->port.uartclk = max3100s[i]->crystal ? 3686400 : 1843200;
797 max3100s[i]->port.fifosize = 16;
798 max3100s[i]->port.ops = &max3100_ops;
799 max3100s[i]->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
800 max3100s[i]->port.line = i;
801 max3100s[i]->port.type = PORT_MAX3100;
802 max3100s[i]->port.dev = &spi->dev;
803 retval = uart_add_one_port(&max3100_uart_driver, &max3100s[i]->port);
804 if (retval < 0)
805 dev_warn(&spi->dev,
806 "uart_add_one_port failed for line %d with error %d\n",
807 i, retval);
808
809 /* set shutdown mode to save power. Will be woken-up on open */
810 if (max3100s[i]->max3100_hw_suspend)
811 max3100s[i]->max3100_hw_suspend(1);
812 else {
813 tx = MAX3100_WC | MAX3100_SHDN;
814 max3100_sr(max3100s[i], tx, &rx);
815 }
816 mutex_unlock(&max3100s_lock);
817 return 0;
818}
819
820static int __devexit max3100_remove(struct spi_device *spi)
821{
822 struct max3100_port *s = dev_get_drvdata(&spi->dev);
823 int i;
824
825 mutex_lock(&max3100s_lock);
826
827 /* find out the index for the chip we are removing */
828 for (i = 0; i < MAX_MAX3100; i++)
829 if (max3100s[i] == s)
830 break;
831
832 dev_dbg(&spi->dev, "%s: removing port %d\n", __func__, i);
833 uart_remove_one_port(&max3100_uart_driver, &max3100s[i]->port);
834 kfree(max3100s[i]);
835 max3100s[i] = NULL;
836
837 /* check if this is the last chip we have */
838 for (i = 0; i < MAX_MAX3100; i++)
839 if (max3100s[i]) {
840 mutex_unlock(&max3100s_lock);
841 return 0;
842 }
843 pr_debug("removing max3100 driver\n");
844 uart_unregister_driver(&max3100_uart_driver);
845
846 mutex_unlock(&max3100s_lock);
847 return 0;
848}
849
850#ifdef CONFIG_PM
851
852static int max3100_suspend(struct spi_device *spi, pm_message_t state)
853{
854 struct max3100_port *s = dev_get_drvdata(&spi->dev);
855
856 dev_dbg(&s->spi->dev, "%s\n", __func__);
857
858 disable_irq(s->irq);
859
860 s->suspending = 1;
861 uart_suspend_port(&max3100_uart_driver, &s->port);
862
863 if (s->max3100_hw_suspend)
864 s->max3100_hw_suspend(1);
865 else {
866 /* no HW suspend, so do SW one */
867 u16 tx, rx;
868
869 tx = MAX3100_WC | MAX3100_SHDN;
870 max3100_sr(s, tx, &rx);
871 }
872 return 0;
873}
874
875static int max3100_resume(struct spi_device *spi)
876{
877 struct max3100_port *s = dev_get_drvdata(&spi->dev);
878
879 dev_dbg(&s->spi->dev, "%s\n", __func__);
880
881 if (s->max3100_hw_suspend)
882 s->max3100_hw_suspend(0);
883 uart_resume_port(&max3100_uart_driver, &s->port);
884 s->suspending = 0;
885
886 enable_irq(s->irq);
887
888 s->conf_commit = 1;
889 if (s->workqueue)
890 max3100_dowork(s);
891
892 return 0;
893}
894
895#else
896#define max3100_suspend NULL
897#define max3100_resume NULL
898#endif
899
900static struct spi_driver max3100_driver = {
901 .driver = {
902 .name = "max3100",
903 .bus = &spi_bus_type,
904 .owner = THIS_MODULE,
905 },
906
907 .probe = max3100_probe,
908 .remove = __devexit_p(max3100_remove),
909 .suspend = max3100_suspend,
910 .resume = max3100_resume,
911};
912
913static int __init max3100_init(void)
914{
915 return spi_register_driver(&max3100_driver);
916}
917module_init(max3100_init);
918
919static void __exit max3100_exit(void)
920{
921 spi_unregister_driver(&max3100_driver);
922}
923module_exit(max3100_exit);
924
925MODULE_DESCRIPTION("MAX3100 driver");
926MODULE_AUTHOR("Christian Pellegrin <chripell@evolware.org>");
927MODULE_LICENSE("GPL");
diff --git a/drivers/serial/pmac_zilog.c b/drivers/serial/pmac_zilog.c
index ad3488504010..9c1243fbd512 100644
--- a/drivers/serial/pmac_zilog.c
+++ b/drivers/serial/pmac_zilog.c
@@ -1538,6 +1538,21 @@ no_dma:
1538 uap->port.type = PORT_PMAC_ZILOG; 1538 uap->port.type = PORT_PMAC_ZILOG;
1539 uap->port.flags = 0; 1539 uap->port.flags = 0;
1540 1540
1541 /*
1542 * Fixup for the port on Gatwick for which the device-tree has
1543 * missing interrupts. Normally, the macio_dev would contain
1544 * fixed up interrupt info, but we use the device-tree directly
1545 * here due to early probing so we need the fixup too.
1546 */
1547 if (uap->port.irq == NO_IRQ &&
1548 np->parent && np->parent->parent &&
1549 of_device_is_compatible(np->parent->parent, "gatwick")) {
1550 /* IRQs on gatwick are offset by 64 */
1551 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1552 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
1553 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
1554 }
1555
1541 /* Setup some valid baud rate information in the register 1556 /* Setup some valid baud rate information in the register
1542 * shadows so we don't write crap there before baud rate is 1557 * shadows so we don't write crap there before baud rate is
1543 * first initialized. 1558 * first initialized.
diff --git a/drivers/serial/sunsu.c b/drivers/serial/sunsu.c
index a4dc79b1d7ab..47c6837850b1 100644
--- a/drivers/serial/sunsu.c
+++ b/drivers/serial/sunsu.c
@@ -1178,7 +1178,7 @@ static struct uart_driver sunsu_reg = {
1178 .major = TTY_MAJOR, 1178 .major = TTY_MAJOR,
1179}; 1179};
1180 1180
1181static int __init sunsu_kbd_ms_init(struct uart_sunsu_port *up) 1181static int __devinit sunsu_kbd_ms_init(struct uart_sunsu_port *up)
1182{ 1182{
1183 int quot, baud; 1183 int quot, baud;
1184#ifdef CONFIG_SERIO 1184#ifdef CONFIG_SERIO
diff --git a/drivers/serial/ucc_uart.c b/drivers/serial/ucc_uart.c
index 315a9333ca3c..7de66c06b05d 100644
--- a/drivers/serial/ucc_uart.c
+++ b/drivers/serial/ucc_uart.c
@@ -1274,6 +1274,7 @@ static int ucc_uart_probe(struct of_device *ofdev,
1274 if (!iprop) { 1274 if (!iprop) {
1275 iprop = of_get_property(np, "device-id", NULL); 1275 iprop = of_get_property(np, "device-id", NULL);
1276 if (!iprop) { 1276 if (!iprop) {
1277 kfree(qe_port);
1277 dev_err(&ofdev->dev, "UCC is unspecified in " 1278 dev_err(&ofdev->dev, "UCC is unspecified in "
1278 "device tree\n"); 1279 "device tree\n");
1279 return -EINVAL; 1280 return -EINVAL;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 03:20:32 -0500