diff options
Diffstat (limited to 'drivers/serial')
-rw-r--r-- | drivers/serial/Kconfig | 4 | ||||
-rw-r--r-- | drivers/serial/atmel_serial.c | 17 | ||||
-rw-r--r-- | drivers/serial/crisv10.c | 4 | ||||
-rw-r--r-- | drivers/serial/crisv10.h | 2 | ||||
-rw-r--r-- | drivers/serial/ioc3_serial.c | 6 | ||||
-rw-r--r-- | drivers/serial/mpc52xx_uart.c | 4 | ||||
-rw-r--r-- | drivers/serial/netx-serial.c | 4 | ||||
-rw-r--r-- | drivers/serial/s3c2440.c | 2 | ||||
-rw-r--r-- | drivers/serial/sh-sci.c | 62 | ||||
-rw-r--r-- | drivers/serial/sh-sci.h | 112 | ||||
-rw-r--r-- | drivers/serial/uartlite.c | 4 |
11 files changed, 88 insertions, 133 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index c94d3c4b7521..579d63a81aa2 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig | |||
@@ -1276,7 +1276,7 @@ config SERIAL_SGI_IOC3 | |||
1276 | say Y or M. Otherwise, say N. | 1276 | say Y or M. Otherwise, say N. |
1277 | 1277 | ||
1278 | config SERIAL_NETX | 1278 | config SERIAL_NETX |
1279 | bool "NetX serial port support" | 1279 | tristate "NetX serial port support" |
1280 | depends on ARM && ARCH_NETX | 1280 | depends on ARM && ARCH_NETX |
1281 | select SERIAL_CORE | 1281 | select SERIAL_CORE |
1282 | help | 1282 | help |
@@ -1288,7 +1288,7 @@ config SERIAL_NETX | |||
1288 | 1288 | ||
1289 | config SERIAL_NETX_CONSOLE | 1289 | config SERIAL_NETX_CONSOLE |
1290 | bool "Console on NetX serial port" | 1290 | bool "Console on NetX serial port" |
1291 | depends on SERIAL_NETX | 1291 | depends on SERIAL_NETX=y |
1292 | select SERIAL_CORE_CONSOLE | 1292 | select SERIAL_CORE_CONSOLE |
1293 | help | 1293 | help |
1294 | If you have enabled the serial port on the Hilscher NetX SoC | 1294 | If you have enabled the serial port on the Hilscher NetX SoC |
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c index 61fb8b6d19af..d5efd6c77904 100644 --- a/drivers/serial/atmel_serial.c +++ b/drivers/serial/atmel_serial.c | |||
@@ -1258,6 +1258,8 @@ static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, | |||
1258 | atmel_port->clk = clk_get(&pdev->dev, "usart"); | 1258 | atmel_port->clk = clk_get(&pdev->dev, "usart"); |
1259 | clk_enable(atmel_port->clk); | 1259 | clk_enable(atmel_port->clk); |
1260 | port->uartclk = clk_get_rate(atmel_port->clk); | 1260 | port->uartclk = clk_get_rate(atmel_port->clk); |
1261 | clk_disable(atmel_port->clk); | ||
1262 | /* only enable clock when USART is in use */ | ||
1261 | } | 1263 | } |
1262 | 1264 | ||
1263 | atmel_port->use_dma_rx = data->use_dma_rx; | 1265 | atmel_port->use_dma_rx = data->use_dma_rx; |
@@ -1379,6 +1381,8 @@ static int __init atmel_console_setup(struct console *co, char *options) | |||
1379 | return -ENODEV; | 1381 | return -ENODEV; |
1380 | } | 1382 | } |
1381 | 1383 | ||
1384 | clk_enable(atmel_ports[co->index].clk); | ||
1385 | |||
1382 | UART_PUT_IDR(port, -1); | 1386 | UART_PUT_IDR(port, -1); |
1383 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); | 1387 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
1384 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | 1388 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); |
@@ -1403,7 +1407,7 @@ static struct console atmel_console = { | |||
1403 | .data = &atmel_uart, | 1407 | .data = &atmel_uart, |
1404 | }; | 1408 | }; |
1405 | 1409 | ||
1406 | #define ATMEL_CONSOLE_DEVICE &atmel_console | 1410 | #define ATMEL_CONSOLE_DEVICE (&atmel_console) |
1407 | 1411 | ||
1408 | /* | 1412 | /* |
1409 | * Early console initialization (before VM subsystem initialized). | 1413 | * Early console initialization (before VM subsystem initialized). |
@@ -1534,6 +1538,15 @@ static int __devinit atmel_serial_probe(struct platform_device *pdev) | |||
1534 | if (ret) | 1538 | if (ret) |
1535 | goto err_add_port; | 1539 | goto err_add_port; |
1536 | 1540 | ||
1541 | if (atmel_is_console_port(&port->uart) | ||
1542 | && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { | ||
1543 | /* | ||
1544 | * The serial core enabled the clock for us, so undo | ||
1545 | * the clk_enable() in atmel_console_setup() | ||
1546 | */ | ||
1547 | clk_disable(port->clk); | ||
1548 | } | ||
1549 | |||
1537 | device_init_wakeup(&pdev->dev, 1); | 1550 | device_init_wakeup(&pdev->dev, 1); |
1538 | platform_set_drvdata(pdev, port); | 1551 | platform_set_drvdata(pdev, port); |
1539 | 1552 | ||
@@ -1544,7 +1557,6 @@ err_add_port: | |||
1544 | port->rx_ring.buf = NULL; | 1557 | port->rx_ring.buf = NULL; |
1545 | err_alloc_ring: | 1558 | err_alloc_ring: |
1546 | if (!atmel_is_console_port(&port->uart)) { | 1559 | if (!atmel_is_console_port(&port->uart)) { |
1547 | clk_disable(port->clk); | ||
1548 | clk_put(port->clk); | 1560 | clk_put(port->clk); |
1549 | port->clk = NULL; | 1561 | port->clk = NULL; |
1550 | } | 1562 | } |
@@ -1568,7 +1580,6 @@ static int __devexit atmel_serial_remove(struct platform_device *pdev) | |||
1568 | 1580 | ||
1569 | /* "port" is allocated statically, so we shouldn't free it */ | 1581 | /* "port" is allocated statically, so we shouldn't free it */ |
1570 | 1582 | ||
1571 | clk_disable(atmel_port->clk); | ||
1572 | clk_put(atmel_port->clk); | 1583 | clk_put(atmel_port->clk); |
1573 | 1584 | ||
1574 | return ret; | 1585 | return ret; |
diff --git a/drivers/serial/crisv10.c b/drivers/serial/crisv10.c index 211c21797ce0..8b2c619a09f2 100644 --- a/drivers/serial/crisv10.c +++ b/drivers/serial/crisv10.c | |||
@@ -34,14 +34,14 @@ static char *serial_version = "$Revision: 1.25 $"; | |||
34 | #include <asm/system.h> | 34 | #include <asm/system.h> |
35 | #include <linux/delay.h> | 35 | #include <linux/delay.h> |
36 | 36 | ||
37 | #include <asm/arch/svinto.h> | 37 | #include <arch/svinto.h> |
38 | 38 | ||
39 | /* non-arch dependent serial structures are in linux/serial.h */ | 39 | /* non-arch dependent serial structures are in linux/serial.h */ |
40 | #include <linux/serial.h> | 40 | #include <linux/serial.h> |
41 | /* while we keep our own stuff (struct e100_serial) in a local .h file */ | 41 | /* while we keep our own stuff (struct e100_serial) in a local .h file */ |
42 | #include "crisv10.h" | 42 | #include "crisv10.h" |
43 | #include <asm/fasttimer.h> | 43 | #include <asm/fasttimer.h> |
44 | #include <asm/arch/io_interface_mux.h> | 44 | #include <arch/io_interface_mux.h> |
45 | 45 | ||
46 | #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER | 46 | #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER |
47 | #ifndef CONFIG_ETRAX_FAST_TIMER | 47 | #ifndef CONFIG_ETRAX_FAST_TIMER |
diff --git a/drivers/serial/crisv10.h b/drivers/serial/crisv10.h index e3c5c8c3c09b..f36a729280bc 100644 --- a/drivers/serial/crisv10.h +++ b/drivers/serial/crisv10.h | |||
@@ -10,7 +10,7 @@ | |||
10 | #include <linux/circ_buf.h> | 10 | #include <linux/circ_buf.h> |
11 | #include <asm/termios.h> | 11 | #include <asm/termios.h> |
12 | #include <asm/dma.h> | 12 | #include <asm/dma.h> |
13 | #include <asm/arch/io_interface_mux.h> | 13 | #include <arch/io_interface_mux.h> |
14 | 14 | ||
15 | /* Software state per channel */ | 15 | /* Software state per channel */ |
16 | 16 | ||
diff --git a/drivers/serial/ioc3_serial.c b/drivers/serial/ioc3_serial.c index 6dd98f9fb89c..ae3699d77dd0 100644 --- a/drivers/serial/ioc3_serial.c +++ b/drivers/serial/ioc3_serial.c | |||
@@ -2149,7 +2149,7 @@ out4: | |||
2149 | return ret; | 2149 | return ret; |
2150 | } | 2150 | } |
2151 | 2151 | ||
2152 | static struct ioc3_submodule ioc3uart_submodule = { | 2152 | static struct ioc3_submodule ioc3uart_ops = { |
2153 | .name = "IOC3uart", | 2153 | .name = "IOC3uart", |
2154 | .probe = ioc3uart_probe, | 2154 | .probe = ioc3uart_probe, |
2155 | .remove = ioc3uart_remove, | 2155 | .remove = ioc3uart_remove, |
@@ -2173,7 +2173,7 @@ static int __devinit ioc3uart_init(void) | |||
2173 | __func__); | 2173 | __func__); |
2174 | return ret; | 2174 | return ret; |
2175 | } | 2175 | } |
2176 | ret = ioc3_register_submodule(&ioc3uart_submodule); | 2176 | ret = ioc3_register_submodule(&ioc3uart_ops); |
2177 | if (ret) | 2177 | if (ret) |
2178 | uart_unregister_driver(&ioc3_uart); | 2178 | uart_unregister_driver(&ioc3_uart); |
2179 | return ret; | 2179 | return ret; |
@@ -2181,7 +2181,7 @@ static int __devinit ioc3uart_init(void) | |||
2181 | 2181 | ||
2182 | static void __devexit ioc3uart_exit(void) | 2182 | static void __devexit ioc3uart_exit(void) |
2183 | { | 2183 | { |
2184 | ioc3_unregister_submodule(&ioc3uart_submodule); | 2184 | ioc3_unregister_submodule(&ioc3uart_ops); |
2185 | uart_unregister_driver(&ioc3_uart); | 2185 | uart_unregister_driver(&ioc3_uart); |
2186 | } | 2186 | } |
2187 | 2187 | ||
diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c index 6117d3db0b66..28c00c3d58f5 100644 --- a/drivers/serial/mpc52xx_uart.c +++ b/drivers/serial/mpc52xx_uart.c | |||
@@ -591,8 +591,8 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, | |||
591 | /* Update the per-port timeout */ | 591 | /* Update the per-port timeout */ |
592 | uart_update_timeout(port, new->c_cflag, baud); | 592 | uart_update_timeout(port, new->c_cflag, baud); |
593 | 593 | ||
594 | /* Do our best to flush TX & RX, so we don't loose anything */ | 594 | /* Do our best to flush TX & RX, so we don't lose anything */ |
595 | /* But we don't wait indefinitly ! */ | 595 | /* But we don't wait indefinitely ! */ |
596 | j = 5000000; /* Maximum wait */ | 596 | j = 5000000; /* Maximum wait */ |
597 | /* FIXME Can't receive chars since set_termios might be called at early | 597 | /* FIXME Can't receive chars since set_termios might be called at early |
598 | * boot for the console, all stuff is not yet ready to receive at that | 598 | * boot for the console, all stuff is not yet ready to receive at that |
diff --git a/drivers/serial/netx-serial.c b/drivers/serial/netx-serial.c index 3f489329e8d3..3e5dda8518b7 100644 --- a/drivers/serial/netx-serial.c +++ b/drivers/serial/netx-serial.c | |||
@@ -42,8 +42,6 @@ | |||
42 | #define SERIAL_NX_MAJOR 204 | 42 | #define SERIAL_NX_MAJOR 204 |
43 | #define MINOR_START 170 | 43 | #define MINOR_START 170 |
44 | 44 | ||
45 | #ifdef CONFIG_SERIAL_NETX_CONSOLE | ||
46 | |||
47 | enum uart_regs { | 45 | enum uart_regs { |
48 | UART_DR = 0x00, | 46 | UART_DR = 0x00, |
49 | UART_SR = 0x04, | 47 | UART_SR = 0x04, |
@@ -528,6 +526,8 @@ static struct netx_port netx_ports[] = { | |||
528 | } | 526 | } |
529 | }; | 527 | }; |
530 | 528 | ||
529 | #ifdef CONFIG_SERIAL_NETX_CONSOLE | ||
530 | |||
531 | static void netx_console_putchar(struct uart_port *port, int ch) | 531 | static void netx_console_putchar(struct uart_port *port, int ch) |
532 | { | 532 | { |
533 | while (readl(port->membase + UART_FR) & FR_BUSY); | 533 | while (readl(port->membase + UART_FR) & FR_BUSY); |
diff --git a/drivers/serial/s3c2440.c b/drivers/serial/s3c2440.c index 317d239ab740..29cbb0afef8e 100644 --- a/drivers/serial/s3c2440.c +++ b/drivers/serial/s3c2440.c | |||
@@ -177,5 +177,5 @@ module_exit(s3c2440_serial_exit); | |||
177 | 177 | ||
178 | MODULE_DESCRIPTION("Samsung S3C2440,S3C2442 SoC Serial port driver"); | 178 | MODULE_DESCRIPTION("Samsung S3C2440,S3C2442 SoC Serial port driver"); |
179 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | 179 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); |
180 | MODULE_LICENSE("GPLi v2"); | 180 | MODULE_LICENSE("GPL v2"); |
181 | MODULE_ALIAS("platform:s3c2440-uart"); | 181 | MODULE_ALIAS("platform:s3c2440-uart"); |
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c index f0658d2c45b2..165fc010978c 100644 --- a/drivers/serial/sh-sci.c +++ b/drivers/serial/sh-sci.c | |||
@@ -144,9 +144,9 @@ static void put_char(struct uart_port *port, char c) | |||
144 | status = sci_in(port, SCxSR); | 144 | status = sci_in(port, SCxSR); |
145 | } while (!(status & SCxSR_TDxE(port))); | 145 | } while (!(status & SCxSR_TDxE(port))); |
146 | 146 | ||
147 | sci_out(port, SCxTDR, c); | ||
148 | sci_in(port, SCxSR); /* Dummy read */ | 147 | sci_in(port, SCxSR); /* Dummy read */ |
149 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | 148 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); |
149 | sci_out(port, SCxTDR, c); | ||
150 | 150 | ||
151 | spin_unlock_irqrestore(&port->lock, flags); | 151 | spin_unlock_irqrestore(&port->lock, flags); |
152 | } | 152 | } |
@@ -250,8 +250,7 @@ static inline void h8300_sci_disable(struct uart_port *port) | |||
250 | } | 250 | } |
251 | #endif | 251 | #endif |
252 | 252 | ||
253 | #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \ | 253 | #if defined(__H8300H__) || defined(__H8300S__) |
254 | defined(__H8300H__) || defined(__H8300S__) | ||
255 | static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag) | 254 | static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag) |
256 | { | 255 | { |
257 | int ch = (port->mapbase - SMR0) >> 3; | 256 | int ch = (port->mapbase - SMR0) >> 3; |
@@ -285,11 +284,6 @@ static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag) | |||
285 | #define sci_init_pins_irda NULL | 284 | #define sci_init_pins_irda NULL |
286 | #endif | 285 | #endif |
287 | 286 | ||
288 | #ifdef SCI_ONLY | ||
289 | #define sci_init_pins_scif NULL | ||
290 | #endif | ||
291 | |||
292 | #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF) | ||
293 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) | 287 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
294 | static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag) | 288 | static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag) |
295 | { | 289 | { |
@@ -449,7 +443,6 @@ static inline int scif_rxroom(struct uart_port *port) | |||
449 | return sci_in(port, SCFDR) & SCIF_RFDC_MASK; | 443 | return sci_in(port, SCFDR) & SCIF_RFDC_MASK; |
450 | } | 444 | } |
451 | #endif | 445 | #endif |
452 | #endif /* SCIF_ONLY || SCI_AND_SCIF */ | ||
453 | 446 | ||
454 | static inline int sci_txroom(struct uart_port *port) | 447 | static inline int sci_txroom(struct uart_port *port) |
455 | { | 448 | { |
@@ -485,12 +478,10 @@ static void sci_transmit_chars(struct uart_port *port) | |||
485 | return; | 478 | return; |
486 | } | 479 | } |
487 | 480 | ||
488 | #ifndef SCI_ONLY | 481 | if (port->type == PORT_SCI) |
489 | if (port->type == PORT_SCIF) | ||
490 | count = scif_txroom(port); | ||
491 | else | ||
492 | #endif | ||
493 | count = sci_txroom(port); | 482 | count = sci_txroom(port); |
483 | else | ||
484 | count = scif_txroom(port); | ||
494 | 485 | ||
495 | do { | 486 | do { |
496 | unsigned char c; | 487 | unsigned char c; |
@@ -519,12 +510,10 @@ static void sci_transmit_chars(struct uart_port *port) | |||
519 | } else { | 510 | } else { |
520 | ctrl = sci_in(port, SCSCR); | 511 | ctrl = sci_in(port, SCSCR); |
521 | 512 | ||
522 | #if !defined(SCI_ONLY) | 513 | if (port->type != PORT_SCI) { |
523 | if (port->type == PORT_SCIF) { | ||
524 | sci_in(port, SCxSR); /* Dummy read */ | 514 | sci_in(port, SCxSR); /* Dummy read */ |
525 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | 515 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); |
526 | } | 516 | } |
527 | #endif | ||
528 | 517 | ||
529 | ctrl |= SCI_CTRL_FLAGS_TIE; | 518 | ctrl |= SCI_CTRL_FLAGS_TIE; |
530 | sci_out(port, SCSCR, ctrl); | 519 | sci_out(port, SCSCR, ctrl); |
@@ -547,12 +536,10 @@ static inline void sci_receive_chars(struct uart_port *port) | |||
547 | return; | 536 | return; |
548 | 537 | ||
549 | while (1) { | 538 | while (1) { |
550 | #if !defined(SCI_ONLY) | 539 | if (port->type == PORT_SCI) |
551 | if (port->type == PORT_SCIF) | ||
552 | count = scif_rxroom(port); | ||
553 | else | ||
554 | #endif | ||
555 | count = sci_rxroom(port); | 540 | count = sci_rxroom(port); |
541 | else | ||
542 | count = scif_rxroom(port); | ||
556 | 543 | ||
557 | /* Don't copy more bytes than there is room for in the buffer */ | 544 | /* Don't copy more bytes than there is room for in the buffer */ |
558 | count = tty_buffer_request_room(tty, count); | 545 | count = tty_buffer_request_room(tty, count); |
@@ -727,7 +714,7 @@ static inline int sci_handle_breaks(struct uart_port *port) | |||
727 | 714 | ||
728 | #if defined(SCIF_ORER) | 715 | #if defined(SCIF_ORER) |
729 | /* XXX: Handle SCIF overrun error */ | 716 | /* XXX: Handle SCIF overrun error */ |
730 | if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) { | 717 | if (port->type != PORT_SCI && (sci_in(port, SCLSR) & SCIF_ORER) != 0) { |
731 | sci_out(port, SCLSR, 0); | 718 | sci_out(port, SCLSR, 0); |
732 | if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) { | 719 | if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) { |
733 | copied++; | 720 | copied++; |
@@ -810,26 +797,27 @@ static irqreturn_t sci_br_interrupt(int irq, void *ptr) | |||
810 | 797 | ||
811 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) | 798 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) |
812 | { | 799 | { |
813 | unsigned short ssr_status, scr_status; | 800 | unsigned short ssr_status, scr_status; |
814 | struct uart_port *port = ptr; | 801 | struct uart_port *port = ptr; |
802 | irqreturn_t ret = IRQ_NONE; | ||
815 | 803 | ||
816 | ssr_status = sci_in(port,SCxSR); | 804 | ssr_status = sci_in(port,SCxSR); |
817 | scr_status = sci_in(port,SCSCR); | 805 | scr_status = sci_in(port,SCSCR); |
818 | 806 | ||
819 | /* Tx Interrupt */ | 807 | /* Tx Interrupt */ |
820 | if ((ssr_status & 0x0020) && (scr_status & 0x0080)) | 808 | if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE)) |
821 | sci_tx_interrupt(irq, ptr); | 809 | ret = sci_tx_interrupt(irq, ptr); |
822 | /* Rx Interrupt */ | 810 | /* Rx Interrupt */ |
823 | if ((ssr_status & 0x0002) && (scr_status & 0x0040)) | 811 | if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE)) |
824 | sci_rx_interrupt(irq, ptr); | 812 | ret = sci_rx_interrupt(irq, ptr); |
825 | /* Error Interrupt */ | 813 | /* Error Interrupt */ |
826 | if ((ssr_status & 0x0080) && (scr_status & 0x0400)) | 814 | if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE)) |
827 | sci_er_interrupt(irq, ptr); | 815 | ret = sci_er_interrupt(irq, ptr); |
828 | /* Break Interrupt */ | 816 | /* Break Interrupt */ |
829 | if ((ssr_status & 0x0010) && (scr_status & 0x0200)) | 817 | if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE)) |
830 | sci_br_interrupt(irq, ptr); | 818 | ret = sci_br_interrupt(irq, ptr); |
831 | 819 | ||
832 | return IRQ_HANDLED; | 820 | return ret; |
833 | } | 821 | } |
834 | 822 | ||
835 | #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK) | 823 | #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK) |
@@ -1054,10 +1042,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, | |||
1054 | 1042 | ||
1055 | sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ | 1043 | sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ |
1056 | 1044 | ||
1057 | #if !defined(SCI_ONLY) | 1045 | if (port->type != PORT_SCI) |
1058 | if (port->type == PORT_SCIF) | ||
1059 | sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); | 1046 | sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); |
1060 | #endif | ||
1061 | 1047 | ||
1062 | smr_val = sci_in(port, SCSMR) & 3; | 1048 | smr_val = sci_in(port, SCSMR) & 3; |
1063 | if ((termios->c_cflag & CSIZE) == CS7) | 1049 | if ((termios->c_cflag & CSIZE) == CS7) |
@@ -1099,6 +1085,7 @@ static const char *sci_type(struct uart_port *port) | |||
1099 | case PORT_SCI: return "sci"; | 1085 | case PORT_SCI: return "sci"; |
1100 | case PORT_SCIF: return "scif"; | 1086 | case PORT_SCIF: return "scif"; |
1101 | case PORT_IRDA: return "irda"; | 1087 | case PORT_IRDA: return "irda"; |
1088 | case PORT_SCIFA: return "scifa"; | ||
1102 | } | 1089 | } |
1103 | 1090 | ||
1104 | return NULL; | 1091 | return NULL; |
@@ -1126,6 +1113,7 @@ static void sci_config_port(struct uart_port *port, int flags) | |||
1126 | s->init_pins = sci_init_pins_sci; | 1113 | s->init_pins = sci_init_pins_sci; |
1127 | break; | 1114 | break; |
1128 | case PORT_SCIF: | 1115 | case PORT_SCIF: |
1116 | case PORT_SCIFA: | ||
1129 | s->init_pins = sci_init_pins_scif; | 1117 | s->init_pins = sci_init_pins_scif; |
1130 | break; | 1118 | break; |
1131 | case PORT_IRDA: | 1119 | case PORT_IRDA: |
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index 7cd28b226800..9f33b064172e 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h | |||
@@ -16,7 +16,6 @@ | |||
16 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ | 16 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ |
17 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ | 17 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ |
18 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | 18 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
19 | # define SCI_AND_SCIF | ||
20 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | 19 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) |
21 | # define SCIF0 0xA4400000 | 20 | # define SCIF0 0xA4400000 |
22 | # define SCIF2 0xA4410000 | 21 | # define SCIF2 0xA4410000 |
@@ -30,17 +29,15 @@ | |||
30 | * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output | 29 | * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output |
31 | */ | 30 | */ |
32 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 | 31 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 |
33 | # define SCIF_ONLY | ||
34 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 32 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
35 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 33 | defined(CONFIG_CPU_SUBTYPE_SH7721) |
36 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ | 34 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ |
37 | # define SCIF_ONLY | ||
38 | #define SCIF_ORER 0x0200 /* overrun error bit */ | 35 | #define SCIF_ORER 0x0200 /* overrun error bit */ |
39 | #elif defined(CONFIG_SH_RTS7751R2D) | 36 | #elif defined(CONFIG_SH_RTS7751R2D) |
37 | # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ | ||
40 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | 38 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
41 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 39 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
42 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 40 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
43 | # define SCIF_ONLY | ||
44 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ | 41 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
45 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | 42 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ |
46 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | 43 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ |
@@ -53,28 +50,24 @@ | |||
53 | # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ | 50 | # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ |
54 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ | 51 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ |
55 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) | 52 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) |
56 | # define SCI_AND_SCIF | ||
57 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | 53 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
58 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ | 54 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ |
59 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ | 55 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ |
60 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ | 56 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ |
61 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 57 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
62 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 58 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
63 | # define SCIF_ONLY | ||
64 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) | 59 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
65 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ | 60 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ |
66 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 61 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
67 | # define PACR 0xa4050100 | 62 | # define PACR 0xa4050100 |
68 | # define PBCR 0xa4050102 | 63 | # define PBCR 0xa4050102 |
69 | # define SCSCR_INIT(port) 0x3B | 64 | # define SCSCR_INIT(port) 0x3B |
70 | # define SCIF_ONLY | ||
71 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) | 65 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
72 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ | 66 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ |
73 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ | 67 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ |
74 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ | 68 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ |
75 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ | 69 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ |
76 | # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ | 70 | # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ |
77 | # define SCIF_ONLY | ||
78 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) | 71 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
79 | # define PADR 0xA4050120 | 72 | # define PADR 0xA4050120 |
80 | # define PSDR 0xA405013e | 73 | # define PSDR 0xA405013e |
@@ -82,7 +75,6 @@ | |||
82 | # define PSCR 0xA405011E | 75 | # define PSCR 0xA405011E |
83 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 76 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
84 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 77 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
85 | # define SCIF_ONLY | ||
86 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) | 78 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) |
87 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ | 79 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ |
88 | # define SCSPTR0 SCPDR0 | 80 | # define SCSPTR0 SCPDR0 |
@@ -97,12 +89,10 @@ | |||
97 | # define SCSPTR5 0xa4050128 | 89 | # define SCSPTR5 0xa4050128 |
98 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 90 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
99 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 91 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
100 | # define SCIF_ONLY | ||
101 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) | 92 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
102 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ | 93 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ |
103 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 94 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
104 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 95 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
105 | # define SCIF_ONLY | ||
106 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | 96 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
107 | # define SCIF_BASE_ADDR 0x01030000 | 97 | # define SCIF_BASE_ADDR 0x01030000 |
108 | # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR | 98 | # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR |
@@ -111,14 +101,11 @@ | |||
111 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ | 101 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ |
112 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ | 102 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ |
113 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ | 103 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ |
114 | # define SCIF_ONLY | ||
115 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) | 104 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) |
116 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | 105 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
117 | # define SCI_ONLY | ||
118 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | 106 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
119 | #elif defined(CONFIG_H8S2678) | 107 | #elif defined(CONFIG_H8S2678) |
120 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | 108 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
121 | # define SCI_ONLY | ||
122 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | 109 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
123 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) | 110 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
124 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | 111 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ |
@@ -126,20 +113,17 @@ | |||
126 | # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ | 113 | # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ |
127 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 114 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
128 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 115 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
129 | # define SCIF_ONLY | ||
130 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) | 116 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
131 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ | 117 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ |
132 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ | 118 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ |
133 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ | 119 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ |
134 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 120 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
135 | # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ | 121 | # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ |
136 | # define SCIF_ONLY | ||
137 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | 122 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
138 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | 123 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ |
139 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ | 124 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ |
140 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | 125 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
141 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 126 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
142 | # define SCIF_ONLY | ||
143 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) | 127 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) |
144 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ | 128 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ |
145 | # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ | 129 | # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ |
@@ -149,7 +133,6 @@ | |||
149 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ | 133 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ |
150 | # define SCIF_OPER 0x0001 /* Overrun error bit */ | 134 | # define SCIF_OPER 0x0001 /* Overrun error bit */ |
151 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 135 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
152 | # define SCIF_ONLY | ||
153 | #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ | 136 | #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ |
154 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ | 137 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ |
155 | defined(CONFIG_CPU_SUBTYPE_SH7263) | 138 | defined(CONFIG_CPU_SUBTYPE_SH7263) |
@@ -158,14 +141,12 @@ | |||
158 | # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ | 141 | # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ |
159 | # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ | 142 | # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ |
160 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 143 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
161 | # define SCIF_ONLY | ||
162 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | 144 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) |
163 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ | 145 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ |
164 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ | 146 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ |
165 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ | 147 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ |
166 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 148 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
167 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 149 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
168 | # define SCIF_ONLY | ||
169 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) | 150 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) |
170 | # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ | 151 | # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ |
171 | # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ | 152 | # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ |
@@ -173,7 +154,6 @@ | |||
173 | # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ | 154 | # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ |
174 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | 155 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
175 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 156 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
176 | # define SCIF_ONLY | ||
177 | #else | 157 | #else |
178 | # error CPU subtype not defined | 158 | # error CPU subtype not defined |
179 | #endif | 159 | #endif |
@@ -186,6 +166,7 @@ | |||
186 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ | 166 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
187 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | 167 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ |
188 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | 168 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ |
169 | defined(CONFIG_CPU_SUBTYPE_SH7722) || \ | ||
189 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | 170 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ |
190 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | 171 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ |
191 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | 172 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ |
@@ -244,55 +225,28 @@ | |||
244 | # define SCIF_TXROOM_MAX 16 | 225 | # define SCIF_TXROOM_MAX 16 |
245 | #endif | 226 | #endif |
246 | 227 | ||
247 | #if defined(SCI_ONLY) | 228 | #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) |
248 | # define SCxSR_TEND(port) SCI_TEND | 229 | #define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) |
249 | # define SCxSR_ERRORS(port) SCI_ERRORS | 230 | #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) |
250 | # define SCxSR_RDxF(port) SCI_RDRF | 231 | #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) |
251 | # define SCxSR_TDxE(port) SCI_TDRE | 232 | #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) |
252 | # define SCxSR_ORER(port) SCI_ORER | 233 | #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) |
253 | # define SCxSR_FER(port) SCI_FER | 234 | #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) |
254 | # define SCxSR_PER(port) SCI_PER | 235 | |
255 | # define SCxSR_BRK(port) 0x00 | ||
256 | # define SCxSR_RDxF_CLEAR(port) 0xbc | ||
257 | # define SCxSR_ERROR_CLEAR(port) 0xc4 | ||
258 | # define SCxSR_TDxE_CLEAR(port) 0x78 | ||
259 | # define SCxSR_BREAK_CLEAR(port) 0xc4 | ||
260 | #elif defined(SCIF_ONLY) | ||
261 | # define SCxSR_TEND(port) SCIF_TEND | ||
262 | # define SCxSR_ERRORS(port) SCIF_ERRORS | ||
263 | # define SCxSR_RDxF(port) SCIF_RDF | ||
264 | # define SCxSR_TDxE(port) SCIF_TDFE | ||
265 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) | 236 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) |
266 | # define SCxSR_ORER(port) SCIF_ORER | 237 | # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) |
267 | #else | 238 | #else |
268 | # define SCxSR_ORER(port) 0x0000 | 239 | # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000) |
269 | #endif | 240 | #endif |
270 | # define SCxSR_FER(port) SCIF_FER | 241 | |
271 | # define SCxSR_PER(port) SCIF_PER | ||
272 | # define SCxSR_BRK(port) SCIF_BRK | ||
273 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 242 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
274 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 243 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
275 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 244 | defined(CONFIG_CPU_SUBTYPE_SH7721) |
276 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) | 245 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) |
277 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) | 246 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) |
278 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) | 247 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) |
279 | # define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3) | 248 | # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) |
280 | #else | ||
281 | /* SH7705 can also use this, clearing is same between 7705 and 7709 */ | ||
282 | # define SCxSR_RDxF_CLEAR(port) 0x00fc | ||
283 | # define SCxSR_ERROR_CLEAR(port) 0x0073 | ||
284 | # define SCxSR_TDxE_CLEAR(port) 0x00df | ||
285 | # define SCxSR_BREAK_CLEAR(port) 0x00e3 | ||
286 | #endif | ||
287 | #else | 249 | #else |
288 | # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) | ||
289 | # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) | ||
290 | # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) | ||
291 | # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) | ||
292 | # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000) | ||
293 | # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) | ||
294 | # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) | ||
295 | # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) | ||
296 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) | 250 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) |
297 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) | 251 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) |
298 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) | 252 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) |
@@ -335,18 +289,18 @@ | |||
335 | #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ | 289 | #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ |
336 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | 290 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ |
337 | { \ | 291 | { \ |
338 | if (port->type == PORT_SCI) { \ | 292 | if (port->type == PORT_SCIF) { \ |
339 | SCI_IN(sci_size, sci_offset) \ | 293 | SCI_IN(scif_size, scif_offset) \ |
340 | } else { \ | 294 | } else { /* PORT_SCI or PORT_SCIFA */ \ |
341 | SCI_IN(scif_size, scif_offset); \ | 295 | SCI_IN(sci_size, sci_offset); \ |
342 | } \ | 296 | } \ |
343 | } \ | 297 | } \ |
344 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | 298 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ |
345 | { \ | 299 | { \ |
346 | if (port->type == PORT_SCI) { \ | 300 | if (port->type == PORT_SCIF) { \ |
347 | SCI_OUT(sci_size, sci_offset, value) \ | 301 | SCI_OUT(scif_size, scif_offset, value) \ |
348 | } else { \ | 302 | } else { /* PORT_SCI or PORT_SCIFA */ \ |
349 | SCI_OUT(scif_size, scif_offset, value); \ | 303 | SCI_OUT(sci_size, sci_offset, value); \ |
350 | } \ | 304 | } \ |
351 | } | 305 | } |
352 | 306 | ||
@@ -574,18 +528,20 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
574 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | 528 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ |
575 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | 529 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ |
576 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | 530 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ |
577 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | 531 | defined(CONFIG_CPU_SUBTYPE_SH7091) |
578 | defined(CONFIG_CPU_SUBTYPE_SH4_202) | ||
579 | static inline int sci_rxd_in(struct uart_port *port) | 532 | static inline int sci_rxd_in(struct uart_port *port) |
580 | { | 533 | { |
581 | #ifndef SCIF_ONLY | ||
582 | if (port->mapbase == 0xffe00000) | 534 | if (port->mapbase == 0xffe00000) |
583 | return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ | 535 | return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ |
584 | #endif | ||
585 | #ifndef SCI_ONLY | ||
586 | if (port->mapbase == 0xffe80000) | 536 | if (port->mapbase == 0xffe80000) |
587 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | 537 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ |
588 | #endif | 538 | return 1; |
539 | } | ||
540 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) | ||
541 | static inline int sci_rxd_in(struct uart_port *port) | ||
542 | { | ||
543 | if (port->mapbase == 0xffe80000) | ||
544 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | ||
589 | return 1; | 545 | return 1; |
590 | } | 546 | } |
591 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | 547 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
@@ -651,7 +607,7 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
651 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | 607 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
652 | static inline int sci_rxd_in(struct uart_port *port) | 608 | static inline int sci_rxd_in(struct uart_port *port) |
653 | { | 609 | { |
654 | return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */ | 610 | return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ |
655 | } | 611 | } |
656 | #elif defined(__H8300H__) || defined(__H8300S__) | 612 | #elif defined(__H8300H__) || defined(__H8300S__) |
657 | static inline int sci_rxd_in(struct uart_port *port) | 613 | static inline int sci_rxd_in(struct uart_port *port) |
diff --git a/drivers/serial/uartlite.c b/drivers/serial/uartlite.c index 6a3f8fb0c9dd..3317148a4b93 100644 --- a/drivers/serial/uartlite.c +++ b/drivers/serial/uartlite.c | |||
@@ -286,8 +286,8 @@ static void ulite_release_port(struct uart_port *port) | |||
286 | 286 | ||
287 | static int ulite_request_port(struct uart_port *port) | 287 | static int ulite_request_port(struct uart_port *port) |
288 | { | 288 | { |
289 | pr_debug("ulite console: port=%p; port->mapbase=%x\n", | 289 | pr_debug("ulite console: port=%p; port->mapbase=%llx\n", |
290 | port, port->mapbase); | 290 | port, (unsigned long long) port->mapbase); |
291 | 291 | ||
292 | if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { | 292 | if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { |
293 | dev_err(port->dev, "Memory region busy\n"); | 293 | dev_err(port->dev, "Memory region busy\n"); |