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-rw-r--r--drivers/serial/Kconfig36
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/amba-pl010.c2
-rw-r--r--drivers/serial/at91_serial.c463
-rw-r--r--drivers/serial/ioc4_serial.c9
-rw-r--r--drivers/serial/netx-serial.c749
-rw-r--r--drivers/serial/pxa.c1
-rw-r--r--drivers/serial/sunsu.c4
-rw-r--r--drivers/serial/sunzilog.c4
9 files changed, 1072 insertions, 197 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 7d22dc0478d3..bef4a9622ed7 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -300,21 +300,22 @@ config SERIAL_AMBA_PL011_CONSOLE
300 kernel at boot time.) 300 kernel at boot time.)
301 301
302config SERIAL_AT91 302config SERIAL_AT91
303 bool "AT91RM9200 serial port support" 303 bool "AT91RM9200 / AT91SAM9261 serial port support"
304 depends on ARM && ARCH_AT91RM9200 304 depends on ARM && (ARCH_AT91RM9200 || ARCH_AT91SAM9261)
305 select SERIAL_CORE 305 select SERIAL_CORE
306 help 306 help
307 This enables the driver for the on-chip UARTs of the AT91RM9200 307 This enables the driver for the on-chip UARTs of the Atmel
308 processor. 308 AT91RM9200 and AT91SAM926 processor.
309 309
310config SERIAL_AT91_CONSOLE 310config SERIAL_AT91_CONSOLE
311 bool "Support for console on AT91RM9200 serial port" 311 bool "Support for console on AT91RM9200 / AT91SAM9261 serial port"
312 depends on SERIAL_AT91=y 312 depends on SERIAL_AT91=y
313 select SERIAL_CORE_CONSOLE 313 select SERIAL_CORE_CONSOLE
314 help 314 help
315 Say Y here if you wish to use a UART on the AT91RM9200 as the system 315 Say Y here if you wish to use a UART on the Atmel AT91RM9200 or
316 console (the system console is the device which receives all kernel 316 AT91SAM9261 as the system console (the system console is the device
317 messages and warnings and which allows logins in single user mode). 317 which receives all kernel messages and warnings and which allows
318 logins in single user mode).
318 319
319config SERIAL_AT91_TTYAT 320config SERIAL_AT91_TTYAT
320 bool "Install as device ttyAT0-4 instead of ttyS0-4" 321 bool "Install as device ttyAT0-4 instead of ttyS0-4"
@@ -936,4 +937,23 @@ config SERIAL_SGI_IOC3
936 If you have an SGI Altix with an IOC3 serial card, 937 If you have an SGI Altix with an IOC3 serial card,
937 say Y or M. Otherwise, say N. 938 say Y or M. Otherwise, say N.
938 939
940config SERIAL_NETX
941 bool "NetX serial port support"
942 depends on ARM && ARCH_NETX
943 select SERIAL_CORE
944 help
945 If you have a machine based on a Hilscher NetX SoC you
946 can enable its onboard serial port by enabling this option.
947
948 To compile this driver as a module, choose M here: the
949 module will be called netx-serial.
950
951config SERIAL_NETX_CONSOLE
952 bool "Console on NetX serial port"
953 depends on SERIAL_NETX
954 select SERIAL_CORE_CONSOLE
955 help
956 If you have enabled the serial port on the Motorola IMX
957 CPU you can make it the console by answering Y to this option.
958
939endmenu 959endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 0a71bf68a03f..927faee0362e 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o
55obj-$(CONFIG_SERIAL_SGI_IOC4) += ioc4_serial.o 55obj-$(CONFIG_SERIAL_SGI_IOC4) += ioc4_serial.o
56obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o 56obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o
57obj-$(CONFIG_SERIAL_AT91) += at91_serial.o 57obj-$(CONFIG_SERIAL_AT91) += at91_serial.o
58obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
diff --git a/drivers/serial/amba-pl010.c b/drivers/serial/amba-pl010.c
index 1631414000a2..e920d196d0b1 100644
--- a/drivers/serial/amba-pl010.c
+++ b/drivers/serial/amba-pl010.c
@@ -52,7 +52,7 @@
52 52
53#include <asm/io.h> 53#include <asm/io.h>
54 54
55#define UART_NR 2 55#define UART_NR 8
56 56
57#define SERIAL_AMBA_MAJOR 204 57#define SERIAL_AMBA_MAJOR 204
58#define SERIAL_AMBA_MINOR 16 58#define SERIAL_AMBA_MINOR 16
diff --git a/drivers/serial/at91_serial.c b/drivers/serial/at91_serial.c
index 6547fe0cef96..db5b25fafed4 100644
--- a/drivers/serial/at91_serial.c
+++ b/drivers/serial/at91_serial.c
@@ -2,7 +2,6 @@
2 * linux/drivers/char/at91_serial.c 2 * linux/drivers/char/at91_serial.c
3 * 3 *
4 * Driver for Atmel AT91RM9200 Serial ports 4 * Driver for Atmel AT91RM9200 Serial ports
5 *
6 * Copyright (C) 2003 Rick Bronson 5 * Copyright (C) 2003 Rick Bronson
7 * 6 *
8 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 7 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
@@ -30,17 +29,19 @@
30#include <linux/slab.h> 29#include <linux/slab.h>
31#include <linux/init.h> 30#include <linux/init.h>
32#include <linux/serial.h> 31#include <linux/serial.h>
32#include <linux/clk.h>
33#include <linux/console.h> 33#include <linux/console.h>
34#include <linux/sysrq.h> 34#include <linux/sysrq.h>
35#include <linux/tty_flip.h> 35#include <linux/tty_flip.h>
36#include <linux/platform_device.h>
36 37
37#include <asm/io.h> 38#include <asm/io.h>
38 39
39#include <asm/arch/at91rm9200_usart.h> 40#include <asm/arch/at91rm9200_usart.h>
40#include <asm/mach/serial_at91rm9200.h> 41#include <asm/arch/at91rm9200_pdc.h>
42#include <asm/mach/serial_at91.h>
41#include <asm/arch/board.h> 43#include <asm/arch/board.h>
42#include <asm/arch/pio.h> 44#include <asm/arch/system.h>
43
44 45
45#if defined(CONFIG_SERIAL_AT91_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 46#if defined(CONFIG_SERIAL_AT91_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
46#define SUPPORT_SYSRQ 47#define SUPPORT_SYSRQ
@@ -67,7 +68,6 @@
67 68
68#endif 69#endif
69 70
70#define AT91_VA_BASE_DBGU ((unsigned long) AT91_VA_BASE_SYS + AT91_DBGU)
71#define AT91_ISR_PASS_LIMIT 256 71#define AT91_ISR_PASS_LIMIT 256
72 72
73#define UART_PUT_CR(port,v) writel(v, (port)->membase + AT91_US_CR) 73#define UART_PUT_CR(port,v) writel(v, (port)->membase + AT91_US_CR)
@@ -87,16 +87,33 @@
87 87
88 /* PDC registers */ 88 /* PDC registers */
89#define UART_PUT_PTCR(port,v) writel(v, (port)->membase + AT91_PDC_PTCR) 89#define UART_PUT_PTCR(port,v) writel(v, (port)->membase + AT91_PDC_PTCR)
90#define UART_GET_PTSR(port) readl((port)->membase + AT91_PDC_PTSR)
91
90#define UART_PUT_RPR(port,v) writel(v, (port)->membase + AT91_PDC_RPR) 92#define UART_PUT_RPR(port,v) writel(v, (port)->membase + AT91_PDC_RPR)
93#define UART_GET_RPR(port) readl((port)->membase + AT91_PDC_RPR)
91#define UART_PUT_RCR(port,v) writel(v, (port)->membase + AT91_PDC_RCR) 94#define UART_PUT_RCR(port,v) writel(v, (port)->membase + AT91_PDC_RCR)
92#define UART_GET_RCR(port) readl((port)->membase + AT91_PDC_RCR)
93#define UART_PUT_RNPR(port,v) writel(v, (port)->membase + AT91_PDC_RNPR) 95#define UART_PUT_RNPR(port,v) writel(v, (port)->membase + AT91_PDC_RNPR)
94#define UART_PUT_RNCR(port,v) writel(v, (port)->membase + AT91_PDC_RNCR) 96#define UART_PUT_RNCR(port,v) writel(v, (port)->membase + AT91_PDC_RNCR)
95 97
98#define UART_PUT_TPR(port,v) writel(v, (port)->membase + AT91_PDC_TPR)
99#define UART_PUT_TCR(port,v) writel(v, (port)->membase + AT91_PDC_TCR)
100//#define UART_PUT_TNPR(port,v) writel(v, (port)->membase + AT91_PDC_TNPR)
101//#define UART_PUT_TNCR(port,v) writel(v, (port)->membase + AT91_PDC_TNCR)
96 102
97static int (*at91_open)(struct uart_port *); 103static int (*at91_open)(struct uart_port *);
98static void (*at91_close)(struct uart_port *); 104static void (*at91_close)(struct uart_port *);
99 105
106/*
107 * We wrap our port structure around the generic uart_port.
108 */
109struct at91_uart_port {
110 struct uart_port uart; /* uart */
111 struct clk *clk; /* uart clock */
112 unsigned short suspended; /* is port suspended? */
113};
114
115static struct at91_uart_port at91_ports[AT91_NR_UART];
116
100#ifdef SUPPORT_SYSRQ 117#ifdef SUPPORT_SYSRQ
101static struct console at91_console; 118static struct console at91_console;
102#endif 119#endif
@@ -115,16 +132,19 @@ static u_int at91_tx_empty(struct uart_port *port)
115static void at91_set_mctrl(struct uart_port *port, u_int mctrl) 132static void at91_set_mctrl(struct uart_port *port, u_int mctrl)
116{ 133{
117 unsigned int control = 0; 134 unsigned int control = 0;
135 unsigned int mode;
118 136
119 /* 137 if (arch_identify() == ARCH_ID_AT91RM9200) {
120 * Errata #39: RTS0 is not internally connected to PA21. We need to drive 138 /*
121 * the pin manually. 139 * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21.
122 */ 140 * We need to drive the pin manually.
123 if (port->mapbase == AT91_VA_BASE_US0) { 141 */
124 if (mctrl & TIOCM_RTS) 142 if (port->mapbase == AT91_BASE_US0) {
125 at91_sys_write(AT91_PIOA + PIO_CODR, AT91_PA21_RTS0); 143 if (mctrl & TIOCM_RTS)
126 else 144 at91_sys_write(AT91_PIOA + PIO_CODR, AT91_PA21_RTS0);
127 at91_sys_write(AT91_PIOA + PIO_SODR, AT91_PA21_RTS0); 145 else
146 at91_sys_write(AT91_PIOA + PIO_SODR, AT91_PA21_RTS0);
147 }
128 } 148 }
129 149
130 if (mctrl & TIOCM_RTS) 150 if (mctrl & TIOCM_RTS)
@@ -137,7 +157,15 @@ static void at91_set_mctrl(struct uart_port *port, u_int mctrl)
137 else 157 else
138 control |= AT91_US_DTRDIS; 158 control |= AT91_US_DTRDIS;
139 159
140 UART_PUT_CR(port,control); 160 UART_PUT_CR(port, control);
161
162 /* Local loopback mode? */
163 mode = UART_GET_MR(port) & ~AT91_US_CHMODE;
164 if (mctrl & TIOCM_LOOP)
165 mode |= AT91_US_CHMODE_LOC_LOOP;
166 else
167 mode |= AT91_US_CHMODE_NORMAL;
168 UART_PUT_MR(port, mode);
141} 169}
142 170
143/* 171/*
@@ -169,8 +197,9 @@ static u_int at91_get_mctrl(struct uart_port *port)
169 */ 197 */
170static void at91_stop_tx(struct uart_port *port) 198static void at91_stop_tx(struct uart_port *port)
171{ 199{
200 struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
201
172 UART_PUT_IDR(port, AT91_US_TXRDY); 202 UART_PUT_IDR(port, AT91_US_TXRDY);
173 port->read_status_mask &= ~AT91_US_TXRDY;
174} 203}
175 204
176/* 205/*
@@ -178,7 +207,8 @@ static void at91_stop_tx(struct uart_port *port)
178 */ 207 */
179static void at91_start_tx(struct uart_port *port) 208static void at91_start_tx(struct uart_port *port)
180{ 209{
181 port->read_status_mask |= AT91_US_TXRDY; 210 struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
211
182 UART_PUT_IER(port, AT91_US_TXRDY); 212 UART_PUT_IER(port, AT91_US_TXRDY);
183} 213}
184 214
@@ -187,6 +217,8 @@ static void at91_start_tx(struct uart_port *port)
187 */ 217 */
188static void at91_stop_rx(struct uart_port *port) 218static void at91_stop_rx(struct uart_port *port)
189{ 219{
220 struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
221
190 UART_PUT_IDR(port, AT91_US_RXRDY); 222 UART_PUT_IDR(port, AT91_US_RXRDY);
191} 223}
192 224
@@ -195,7 +227,6 @@ static void at91_stop_rx(struct uart_port *port)
195 */ 227 */
196static void at91_enable_ms(struct uart_port *port) 228static void at91_enable_ms(struct uart_port *port)
197{ 229{
198 port->read_status_mask |= (AT91_US_RIIC | AT91_US_DSRIC | AT91_US_DCDIC | AT91_US_CTSIC);
199 UART_PUT_IER(port, AT91_US_RIIC | AT91_US_DSRIC | AT91_US_DCDIC | AT91_US_CTSIC); 230 UART_PUT_IER(port, AT91_US_RIIC | AT91_US_DSRIC | AT91_US_DCDIC | AT91_US_CTSIC);
200} 231}
201 232
@@ -218,8 +249,8 @@ static void at91_rx_chars(struct uart_port *port, struct pt_regs *regs)
218 struct tty_struct *tty = port->info->tty; 249 struct tty_struct *tty = port->info->tty;
219 unsigned int status, ch, flg; 250 unsigned int status, ch, flg;
220 251
221 status = UART_GET_CSR(port) & port->read_status_mask; 252 status = UART_GET_CSR(port);
222 while (status & (AT91_US_RXRDY)) { 253 while (status & AT91_US_RXRDY) {
223 ch = UART_GET_CHAR(port); 254 ch = UART_GET_CHAR(port);
224 255
225 port->icount.rx++; 256 port->icount.rx++;
@@ -230,40 +261,38 @@ static void at91_rx_chars(struct uart_port *port, struct pt_regs *regs)
230 * note that the error handling code is 261 * note that the error handling code is
231 * out of the main execution path 262 * out of the main execution path
232 */ 263 */
233 if (unlikely(status & (AT91_US_PARE | AT91_US_FRAME | AT91_US_OVRE))) { 264 if (unlikely(status & (AT91_US_PARE | AT91_US_FRAME | AT91_US_OVRE | AT91_US_RXBRK))) {
234 UART_PUT_CR(port, AT91_US_RSTSTA); /* clear error */ 265 UART_PUT_CR(port, AT91_US_RSTSTA); /* clear error */
235 if (status & (AT91_US_PARE)) 266 if (status & AT91_US_RXBRK) {
267 status &= ~(AT91_US_PARE | AT91_US_FRAME); /* ignore side-effect */
268 port->icount.brk++;
269 if (uart_handle_break(port))
270 goto ignore_char;
271 }
272 if (status & AT91_US_PARE)
236 port->icount.parity++; 273 port->icount.parity++;
237 if (status & (AT91_US_FRAME)) 274 if (status & AT91_US_FRAME)
238 port->icount.frame++; 275 port->icount.frame++;
239 if (status & (AT91_US_OVRE)) 276 if (status & AT91_US_OVRE)
240 port->icount.overrun++; 277 port->icount.overrun++;
241 278
242 if (status & AT91_US_PARE) 279 status &= port->read_status_mask;
280
281 if (status & AT91_US_RXBRK)
282 flg = TTY_BREAK;
283 else if (status & AT91_US_PARE)
243 flg = TTY_PARITY; 284 flg = TTY_PARITY;
244 else if (status & AT91_US_FRAME) 285 else if (status & AT91_US_FRAME)
245 flg = TTY_FRAME; 286 flg = TTY_FRAME;
246 if (status & AT91_US_OVRE) {
247 /*
248 * overrun does *not* affect the character
249 * we read from the FIFO
250 */
251 tty_insert_flip_char(tty, ch, flg);
252 ch = 0;
253 flg = TTY_OVERRUN;
254 }
255#ifdef SUPPORT_SYSRQ
256 port->sysrq = 0;
257#endif
258 } 287 }
259 288
260 if (uart_handle_sysrq_char(port, ch, regs)) 289 if (uart_handle_sysrq_char(port, ch, regs))
261 goto ignore_char; 290 goto ignore_char;
262 291
263 tty_insert_flip_char(tty, ch, flg); 292 uart_insert_char(port, status, AT91_US_OVRE, ch, flg);
264 293
265 ignore_char: 294 ignore_char:
266 status = UART_GET_CSR(port) & port->read_status_mask; 295 status = UART_GET_CSR(port);
267 } 296 }
268 297
269 tty_flip_buffer_push(tty); 298 tty_flip_buffer_push(tty);
@@ -308,40 +337,35 @@ static void at91_tx_chars(struct uart_port *port)
308static irqreturn_t at91_interrupt(int irq, void *dev_id, struct pt_regs *regs) 337static irqreturn_t at91_interrupt(int irq, void *dev_id, struct pt_regs *regs)
309{ 338{
310 struct uart_port *port = dev_id; 339 struct uart_port *port = dev_id;
340 struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
311 unsigned int status, pending, pass_counter = 0; 341 unsigned int status, pending, pass_counter = 0;
312 342
313 status = UART_GET_CSR(port); 343 status = UART_GET_CSR(port);
314 pending = status & port->read_status_mask; 344 pending = status & UART_GET_IMR(port);
315 if (pending) { 345 while (pending) {
316 do { 346 /* Interrupt receive */
317 if (pending & AT91_US_RXRDY) 347 if (pending & AT91_US_RXRDY)
318 at91_rx_chars(port, regs); 348 at91_rx_chars(port, regs);
319 349
320 /* Clear the relevent break bits */ 350 // TODO: All reads to CSR will clear these interrupts!
321 if (pending & AT91_US_RXBRK) { 351 if (pending & AT91_US_RIIC) port->icount.rng++;
322 UART_PUT_CR(port, AT91_US_RSTSTA); 352 if (pending & AT91_US_DSRIC) port->icount.dsr++;
323 port->icount.brk++; 353 if (pending & AT91_US_DCDIC)
324 uart_handle_break(port); 354 uart_handle_dcd_change(port, !(status & AT91_US_DCD));
325 } 355 if (pending & AT91_US_CTSIC)
356 uart_handle_cts_change(port, !(status & AT91_US_CTS));
357 if (pending & (AT91_US_RIIC | AT91_US_DSRIC | AT91_US_DCDIC | AT91_US_CTSIC))
358 wake_up_interruptible(&port->info->delta_msr_wait);
359
360 /* Interrupt transmit */
361 if (pending & AT91_US_TXRDY)
362 at91_tx_chars(port);
363
364 if (pass_counter++ > AT91_ISR_PASS_LIMIT)
365 break;
326 366
327 // TODO: All reads to CSR will clear these interrupts! 367 status = UART_GET_CSR(port);
328 if (pending & AT91_US_RIIC) port->icount.rng++; 368 pending = status & UART_GET_IMR(port);
329 if (pending & AT91_US_DSRIC) port->icount.dsr++;
330 if (pending & AT91_US_DCDIC)
331 uart_handle_dcd_change(port, !(status & AT91_US_DCD));
332 if (pending & AT91_US_CTSIC)
333 uart_handle_cts_change(port, !(status & AT91_US_CTS));
334 if (pending & (AT91_US_RIIC | AT91_US_DSRIC | AT91_US_DCDIC | AT91_US_CTSIC))
335 wake_up_interruptible(&port->info->delta_msr_wait);
336
337 if (pending & AT91_US_TXRDY)
338 at91_tx_chars(port);
339 if (pass_counter++ > AT91_ISR_PASS_LIMIT)
340 break;
341
342 status = UART_GET_CSR(port);
343 pending = status & port->read_status_mask;
344 } while (pending);
345 } 369 }
346 return IRQ_HANDLED; 370 return IRQ_HANDLED;
347} 371}
@@ -351,6 +375,7 @@ static irqreturn_t at91_interrupt(int irq, void *dev_id, struct pt_regs *regs)
351 */ 375 */
352static int at91_startup(struct uart_port *port) 376static int at91_startup(struct uart_port *port)
353{ 377{
378 struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
354 int retval; 379 int retval;
355 380
356 /* 381 /*
@@ -381,14 +406,14 @@ static int at91_startup(struct uart_port *port)
381 } 406 }
382 } 407 }
383 408
384 port->read_status_mask = AT91_US_RXRDY | AT91_US_TXRDY | AT91_US_OVRE
385 | AT91_US_FRAME | AT91_US_PARE | AT91_US_RXBRK;
386 /* 409 /*
387 * Finally, enable the serial port 410 * Finally, enable the serial port
388 */ 411 */
389 UART_PUT_CR(port, AT91_US_RSTSTA | AT91_US_RSTRX); 412 UART_PUT_CR(port, AT91_US_RSTSTA | AT91_US_RSTRX);
390 UART_PUT_CR(port, AT91_US_TXEN | AT91_US_RXEN); /* enable xmit & rcvr */ 413 UART_PUT_CR(port, AT91_US_TXEN | AT91_US_RXEN); /* enable xmit & rcvr */
391 UART_PUT_IER(port, AT91_US_RXRDY); /* do receive only */ 414
415 UART_PUT_IER(port, AT91_US_RXRDY); /* enable receive only */
416
392 return 0; 417 return 0;
393} 418}
394 419
@@ -397,6 +422,8 @@ static int at91_startup(struct uart_port *port)
397 */ 422 */
398static void at91_shutdown(struct uart_port *port) 423static void at91_shutdown(struct uart_port *port)
399{ 424{
425 struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
426
400 /* 427 /*
401 * Disable all interrupts, port and break condition. 428 * Disable all interrupts, port and break condition.
402 */ 429 */
@@ -421,21 +448,22 @@ static void at91_shutdown(struct uart_port *port)
421 */ 448 */
422static void at91_serial_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) 449static void at91_serial_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
423{ 450{
451 struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
452
424 switch (state) { 453 switch (state) {
425 case 0: 454 case 0:
426 /* 455 /*
427 * Enable the peripheral clock for this serial port. 456 * Enable the peripheral clock for this serial port.
428 * This is called on uart_open() or a resume event. 457 * This is called on uart_open() or a resume event.
429 */ 458 */
430 at91_sys_write(AT91_PMC_PCER, 1 << port->irq); 459 clk_enable(at91_port->clk);
431 break; 460 break;
432 case 3: 461 case 3:
433 /* 462 /*
434 * Disable the peripheral clock for this serial port. 463 * Disable the peripheral clock for this serial port.
435 * This is called on uart_close() or a suspend event. 464 * This is called on uart_close() or a suspend event.
436 */ 465 */
437 if (port->irq != AT91_ID_SYS) /* is this a shared clock? */ 466 clk_disable(at91_port->clk);
438 at91_sys_write(AT91_PMC_PCDR, 1 << port->irq);
439 break; 467 break;
440 default: 468 default:
441 printk(KERN_ERR "at91_serial: unknown pm %d\n", state); 469 printk(KERN_ERR "at91_serial: unknown pm %d\n", state);
@@ -494,9 +522,9 @@ static void at91_set_termios(struct uart_port *port, struct termios * termios, s
494 522
495 spin_lock_irqsave(&port->lock, flags); 523 spin_lock_irqsave(&port->lock, flags);
496 524
497 port->read_status_mask |= AT91_US_OVRE; 525 port->read_status_mask = AT91_US_OVRE;
498 if (termios->c_iflag & INPCK) 526 if (termios->c_iflag & INPCK)
499 port->read_status_mask |= AT91_US_FRAME | AT91_US_PARE; 527 port->read_status_mask |= (AT91_US_FRAME | AT91_US_PARE);
500 if (termios->c_iflag & (BRKINT | PARMRK)) 528 if (termios->c_iflag & (BRKINT | PARMRK))
501 port->read_status_mask |= AT91_US_RXBRK; 529 port->read_status_mask |= AT91_US_RXBRK;
502 530
@@ -552,7 +580,7 @@ static void at91_set_termios(struct uart_port *port, struct termios * termios, s
552 */ 580 */
553static const char *at91_type(struct uart_port *port) 581static const char *at91_type(struct uart_port *port)
554{ 582{
555 return (port->type == PORT_AT91RM9200) ? "AT91_SERIAL" : NULL; 583 return (port->type == PORT_AT91) ? "AT91_SERIAL" : NULL;
556} 584}
557 585
558/* 586/*
@@ -560,8 +588,15 @@ static const char *at91_type(struct uart_port *port)
560 */ 588 */
561static void at91_release_port(struct uart_port *port) 589static void at91_release_port(struct uart_port *port)
562{ 590{
563 release_mem_region(port->mapbase, 591 struct platform_device *pdev = to_platform_device(port->dev);
564 (port->mapbase == AT91_VA_BASE_DBGU) ? 512 : SZ_16K); 592 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
593
594 release_mem_region(port->mapbase, size);
595
596 if (port->flags & UPF_IOREMAP) {
597 iounmap(port->membase);
598 port->membase = NULL;
599 }
565} 600}
566 601
567/* 602/*
@@ -569,10 +604,21 @@ static void at91_release_port(struct uart_port *port)
569 */ 604 */
570static int at91_request_port(struct uart_port *port) 605static int at91_request_port(struct uart_port *port)
571{ 606{
572 return request_mem_region(port->mapbase, 607 struct platform_device *pdev = to_platform_device(port->dev);
573 (port->mapbase == AT91_VA_BASE_DBGU) ? 512 : SZ_16K, 608 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
574 "at91_serial") != NULL ? 0 : -EBUSY; 609
610 if (!request_mem_region(port->mapbase, size, "at91_serial"))
611 return -EBUSY;
612
613 if (port->flags & UPF_IOREMAP) {
614 port->membase = ioremap(port->mapbase, size);
615 if (port->membase == NULL) {
616 release_mem_region(port->mapbase, size);
617 return -ENOMEM;
618 }
619 }
575 620
621 return 0;
576} 622}
577 623
578/* 624/*
@@ -581,7 +627,7 @@ static int at91_request_port(struct uart_port *port)
581static void at91_config_port(struct uart_port *port, int flags) 627static void at91_config_port(struct uart_port *port, int flags)
582{ 628{
583 if (flags & UART_CONFIG_TYPE) { 629 if (flags & UART_CONFIG_TYPE) {
584 port->type = PORT_AT91RM9200; 630 port->type = PORT_AT91;
585 at91_request_port(port); 631 at91_request_port(port);
586 } 632 }
587} 633}
@@ -592,7 +638,7 @@ static void at91_config_port(struct uart_port *port, int flags)
592static int at91_verify_port(struct uart_port *port, struct serial_struct *ser) 638static int at91_verify_port(struct uart_port *port, struct serial_struct *ser)
593{ 639{
594 int ret = 0; 640 int ret = 0;
595 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AT91RM9200) 641 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AT91)
596 ret = -EINVAL; 642 ret = -EINVAL;
597 if (port->irq != ser->irq) 643 if (port->irq != ser->irq)
598 ret = -EINVAL; 644 ret = -EINVAL;
@@ -624,33 +670,47 @@ static struct uart_ops at91_pops = {
624 .type = at91_type, 670 .type = at91_type,
625 .release_port = at91_release_port, 671 .release_port = at91_release_port,
626 .request_port = at91_request_port, 672 .request_port = at91_request_port,
627 .config_port = at91_config_port, 673 .config_port = at91_config_port,
628 .verify_port = at91_verify_port, 674 .verify_port = at91_verify_port,
629 .pm = at91_serial_pm, 675 .pm = at91_serial_pm,
630}; 676};
631 677
632static struct uart_port at91_ports[AT91_NR_UART]; 678/*
633 679 * Configure the port from the platform device resource info.
634void __init at91_init_ports(void) 680 */
681static void __devinit at91_init_port(struct at91_uart_port *at91_port, struct platform_device *pdev)
635{ 682{
636 static int first = 1; 683 struct uart_port *port = &at91_port->uart;
637 int i; 684 struct at91_uart_data *data = pdev->dev.platform_data;
638 685
639 if (!first) 686 port->iotype = UPIO_MEM;
640 return; 687 port->flags = UPF_BOOT_AUTOCONF;
641 first = 0; 688 port->ops = &at91_pops;
689 port->fifosize = 1;
690 port->line = pdev->id;
691 port->dev = &pdev->dev;
692
693 port->mapbase = pdev->resource[0].start;
694 port->irq = pdev->resource[1].start;
695
696 if (port->mapbase == AT91_VA_BASE_SYS + AT91_DBGU) /* Part of system perpherals - already mapped */
697 port->membase = (void __iomem *) port->mapbase;
698 else {
699 port->flags |= UPF_IOREMAP;
700 port->membase = NULL;
701 }
642 702
643 for (i = 0; i < AT91_NR_UART; i++) { 703 if (!at91_port->clk) { /* for console, the clock could already be configured */
644 at91_ports[i].iotype = UPIO_MEM; 704 at91_port->clk = clk_get(&pdev->dev, "usart");
645 at91_ports[i].flags = UPF_BOOT_AUTOCONF; 705 clk_enable(at91_port->clk);
646 at91_ports[i].uartclk = at91_master_clock; 706 port->uartclk = clk_get_rate(at91_port->clk);
647 at91_ports[i].ops = &at91_pops; 707 }
648 at91_ports[i].fifosize = 1;
649 at91_ports[i].line = i;
650 }
651} 708}
652 709
653void __init at91_register_uart_fns(struct at91rm9200_port_fns *fns) 710/*
711 * Register board-specific modem-control line handlers.
712 */
713void __init at91_register_uart_fns(struct at91_port_fns *fns)
654{ 714{
655 if (fns->enable_ms) 715 if (fns->enable_ms)
656 at91_pops.enable_ms = fns->enable_ms; 716 at91_pops.enable_ms = fns->enable_ms;
@@ -664,51 +724,6 @@ void __init at91_register_uart_fns(struct at91rm9200_port_fns *fns)
664 at91_pops.set_wake = fns->set_wake; 724 at91_pops.set_wake = fns->set_wake;
665} 725}
666 726
667/*
668 * Setup ports.
669 */
670void __init at91_register_uart(int idx, int port)
671{
672 if ((idx < 0) || (idx >= AT91_NR_UART)) {
673 printk(KERN_ERR "%s: bad index number %d\n", __FUNCTION__, idx);
674 return;
675 }
676
677 switch (port) {
678 case 0:
679 at91_ports[idx].membase = (void __iomem *) AT91_VA_BASE_US0;
680 at91_ports[idx].mapbase = AT91_VA_BASE_US0;
681 at91_ports[idx].irq = AT91_ID_US0;
682 AT91_CfgPIO_USART0();
683 break;
684 case 1:
685 at91_ports[idx].membase = (void __iomem *) AT91_VA_BASE_US1;
686 at91_ports[idx].mapbase = AT91_VA_BASE_US1;
687 at91_ports[idx].irq = AT91_ID_US1;
688 AT91_CfgPIO_USART1();
689 break;
690 case 2:
691 at91_ports[idx].membase = (void __iomem *) AT91_VA_BASE_US2;
692 at91_ports[idx].mapbase = AT91_VA_BASE_US2;
693 at91_ports[idx].irq = AT91_ID_US2;
694 AT91_CfgPIO_USART2();
695 break;
696 case 3:
697 at91_ports[idx].membase = (void __iomem *) AT91_VA_BASE_US3;
698 at91_ports[idx].mapbase = AT91_VA_BASE_US3;
699 at91_ports[idx].irq = AT91_ID_US3;
700 AT91_CfgPIO_USART3();
701 break;
702 case 4:
703 at91_ports[idx].membase = (void __iomem *) AT91_VA_BASE_DBGU;
704 at91_ports[idx].mapbase = AT91_VA_BASE_DBGU;
705 at91_ports[idx].irq = AT91_ID_SYS;
706 AT91_CfgPIO_DBGU();
707 break;
708 default:
709 printk(KERN_ERR "%s : bad port number %d\n", __FUNCTION__, port);
710 }
711}
712 727
713#ifdef CONFIG_SERIAL_AT91_CONSOLE 728#ifdef CONFIG_SERIAL_AT91_CONSOLE
714static void at91_console_putchar(struct uart_port *port, int ch) 729static void at91_console_putchar(struct uart_port *port, int ch)
@@ -723,7 +738,7 @@ static void at91_console_putchar(struct uart_port *port, int ch)
723 */ 738 */
724static void at91_console_write(struct console *co, const char *s, u_int count) 739static void at91_console_write(struct console *co, const char *s, u_int count)
725{ 740{
726 struct uart_port *port = at91_ports + co->index; 741 struct uart_port *port = &at91_ports[co->index].uart;
727 unsigned int status, imr; 742 unsigned int status, imr;
728 743
729 /* 744 /*
@@ -778,23 +793,15 @@ static void __init at91_console_get_options(struct uart_port *port, int *baud, i
778 793
779static int __init at91_console_setup(struct console *co, char *options) 794static int __init at91_console_setup(struct console *co, char *options)
780{ 795{
781 struct uart_port *port; 796 struct uart_port *port = &at91_ports[co->index].uart;
782 int baud = 115200; 797 int baud = 115200;
783 int bits = 8; 798 int bits = 8;
784 int parity = 'n'; 799 int parity = 'n';
785 int flow = 'n'; 800 int flow = 'n';
786 801
787 /* 802 if (port->membase == 0) /* Port not initialized yet - delay setup */
788 * Check whether an invalid uart number has been specified, and 803 return -ENODEV;
789 * if so, search for the first available port that does have
790 * console support.
791 */
792 port = uart_get_console(at91_ports, AT91_NR_UART, co);
793 804
794 /*
795 * Enable the serial console, in-case bootloader did not do it.
796 */
797 at91_sys_write(AT91_PMC_PCER, 1 << port->irq); /* enable clock */
798 UART_PUT_IDR(port, -1); /* disable interrupts */ 805 UART_PUT_IDR(port, -1); /* disable interrupts */
799 UART_PUT_CR(port, AT91_US_RSTSTA | AT91_US_RSTRX); 806 UART_PUT_CR(port, AT91_US_RSTSTA | AT91_US_RSTRX);
800 UART_PUT_CR(port, AT91_US_TXEN | AT91_US_RXEN); 807 UART_PUT_CR(port, AT91_US_TXEN | AT91_US_RXEN);
@@ -821,23 +828,40 @@ static struct console at91_console = {
821 828
822#define AT91_CONSOLE_DEVICE &at91_console 829#define AT91_CONSOLE_DEVICE &at91_console
823 830
824static int __init at91_console_init(void) 831/*
832 * Early console initialization (before VM subsystem initialized).
833 */
834static int __init at91_console_init(void)
825{ 835{
826 at91_init_ports(); 836 if (at91_default_console_device) {
837 add_preferred_console(AT91_DEVICENAME, at91_default_console_device->id, NULL);
838 at91_init_port(&(at91_ports[at91_default_console_device->id]), at91_default_console_device);
839 register_console(&at91_console);
840 }
827 841
828 at91_console.index = at91_console_port;
829 register_console(&at91_console);
830 return 0; 842 return 0;
831} 843}
832console_initcall(at91_console_init); 844console_initcall(at91_console_init);
833 845
846/*
847 * Late console initialization.
848 */
849static int __init at91_late_console_init(void)
850{
851 if (at91_default_console_device && !(at91_console.flags & CON_ENABLED))
852 register_console(&at91_console);
853
854 return 0;
855}
856core_initcall(at91_late_console_init);
857
834#else 858#else
835#define AT91_CONSOLE_DEVICE NULL 859#define AT91_CONSOLE_DEVICE NULL
836#endif 860#endif
837 861
838static struct uart_driver at91_uart = { 862static struct uart_driver at91_uart = {
839 .owner = THIS_MODULE, 863 .owner = THIS_MODULE,
840 .driver_name = AT91_DEVICENAME, 864 .driver_name = "at91_serial",
841 .dev_name = AT91_DEVICENAME, 865 .dev_name = AT91_DEVICENAME,
842 .devfs_name = AT91_DEVICENAME, 866 .devfs_name = AT91_DEVICENAME,
843 .major = SERIAL_AT91_MAJOR, 867 .major = SERIAL_AT91_MAJOR,
@@ -846,33 +870,106 @@ static struct uart_driver at91_uart = {
846 .cons = AT91_CONSOLE_DEVICE, 870 .cons = AT91_CONSOLE_DEVICE,
847}; 871};
848 872
849static int __init at91_serial_init(void) 873#ifdef CONFIG_PM
874static int at91_serial_suspend(struct platform_device *pdev, pm_message_t state)
850{ 875{
851 int ret, i; 876 struct uart_port *port = platform_get_drvdata(pdev);
877 struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
878
879 if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock())
880 enable_irq_wake(port->irq);
881 else {
882 disable_irq_wake(port->irq);
883 uart_suspend_port(&at91_uart, port);
884 at91_port->suspended = 1;
885 }
852 886
853 at91_init_ports(); 887 return 0;
888}
854 889
855 ret = uart_register_driver(&at91_uart); 890static int at91_serial_resume(struct platform_device *pdev)
856 if (ret) 891{
857 return ret; 892 struct uart_port *port = platform_get_drvdata(pdev);
893 struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
858 894
859 for (i = 0; i < AT91_NR_UART; i++) { 895 if (at91_port->suspended) {
860 if (at91_serial_map[i] >= 0) 896 uart_resume_port(&at91_uart, port);
861 uart_add_one_port(&at91_uart, &at91_ports[i]); 897 at91_port->suspended = 0;
862 } 898 }
863 899
864 return 0; 900 return 0;
865} 901}
902#else
903#define at91_serial_suspend NULL
904#define at91_serial_resume NULL
905#endif
866 906
867static void __exit at91_serial_exit(void) 907static int __devinit at91_serial_probe(struct platform_device *pdev)
868{ 908{
869 int i; 909 struct at91_uart_port *port;
910 int ret;
870 911
871 for (i = 0; i < AT91_NR_UART; i++) { 912 port = &at91_ports[pdev->id];
872 if (at91_serial_map[i] >= 0) 913 at91_init_port(port, pdev);
873 uart_remove_one_port(&at91_uart, &at91_ports[i]);
874 }
875 914
915 ret = uart_add_one_port(&at91_uart, &port->uart);
916 if (!ret) {
917 device_init_wakeup(&pdev->dev, 1);
918 platform_set_drvdata(pdev, port);
919 }
920
921 return ret;
922}
923
924static int __devexit at91_serial_remove(struct platform_device *pdev)
925{
926 struct uart_port *port = platform_get_drvdata(pdev);
927 struct at91_uart_port *at91_port = (struct at91_uart_port *) port;
928 int ret = 0;
929
930 clk_disable(at91_port->clk);
931 clk_put(at91_port->clk);
932
933 device_init_wakeup(&pdev->dev, 0);
934 platform_set_drvdata(pdev, NULL);
935
936 if (port) {
937 ret = uart_remove_one_port(&at91_uart, port);
938 kfree(port);
939 }
940
941 return ret;
942}
943
944static struct platform_driver at91_serial_driver = {
945 .probe = at91_serial_probe,
946 .remove = __devexit_p(at91_serial_remove),
947 .suspend = at91_serial_suspend,
948 .resume = at91_serial_resume,
949 .driver = {
950 .name = "at91_usart",
951 .owner = THIS_MODULE,
952 },
953};
954
955static int __init at91_serial_init(void)
956{
957 int ret;
958
959 ret = uart_register_driver(&at91_uart);
960 if (ret)
961 return ret;
962
963 ret = platform_driver_register(&at91_serial_driver);
964 if (ret)
965 uart_unregister_driver(&at91_uart);
966
967 return ret;
968}
969
970static void __exit at91_serial_exit(void)
971{
972 platform_driver_unregister(&at91_serial_driver);
876 uart_unregister_driver(&at91_uart); 973 uart_unregister_driver(&at91_uart);
877} 974}
878 975
diff --git a/drivers/serial/ioc4_serial.c b/drivers/serial/ioc4_serial.c
index c620209d7b9a..717e47bbd784 100644
--- a/drivers/serial/ioc4_serial.c
+++ b/drivers/serial/ioc4_serial.c
@@ -2646,7 +2646,10 @@ static int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
2646 struct ioc4_port *port; 2646 struct ioc4_port *port;
2647 struct ioc4_soft *soft; 2647 struct ioc4_soft *soft;
2648 2648
2649 /* If serial driver did not attach, don't try to detach */
2649 control = idd->idd_serial_data; 2650 control = idd->idd_serial_data;
2651 if (!control)
2652 return 0;
2650 2653
2651 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) { 2654 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2652 for (port_type = UART_PORT_MIN; 2655 for (port_type = UART_PORT_MIN;
@@ -2778,6 +2781,12 @@ ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2778 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __FUNCTION__, idd->idd_pdev, 2781 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __FUNCTION__, idd->idd_pdev,
2779 idd->idd_pci_id)); 2782 idd->idd_pci_id));
2780 2783
2784 /* PCI-RT does not bring out serial connections.
2785 * Do not attach to this particular IOC4.
2786 */
2787 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
2788 return 0;
2789
2781 /* request serial registers */ 2790 /* request serial registers */
2782 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET; 2791 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET;
2783 2792
diff --git a/drivers/serial/netx-serial.c b/drivers/serial/netx-serial.c
new file mode 100644
index 000000000000..c1adc9e4b239
--- /dev/null
+++ b/drivers/serial/netx-serial.c
@@ -0,0 +1,749 @@
1/*
2 * drivers/serial/netx-serial.c
3 *
4 * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/config.h>
21
22#if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23#define SUPPORT_SYSRQ
24#endif
25
26#include <linux/device.h>
27#include <linux/module.h>
28#include <linux/ioport.h>
29#include <linux/init.h>
30#include <linux/console.h>
31#include <linux/sysrq.h>
32#include <linux/platform_device.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37
38#include <asm/io.h>
39#include <asm/irq.h>
40#include <asm/hardware.h>
41#include <asm/arch/netx-regs.h>
42
43/* We've been assigned a range on the "Low-density serial ports" major */
44#define SERIAL_NX_MAJOR 204
45#define MINOR_START 170
46
47#ifdef CONFIG_SERIAL_NETX_CONSOLE
48
49enum uart_regs {
50 UART_DR = 0x00,
51 UART_SR = 0x04,
52 UART_LINE_CR = 0x08,
53 UART_BAUDDIV_MSB = 0x0c,
54 UART_BAUDDIV_LSB = 0x10,
55 UART_CR = 0x14,
56 UART_FR = 0x18,
57 UART_IIR = 0x1c,
58 UART_ILPR = 0x20,
59 UART_RTS_CR = 0x24,
60 UART_RTS_LEAD = 0x28,
61 UART_RTS_TRAIL = 0x2c,
62 UART_DRV_ENABLE = 0x30,
63 UART_BRM_CR = 0x34,
64 UART_RXFIFO_IRQLEVEL = 0x38,
65 UART_TXFIFO_IRQLEVEL = 0x3c,
66};
67
68#define SR_FE (1<<0)
69#define SR_PE (1<<1)
70#define SR_BE (1<<2)
71#define SR_OE (1<<3)
72
73#define LINE_CR_BRK (1<<0)
74#define LINE_CR_PEN (1<<1)
75#define LINE_CR_EPS (1<<2)
76#define LINE_CR_STP2 (1<<3)
77#define LINE_CR_FEN (1<<4)
78#define LINE_CR_5BIT (0<<5)
79#define LINE_CR_6BIT (1<<5)
80#define LINE_CR_7BIT (2<<5)
81#define LINE_CR_8BIT (3<<5)
82#define LINE_CR_BITS_MASK (3<<5)
83
84#define CR_UART_EN (1<<0)
85#define CR_SIREN (1<<1)
86#define CR_SIRLP (1<<2)
87#define CR_MSIE (1<<3)
88#define CR_RIE (1<<4)
89#define CR_TIE (1<<5)
90#define CR_RTIE (1<<6)
91#define CR_LBE (1<<7)
92
93#define FR_CTS (1<<0)
94#define FR_DSR (1<<1)
95#define FR_DCD (1<<2)
96#define FR_BUSY (1<<3)
97#define FR_RXFE (1<<4)
98#define FR_TXFF (1<<5)
99#define FR_RXFF (1<<6)
100#define FR_TXFE (1<<7)
101
102#define IIR_MIS (1<<0)
103#define IIR_RIS (1<<1)
104#define IIR_TIS (1<<2)
105#define IIR_RTIS (1<<3)
106#define IIR_MASK 0xf
107
108#define RTS_CR_AUTO (1<<0)
109#define RTS_CR_RTS (1<<1)
110#define RTS_CR_COUNT (1<<2)
111#define RTS_CR_MOD2 (1<<3)
112#define RTS_CR_RTS_POL (1<<4)
113#define RTS_CR_CTS_CTR (1<<5)
114#define RTS_CR_CTS_POL (1<<6)
115#define RTS_CR_STICK (1<<7)
116
117#define UART_PORT_SIZE 0x40
118#define DRIVER_NAME "netx-uart"
119
120struct netx_port {
121 struct uart_port port;
122};
123
124static void netx_stop_tx(struct uart_port *port)
125{
126 unsigned int val;
127 val = readl(port->membase + UART_CR);
128 writel(val & ~CR_TIE, port->membase + UART_CR);
129}
130
131static void netx_stop_rx(struct uart_port *port)
132{
133 unsigned int val;
134 val = readl(port->membase + UART_CR);
135 writel(val & ~CR_RIE, port->membase + UART_CR);
136}
137
138static void netx_enable_ms(struct uart_port *port)
139{
140 unsigned int val;
141 val = readl(port->membase + UART_CR);
142 writel(val | CR_MSIE, port->membase + UART_CR);
143}
144
145static inline void netx_transmit_buffer(struct uart_port *port)
146{
147 struct circ_buf *xmit = &port->info->xmit;
148
149 if (port->x_char) {
150 writel(port->x_char, port->membase + UART_DR);
151 port->icount.tx++;
152 port->x_char = 0;
153 return;
154 }
155
156 if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
157 netx_stop_tx(port);
158 return;
159 }
160
161 do {
162 /* send xmit->buf[xmit->tail]
163 * out the port here */
164 writel(xmit->buf[xmit->tail], port->membase + UART_DR);
165 xmit->tail = (xmit->tail + 1) &
166 (UART_XMIT_SIZE - 1);
167 port->icount.tx++;
168 if (uart_circ_empty(xmit))
169 break;
170 } while (!(readl(port->membase + UART_FR) & FR_TXFF));
171
172 if (uart_circ_empty(xmit))
173 netx_stop_tx(port);
174}
175
176static void netx_start_tx(struct uart_port *port)
177{
178 writel(
179 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);
180
181 if (!(readl(port->membase + UART_FR) & FR_TXFF))
182 netx_transmit_buffer(port);
183}
184
185static unsigned int netx_tx_empty(struct uart_port *port)
186{
187 return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
188}
189
190static void netx_txint(struct uart_port *port)
191{
192 struct circ_buf *xmit = &port->info->xmit;
193
194 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
195 netx_stop_tx(port);
196 return;
197 }
198
199 netx_transmit_buffer(port);
200
201 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
202 uart_write_wakeup(port);
203}
204
205static void netx_rxint(struct uart_port *port, struct pt_regs *regs)
206{
207 unsigned char rx, flg, status;
208 struct tty_struct *tty = port->info->tty;
209
210 while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
211 rx = readl(port->membase + UART_DR);
212 flg = TTY_NORMAL;
213 port->icount.rx++;
214 status = readl(port->membase + UART_SR);
215 if (status & SR_BE) {
216 writel(0, port->membase + UART_SR);
217 if (uart_handle_break(port))
218 continue;
219 }
220
221 if (unlikely(status & (SR_FE | SR_PE | SR_OE))) {
222
223 if (status & SR_PE)
224 port->icount.parity++;
225 else if (status & SR_FE)
226 port->icount.frame++;
227 if (status & SR_OE)
228 port->icount.overrun++;
229
230 status &= port->read_status_mask;
231
232 if (status & SR_BE)
233 flg = TTY_BREAK;
234 else if (status & SR_PE)
235 flg = TTY_PARITY;
236 else if (status & SR_FE)
237 flg = TTY_FRAME;
238 }
239
240 if (uart_handle_sysrq_char(port, rx, regs))
241 continue;
242
243 uart_insert_char(port, status, SR_OE, rx, flg);
244 }
245
246 tty_flip_buffer_push(tty);
247 return;
248}
249
250static irqreturn_t netx_int(int irq, void *dev_id, struct pt_regs *regs)
251{
252 struct uart_port *port = (struct uart_port *)dev_id;
253 unsigned long flags;
254 unsigned char status;
255
256 spin_lock_irqsave(&port->lock,flags);
257
258 status = readl(port->membase + UART_IIR) & IIR_MASK;
259 while (status) {
260 if (status & IIR_RIS)
261 netx_rxint(port, regs);
262 if (status & IIR_TIS)
263 netx_txint(port);
264 if (status & IIR_MIS) {
265 if (readl(port->membase + UART_FR) & FR_CTS)
266 uart_handle_cts_change(port, 1);
267 else
268 uart_handle_cts_change(port, 0);
269 }
270 writel(0, port->membase + UART_IIR);
271 status = readl(port->membase + UART_IIR) & IIR_MASK;
272 }
273
274 spin_unlock_irqrestore(&port->lock,flags);
275 return IRQ_HANDLED;
276}
277
278static unsigned int netx_get_mctrl(struct uart_port *port)
279{
280 unsigned int ret = TIOCM_DSR | TIOCM_CAR;
281
282 if (readl(port->membase + UART_FR) & FR_CTS)
283 ret |= TIOCM_CTS;
284
285 return ret;
286}
287
288static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl)
289{
290 unsigned int val;
291
292 if (mctrl & TIOCM_RTS) {
293 val = readl(port->membase + UART_RTS_CR);
294 writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);
295 }
296}
297
298static void netx_break_ctl(struct uart_port *port, int break_state)
299{
300 unsigned int line_cr;
301 spin_lock_irq(&port->lock);
302
303 line_cr = readl(port->membase + UART_LINE_CR);
304 if (break_state != 0)
305 line_cr |= LINE_CR_BRK;
306 else
307 line_cr &= ~LINE_CR_BRK;
308 writel(line_cr, port->membase + UART_LINE_CR);
309
310 spin_unlock_irq(&port->lock);
311}
312
313static int netx_startup(struct uart_port *port)
314{
315 int ret;
316
317 ret = request_irq(port->irq, netx_int, 0,
318 DRIVER_NAME, port);
319 if (ret) {
320 dev_err(port->dev, "unable to grab irq%d\n",port->irq);
321 goto exit;
322 }
323
324 writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,
325 port->membase + UART_LINE_CR);
326
327 writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN,
328 port->membase + UART_CR);
329
330exit:
331 return ret;
332}
333
334static void netx_shutdown(struct uart_port *port)
335{
336 writel(0, port->membase + UART_CR) ;
337
338 free_irq(port->irq, port);
339}
340
341static void
342netx_set_termios(struct uart_port *port, struct termios *termios,
343 struct termios *old)
344{
345 unsigned int baud, quot;
346 unsigned char old_cr;
347 unsigned char line_cr = LINE_CR_FEN;
348 unsigned char rts_cr = 0;
349
350 switch (termios->c_cflag & CSIZE) {
351 case CS5:
352 line_cr |= LINE_CR_5BIT;
353 break;
354 case CS6:
355 line_cr |= LINE_CR_6BIT;
356 break;
357 case CS7:
358 line_cr |= LINE_CR_7BIT;
359 break;
360 case CS8:
361 line_cr |= LINE_CR_8BIT;
362 break;
363 }
364
365 if (termios->c_cflag & CSTOPB)
366 line_cr |= LINE_CR_STP2;
367
368 if (termios->c_cflag & PARENB) {
369 line_cr |= LINE_CR_PEN;
370 if (!(termios->c_cflag & PARODD))
371 line_cr |= LINE_CR_EPS;
372 }
373
374 if (termios->c_cflag & CRTSCTS)
375 rts_cr = RTS_CR_AUTO | RTS_CR_CTS_CTR | RTS_CR_RTS_POL;
376
377 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
378 quot = baud * 4096;
379 quot /= 1000;
380 quot *= 256;
381 quot /= 100000;
382
383 spin_lock_irq(&port->lock);
384
385 uart_update_timeout(port, termios->c_cflag, baud);
386
387 old_cr = readl(port->membase + UART_CR);
388
389 /* disable interrupts */
390 writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE),
391 port->membase + UART_CR);
392
393 /* drain transmitter */
394 while (readl(port->membase + UART_FR) & FR_BUSY);
395
396 /* disable UART */
397 writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);
398
399 /* modem status interrupts */
400 old_cr &= ~CR_MSIE;
401 if (UART_ENABLE_MS(port, termios->c_cflag))
402 old_cr |= CR_MSIE;
403
404 writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
405 writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
406 writel(line_cr, port->membase + UART_LINE_CR);
407
408 writel(rts_cr, port->membase + UART_RTS_CR);
409
410 /*
411 * Characters to ignore
412 */
413 port->ignore_status_mask = 0;
414 if (termios->c_iflag & IGNPAR)
415 port->ignore_status_mask |= SR_PE;
416 if (termios->c_iflag & IGNBRK) {
417 port->ignore_status_mask |= SR_BE;
418 /*
419 * If we're ignoring parity and break indicators,
420 * ignore overruns too (for real raw support).
421 */
422 if (termios->c_iflag & IGNPAR)
423 port->ignore_status_mask |= SR_PE;
424 }
425
426 port->read_status_mask = 0;
427 if (termios->c_iflag & (BRKINT | PARMRK))
428 port->read_status_mask |= SR_BE;
429 if (termios->c_iflag & INPCK)
430 port->read_status_mask |= SR_PE | SR_FE;
431
432 writel(old_cr, port->membase + UART_CR);
433
434 spin_unlock_irq(&port->lock);
435}
436
437static const char *netx_type(struct uart_port *port)
438{
439 return port->type == PORT_NETX ? "NETX" : NULL;
440}
441
442static void netx_release_port(struct uart_port *port)
443{
444 release_mem_region(port->mapbase, UART_PORT_SIZE);
445}
446
447static int netx_request_port(struct uart_port *port)
448{
449 return request_mem_region(port->mapbase, UART_PORT_SIZE,
450 DRIVER_NAME) != NULL ? 0 : -EBUSY;
451}
452
453static void netx_config_port(struct uart_port *port, int flags)
454{
455 if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0)
456 port->type = PORT_NETX;
457}
458
459static int
460netx_verify_port(struct uart_port *port, struct serial_struct *ser)
461{
462 int ret = 0;
463
464 if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX)
465 ret = -EINVAL;
466
467 return ret;
468}
469
470static struct uart_ops netx_pops = {
471 .tx_empty = netx_tx_empty,
472 .set_mctrl = netx_set_mctrl,
473 .get_mctrl = netx_get_mctrl,
474 .stop_tx = netx_stop_tx,
475 .start_tx = netx_start_tx,
476 .stop_rx = netx_stop_rx,
477 .enable_ms = netx_enable_ms,
478 .break_ctl = netx_break_ctl,
479 .startup = netx_startup,
480 .shutdown = netx_shutdown,
481 .set_termios = netx_set_termios,
482 .type = netx_type,
483 .release_port = netx_release_port,
484 .request_port = netx_request_port,
485 .config_port = netx_config_port,
486 .verify_port = netx_verify_port,
487};
488
489static struct netx_port netx_ports[] = {
490 {
491 .port = {
492 .type = PORT_NETX,
493 .iotype = UPIO_MEM,
494 .membase = (char __iomem *)io_p2v(NETX_PA_UART0),
495 .mapbase = NETX_PA_UART0,
496 .irq = NETX_IRQ_UART0,
497 .uartclk = 100000000,
498 .fifosize = 16,
499 .flags = UPF_BOOT_AUTOCONF,
500 .ops = &netx_pops,
501 .line = 0,
502 },
503 }, {
504 .port = {
505 .type = PORT_NETX,
506 .iotype = UPIO_MEM,
507 .membase = (char __iomem *)io_p2v(NETX_PA_UART1),
508 .mapbase = NETX_PA_UART1,
509 .irq = NETX_IRQ_UART1,
510 .uartclk = 100000000,
511 .fifosize = 16,
512 .flags = UPF_BOOT_AUTOCONF,
513 .ops = &netx_pops,
514 .line = 1,
515 },
516 }, {
517 .port = {
518 .type = PORT_NETX,
519 .iotype = UPIO_MEM,
520 .membase = (char __iomem *)io_p2v(NETX_PA_UART2),
521 .mapbase = NETX_PA_UART2,
522 .irq = NETX_IRQ_UART2,
523 .uartclk = 100000000,
524 .fifosize = 16,
525 .flags = UPF_BOOT_AUTOCONF,
526 .ops = &netx_pops,
527 .line = 2,
528 },
529 }
530};
531
532static void netx_console_putchar(struct uart_port *port, int ch)
533{
534 while (readl(port->membase + UART_FR) & FR_BUSY);
535 writel(ch, port->membase + UART_DR);
536}
537
538static void
539netx_console_write(struct console *co, const char *s, unsigned int count)
540{
541 struct uart_port *port = &netx_ports[co->index].port;
542 unsigned char cr_save;
543
544 cr_save = readl(port->membase + UART_CR);
545 writel(cr_save | CR_UART_EN, port->membase + UART_CR);
546
547 uart_console_write(port, s, count, netx_console_putchar);
548
549 while (readl(port->membase + UART_FR) & FR_BUSY);
550 writel(cr_save, port->membase + UART_CR);
551}
552
553static void __init
554netx_console_get_options(struct uart_port *port, int *baud,
555 int *parity, int *bits, int *flow)
556{
557 unsigned char line_cr;
558
559 *baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) |
560 readl(port->membase + UART_BAUDDIV_LSB);
561 *baud *= 1000;
562 *baud /= 4096;
563 *baud *= 1000;
564 *baud /= 256;
565 *baud *= 100;
566
567 line_cr = readl(port->membase + UART_LINE_CR);
568 *parity = 'n';
569 if (line_cr & LINE_CR_PEN) {
570 if (line_cr & LINE_CR_EPS)
571 *parity = 'e';
572 else
573 *parity = 'o';
574 }
575
576 switch (line_cr & LINE_CR_BITS_MASK) {
577 case LINE_CR_8BIT:
578 *bits = 8;
579 break;
580 case LINE_CR_7BIT:
581 *bits = 7;
582 break;
583 case LINE_CR_6BIT:
584 *bits = 6;
585 break;
586 case LINE_CR_5BIT:
587 *bits = 5;
588 break;
589 }
590
591 if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
592 *flow = 'r';
593}
594
595static int __init
596netx_console_setup(struct console *co, char *options)
597{
598 struct netx_port *sport;
599 int baud = 9600;
600 int bits = 8;
601 int parity = 'n';
602 int flow = 'n';
603
604 /*
605 * Check whether an invalid uart number has been specified, and
606 * if so, search for the first available port that does have
607 * console support.
608 */
609 if (co->index == -1 || co->index >= ARRAY_SIZE(netx_ports))
610 co->index = 0;
611 sport = &netx_ports[co->index];
612
613 if (options) {
614 uart_parse_options(options, &baud, &parity, &bits, &flow);
615 } else {
616 /* if the UART is enabled, assume it has been correctly setup
617 * by the bootloader and get the options
618 */
619 if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
620 netx_console_get_options(&sport->port, &baud,
621 &parity, &bits, &flow);
622 }
623
624 }
625
626 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
627}
628
629static struct uart_driver netx_reg;
630static struct console netx_console = {
631 .name = "ttyNX",
632 .write = netx_console_write,
633 .device = uart_console_device,
634 .setup = netx_console_setup,
635 .flags = CON_PRINTBUFFER,
636 .index = -1,
637 .data = &netx_reg,
638};
639
640static int __init netx_console_init(void)
641{
642 register_console(&netx_console);
643 return 0;
644}
645console_initcall(netx_console_init);
646
647#define NETX_CONSOLE &netx_console
648#else
649#define NETX_CONSOLE NULL
650#endif
651
652static struct uart_driver netx_reg = {
653 .owner = THIS_MODULE,
654 .driver_name = DRIVER_NAME,
655 .dev_name = "ttyNX",
656 .major = SERIAL_NX_MAJOR,
657 .minor = MINOR_START,
658 .nr = ARRAY_SIZE(netx_ports),
659 .cons = NETX_CONSOLE,
660};
661
662static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state)
663{
664 struct netx_port *sport = platform_get_drvdata(pdev);
665
666 if (sport)
667 uart_suspend_port(&netx_reg, &sport->port);
668
669 return 0;
670}
671
672static int serial_netx_resume(struct platform_device *pdev)
673{
674 struct netx_port *sport = platform_get_drvdata(pdev);
675
676 if (sport)
677 uart_resume_port(&netx_reg, &sport->port);
678
679 return 0;
680}
681
682static int serial_netx_probe(struct platform_device *pdev)
683{
684 struct uart_port *port = &netx_ports[pdev->id].port;
685
686 dev_info(&pdev->dev, "initialising\n");
687
688 port->dev = &pdev->dev;
689
690 writel(1, port->membase + UART_RXFIFO_IRQLEVEL);
691 uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port);
692 platform_set_drvdata(pdev, &netx_ports[pdev->id]);
693
694 return 0;
695}
696
697static int serial_netx_remove(struct platform_device *pdev)
698{
699 struct netx_port *sport = platform_get_drvdata(pdev);
700
701 platform_set_drvdata(pdev, NULL);
702
703 if (sport)
704 uart_remove_one_port(&netx_reg, &sport->port);
705
706 return 0;
707}
708
709static struct platform_driver serial_netx_driver = {
710 .probe = serial_netx_probe,
711 .remove = serial_netx_remove,
712
713 .suspend = serial_netx_suspend,
714 .resume = serial_netx_resume,
715
716 .driver = {
717 .name = DRIVER_NAME,
718 },
719};
720
721static int __init netx_serial_init(void)
722{
723 int ret;
724
725 printk(KERN_INFO "Serial: NetX driver\n");
726
727 ret = uart_register_driver(&netx_reg);
728 if (ret)
729 return ret;
730
731 ret = platform_driver_register(&serial_netx_driver);
732 if (ret != 0)
733 uart_unregister_driver(&netx_reg);
734
735 return 0;
736}
737
738static void __exit netx_serial_exit(void)
739{
740 platform_driver_unregister(&serial_netx_driver);
741 uart_unregister_driver(&netx_reg);
742}
743
744module_init(netx_serial_init);
745module_exit(netx_serial_exit);
746
747MODULE_AUTHOR("Sascha Hauer");
748MODULE_DESCRIPTION("NetX serial port driver");
749MODULE_LICENSE("GPL");
diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c
index 77d4568ccc3a..ae3649568541 100644
--- a/drivers/serial/pxa.c
+++ b/drivers/serial/pxa.c
@@ -269,7 +269,6 @@ static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
269 unsigned char status; 269 unsigned char status;
270 unsigned int ret; 270 unsigned int ret;
271 271
272return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
273 status = serial_in(up, UART_MSR); 272 status = serial_in(up, UART_MSR);
274 273
275 ret = 0; 274 ret = 0;
diff --git a/drivers/serial/sunsu.c b/drivers/serial/sunsu.c
index 2b4f96541b8e..4cdb610cdd37 100644
--- a/drivers/serial/sunsu.c
+++ b/drivers/serial/sunsu.c
@@ -1295,9 +1295,9 @@ static int __init sunsu_kbd_ms_init(struct uart_sunsu_port *up, int channel)
1295 if (up->port.type == PORT_UNKNOWN) 1295 if (up->port.type == PORT_UNKNOWN)
1296 return -1; 1296 return -1;
1297 1297
1298 printk(KERN_INFO "su%d at 0x%p (irq = %s) is a %s\n", 1298 printk(KERN_INFO "su%d at 0x%p (irq = %d) is a %s\n",
1299 channel, 1299 channel,
1300 up->port.membase, __irq_itoa(up->port.irq), 1300 up->port.membase, up->port.irq,
1301 sunsu_type(&up->port)); 1301 sunsu_type(&up->port));
1302 1302
1303#ifdef CONFIG_SERIO 1303#ifdef CONFIG_SERIO
diff --git a/drivers/serial/sunzilog.c b/drivers/serial/sunzilog.c
index cd49ebbf4a45..5b6569728a9c 100644
--- a/drivers/serial/sunzilog.c
+++ b/drivers/serial/sunzilog.c
@@ -1540,8 +1540,8 @@ static void __init sunzilog_init_kbdms(struct uart_sunzilog_port *up, int channe
1540 up->cflag = B4800 | CS8 | CLOCAL | CREAD; 1540 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1541 baud = 4800; 1541 baud = 4800;
1542 } 1542 }
1543 printk(KERN_INFO "zs%d at 0x%p (irq = %s) is a SunZilog\n", 1543 printk(KERN_INFO "zs%d at 0x%p (irq = %d) is a SunZilog\n",
1544 channel, up->port.membase, __irq_itoa(zilog_irq)); 1544 channel, up->port.membase, zilog_irq);
1545 1545
1546 up->curregs[R15] = BRKIE; 1546 up->curregs[R15] = BRKIE;
1547 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); 1547 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 15:26:37 -0500