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-rw-r--r--drivers/serial/Kconfig4
-rw-r--r--drivers/serial/s5pv210.c8
-rw-r--r--drivers/serial/samsung.c9
-rw-r--r--drivers/serial/sh-sci.c42
-rw-r--r--drivers/serial/sh-sci.h29
5 files changed, 74 insertions, 18 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index a22e60c06f48..12900f7083b0 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -536,8 +536,8 @@ config SERIAL_S3C6400
536 536
537config SERIAL_S5PV210 537config SERIAL_S5PV210
538 tristate "Samsung S5PV210 Serial port support" 538 tristate "Samsung S5PV210 Serial port support"
539 depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442) 539 depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442 || CPU_S5PV310)
540 select SERIAL_SAMSUNG_UARTS_4 if CPU_S5PV210 540 select SERIAL_SAMSUNG_UARTS_4 if (CPU_S5PV210 || CPU_S5PV310)
541 default y 541 default y
542 help 542 help
543 Serial port support for Samsung's S5P Family of SoC's 543 Serial port support for Samsung's S5P Family of SoC's
diff --git a/drivers/serial/s5pv210.c b/drivers/serial/s5pv210.c
index 4a789e5361a4..6ebccd70a707 100644
--- a/drivers/serial/s5pv210.c
+++ b/drivers/serial/s5pv210.c
@@ -28,8 +28,12 @@
28static int s5pv210_serial_setsource(struct uart_port *port, 28static int s5pv210_serial_setsource(struct uart_port *port,
29 struct s3c24xx_uart_clksrc *clk) 29 struct s3c24xx_uart_clksrc *clk)
30{ 30{
31 struct s3c2410_uartcfg *cfg = port->dev->platform_data;
31 unsigned long ucon = rd_regl(port, S3C2410_UCON); 32 unsigned long ucon = rd_regl(port, S3C2410_UCON);
32 33
34 if ((cfg->clocks_size) == 1)
35 return 0;
36
33 if (strcmp(clk->name, "pclk") == 0) 37 if (strcmp(clk->name, "pclk") == 0)
34 ucon &= ~S5PV210_UCON_CLKMASK; 38 ucon &= ~S5PV210_UCON_CLKMASK;
35 else if (strcmp(clk->name, "uclk1") == 0) 39 else if (strcmp(clk->name, "uclk1") == 0)
@@ -47,10 +51,14 @@ static int s5pv210_serial_setsource(struct uart_port *port,
47static int s5pv210_serial_getsource(struct uart_port *port, 51static int s5pv210_serial_getsource(struct uart_port *port,
48 struct s3c24xx_uart_clksrc *clk) 52 struct s3c24xx_uart_clksrc *clk)
49{ 53{
54 struct s3c2410_uartcfg *cfg = port->dev->platform_data;
50 u32 ucon = rd_regl(port, S3C2410_UCON); 55 u32 ucon = rd_regl(port, S3C2410_UCON);
51 56
52 clk->divisor = 1; 57 clk->divisor = 1;
53 58
59 if ((cfg->clocks_size) == 1)
60 return 0;
61
54 switch (ucon & S5PV210_UCON_CLKMASK) { 62 switch (ucon & S5PV210_UCON_CLKMASK) {
55 case S5PV210_UCON_PCLK: 63 case S5PV210_UCON_PCLK:
56 clk->name = "pclk"; 64 clk->name = "pclk";
diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c
index a9d6c5626a0a..b1156ba8ad14 100644
--- a/drivers/serial/samsung.c
+++ b/drivers/serial/samsung.c
@@ -705,8 +705,13 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
705 if (ourport->info->has_divslot) { 705 if (ourport->info->has_divslot) {
706 unsigned int div = ourport->baudclk_rate / baud; 706 unsigned int div = ourport->baudclk_rate / baud;
707 707
708 udivslot = udivslot_table[div & 15]; 708 if (cfg->has_fracval) {
709 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15); 709 udivslot = (div & 15);
710 dbg("fracval = %04x\n", udivslot);
711 } else {
712 udivslot = udivslot_table[div & 15];
713 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
714 }
710 } 715 }
711 716
712 switch (termios->c_cflag & CSIZE) { 717 switch (termios->c_cflag & CSIZE) {
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 5f90fcd7d107..c291b3add1d2 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -346,6 +346,27 @@ static int scif_rxfill(struct uart_port *port)
346 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; 346 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
347 } 347 }
348} 348}
349#elif defined(CONFIG_ARCH_SH7372)
350static int scif_txfill(struct uart_port *port)
351{
352 if (port->type == PORT_SCIFA)
353 return sci_in(port, SCFDR) >> 8;
354 else
355 return sci_in(port, SCTFDR);
356}
357
358static int scif_txroom(struct uart_port *port)
359{
360 return port->fifosize - scif_txfill(port);
361}
362
363static int scif_rxfill(struct uart_port *port)
364{
365 if (port->type == PORT_SCIFA)
366 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
367 else
368 return sci_in(port, SCRFDR);
369}
349#else 370#else
350static int scif_txfill(struct uart_port *port) 371static int scif_txfill(struct uart_port *port)
351{ 372{
@@ -683,7 +704,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
683 u16 ssr = sci_in(port, SCxSR); 704 u16 ssr = sci_in(port, SCxSR);
684 705
685 /* Disable future Rx interrupts */ 706 /* Disable future Rx interrupts */
686 if (port->type == PORT_SCIFA) { 707 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
687 disable_irq_nosync(irq); 708 disable_irq_nosync(irq);
688 scr |= 0x4000; 709 scr |= 0x4000;
689 } else { 710 } else {
@@ -928,7 +949,7 @@ static void sci_dma_tx_complete(void *arg)
928 949
929 if (!uart_circ_empty(xmit)) { 950 if (!uart_circ_empty(xmit)) {
930 schedule_work(&s->work_tx); 951 schedule_work(&s->work_tx);
931 } else if (port->type == PORT_SCIFA) { 952 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
932 u16 ctrl = sci_in(port, SCSCR); 953 u16 ctrl = sci_in(port, SCSCR);
933 sci_out(port, SCSCR, ctrl & ~SCI_CTRL_FLAGS_TIE); 954 sci_out(port, SCSCR, ctrl & ~SCI_CTRL_FLAGS_TIE);
934 } 955 }
@@ -1184,7 +1205,7 @@ static void sci_start_tx(struct uart_port *port)
1184 unsigned short ctrl; 1205 unsigned short ctrl;
1185 1206
1186#ifdef CONFIG_SERIAL_SH_SCI_DMA 1207#ifdef CONFIG_SERIAL_SH_SCI_DMA
1187 if (port->type == PORT_SCIFA) { 1208 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1188 u16 new, scr = sci_in(port, SCSCR); 1209 u16 new, scr = sci_in(port, SCSCR);
1189 if (s->chan_tx) 1210 if (s->chan_tx)
1190 new = scr | 0x8000; 1211 new = scr | 0x8000;
@@ -1197,7 +1218,7 @@ static void sci_start_tx(struct uart_port *port)
1197 s->cookie_tx < 0) 1218 s->cookie_tx < 0)
1198 schedule_work(&s->work_tx); 1219 schedule_work(&s->work_tx);
1199#endif 1220#endif
1200 if (!s->chan_tx || port->type == PORT_SCIFA) { 1221 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1201 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 1222 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1202 ctrl = sci_in(port, SCSCR); 1223 ctrl = sci_in(port, SCSCR);
1203 sci_out(port, SCSCR, ctrl | SCI_CTRL_FLAGS_TIE); 1224 sci_out(port, SCSCR, ctrl | SCI_CTRL_FLAGS_TIE);
@@ -1210,7 +1231,7 @@ static void sci_stop_tx(struct uart_port *port)
1210 1231
1211 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 1232 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1212 ctrl = sci_in(port, SCSCR); 1233 ctrl = sci_in(port, SCSCR);
1213 if (port->type == PORT_SCIFA) 1234 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1214 ctrl &= ~0x8000; 1235 ctrl &= ~0x8000;
1215 ctrl &= ~SCI_CTRL_FLAGS_TIE; 1236 ctrl &= ~SCI_CTRL_FLAGS_TIE;
1216 sci_out(port, SCSCR, ctrl); 1237 sci_out(port, SCSCR, ctrl);
@@ -1222,7 +1243,7 @@ static void sci_start_rx(struct uart_port *port)
1222 1243
1223 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ 1244 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
1224 ctrl |= sci_in(port, SCSCR); 1245 ctrl |= sci_in(port, SCSCR);
1225 if (port->type == PORT_SCIFA) 1246 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1226 ctrl &= ~0x4000; 1247 ctrl &= ~0x4000;
1227 sci_out(port, SCSCR, ctrl); 1248 sci_out(port, SCSCR, ctrl);
1228} 1249}
@@ -1233,7 +1254,7 @@ static void sci_stop_rx(struct uart_port *port)
1233 1254
1234 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ 1255 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1235 ctrl = sci_in(port, SCSCR); 1256 ctrl = sci_in(port, SCSCR);
1236 if (port->type == PORT_SCIFA) 1257 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1237 ctrl &= ~0x4000; 1258 ctrl &= ~0x4000;
1238 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); 1259 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
1239 sci_out(port, SCSCR, ctrl); 1260 sci_out(port, SCSCR, ctrl);
@@ -1271,7 +1292,7 @@ static void rx_timer_fn(unsigned long arg)
1271 struct uart_port *port = &s->port; 1292 struct uart_port *port = &s->port;
1272 u16 scr = sci_in(port, SCSCR); 1293 u16 scr = sci_in(port, SCSCR);
1273 1294
1274 if (port->type == PORT_SCIFA) { 1295 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1275 scr &= ~0x4000; 1296 scr &= ~0x4000;
1276 enable_irq(s->irqs[1]); 1297 enable_irq(s->irqs[1]);
1277 } 1298 }
@@ -1524,6 +1545,8 @@ static const char *sci_type(struct uart_port *port)
1524 return "scif"; 1545 return "scif";
1525 case PORT_SCIFA: 1546 case PORT_SCIFA:
1526 return "scifa"; 1547 return "scifa";
1548 case PORT_SCIFB:
1549 return "scifb";
1527 } 1550 }
1528 1551
1529 return NULL; 1552 return NULL;
@@ -1612,6 +1635,9 @@ static int __devinit sci_init_single(struct platform_device *dev,
1612 port->line = index; 1635 port->line = index;
1613 1636
1614 switch (p->type) { 1637 switch (p->type) {
1638 case PORT_SCIFB:
1639 port->fifosize = 256;
1640 break;
1615 case PORT_SCIFA: 1641 case PORT_SCIFA:
1616 port->fifosize = 64; 1642 port->fifosize = 64;
1617 break; 1643 break;
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index f70c49f915fa..9b52f77a9305 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -322,7 +322,7 @@
322#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ 322#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
323 static inline unsigned int sci_##name##_in(struct uart_port *port) \ 323 static inline unsigned int sci_##name##_in(struct uart_port *port) \
324 { \ 324 { \
325 if (port->type == PORT_SCIF) { \ 325 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
326 SCI_IN(scif_size, scif_offset) \ 326 SCI_IN(scif_size, scif_offset) \
327 } else { /* PORT_SCI or PORT_SCIFA */ \ 327 } else { /* PORT_SCI or PORT_SCIFA */ \
328 SCI_IN(sci_size, sci_offset); \ 328 SCI_IN(sci_size, sci_offset); \
@@ -330,7 +330,7 @@
330 } \ 330 } \
331 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ 331 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
332 { \ 332 { \
333 if (port->type == PORT_SCIF) { \ 333 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
334 SCI_OUT(scif_size, scif_offset, value) \ 334 SCI_OUT(scif_size, scif_offset, value) \
335 } else { /* PORT_SCI or PORT_SCIFA */ \ 335 } else { /* PORT_SCI or PORT_SCIFA */ \
336 SCI_OUT(sci_size, sci_offset, value); \ 336 SCI_OUT(sci_size, sci_offset, value); \
@@ -384,8 +384,12 @@
384 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 384 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
385 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 385 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
386 defined(CONFIG_ARCH_SH7367) || \ 386 defined(CONFIG_ARCH_SH7367) || \
387 defined(CONFIG_ARCH_SH7377) || \ 387 defined(CONFIG_ARCH_SH7377)
388 defined(CONFIG_ARCH_SH7372) 388#define SCIF_FNS(name, scif_offset, scif_size) \
389 CPU_SCIF_FNS(name, scif_offset, scif_size)
390#elif defined(CONFIG_ARCH_SH7372)
391#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \
392 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size)
389#define SCIF_FNS(name, scif_offset, scif_size) \ 393#define SCIF_FNS(name, scif_offset, scif_size) \
390 CPU_SCIF_FNS(name, scif_offset, scif_size) 394 CPU_SCIF_FNS(name, scif_offset, scif_size)
391#else 395#else
@@ -422,8 +426,7 @@
422 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 426 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
423 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 427 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
424 defined(CONFIG_ARCH_SH7367) || \ 428 defined(CONFIG_ARCH_SH7367) || \
425 defined(CONFIG_ARCH_SH7377) || \ 429 defined(CONFIG_ARCH_SH7377)
426 defined(CONFIG_ARCH_SH7372)
427 430
428SCIF_FNS(SCSMR, 0x00, 16) 431SCIF_FNS(SCSMR, 0x00, 16)
429SCIF_FNS(SCBRR, 0x04, 8) 432SCIF_FNS(SCBRR, 0x04, 8)
@@ -436,6 +439,20 @@ SCIF_FNS(SCFDR, 0x1c, 16)
436SCIF_FNS(SCxTDR, 0x20, 8) 439SCIF_FNS(SCxTDR, 0x20, 8)
437SCIF_FNS(SCxRDR, 0x24, 8) 440SCIF_FNS(SCxRDR, 0x24, 8)
438SCIF_FNS(SCLSR, 0x00, 0) 441SCIF_FNS(SCLSR, 0x00, 0)
442#elif defined(CONFIG_ARCH_SH7372)
443SCIF_FNS(SCSMR, 0x00, 16)
444SCIF_FNS(SCBRR, 0x04, 8)
445SCIF_FNS(SCSCR, 0x08, 16)
446SCIF_FNS(SCTDSR, 0x0c, 16)
447SCIF_FNS(SCFER, 0x10, 16)
448SCIF_FNS(SCxSR, 0x14, 16)
449SCIF_FNS(SCFCR, 0x18, 16)
450SCIF_FNS(SCFDR, 0x1c, 16)
451SCIF_FNS(SCTFDR, 0x38, 16)
452SCIF_FNS(SCRFDR, 0x3c, 16)
453SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
454SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
455SCIF_FNS(SCLSR, 0x00, 0)
439#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ 456#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
440 defined(CONFIG_CPU_SUBTYPE_SH7724) 457 defined(CONFIG_CPU_SUBTYPE_SH7724)
441SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) 458SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)