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-rw-r--r--drivers/serial/8250_hp300.c10
-rw-r--r--drivers/serial/ioc4_serial.c387
-rw-r--r--drivers/serial/mpc52xx_uart.c2
-rw-r--r--drivers/serial/mpsc.c260
-rw-r--r--drivers/serial/mpsc.h289
5 files changed, 511 insertions, 437 deletions
diff --git a/drivers/serial/8250_hp300.c b/drivers/serial/8250_hp300.c
index 4315afe9c080..53e81a44c1a3 100644
--- a/drivers/serial/8250_hp300.c
+++ b/drivers/serial/8250_hp300.c
@@ -55,6 +55,8 @@ static struct dio_driver hpdca_driver = {
55 55
56#endif 56#endif
57 57
58static unsigned int num_ports;
59
58extern int hp300_uart_scode; 60extern int hp300_uart_scode;
59 61
60/* Offset to UART registers from base of DCA */ 62/* Offset to UART registers from base of DCA */
@@ -199,6 +201,8 @@ static int __devinit hpdca_init_one(struct dio_dev *d,
199 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_ID, 0xff); 201 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_ID, 0xff);
200 udelay(100); 202 udelay(100);
201 203
204 num_ports++;
205
202 return 0; 206 return 0;
203} 207}
204#endif 208#endif
@@ -206,7 +210,6 @@ static int __devinit hpdca_init_one(struct dio_dev *d,
206static int __init hp300_8250_init(void) 210static int __init hp300_8250_init(void)
207{ 211{
208 static int called = 0; 212 static int called = 0;
209 int num_ports;
210#ifdef CONFIG_HPAPCI 213#ifdef CONFIG_HPAPCI
211 int line; 214 int line;
212 unsigned long base; 215 unsigned long base;
@@ -221,11 +224,8 @@ static int __init hp300_8250_init(void)
221 if (!MACH_IS_HP300) 224 if (!MACH_IS_HP300)
222 return -ENODEV; 225 return -ENODEV;
223 226
224 num_ports = 0;
225
226#ifdef CONFIG_HPDCA 227#ifdef CONFIG_HPDCA
227 if (dio_module_init(&hpdca_driver) == 0) 228 dio_register_driver(&hpdca_driver);
228 num_ports++;
229#endif 229#endif
230#ifdef CONFIG_HPAPCI 230#ifdef CONFIG_HPAPCI
231 if (hp300_model < HP_400) { 231 if (hp300_model < HP_400) {
diff --git a/drivers/serial/ioc4_serial.c b/drivers/serial/ioc4_serial.c
index a37579ce6d76..c620209d7b9a 100644
--- a/drivers/serial/ioc4_serial.c
+++ b/drivers/serial/ioc4_serial.c
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved. 6 * Copyright (C) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
7 */ 7 */
8 8
9 9
@@ -323,9 +323,12 @@ static unsigned int Num_of_ioc4_cards;
323#define IOC4_FIFO_CHARS 255 323#define IOC4_FIFO_CHARS 255
324 324
325/* Device name we're using */ 325/* Device name we're using */
326#define DEVICE_NAME "ttyIOC" 326#define DEVICE_NAME_RS232 "ttyIOC"
327#define DEVICE_MAJOR 204 327#define DEVICE_NAME_RS422 "ttyAIOC"
328#define DEVICE_MINOR 50 328#define DEVICE_MAJOR 204
329#define DEVICE_MINOR_RS232 50
330#define DEVICE_MINOR_RS422 84
331
329 332
330/* register offsets */ 333/* register offsets */
331#define IOC4_SERIAL_OFFSET 0x300 334#define IOC4_SERIAL_OFFSET 0x300
@@ -341,10 +344,8 @@ static unsigned int Num_of_ioc4_cards;
341#define MAX_BAUD_SUPPORTED 115200 344#define MAX_BAUD_SUPPORTED 115200
342 345
343/* protocol types supported */ 346/* protocol types supported */
344enum sio_proto { 347#define PROTO_RS232 3
345 PROTO_RS232, 348#define PROTO_RS422 7
346 PROTO_RS422
347};
348 349
349/* Notification types */ 350/* Notification types */
350#define N_DATA_READY 0x01 351#define N_DATA_READY 0x01
@@ -395,11 +396,17 @@ enum sio_proto {
395/* 396/*
396 * This is the entry saved by the driver - one per card 397 * This is the entry saved by the driver - one per card
397 */ 398 */
399
400#define UART_PORT_MIN 0
401#define UART_PORT_RS232 UART_PORT_MIN
402#define UART_PORT_RS422 1
403#define UART_PORT_COUNT 2 /* one for each mode */
404
398struct ioc4_control { 405struct ioc4_control {
399 int ic_irq; 406 int ic_irq;
400 struct { 407 struct {
401 /* uart ports are allocated here */ 408 /* uart ports are allocated here - 1 for rs232, 1 for rs422 */
402 struct uart_port icp_uart_port; 409 struct uart_port icp_uart_port[UART_PORT_COUNT];
403 /* Handy reference material */ 410 /* Handy reference material */
404 struct ioc4_port *icp_port; 411 struct ioc4_port *icp_port;
405 } ic_port[IOC4_NUM_SERIAL_PORTS]; 412 } ic_port[IOC4_NUM_SERIAL_PORTS];
@@ -443,7 +450,9 @@ struct ioc4_soft {
443 450
444/* Local port info for each IOC4 serial ports */ 451/* Local port info for each IOC4 serial ports */
445struct ioc4_port { 452struct ioc4_port {
446 struct uart_port *ip_port; 453 struct uart_port *ip_port; /* current active port ptr */
454 /* Ptrs for all ports */
455 struct uart_port *ip_all_ports[UART_PORT_COUNT];
447 /* Back ptrs for this port */ 456 /* Back ptrs for this port */
448 struct ioc4_control *ip_control; 457 struct ioc4_control *ip_control;
449 struct pci_dev *ip_pdev; 458 struct pci_dev *ip_pdev;
@@ -502,6 +511,9 @@ struct ioc4_port {
502#define DCD_ON 0x02 511#define DCD_ON 0x02
503#define LOWAT_WRITTEN 0x04 512#define LOWAT_WRITTEN 0x04
504#define READ_ABORTED 0x08 513#define READ_ABORTED 0x08
514#define PORT_ACTIVE 0x10
515#define PORT_INACTIVE 0 /* This is the value when "off" */
516
505 517
506/* Since each port has different register offsets and bitmasks 518/* Since each port has different register offsets and bitmasks
507 * for everything, we'll store those that we need in tables so we 519 * for everything, we'll store those that we need in tables so we
@@ -623,6 +635,23 @@ struct ring_buffer {
623static void receive_chars(struct uart_port *); 635static void receive_chars(struct uart_port *);
624static void handle_intr(void *arg, uint32_t sio_ir); 636static void handle_intr(void *arg, uint32_t sio_ir);
625 637
638/*
639 * port_is_active - determines if this port is currently active
640 * @port: ptr to soft struct for this port
641 * @uart_port: uart port to test for
642 */
643static inline int port_is_active(struct ioc4_port *port,
644 struct uart_port *uart_port)
645{
646 if (port) {
647 if ((port->ip_flags & PORT_ACTIVE)
648 && (port->ip_port == uart_port))
649 return 1;
650 }
651 return 0;
652}
653
654
626/** 655/**
627 * write_ireg - write the interrupt regs 656 * write_ireg - write the interrupt regs
628 * @ioc4_soft: ptr to soft struct for this port 657 * @ioc4_soft: ptr to soft struct for this port
@@ -708,19 +737,33 @@ static int set_baud(struct ioc4_port *port, int baud)
708/** 737/**
709 * get_ioc4_port - given a uart port, return the control structure 738 * get_ioc4_port - given a uart port, return the control structure
710 * @port: uart port 739 * @port: uart port
740 * @set: set this port as current
711 */ 741 */
712static struct ioc4_port *get_ioc4_port(struct uart_port *the_port) 742static struct ioc4_port *get_ioc4_port(struct uart_port *the_port, int set)
713{ 743{
714 struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev); 744 struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev);
715 struct ioc4_control *control = idd->idd_serial_data; 745 struct ioc4_control *control = idd->idd_serial_data;
716 int ii; 746 struct ioc4_port *port;
747 int port_num, port_type;
717 748
718 if (control) { 749 if (control) {
719 for ( ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++ ) { 750 for ( port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS;
720 if (!control->ic_port[ii].icp_port) 751 port_num++ ) {
752 port = control->ic_port[port_num].icp_port;
753 if (!port)
721 continue; 754 continue;
722 if (the_port == control->ic_port[ii].icp_port->ip_port) 755 for (port_type = UART_PORT_MIN;
723 return control->ic_port[ii].icp_port; 756 port_type < UART_PORT_COUNT;
757 port_type++) {
758 if (the_port == port->ip_all_ports
759 [port_type]) {
760 /* set local copy */
761 if (set) {
762 port->ip_port = the_port;
763 }
764 return port;
765 }
766 }
724 } 767 }
725 } 768 }
726 return NULL; 769 return NULL;
@@ -946,6 +989,7 @@ intr_connect(struct ioc4_soft *soft, int type,
946 * @arg: handler arg 989 * @arg: handler arg
947 * @regs: registers 990 * @regs: registers
948 */ 991 */
992
949static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs) 993static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs)
950{ 994{
951 struct ioc4_soft *soft; 995 struct ioc4_soft *soft;
@@ -953,7 +997,7 @@ static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs)
953 int xx, num_intrs = 0; 997 int xx, num_intrs = 0;
954 int intr_type; 998 int intr_type;
955 int handled = 0; 999 int handled = 0;
956 struct ioc4_intr_info *ii; 1000 struct ioc4_intr_info *intr_info;
957 1001
958 soft = arg; 1002 soft = arg;
959 for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) { 1003 for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) {
@@ -966,13 +1010,13 @@ static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs)
966 * which interrupt bits are set. 1010 * which interrupt bits are set.
967 */ 1011 */
968 for (xx = 0; xx < num_intrs; xx++) { 1012 for (xx = 0; xx < num_intrs; xx++) {
969 ii = &soft->is_intr_type[intr_type].is_intr_info[xx]; 1013 intr_info = &soft->is_intr_type[intr_type].is_intr_info[xx];
970 if ((this_mir = this_ir & ii->sd_bits)) { 1014 if ((this_mir = this_ir & intr_info->sd_bits)) {
971 /* Disable owned interrupts, call handler */ 1015 /* Disable owned interrupts, call handler */
972 handled++; 1016 handled++;
973 write_ireg(soft, ii->sd_bits, IOC4_W_IEC, 1017 write_ireg(soft, intr_info->sd_bits, IOC4_W_IEC,
974 intr_type); 1018 intr_type);
975 ii->sd_intr(ii->sd_info, this_mir); 1019 intr_info->sd_intr(intr_info->sd_info, this_mir);
976 this_ir &= ~this_mir; 1020 this_ir &= ~this_mir;
977 } 1021 }
978 } 1022 }
@@ -980,7 +1024,6 @@ static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs)
980#ifdef DEBUG_INTERRUPTS 1024#ifdef DEBUG_INTERRUPTS
981 { 1025 {
982 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr; 1026 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
983 spinlock_t *lp = &soft->is_ir_lock;
984 unsigned long flag; 1027 unsigned long flag;
985 1028
986 spin_lock_irqsave(&soft->is_ir_lock, flag); 1029 spin_lock_irqsave(&soft->is_ir_lock, flag);
@@ -1177,7 +1220,7 @@ static inline int local_open(struct ioc4_port *port)
1177{ 1220{
1178 int spiniter = 0; 1221 int spiniter = 0;
1179 1222
1180 port->ip_flags = 0; 1223 port->ip_flags = PORT_ACTIVE;
1181 1224
1182 /* Pause the DMA interface if necessary */ 1225 /* Pause the DMA interface if necessary */
1183 if (port->ip_sscr & IOC4_SSCR_DMA_EN) { 1226 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
@@ -1187,6 +1230,7 @@ static inline int local_open(struct ioc4_port *port)
1187 & IOC4_SSCR_PAUSE_STATE) == 0) { 1230 & IOC4_SSCR_PAUSE_STATE) == 0) {
1188 spiniter++; 1231 spiniter++;
1189 if (spiniter > MAXITER) { 1232 if (spiniter > MAXITER) {
1233 port->ip_flags = PORT_INACTIVE;
1190 return -1; 1234 return -1;
1191 } 1235 }
1192 } 1236 }
@@ -1506,14 +1550,13 @@ static int set_notification(struct ioc4_port *port, int mask, int set_on)
1506/** 1550/**
1507 * set_mcr - set the master control reg 1551 * set_mcr - set the master control reg
1508 * @the_port: port to use 1552 * @the_port: port to use
1509 * @set: set ?
1510 * @mask1: mcr mask 1553 * @mask1: mcr mask
1511 * @mask2: shadow mask 1554 * @mask2: shadow mask
1512 */ 1555 */
1513static inline int set_mcr(struct uart_port *the_port, int set, 1556static inline int set_mcr(struct uart_port *the_port,
1514 int mask1, int mask2) 1557 int mask1, int mask2)
1515{ 1558{
1516 struct ioc4_port *port = get_ioc4_port(the_port); 1559 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1517 uint32_t shadow; 1560 uint32_t shadow;
1518 int spiniter = 0; 1561 int spiniter = 0;
1519 char mcr; 1562 char mcr;
@@ -1536,13 +1579,9 @@ static inline int set_mcr(struct uart_port *the_port, int set,
1536 mcr = (shadow & 0xff000000) >> 24; 1579 mcr = (shadow & 0xff000000) >> 24;
1537 1580
1538 /* Set new value */ 1581 /* Set new value */
1539 if (set) { 1582 mcr |= mask1;
1540 mcr |= mask1; 1583 shadow |= mask2;
1541 shadow |= mask2; 1584
1542 } else {
1543 mcr &= ~mask1;
1544 shadow &= ~mask2;
1545 }
1546 writeb(mcr, &port->ip_uart_regs->i4u_mcr); 1585 writeb(mcr, &port->ip_uart_regs->i4u_mcr);
1547 writel(shadow, &port->ip_serial_regs->shadow); 1586 writel(shadow, &port->ip_serial_regs->shadow);
1548 1587
@@ -1558,7 +1597,7 @@ static inline int set_mcr(struct uart_port *the_port, int set,
1558 * @port: port to use 1597 * @port: port to use
1559 * @proto: protocol to use 1598 * @proto: protocol to use
1560 */ 1599 */
1561static int ioc4_set_proto(struct ioc4_port *port, enum sio_proto proto) 1600static int ioc4_set_proto(struct ioc4_port *port, int proto)
1562{ 1601{
1563 struct hooks *hooks = port->ip_hooks; 1602 struct hooks *hooks = port->ip_hooks;
1564 1603
@@ -1589,7 +1628,7 @@ static void transmit_chars(struct uart_port *the_port)
1589 int result; 1628 int result;
1590 char *start; 1629 char *start;
1591 struct tty_struct *tty; 1630 struct tty_struct *tty;
1592 struct ioc4_port *port = get_ioc4_port(the_port); 1631 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1593 struct uart_info *info; 1632 struct uart_info *info;
1594 1633
1595 if (!the_port) 1634 if (!the_port)
@@ -1645,7 +1684,7 @@ static void
1645ioc4_change_speed(struct uart_port *the_port, 1684ioc4_change_speed(struct uart_port *the_port,
1646 struct termios *new_termios, struct termios *old_termios) 1685 struct termios *new_termios, struct termios *old_termios)
1647{ 1686{
1648 struct ioc4_port *port = get_ioc4_port(the_port); 1687 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1649 int baud, bits; 1688 int baud, bits;
1650 unsigned cflag; 1689 unsigned cflag;
1651 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8; 1690 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
@@ -1752,7 +1791,7 @@ static inline int ic4_startup_local(struct uart_port *the_port)
1752 if (!the_port) 1791 if (!the_port)
1753 return -1; 1792 return -1;
1754 1793
1755 port = get_ioc4_port(the_port); 1794 port = get_ioc4_port(the_port, 0);
1756 if (!port) 1795 if (!port)
1757 return -1; 1796 return -1;
1758 1797
@@ -1760,6 +1799,9 @@ static inline int ic4_startup_local(struct uart_port *the_port)
1760 1799
1761 local_open(port); 1800 local_open(port);
1762 1801
1802 /* set the protocol - mapbase has the port type */
1803 ioc4_set_proto(port, the_port->mapbase);
1804
1763 /* set the speed of the serial port */ 1805 /* set the speed of the serial port */
1764 ioc4_change_speed(the_port, info->tty->termios, (struct termios *)0); 1806 ioc4_change_speed(the_port, info->tty->termios, (struct termios *)0);
1765 1807
@@ -1768,17 +1810,17 @@ static inline int ic4_startup_local(struct uart_port *the_port)
1768 1810
1769/* 1811/*
1770 * ioc4_cb_output_lowat - called when the output low water mark is hit 1812 * ioc4_cb_output_lowat - called when the output low water mark is hit
1771 * @port: port to output 1813 * @the_port: port to output
1772 */ 1814 */
1773static void ioc4_cb_output_lowat(struct ioc4_port *port) 1815static void ioc4_cb_output_lowat(struct uart_port *the_port)
1774{ 1816{
1775 unsigned long pflags; 1817 unsigned long pflags;
1776 1818
1777 /* ip_lock is set on the call here */ 1819 /* ip_lock is set on the call here */
1778 if (port->ip_port) { 1820 if (the_port) {
1779 spin_lock_irqsave(&port->ip_port->lock, pflags); 1821 spin_lock_irqsave(&the_port->lock, pflags);
1780 transmit_chars(port->ip_port); 1822 transmit_chars(the_port);
1781 spin_unlock_irqrestore(&port->ip_port->lock, pflags); 1823 spin_unlock_irqrestore(&the_port->lock, pflags);
1782 } 1824 }
1783} 1825}
1784 1826
@@ -1923,7 +1965,7 @@ static void handle_intr(void *arg, uint32_t sio_ir)
1923 &port->ip_mem->sio_ir.raw); 1965 &port->ip_mem->sio_ir.raw);
1924 1966
1925 if (port->ip_notify & N_OUTPUT_LOWAT) 1967 if (port->ip_notify & N_OUTPUT_LOWAT)
1926 ioc4_cb_output_lowat(port); 1968 ioc4_cb_output_lowat(port->ip_port);
1927 } 1969 }
1928 1970
1929 /* Handle tx_mt. Must come after tx_explicit. */ 1971 /* Handle tx_mt. Must come after tx_explicit. */
@@ -1936,7 +1978,7 @@ static void handle_intr(void *arg, uint32_t sio_ir)
1936 * So send the notification now. 1978 * So send the notification now.
1937 */ 1979 */
1938 if (port->ip_notify & N_OUTPUT_LOWAT) { 1980 if (port->ip_notify & N_OUTPUT_LOWAT) {
1939 ioc4_cb_output_lowat(port); 1981 ioc4_cb_output_lowat(port->ip_port);
1940 1982
1941 /* We need to reload the sio_ir since the lowat 1983 /* We need to reload the sio_ir since the lowat
1942 * call may have caused another write to occur, 1984 * call may have caused another write to occur,
@@ -2023,7 +2065,7 @@ static inline int do_read(struct uart_port *the_port, unsigned char *buf,
2023 int len) 2065 int len)
2024{ 2066{
2025 int prod_ptr, cons_ptr, total; 2067 int prod_ptr, cons_ptr, total;
2026 struct ioc4_port *port = get_ioc4_port(the_port); 2068 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2027 struct ring *inring; 2069 struct ring *inring;
2028 struct ring_entry *entry; 2070 struct ring_entry *entry;
2029 struct hooks *hooks = port->ip_hooks; 2071 struct hooks *hooks = port->ip_hooks;
@@ -2335,17 +2377,27 @@ static void receive_chars(struct uart_port *the_port)
2335 */ 2377 */
2336static const char *ic4_type(struct uart_port *the_port) 2378static const char *ic4_type(struct uart_port *the_port)
2337{ 2379{
2338 return "SGI IOC4 Serial"; 2380 if (the_port->mapbase == PROTO_RS232)
2381 return "SGI IOC4 Serial [rs232]";
2382 else
2383 return "SGI IOC4 Serial [rs422]";
2339} 2384}
2340 2385
2341/** 2386/**
2342 * ic4_tx_empty - Is the transmitter empty? We pretend we're always empty 2387 * ic4_tx_empty - Is the transmitter empty?
2343 * @port: Port to operate on (we ignore since we always return 1) 2388 * @port: Port to operate on
2344 * 2389 *
2345 */ 2390 */
2346static unsigned int ic4_tx_empty(struct uart_port *the_port) 2391static unsigned int ic4_tx_empty(struct uart_port *the_port)
2347{ 2392{
2348 return 1; 2393 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2394 unsigned int ret = 0;
2395
2396 if (port_is_active(port, the_port)) {
2397 if (readl(&port->ip_serial_regs->shadow) & IOC4_SHADOW_TEMT)
2398 ret = TIOCSER_TEMT;
2399 }
2400 return ret;
2349} 2401}
2350 2402
2351/** 2403/**
@@ -2355,6 +2407,10 @@ static unsigned int ic4_tx_empty(struct uart_port *the_port)
2355 */ 2407 */
2356static void ic4_stop_tx(struct uart_port *the_port) 2408static void ic4_stop_tx(struct uart_port *the_port)
2357{ 2409{
2410 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2411
2412 if (port_is_active(port, the_port))
2413 set_notification(port, N_OUTPUT_LOWAT, 0);
2358} 2414}
2359 2415
2360/** 2416/**
@@ -2377,11 +2433,12 @@ static void ic4_shutdown(struct uart_port *the_port)
2377 struct ioc4_port *port; 2433 struct ioc4_port *port;
2378 struct uart_info *info; 2434 struct uart_info *info;
2379 2435
2380 port = get_ioc4_port(the_port); 2436 port = get_ioc4_port(the_port, 0);
2381 if (!port) 2437 if (!port)
2382 return; 2438 return;
2383 2439
2384 info = the_port->info; 2440 info = the_port->info;
2441 port->ip_port = NULL;
2385 2442
2386 wake_up_interruptible(&info->delta_msr_wait); 2443 wake_up_interruptible(&info->delta_msr_wait);
2387 2444
@@ -2390,6 +2447,7 @@ static void ic4_shutdown(struct uart_port *the_port)
2390 2447
2391 spin_lock_irqsave(&the_port->lock, port_flags); 2448 spin_lock_irqsave(&the_port->lock, port_flags);
2392 set_notification(port, N_ALL, 0); 2449 set_notification(port, N_ALL, 0);
2450 port->ip_flags = PORT_INACTIVE;
2393 spin_unlock_irqrestore(&the_port->lock, port_flags); 2451 spin_unlock_irqrestore(&the_port->lock, port_flags);
2394} 2452}
2395 2453
@@ -2402,6 +2460,11 @@ static void ic4_shutdown(struct uart_port *the_port)
2402static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl) 2460static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2403{ 2461{
2404 unsigned char mcr = 0; 2462 unsigned char mcr = 0;
2463 struct ioc4_port *port;
2464
2465 port = get_ioc4_port(the_port, 0);
2466 if (!port_is_active(port, the_port))
2467 return;
2405 2468
2406 if (mctrl & TIOCM_RTS) 2469 if (mctrl & TIOCM_RTS)
2407 mcr |= UART_MCR_RTS; 2470 mcr |= UART_MCR_RTS;
@@ -2414,7 +2477,7 @@ static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2414 if (mctrl & TIOCM_LOOP) 2477 if (mctrl & TIOCM_LOOP)
2415 mcr |= UART_MCR_LOOP; 2478 mcr |= UART_MCR_LOOP;
2416 2479
2417 set_mcr(the_port, 1, mcr, IOC4_SHADOW_DTR); 2480 set_mcr(the_port, mcr, IOC4_SHADOW_DTR);
2418} 2481}
2419 2482
2420/** 2483/**
@@ -2424,11 +2487,11 @@ static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2424 */ 2487 */
2425static unsigned int ic4_get_mctrl(struct uart_port *the_port) 2488static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2426{ 2489{
2427 struct ioc4_port *port = get_ioc4_port(the_port); 2490 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2428 uint32_t shadow; 2491 uint32_t shadow;
2429 unsigned int ret = 0; 2492 unsigned int ret = 0;
2430 2493
2431 if (!port) 2494 if (!port_is_active(port, the_port))
2432 return 0; 2495 return 0;
2433 2496
2434 shadow = readl(&port->ip_serial_regs->shadow); 2497 shadow = readl(&port->ip_serial_regs->shadow);
@@ -2448,9 +2511,9 @@ static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2448 */ 2511 */
2449static void ic4_start_tx(struct uart_port *the_port) 2512static void ic4_start_tx(struct uart_port *the_port)
2450{ 2513{
2451 struct ioc4_port *port = get_ioc4_port(the_port); 2514 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2452 2515
2453 if (port) { 2516 if (port_is_active(port, the_port)) {
2454 set_notification(port, N_OUTPUT_LOWAT, 1); 2517 set_notification(port, N_OUTPUT_LOWAT, 1);
2455 enable_intrs(port, port->ip_hooks->intr_tx_mt); 2518 enable_intrs(port, port->ip_hooks->intr_tx_mt);
2456 } 2519 }
@@ -2467,7 +2530,7 @@ static void ic4_break_ctl(struct uart_port *the_port, int break_state)
2467} 2530}
2468 2531
2469/** 2532/**
2470 * ic4_startup - Start up the serial port - always return 0 (We're always on) 2533 * ic4_startup - Start up the serial port
2471 * @port: Port to operate on 2534 * @port: Port to operate on
2472 * 2535 *
2473 */ 2536 */
@@ -2479,17 +2542,16 @@ static int ic4_startup(struct uart_port *the_port)
2479 struct uart_info *info; 2542 struct uart_info *info;
2480 unsigned long port_flags; 2543 unsigned long port_flags;
2481 2544
2482 if (!the_port) { 2545 if (!the_port)
2483 return -ENODEV; 2546 return -ENODEV;
2484 } 2547 port = get_ioc4_port(the_port, 1);
2485 port = get_ioc4_port(the_port); 2548 if (!port)
2486 if (!port) {
2487 return -ENODEV; 2549 return -ENODEV;
2488 }
2489 info = the_port->info; 2550 info = the_port->info;
2490 2551
2491 control = port->ip_control; 2552 control = port->ip_control;
2492 if (!control) { 2553 if (!control) {
2554 port->ip_port = NULL;
2493 return -ENODEV; 2555 return -ENODEV;
2494 } 2556 }
2495 2557
@@ -2551,28 +2613,104 @@ static struct uart_ops ioc4_ops = {
2551 * Boot-time initialization code 2613 * Boot-time initialization code
2552 */ 2614 */
2553 2615
2554static struct uart_driver ioc4_uart = { 2616static struct uart_driver ioc4_uart_rs232 = {
2555 .owner = THIS_MODULE, 2617 .owner = THIS_MODULE,
2556 .driver_name = "ioc4_serial", 2618 .driver_name = "ioc4_serial_rs232",
2557 .dev_name = DEVICE_NAME, 2619 .dev_name = DEVICE_NAME_RS232,
2558 .major = DEVICE_MAJOR, 2620 .major = DEVICE_MAJOR,
2559 .minor = DEVICE_MINOR, 2621 .minor = DEVICE_MINOR_RS232,
2560 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS, 2622 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2561}; 2623};
2562 2624
2625static struct uart_driver ioc4_uart_rs422 = {
2626 .owner = THIS_MODULE,
2627 .driver_name = "ioc4_serial_rs422",
2628 .dev_name = DEVICE_NAME_RS422,
2629 .major = DEVICE_MAJOR,
2630 .minor = DEVICE_MINOR_RS422,
2631 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2632};
2633
2634
2563/** 2635/**
2564 * ioc4_serial_core_attach - register with serial core 2636 * ioc4_serial_remove_one - detach function
2637 *
2638 * @idd: IOC4 master module data for this IOC4
2639 */
2640
2641static int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
2642{
2643 int port_num, port_type;
2644 struct ioc4_control *control;
2645 struct uart_port *the_port;
2646 struct ioc4_port *port;
2647 struct ioc4_soft *soft;
2648
2649 control = idd->idd_serial_data;
2650
2651 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2652 for (port_type = UART_PORT_MIN;
2653 port_type < UART_PORT_COUNT;
2654 port_type++) {
2655 the_port = &control->ic_port[port_num].icp_uart_port
2656 [port_type];
2657 if (the_port) {
2658 switch (port_type) {
2659 case UART_PORT_RS422:
2660 uart_remove_one_port(&ioc4_uart_rs422,
2661 the_port);
2662 break;
2663 default:
2664 case UART_PORT_RS232:
2665 uart_remove_one_port(&ioc4_uart_rs232,
2666 the_port);
2667 break;
2668 }
2669 }
2670 }
2671 port = control->ic_port[port_num].icp_port;
2672 /* we allocate in pairs */
2673 if (!(port_num & 1) && port) {
2674 pci_free_consistent(port->ip_pdev,
2675 TOTAL_RING_BUF_SIZE,
2676 port->ip_cpu_ringbuf,
2677 port->ip_dma_ringbuf);
2678 kfree(port);
2679 }
2680 }
2681 soft = control->ic_soft;
2682 if (soft) {
2683 free_irq(control->ic_irq, soft);
2684 if (soft->is_ioc4_serial_addr) {
2685 release_region((unsigned long)
2686 soft->is_ioc4_serial_addr,
2687 sizeof(struct ioc4_serial));
2688 }
2689 kfree(soft);
2690 }
2691 kfree(control);
2692 idd->idd_serial_data = NULL;
2693
2694 return 0;
2695}
2696
2697
2698/**
2699 * ioc4_serial_core_attach_rs232 - register with serial core
2565 * This is done during pci probing 2700 * This is done during pci probing
2566 * @pdev: handle for this card 2701 * @pdev: handle for this card
2567 */ 2702 */
2568static inline int 2703static inline int
2569ioc4_serial_core_attach(struct pci_dev *pdev) 2704ioc4_serial_core_attach(struct pci_dev *pdev, int port_type)
2570{ 2705{
2571 struct ioc4_port *port; 2706 struct ioc4_port *port;
2572 struct uart_port *the_port; 2707 struct uart_port *the_port;
2573 struct ioc4_driver_data *idd = pci_get_drvdata(pdev); 2708 struct ioc4_driver_data *idd = pci_get_drvdata(pdev);
2574 struct ioc4_control *control = idd->idd_serial_data; 2709 struct ioc4_control *control = idd->idd_serial_data;
2575 int ii; 2710 int port_num;
2711 int port_type_idx;
2712 struct uart_driver *u_driver;
2713
2576 2714
2577 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n", 2715 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n",
2578 __FUNCTION__, pdev, (void *)control)); 2716 __FUNCTION__, pdev, (void *)control));
@@ -2580,28 +2718,36 @@ ioc4_serial_core_attach(struct pci_dev *pdev)
2580 if (!control) 2718 if (!control)
2581 return -ENODEV; 2719 return -ENODEV;
2582 2720
2721 port_type_idx = (port_type == PROTO_RS232) ? UART_PORT_RS232
2722 : UART_PORT_RS422;
2723
2724 u_driver = (port_type == PROTO_RS232) ? &ioc4_uart_rs232
2725 : &ioc4_uart_rs422;
2726
2583 /* once around for each port on this card */ 2727 /* once around for each port on this card */
2584 for (ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++) { 2728 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2585 the_port = &control->ic_port[ii].icp_uart_port; 2729 the_port = &control->ic_port[port_num].icp_uart_port
2586 port = control->ic_port[ii].icp_port; 2730 [port_type_idx];
2587 port->ip_port = the_port; 2731 port = control->ic_port[port_num].icp_port;
2732 port->ip_all_ports[port_type_idx] = the_port;
2588 2733
2589 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p\n", 2734 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p : type %s\n",
2590 __FUNCTION__, (void *)the_port, 2735 __FUNCTION__, (void *)the_port,
2591 (void *)port)); 2736 (void *)port,
2737 port_type == PROTO_RS232 ? "rs232" : "rs422"));
2592 2738
2593 /* membase, iobase and mapbase just need to be non-0 */ 2739 /* membase, iobase and mapbase just need to be non-0 */
2594 the_port->membase = (unsigned char __iomem *)1; 2740 the_port->membase = (unsigned char __iomem *)1;
2595 the_port->iobase = (pdev->bus->number << 16) | ii; 2741 the_port->iobase = (pdev->bus->number << 16) | port_num;
2596 the_port->line = (Num_of_ioc4_cards << 2) | ii; 2742 the_port->line = (Num_of_ioc4_cards << 2) | port_num;
2597 the_port->mapbase = 1; 2743 the_port->mapbase = port_type;
2598 the_port->type = PORT_16550A; 2744 the_port->type = PORT_16550A;
2599 the_port->fifosize = IOC4_FIFO_CHARS; 2745 the_port->fifosize = IOC4_FIFO_CHARS;
2600 the_port->ops = &ioc4_ops; 2746 the_port->ops = &ioc4_ops;
2601 the_port->irq = control->ic_irq; 2747 the_port->irq = control->ic_irq;
2602 the_port->dev = &pdev->dev; 2748 the_port->dev = &pdev->dev;
2603 spin_lock_init(&the_port->lock); 2749 spin_lock_init(&the_port->lock);
2604 if (uart_add_one_port(&ioc4_uart, the_port) < 0) { 2750 if (uart_add_one_port(u_driver, the_port) < 0) {
2605 printk(KERN_WARNING 2751 printk(KERN_WARNING
2606 "%s: unable to add port %d bus %d\n", 2752 "%s: unable to add port %d bus %d\n",
2607 __FUNCTION__, the_port->line, pdev->bus->number); 2753 __FUNCTION__, the_port->line, pdev->bus->number);
@@ -2610,8 +2756,6 @@ ioc4_serial_core_attach(struct pci_dev *pdev)
2610 ("IOC4 serial port %d irq = %d, bus %d\n", 2756 ("IOC4 serial port %d irq = %d, bus %d\n",
2611 the_port->line, the_port->irq, pdev->bus->number)); 2757 the_port->line, the_port->irq, pdev->bus->number));
2612 } 2758 }
2613 /* all ports are rs232 for now */
2614 ioc4_set_proto(port, PROTO_RS232);
2615 } 2759 }
2616 return 0; 2760 return 0;
2617} 2761}
@@ -2631,7 +2775,8 @@ ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2631 int ret = 0; 2775 int ret = 0;
2632 2776
2633 2777
2634 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __FUNCTION__, idd->idd_pdev, idd->idd_pci_id)); 2778 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __FUNCTION__, idd->idd_pdev,
2779 idd->idd_pci_id));
2635 2780
2636 /* request serial registers */ 2781 /* request serial registers */
2637 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET; 2782 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET;
@@ -2653,11 +2798,11 @@ ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2653 goto out2; 2798 goto out2;
2654 } 2799 }
2655 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n", 2800 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n",
2656 __FUNCTION__, (void *)idd->idd_misc_regs, (void *)serial)); 2801 __FUNCTION__, (void *)idd->idd_misc_regs,
2802 (void *)serial));
2657 2803
2658 /* Get memory for the new card */ 2804 /* Get memory for the new card */
2659 control = kmalloc(sizeof(struct ioc4_control) * IOC4_NUM_SERIAL_PORTS, 2805 control = kmalloc(sizeof(struct ioc4_control), GFP_KERNEL);
2660 GFP_KERNEL);
2661 2806
2662 if (!control) { 2807 if (!control) {
2663 printk(KERN_WARNING "ioc4_attach_one" 2808 printk(KERN_WARNING "ioc4_attach_one"
@@ -2702,7 +2847,7 @@ ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2702 2847
2703 /* Hook up interrupt handler */ 2848 /* Hook up interrupt handler */
2704 if (!request_irq(idd->idd_pdev->irq, ioc4_intr, SA_SHIRQ, 2849 if (!request_irq(idd->idd_pdev->irq, ioc4_intr, SA_SHIRQ,
2705 "sgi-ioc4serial", (void *)soft)) { 2850 "sgi-ioc4serial", soft)) {
2706 control->ic_irq = idd->idd_pdev->irq; 2851 control->ic_irq = idd->idd_pdev->irq;
2707 } else { 2852 } else {
2708 printk(KERN_WARNING 2853 printk(KERN_WARNING
@@ -2713,16 +2858,21 @@ ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2713 if (ret) 2858 if (ret)
2714 goto out4; 2859 goto out4;
2715 2860
2716 /* register port with the serial core */ 2861 /* register port with the serial core - 1 rs232, 1 rs422 */
2717 2862
2718 if ((ret = ioc4_serial_core_attach(idd->idd_pdev))) 2863 if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS232)))
2719 goto out4; 2864 goto out4;
2720 2865
2866 if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS422)))
2867 goto out5;
2868
2721 Num_of_ioc4_cards++; 2869 Num_of_ioc4_cards++;
2722 2870
2723 return ret; 2871 return ret;
2724 2872
2725 /* error exits that give back resources */ 2873 /* error exits that give back resources */
2874out5:
2875 ioc4_serial_remove_one(idd);
2726out4: 2876out4:
2727 kfree(soft); 2877 kfree(soft);
2728out3: 2878out3:
@@ -2735,52 +2885,6 @@ out1:
2735} 2885}
2736 2886
2737 2887
2738/**
2739 * ioc4_serial_remove_one - detach function
2740 *
2741 * @idd: IOC4 master module data for this IOC4
2742 */
2743
2744int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
2745{
2746 int ii;
2747 struct ioc4_control *control;
2748 struct uart_port *the_port;
2749 struct ioc4_port *port;
2750 struct ioc4_soft *soft;
2751
2752 control = idd->idd_serial_data;
2753
2754 for (ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++) {
2755 the_port = &control->ic_port[ii].icp_uart_port;
2756 if (the_port) {
2757 uart_remove_one_port(&ioc4_uart, the_port);
2758 }
2759 port = control->ic_port[ii].icp_port;
2760 if (!(ii & 1) && port) {
2761 pci_free_consistent(port->ip_pdev,
2762 TOTAL_RING_BUF_SIZE,
2763 (void *)port->ip_cpu_ringbuf,
2764 port->ip_dma_ringbuf);
2765 kfree(port);
2766 }
2767 }
2768 soft = control->ic_soft;
2769 if (soft) {
2770 free_irq(control->ic_irq, (void *)soft);
2771 if (soft->is_ioc4_serial_addr) {
2772 release_region((unsigned long)
2773 soft->is_ioc4_serial_addr,
2774 sizeof(struct ioc4_serial));
2775 }
2776 kfree(soft);
2777 }
2778 kfree(control);
2779 idd->idd_serial_data = NULL;
2780
2781 return 0;
2782}
2783
2784static struct ioc4_submodule ioc4_serial_submodule = { 2888static struct ioc4_submodule ioc4_serial_submodule = {
2785 .is_name = "IOC4_serial", 2889 .is_name = "IOC4_serial",
2786 .is_owner = THIS_MODULE, 2890 .is_owner = THIS_MODULE,
@@ -2796,9 +2900,15 @@ int ioc4_serial_init(void)
2796 int ret; 2900 int ret;
2797 2901
2798 /* register with serial core */ 2902 /* register with serial core */
2799 if ((ret = uart_register_driver(&ioc4_uart)) < 0) { 2903 if ((ret = uart_register_driver(&ioc4_uart_rs232)) < 0) {
2904 printk(KERN_WARNING
2905 "%s: Couldn't register rs232 IOC4 serial driver\n",
2906 __FUNCTION__);
2907 return ret;
2908 }
2909 if ((ret = uart_register_driver(&ioc4_uart_rs422)) < 0) {
2800 printk(KERN_WARNING 2910 printk(KERN_WARNING
2801 "%s: Couldn't register IOC4 serial driver\n", 2911 "%s: Couldn't register rs422 IOC4 serial driver\n",
2802 __FUNCTION__); 2912 __FUNCTION__);
2803 return ret; 2913 return ret;
2804 } 2914 }
@@ -2810,7 +2920,8 @@ int ioc4_serial_init(void)
2810static void __devexit ioc4_serial_exit(void) 2920static void __devexit ioc4_serial_exit(void)
2811{ 2921{
2812 ioc4_unregister_submodule(&ioc4_serial_submodule); 2922 ioc4_unregister_submodule(&ioc4_serial_submodule);
2813 uart_unregister_driver(&ioc4_uart); 2923 uart_unregister_driver(&ioc4_uart_rs232);
2924 uart_unregister_driver(&ioc4_uart_rs422);
2814} 2925}
2815 2926
2816module_init(ioc4_serial_init); 2927module_init(ioc4_serial_init);
diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c
index 928e6cf12dca..6459edc7f5c5 100644
--- a/drivers/serial/mpc52xx_uart.c
+++ b/drivers/serial/mpc52xx_uart.c
@@ -40,7 +40,7 @@
40 * and so on). So the PSC1 is mapped to /dev/ttyPSC0, PSC2 to /dev/ttyPSC1 and 40 * and so on). So the PSC1 is mapped to /dev/ttyPSC0, PSC2 to /dev/ttyPSC1 and
41 * so on. But be warned, it's an ABSOLUTE REQUIREMENT ! This is needed mainly 41 * so on. But be warned, it's an ABSOLUTE REQUIREMENT ! This is needed mainly
42 * fpr the console code : without this 1:1 mapping, at early boot time, when we 42 * fpr the console code : without this 1:1 mapping, at early boot time, when we
43 * are parsing the kernel args console=ttyPSC?, we wouldn't know wich PSC it 43 * are parsing the kernel args console=ttyPSC?, we wouldn't know which PSC it
44 * will be mapped to. 44 * will be mapped to.
45 */ 45 */
46 46
diff --git a/drivers/serial/mpsc.c b/drivers/serial/mpsc.c
index 0ca83ac31d07..94681922ea0a 100644
--- a/drivers/serial/mpsc.c
+++ b/drivers/serial/mpsc.c
@@ -1,6 +1,4 @@
1/* 1/*
2 * drivers/serial/mpsc.c
3 *
4 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240, 2 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
5 * GT64260, MV64340, MV64360, GT96100, ... ). 3 * GT64260, MV64340, MV64360, GT96100, ... ).
6 * 4 *
@@ -52,9 +50,263 @@
52 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG. 50 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
53 */ 51 */
54 52
53#include <linux/config.h>
54
55#if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
56#define SUPPORT_SYSRQ
57#endif
58
59#include <linux/module.h>
60#include <linux/moduleparam.h>
61#include <linux/tty.h>
62#include <linux/tty_flip.h>
63#include <linux/ioport.h>
64#include <linux/init.h>
65#include <linux/console.h>
66#include <linux/sysrq.h>
67#include <linux/serial.h>
68#include <linux/serial_core.h>
69#include <linux/delay.h>
70#include <linux/device.h>
71#include <linux/dma-mapping.h>
72#include <linux/mv643xx.h>
55#include <linux/platform_device.h> 73#include <linux/platform_device.h>
56 74
57#include "mpsc.h" 75#include <asm/io.h>
76#include <asm/irq.h>
77
78#if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
79#define SUPPORT_SYSRQ
80#endif
81
82#define MPSC_NUM_CTLRS 2
83
84/*
85 * Descriptors and buffers must be cache line aligned.
86 * Buffers lengths must be multiple of cache line size.
87 * Number of Tx & Rx descriptors must be powers of 2.
88 */
89#define MPSC_RXR_ENTRIES 32
90#define MPSC_RXRE_SIZE dma_get_cache_alignment()
91#define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
92#define MPSC_RXBE_SIZE dma_get_cache_alignment()
93#define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
94
95#define MPSC_TXR_ENTRIES 32
96#define MPSC_TXRE_SIZE dma_get_cache_alignment()
97#define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
98#define MPSC_TXBE_SIZE dma_get_cache_alignment()
99#define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
100
101#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \
102 MPSC_TXR_SIZE + MPSC_TXB_SIZE + \
103 dma_get_cache_alignment() /* for alignment */)
104
105/* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
106struct mpsc_rx_desc {
107 u16 bufsize;
108 u16 bytecnt;
109 u32 cmdstat;
110 u32 link;
111 u32 buf_ptr;
112} __attribute((packed));
113
114struct mpsc_tx_desc {
115 u16 bytecnt;
116 u16 shadow;
117 u32 cmdstat;
118 u32 link;
119 u32 buf_ptr;
120} __attribute((packed));
121
122/*
123 * Some regs that have the erratum that you can't read them are are shared
124 * between the two MPSC controllers. This struct contains those shared regs.
125 */
126struct mpsc_shared_regs {
127 phys_addr_t mpsc_routing_base_p;
128 phys_addr_t sdma_intr_base_p;
129
130 void __iomem *mpsc_routing_base;
131 void __iomem *sdma_intr_base;
132
133 u32 MPSC_MRR_m;
134 u32 MPSC_RCRR_m;
135 u32 MPSC_TCRR_m;
136 u32 SDMA_INTR_CAUSE_m;
137 u32 SDMA_INTR_MASK_m;
138};
139
140/* The main driver data structure */
141struct mpsc_port_info {
142 struct uart_port port; /* Overlay uart_port structure */
143
144 /* Internal driver state for this ctlr */
145 u8 ready;
146 u8 rcv_data;
147 tcflag_t c_iflag; /* save termios->c_iflag */
148 tcflag_t c_cflag; /* save termios->c_cflag */
149
150 /* Info passed in from platform */
151 u8 mirror_regs; /* Need to mirror regs? */
152 u8 cache_mgmt; /* Need manual cache mgmt? */
153 u8 brg_can_tune; /* BRG has baud tuning? */
154 u32 brg_clk_src;
155 u16 mpsc_max_idle;
156 int default_baud;
157 int default_bits;
158 int default_parity;
159 int default_flow;
160
161 /* Physical addresses of various blocks of registers (from platform) */
162 phys_addr_t mpsc_base_p;
163 phys_addr_t sdma_base_p;
164 phys_addr_t brg_base_p;
165
166 /* Virtual addresses of various blocks of registers (from platform) */
167 void __iomem *mpsc_base;
168 void __iomem *sdma_base;
169 void __iomem *brg_base;
170
171 /* Descriptor ring and buffer allocations */
172 void *dma_region;
173 dma_addr_t dma_region_p;
174
175 dma_addr_t rxr; /* Rx descriptor ring */
176 dma_addr_t rxr_p; /* Phys addr of rxr */
177 u8 *rxb; /* Rx Ring I/O buf */
178 u8 *rxb_p; /* Phys addr of rxb */
179 u32 rxr_posn; /* First desc w/ Rx data */
180
181 dma_addr_t txr; /* Tx descriptor ring */
182 dma_addr_t txr_p; /* Phys addr of txr */
183 u8 *txb; /* Tx Ring I/O buf */
184 u8 *txb_p; /* Phys addr of txb */
185 int txr_head; /* Where new data goes */
186 int txr_tail; /* Where sent data comes off */
187
188 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
189 u32 MPSC_MPCR_m;
190 u32 MPSC_CHR_1_m;
191 u32 MPSC_CHR_2_m;
192 u32 MPSC_CHR_10_m;
193 u32 BRG_BCR_m;
194 struct mpsc_shared_regs *shared_regs;
195};
196
197/* Hooks to platform-specific code */
198int mpsc_platform_register_driver(void);
199void mpsc_platform_unregister_driver(void);
200
201/* Hooks back in to mpsc common to be called by platform-specific code */
202struct mpsc_port_info *mpsc_device_probe(int index);
203struct mpsc_port_info *mpsc_device_remove(int index);
204
205/* Main MPSC Configuration Register Offsets */
206#define MPSC_MMCRL 0x0000
207#define MPSC_MMCRH 0x0004
208#define MPSC_MPCR 0x0008
209#define MPSC_CHR_1 0x000c
210#define MPSC_CHR_2 0x0010
211#define MPSC_CHR_3 0x0014
212#define MPSC_CHR_4 0x0018
213#define MPSC_CHR_5 0x001c
214#define MPSC_CHR_6 0x0020
215#define MPSC_CHR_7 0x0024
216#define MPSC_CHR_8 0x0028
217#define MPSC_CHR_9 0x002c
218#define MPSC_CHR_10 0x0030
219#define MPSC_CHR_11 0x0034
220
221#define MPSC_MPCR_FRZ (1 << 9)
222#define MPSC_MPCR_CL_5 0
223#define MPSC_MPCR_CL_6 1
224#define MPSC_MPCR_CL_7 2
225#define MPSC_MPCR_CL_8 3
226#define MPSC_MPCR_SBL_1 0
227#define MPSC_MPCR_SBL_2 1
228
229#define MPSC_CHR_2_TEV (1<<1)
230#define MPSC_CHR_2_TA (1<<7)
231#define MPSC_CHR_2_TTCS (1<<9)
232#define MPSC_CHR_2_REV (1<<17)
233#define MPSC_CHR_2_RA (1<<23)
234#define MPSC_CHR_2_CRD (1<<25)
235#define MPSC_CHR_2_EH (1<<31)
236#define MPSC_CHR_2_PAR_ODD 0
237#define MPSC_CHR_2_PAR_SPACE 1
238#define MPSC_CHR_2_PAR_EVEN 2
239#define MPSC_CHR_2_PAR_MARK 3
240
241/* MPSC Signal Routing */
242#define MPSC_MRR 0x0000
243#define MPSC_RCRR 0x0004
244#define MPSC_TCRR 0x0008
245
246/* Serial DMA Controller Interface Registers */
247#define SDMA_SDC 0x0000
248#define SDMA_SDCM 0x0008
249#define SDMA_RX_DESC 0x0800
250#define SDMA_RX_BUF_PTR 0x0808
251#define SDMA_SCRDP 0x0810
252#define SDMA_TX_DESC 0x0c00
253#define SDMA_SCTDP 0x0c10
254#define SDMA_SFTDP 0x0c14
255
256#define SDMA_DESC_CMDSTAT_PE (1<<0)
257#define SDMA_DESC_CMDSTAT_CDL (1<<1)
258#define SDMA_DESC_CMDSTAT_FR (1<<3)
259#define SDMA_DESC_CMDSTAT_OR (1<<6)
260#define SDMA_DESC_CMDSTAT_BR (1<<9)
261#define SDMA_DESC_CMDSTAT_MI (1<<10)
262#define SDMA_DESC_CMDSTAT_A (1<<11)
263#define SDMA_DESC_CMDSTAT_AM (1<<12)
264#define SDMA_DESC_CMDSTAT_CT (1<<13)
265#define SDMA_DESC_CMDSTAT_C (1<<14)
266#define SDMA_DESC_CMDSTAT_ES (1<<15)
267#define SDMA_DESC_CMDSTAT_L (1<<16)
268#define SDMA_DESC_CMDSTAT_F (1<<17)
269#define SDMA_DESC_CMDSTAT_P (1<<18)
270#define SDMA_DESC_CMDSTAT_EI (1<<23)
271#define SDMA_DESC_CMDSTAT_O (1<<31)
272
273#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
274 SDMA_DESC_CMDSTAT_EI)
275
276#define SDMA_SDC_RFT (1<<0)
277#define SDMA_SDC_SFM (1<<1)
278#define SDMA_SDC_BLMR (1<<6)
279#define SDMA_SDC_BLMT (1<<7)
280#define SDMA_SDC_POVR (1<<8)
281#define SDMA_SDC_RIFB (1<<9)
282
283#define SDMA_SDCM_ERD (1<<7)
284#define SDMA_SDCM_AR (1<<15)
285#define SDMA_SDCM_STD (1<<16)
286#define SDMA_SDCM_TXD (1<<23)
287#define SDMA_SDCM_AT (1<<31)
288
289#define SDMA_0_CAUSE_RXBUF (1<<0)
290#define SDMA_0_CAUSE_RXERR (1<<1)
291#define SDMA_0_CAUSE_TXBUF (1<<2)
292#define SDMA_0_CAUSE_TXEND (1<<3)
293#define SDMA_1_CAUSE_RXBUF (1<<8)
294#define SDMA_1_CAUSE_RXERR (1<<9)
295#define SDMA_1_CAUSE_TXBUF (1<<10)
296#define SDMA_1_CAUSE_TXEND (1<<11)
297
298#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
299 SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
300#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
301 SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
302
303/* SDMA Interrupt registers */
304#define SDMA_INTR_CAUSE 0x0000
305#define SDMA_INTR_MASK 0x0080
306
307/* Baud Rate Generator Interface Registers */
308#define BRG_BCR 0x0000
309#define BRG_BTR 0x0004
58 310
59/* 311/*
60 * Define how this driver is known to the outside (we've been assigned a 312 * Define how this driver is known to the outside (we've been assigned a
@@ -1165,7 +1417,7 @@ mpsc_startup(struct uart_port *port)
1165 flag = SA_SHIRQ; 1417 flag = SA_SHIRQ;
1166 1418
1167 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag, 1419 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
1168 "mpsc/sdma", pi)) 1420 "mpsc-sdma", pi))
1169 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n", 1421 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
1170 pi->port.irq); 1422 pi->port.irq);
1171 1423
diff --git a/drivers/serial/mpsc.h b/drivers/serial/mpsc.h
deleted file mode 100644
index 678dbcf06c8f..000000000000
--- a/drivers/serial/mpsc.h
+++ /dev/null
@@ -1,289 +0,0 @@
1/*
2 * drivers/serial/mpsc.h
3 *
4 * Author: Mark A. Greer <mgreer@mvista.com>
5 *
6 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#ifndef __MPSC_H__
13#define __MPSC_H__
14
15#include <linux/config.h>
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/tty.h>
19#include <linux/tty_flip.h>
20#include <linux/ioport.h>
21#include <linux/init.h>
22#include <linux/console.h>
23#include <linux/sysrq.h>
24#include <linux/serial.h>
25#include <linux/serial_core.h>
26#include <linux/delay.h>
27#include <linux/device.h>
28#include <linux/dma-mapping.h>
29#include <linux/mv643xx.h>
30
31#include <asm/io.h>
32#include <asm/irq.h>
33
34#if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
35#define SUPPORT_SYSRQ
36#endif
37
38#define MPSC_NUM_CTLRS 2
39
40/*
41 * Descriptors and buffers must be cache line aligned.
42 * Buffers lengths must be multiple of cache line size.
43 * Number of Tx & Rx descriptors must be powers of 2.
44 */
45#define MPSC_RXR_ENTRIES 32
46#define MPSC_RXRE_SIZE dma_get_cache_alignment()
47#define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
48#define MPSC_RXBE_SIZE dma_get_cache_alignment()
49#define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
50
51#define MPSC_TXR_ENTRIES 32
52#define MPSC_TXRE_SIZE dma_get_cache_alignment()
53#define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
54#define MPSC_TXBE_SIZE dma_get_cache_alignment()
55#define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
56
57#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \
58 MPSC_TXR_SIZE + MPSC_TXB_SIZE + \
59 dma_get_cache_alignment() /* for alignment */)
60
61/* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
62struct mpsc_rx_desc {
63 u16 bufsize;
64 u16 bytecnt;
65 u32 cmdstat;
66 u32 link;
67 u32 buf_ptr;
68} __attribute((packed));
69
70struct mpsc_tx_desc {
71 u16 bytecnt;
72 u16 shadow;
73 u32 cmdstat;
74 u32 link;
75 u32 buf_ptr;
76} __attribute((packed));
77
78/*
79 * Some regs that have the erratum that you can't read them are are shared
80 * between the two MPSC controllers. This struct contains those shared regs.
81 */
82struct mpsc_shared_regs {
83 phys_addr_t mpsc_routing_base_p;
84 phys_addr_t sdma_intr_base_p;
85
86 void __iomem *mpsc_routing_base;
87 void __iomem *sdma_intr_base;
88
89 u32 MPSC_MRR_m;
90 u32 MPSC_RCRR_m;
91 u32 MPSC_TCRR_m;
92 u32 SDMA_INTR_CAUSE_m;
93 u32 SDMA_INTR_MASK_m;
94};
95
96/* The main driver data structure */
97struct mpsc_port_info {
98 struct uart_port port; /* Overlay uart_port structure */
99
100 /* Internal driver state for this ctlr */
101 u8 ready;
102 u8 rcv_data;
103 tcflag_t c_iflag; /* save termios->c_iflag */
104 tcflag_t c_cflag; /* save termios->c_cflag */
105
106 /* Info passed in from platform */
107 u8 mirror_regs; /* Need to mirror regs? */
108 u8 cache_mgmt; /* Need manual cache mgmt? */
109 u8 brg_can_tune; /* BRG has baud tuning? */
110 u32 brg_clk_src;
111 u16 mpsc_max_idle;
112 int default_baud;
113 int default_bits;
114 int default_parity;
115 int default_flow;
116
117 /* Physical addresses of various blocks of registers (from platform) */
118 phys_addr_t mpsc_base_p;
119 phys_addr_t sdma_base_p;
120 phys_addr_t brg_base_p;
121
122 /* Virtual addresses of various blocks of registers (from platform) */
123 void __iomem *mpsc_base;
124 void __iomem *sdma_base;
125 void __iomem *brg_base;
126
127 /* Descriptor ring and buffer allocations */
128 void *dma_region;
129 dma_addr_t dma_region_p;
130
131 dma_addr_t rxr; /* Rx descriptor ring */
132 dma_addr_t rxr_p; /* Phys addr of rxr */
133 u8 *rxb; /* Rx Ring I/O buf */
134 u8 *rxb_p; /* Phys addr of rxb */
135 u32 rxr_posn; /* First desc w/ Rx data */
136
137 dma_addr_t txr; /* Tx descriptor ring */
138 dma_addr_t txr_p; /* Phys addr of txr */
139 u8 *txb; /* Tx Ring I/O buf */
140 u8 *txb_p; /* Phys addr of txb */
141 int txr_head; /* Where new data goes */
142 int txr_tail; /* Where sent data comes off */
143
144 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
145 u32 MPSC_MPCR_m;
146 u32 MPSC_CHR_1_m;
147 u32 MPSC_CHR_2_m;
148 u32 MPSC_CHR_10_m;
149 u32 BRG_BCR_m;
150 struct mpsc_shared_regs *shared_regs;
151};
152
153/* Hooks to platform-specific code */
154int mpsc_platform_register_driver(void);
155void mpsc_platform_unregister_driver(void);
156
157/* Hooks back in to mpsc common to be called by platform-specific code */
158struct mpsc_port_info *mpsc_device_probe(int index);
159struct mpsc_port_info *mpsc_device_remove(int index);
160
161/*
162 *****************************************************************************
163 *
164 * Multi-Protocol Serial Controller Interface Registers
165 *
166 *****************************************************************************
167 */
168
169/* Main Configuratino Register Offsets */
170#define MPSC_MMCRL 0x0000
171#define MPSC_MMCRH 0x0004
172#define MPSC_MPCR 0x0008
173#define MPSC_CHR_1 0x000c
174#define MPSC_CHR_2 0x0010
175#define MPSC_CHR_3 0x0014
176#define MPSC_CHR_4 0x0018
177#define MPSC_CHR_5 0x001c
178#define MPSC_CHR_6 0x0020
179#define MPSC_CHR_7 0x0024
180#define MPSC_CHR_8 0x0028
181#define MPSC_CHR_9 0x002c
182#define MPSC_CHR_10 0x0030
183#define MPSC_CHR_11 0x0034
184
185#define MPSC_MPCR_FRZ (1 << 9)
186#define MPSC_MPCR_CL_5 0
187#define MPSC_MPCR_CL_6 1
188#define MPSC_MPCR_CL_7 2
189#define MPSC_MPCR_CL_8 3
190#define MPSC_MPCR_SBL_1 0
191#define MPSC_MPCR_SBL_2 1
192
193#define MPSC_CHR_2_TEV (1<<1)
194#define MPSC_CHR_2_TA (1<<7)
195#define MPSC_CHR_2_TTCS (1<<9)
196#define MPSC_CHR_2_REV (1<<17)
197#define MPSC_CHR_2_RA (1<<23)
198#define MPSC_CHR_2_CRD (1<<25)
199#define MPSC_CHR_2_EH (1<<31)
200#define MPSC_CHR_2_PAR_ODD 0
201#define MPSC_CHR_2_PAR_SPACE 1
202#define MPSC_CHR_2_PAR_EVEN 2
203#define MPSC_CHR_2_PAR_MARK 3
204
205/* MPSC Signal Routing */
206#define MPSC_MRR 0x0000
207#define MPSC_RCRR 0x0004
208#define MPSC_TCRR 0x0008
209
210/*
211 *****************************************************************************
212 *
213 * Serial DMA Controller Interface Registers
214 *
215 *****************************************************************************
216 */
217
218#define SDMA_SDC 0x0000
219#define SDMA_SDCM 0x0008
220#define SDMA_RX_DESC 0x0800
221#define SDMA_RX_BUF_PTR 0x0808
222#define SDMA_SCRDP 0x0810
223#define SDMA_TX_DESC 0x0c00
224#define SDMA_SCTDP 0x0c10
225#define SDMA_SFTDP 0x0c14
226
227#define SDMA_DESC_CMDSTAT_PE (1<<0)
228#define SDMA_DESC_CMDSTAT_CDL (1<<1)
229#define SDMA_DESC_CMDSTAT_FR (1<<3)
230#define SDMA_DESC_CMDSTAT_OR (1<<6)
231#define SDMA_DESC_CMDSTAT_BR (1<<9)
232#define SDMA_DESC_CMDSTAT_MI (1<<10)
233#define SDMA_DESC_CMDSTAT_A (1<<11)
234#define SDMA_DESC_CMDSTAT_AM (1<<12)
235#define SDMA_DESC_CMDSTAT_CT (1<<13)
236#define SDMA_DESC_CMDSTAT_C (1<<14)
237#define SDMA_DESC_CMDSTAT_ES (1<<15)
238#define SDMA_DESC_CMDSTAT_L (1<<16)
239#define SDMA_DESC_CMDSTAT_F (1<<17)
240#define SDMA_DESC_CMDSTAT_P (1<<18)
241#define SDMA_DESC_CMDSTAT_EI (1<<23)
242#define SDMA_DESC_CMDSTAT_O (1<<31)
243
244#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
245 SDMA_DESC_CMDSTAT_EI)
246
247#define SDMA_SDC_RFT (1<<0)
248#define SDMA_SDC_SFM (1<<1)
249#define SDMA_SDC_BLMR (1<<6)
250#define SDMA_SDC_BLMT (1<<7)
251#define SDMA_SDC_POVR (1<<8)
252#define SDMA_SDC_RIFB (1<<9)
253
254#define SDMA_SDCM_ERD (1<<7)
255#define SDMA_SDCM_AR (1<<15)
256#define SDMA_SDCM_STD (1<<16)
257#define SDMA_SDCM_TXD (1<<23)
258#define SDMA_SDCM_AT (1<<31)
259
260#define SDMA_0_CAUSE_RXBUF (1<<0)
261#define SDMA_0_CAUSE_RXERR (1<<1)
262#define SDMA_0_CAUSE_TXBUF (1<<2)
263#define SDMA_0_CAUSE_TXEND (1<<3)
264#define SDMA_1_CAUSE_RXBUF (1<<8)
265#define SDMA_1_CAUSE_RXERR (1<<9)
266#define SDMA_1_CAUSE_TXBUF (1<<10)
267#define SDMA_1_CAUSE_TXEND (1<<11)
268
269#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
270 SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
271#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
272 SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
273
274/* SDMA Interrupt registers */
275#define SDMA_INTR_CAUSE 0x0000
276#define SDMA_INTR_MASK 0x0080
277
278/*
279 *****************************************************************************
280 *
281 * Baud Rate Generator Interface Registers
282 *
283 *****************************************************************************
284 */
285
286#define BRG_BCR 0x0000
287#define BRG_BTR 0x0004
288
289#endif /* __MPSC_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 04:12:40 -0500