5 files changed, 389 insertions, 194 deletions

diff --git a/drivers/serial/amba-pl010.c b/drivers/serial/amba-pl010.c
index f69bd097166e..1a9a24b82636 100644
--- a/drivers/serial/amba-pl010.c
+++ b/drivers/serial/amba-pl010.c
@@ -48,6 +48,7 @@
 #include <linux/serial.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
+#include <linux/clk.h>
 
 #include <asm/io.h>
 
@@ -70,6 +71,7 @@
  */
 struct uart_amba_port {
         struct uart_port        port;
+        struct clk              *clk;
         struct amba_device      *dev;
         struct amba_pl010_data  *data;
         unsigned int            old_status;
@@ -77,73 +79,77 @@ struct uart_amba_port {
 
 static void pl010_stop_tx(struct uart_port *port)
 {
+        struct uart_amba_port *uap = (struct uart_amba_port *)port;
         unsigned int cr;
 
-        cr = readb(port->membase + UART010_CR);
+        cr = readb(uap->port.membase + UART010_CR);
         cr &= ~UART010_CR_TIE;
-        writel(cr, port->membase + UART010_CR);
+        writel(cr, uap->port.membase + UART010_CR);
 }
 
 static void pl010_start_tx(struct uart_port *port)
 {
+        struct uart_amba_port *uap = (struct uart_amba_port *)port;
         unsigned int cr;
 
-        cr = readb(port->membase + UART010_CR);
+        cr = readb(uap->port.membase + UART010_CR);
         cr |= UART010_CR_TIE;
-        writel(cr, port->membase + UART010_CR);
+        writel(cr, uap->port.membase + UART010_CR);
 }
 
 static void pl010_stop_rx(struct uart_port *port)
 {
+        struct uart_amba_port *uap = (struct uart_amba_port *)port;
         unsigned int cr;
 
-        cr = readb(port->membase + UART010_CR);
+        cr = readb(uap->port.membase + UART010_CR);
         cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
-        writel(cr, port->membase + UART010_CR);
+        writel(cr, uap->port.membase + UART010_CR);
 }
 
 static void pl010_enable_ms(struct uart_port *port)
 {
+        struct uart_amba_port *uap = (struct uart_amba_port *)port;
         unsigned int cr;
 
-        cr = readb(port->membase + UART010_CR);
+        cr = readb(uap->port.membase + UART010_CR);
         cr |= UART010_CR_MSIE;
-        writel(cr, port->membase + UART010_CR);
+        writel(cr, uap->port.membase + UART010_CR);
 }
 
-static void pl010_rx_chars(struct uart_port *port)
+static void pl010_rx_chars(struct uart_amba_port *uap)
 {
-        struct tty_struct *tty = port->info->tty;
+        struct tty_struct *tty = uap->port.info->tty;
         unsigned int status, ch, flag, rsr, max_count = 256;
 
-        status = readb(port->membase + UART01x_FR);
+        status = readb(uap->port.membase + UART01x_FR);
         while (UART_RX_DATA(status) && max_count--) {
-                ch = readb(port->membase + UART01x_DR);
+                ch = readb(uap->port.membase + UART01x_DR);
                 flag = TTY_NORMAL;
 
-                port->icount.rx++;
+                uap->port.icount.rx++;
 
                 /*
                  * Note that the error handling code is
                  * out of the main execution path
                  */
-                rsr = readb(port->membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
+                rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
                 if (unlikely(rsr & UART01x_RSR_ANY)) {
-                        writel(0, port->membase + UART01x_ECR);
+                        writel(0, uap->port.membase + UART01x_ECR);
 
                         if (rsr & UART01x_RSR_BE) {
                                 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
-                                port->icount.brk++;
-                                if (uart_handle_break(port))
+                                uap->port.icount.brk++;
+                                if (uart_handle_break(&uap->port))
                                         goto ignore_char;
                         } else if (rsr & UART01x_RSR_PE)
-                                port->icount.parity++;
+                                uap->port.icount.parity++;
                         else if (rsr & UART01x_RSR_FE)
-                                port->icount.frame++;
+                                uap->port.icount.frame++;
                         if (rsr & UART01x_RSR_OE)
-                                port->icount.overrun++;
+                                uap->port.icount.overrun++;
 
-                        rsr &= port->read_status_mask;
+                        rsr &= uap->port.read_status_mask;
 
                         if (rsr & UART01x_RSR_BE)
                                 flag = TTY_BREAK;
@@ -153,53 +159,52 @@ static void pl010_rx_chars(struct uart_port *port)
                                 flag = TTY_FRAME;
                 }
 
-                if (uart_handle_sysrq_char(port, ch))
+                if (uart_handle_sysrq_char(&uap->port, ch))
                         goto ignore_char;
 
-                uart_insert_char(port, rsr, UART01x_RSR_OE, ch, flag);
+                uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
 
         ignore_char:
-                status = readb(port->membase + UART01x_FR);
+                status = readb(uap->port.membase + UART01x_FR);
         }
         tty_flip_buffer_push(tty);
         return;
 }
 
-static void pl010_tx_chars(struct uart_port *port)
+static void pl010_tx_chars(struct uart_amba_port *uap)
 {
-        struct circ_buf *xmit = &port->info->xmit;
+        struct circ_buf *xmit = &uap->port.info->xmit;
         int count;
 
-        if (port->x_char) {
-                writel(port->x_char, port->membase + UART01x_DR);
-                port->icount.tx++;
-                port->x_char = 0;
+        if (uap->port.x_char) {
+                writel(uap->port.x_char, uap->port.membase + UART01x_DR);
+                uap->port.icount.tx++;
+                uap->port.x_char = 0;
                 return;
         }
-        if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
-                pl010_stop_tx(port);
+        if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
+                pl010_stop_tx(&uap->port);
                 return;
         }
 
-        count = port->fifosize >> 1;
+        count = uap->port.fifosize >> 1;
         do {
-                writel(xmit->buf[xmit->tail], port->membase + UART01x_DR);
+                writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
-                port->icount.tx++;
+                uap->port.icount.tx++;
                 if (uart_circ_empty(xmit))
                         break;
         } while (--count > 0);
 
         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
-                uart_write_wakeup(port);
+                uart_write_wakeup(&uap->port);
 
         if (uart_circ_empty(xmit))
-                pl010_stop_tx(port);
+                pl010_stop_tx(&uap->port);
 }
 
-static void pl010_modem_status(struct uart_port *port)
+static void pl010_modem_status(struct uart_amba_port *uap)
 {
-        struct uart_amba_port *uap = (struct uart_amba_port *)port;
         unsigned int status, delta;
 
         writel(0, uap->port.membase + UART010_ICR);
@@ -226,47 +231,50 @@ static void pl010_modem_status(struct uart_port *port)
 
 static irqreturn_t pl010_int(int irq, void *dev_id)
 {
-        struct uart_port *port = dev_id;
+        struct uart_amba_port *uap = dev_id;
         unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
         int handled = 0;
 
-        spin_lock(&port->lock);
+        spin_lock(&uap->port.lock);
 
-        status = readb(port->membase + UART010_IIR);
+        status = readb(uap->port.membase + UART010_IIR);
         if (status) {
                 do {
                         if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
-                                pl010_rx_chars(port);
+                                pl010_rx_chars(uap);
                         if (status & UART010_IIR_MIS)
-                                pl010_modem_status(port);
+                                pl010_modem_status(uap);
                         if (status & UART010_IIR_TIS)
-                                pl010_tx_chars(port);
+                                pl010_tx_chars(uap);
 
                         if (pass_counter-- == 0)
                                 break;
 
-                        status = readb(port->membase + UART010_IIR);
+                        status = readb(uap->port.membase + UART010_IIR);
                 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
                                    UART010_IIR_TIS));
                 handled = 1;
         }
 
-        spin_unlock(&port->lock);
+        spin_unlock(&uap->port.lock);
 
         return IRQ_RETVAL(handled);
 }
 
 static unsigned int pl010_tx_empty(struct uart_port *port)
 {
-        return readb(port->membase + UART01x_FR) & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
+        struct uart_amba_port *uap = (struct uart_amba_port *)port;
+        unsigned int status = readb(uap->port.membase + UART01x_FR);
+        return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
 }
 
 static unsigned int pl010_get_mctrl(struct uart_port *port)
 {
+        struct uart_amba_port *uap = (struct uart_amba_port *)port;
         unsigned int result = 0;
         unsigned int status;
 
-        status = readb(port->membase + UART01x_FR);
+        status = readb(uap->port.membase + UART01x_FR);
         if (status & UART01x_FR_DCD)
                 result |= TIOCM_CAR;
         if (status & UART01x_FR_DSR)
@@ -287,17 +295,18 @@ static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
 
 static void pl010_break_ctl(struct uart_port *port, int break_state)
 {
+        struct uart_amba_port *uap = (struct uart_amba_port *)port;
         unsigned long flags;
         unsigned int lcr_h;
 
-        spin_lock_irqsave(&port->lock, flags);
-        lcr_h = readb(port->membase + UART010_LCRH);
+        spin_lock_irqsave(&uap->port.lock, flags);
+        lcr_h = readb(uap->port.membase + UART010_LCRH);
         if (break_state == -1)
                 lcr_h |= UART01x_LCRH_BRK;
         else
                 lcr_h &= ~UART01x_LCRH_BRK;
-        writel(lcr_h, port->membase + UART010_LCRH);
-        spin_unlock_irqrestore(&port->lock, flags);
+        writel(lcr_h, uap->port.membase + UART010_LCRH);
+        spin_unlock_irqrestore(&uap->port.lock, flags);
 }
 
 static int pl010_startup(struct uart_port *port)
@@ -306,48 +315,70 @@ static int pl010_startup(struct uart_port *port)
         int retval;
 
         /*
+         * Try to enable the clock producer.
+         */
+        retval = clk_enable(uap->clk);
+        if (retval)
+                goto out;
+
+        uap->port.uartclk = clk_get_rate(uap->clk);
+
+        /*
          * Allocate the IRQ
          */
-        retval = request_irq(port->irq, pl010_int, 0, "uart-pl010", port);
+        retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap);
         if (retval)
-                return retval;
+                goto clk_dis;
 
         /*
          * initialise the old status of the modem signals
          */
-        uap->old_status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
+        uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
 
         /*
          * Finally, enable interrupts
          */
         writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
-               port->membase + UART010_CR);
+               uap->port.membase + UART010_CR);
 
         return 0;
+
+ clk_dis:
+        clk_disable(uap->clk);
+ out:
+        return retval;
 }
 
 static void pl010_shutdown(struct uart_port *port)
 {
+        struct uart_amba_port *uap = (struct uart_amba_port *)port;
+
         /*
          * Free the interrupt
          */
-        free_irq(port->irq, port);
+        free_irq(uap->port.irq, uap);
 
         /*
          * disable all interrupts, disable the port
          */
-        writel(0, port->membase + UART010_CR);
+        writel(0, uap->port.membase + UART010_CR);
 
         /* disable break condition and fifos */
-        writel(readb(port->membase + UART010_LCRH) &
+        writel(readb(uap->port.membase + UART010_LCRH) &
                 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
-               port->membase + UART010_LCRH);
+               uap->port.membase + UART010_LCRH);
+
+        /*
+         * Shut down the clock producer
+         */
+        clk_disable(uap->clk);
 }
 
 static void
 pl010_set_termios(struct uart_port *port, struct ktermios *termios,
                      struct ktermios *old)
 {
+        struct uart_amba_port *uap = (struct uart_amba_port *)port;
         unsigned int lcr_h, old_cr;
         unsigned long flags;
         unsigned int baud, quot;
@@ -355,7 +386,7 @@ pl010_set_termios(struct uart_port *port, struct ktermios *termios,
         /*
          * Ask the core to calculate the divisor for us.
          */
-        baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 
+        baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16); 
         quot = uart_get_divisor(port, baud);
 
         switch (termios->c_cflag & CSIZE) {
@@ -379,66 +410,66 @@ pl010_set_termios(struct uart_port *port, struct ktermios *termios,
                 if (!(termios->c_cflag & PARODD))
                         lcr_h |= UART01x_LCRH_EPS;
         }
-        if (port->fifosize > 1)
+        if (uap->port.fifosize > 1)
                 lcr_h |= UART01x_LCRH_FEN;
 
-        spin_lock_irqsave(&port->lock, flags);
+        spin_lock_irqsave(&uap->port.lock, flags);
 
         /*
          * Update the per-port timeout.
          */
         uart_update_timeout(port, termios->c_cflag, baud);
 
-        port->read_status_mask = UART01x_RSR_OE;
+        uap->port.read_status_mask = UART01x_RSR_OE;
         if (termios->c_iflag & INPCK)
-                port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
+                uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
         if (termios->c_iflag & (BRKINT | PARMRK))
-                port->read_status_mask |= UART01x_RSR_BE;
+                uap->port.read_status_mask |= UART01x_RSR_BE;
 
         /*
          * Characters to ignore
          */
-        port->ignore_status_mask = 0;
+        uap->port.ignore_status_mask = 0;
         if (termios->c_iflag & IGNPAR)
-                port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
+                uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
         if (termios->c_iflag & IGNBRK) {
-                port->ignore_status_mask |= UART01x_RSR_BE;
+                uap->port.ignore_status_mask |= UART01x_RSR_BE;
                 /*
                  * If we're ignoring parity and break indicators,
                  * ignore overruns too (for real raw support).
                  */
                 if (termios->c_iflag & IGNPAR)
-                        port->ignore_status_mask |= UART01x_RSR_OE;
+                        uap->port.ignore_status_mask |= UART01x_RSR_OE;
         }
 
         /*
          * Ignore all characters if CREAD is not set.
          */
         if ((termios->c_cflag & CREAD) == 0)
-                port->ignore_status_mask |= UART_DUMMY_RSR_RX;
+                uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
 
         /* first, disable everything */
-        old_cr = readb(port->membase + UART010_CR) & ~UART010_CR_MSIE;
+        old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
 
         if (UART_ENABLE_MS(port, termios->c_cflag))
                 old_cr |= UART010_CR_MSIE;
 
-        writel(0, port->membase + UART010_CR);
+        writel(0, uap->port.membase + UART010_CR);
 
         /* Set baud rate */
         quot -= 1;
-        writel((quot & 0xf00) >> 8, port->membase + UART010_LCRM);
-        writel(quot & 0xff, port->membase + UART010_LCRL);
+        writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
+        writel(quot & 0xff, uap->port.membase + UART010_LCRL);
 
         /*
          * ----------v----------v----------v----------v-----
          * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
          * ----------^----------^----------^----------^-----
          */
-        writel(lcr_h, port->membase + UART010_LCRH);
-        writel(old_cr, port->membase + UART010_CR);
+        writel(lcr_h, uap->port.membase + UART010_LCRH);
+        writel(old_cr, uap->port.membase + UART010_CR);
 
-        spin_unlock_irqrestore(&port->lock, flags);
+        spin_unlock_irqrestore(&uap->port.lock, flags);
 }
 
 static const char *pl010_type(struct uart_port *port)
@@ -514,47 +545,52 @@ static struct uart_amba_port *amba_ports[UART_NR];
 
 static void pl010_console_putchar(struct uart_port *port, int ch)
 {
+        struct uart_amba_port *uap = (struct uart_amba_port *)port;
         unsigned int status;
 
         do {
-                status = readb(port->membase + UART01x_FR);
+                status = readb(uap->port.membase + UART01x_FR);
                 barrier();
         } while (!UART_TX_READY(status));
-        writel(ch, port->membase + UART01x_DR);
+        writel(ch, uap->port.membase + UART01x_DR);
 }
 
 static void
 pl010_console_write(struct console *co, const char *s, unsigned int count)
 {
-        struct uart_port *port = &amba_ports[co->index]->port;
+        struct uart_amba_port *uap = amba_ports[co->index];
         unsigned int status, old_cr;
 
+        clk_enable(uap->clk);
+
         /*
          *      First save the CR then disable the interrupts
          */
-        old_cr = readb(port->membase + UART010_CR);
-        writel(UART01x_CR_UARTEN, port->membase + UART010_CR);
+        old_cr = readb(uap->port.membase + UART010_CR);
+        writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
 
-        uart_console_write(port, s, count, pl010_console_putchar);
+        uart_console_write(&uap->port, s, count, pl010_console_putchar);
 
         /*
          *      Finally, wait for transmitter to become empty
          *      and restore the TCR
          */
         do {
-                status = readb(port->membase + UART01x_FR);
+                status = readb(uap->port.membase + UART01x_FR);
                 barrier();
         } while (status & UART01x_FR_BUSY);
-        writel(old_cr, port->membase + UART010_CR);
+        writel(old_cr, uap->port.membase + UART010_CR);
+
+        clk_disable(uap->clk);
 }
 
 static void __init
-pl010_console_get_options(struct uart_port *port, int *baud,
+pl010_console_get_options(struct uart_amba_port *uap, int *baud,
                              int *parity, int *bits)
 {
-        if (readb(port->membase + UART010_CR) & UART01x_CR_UARTEN) {
+        if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
                 unsigned int lcr_h, quot;
-                lcr_h = readb(port->membase + UART010_LCRH);
+                lcr_h = readb(uap->port.membase + UART010_LCRH);
 
                 *parity = 'n';
                 if (lcr_h & UART01x_LCRH_PEN) {
@@ -569,14 +605,15 @@ pl010_console_get_options(struct uart_port *port, int *baud,
                 else
                         *bits = 8;
 
-                quot = readb(port->membase + UART010_LCRL) | readb(port->membase + UART010_LCRM) << 8;
-                *baud = port->uartclk / (16 * (quot + 1));
+                quot = readb(uap->port.membase + UART010_LCRL) |
+                       readb(uap->port.membase + UART010_LCRM) << 8;
+                *baud = uap->port.uartclk / (16 * (quot + 1));
         }
 }
 
 static int __init pl010_console_setup(struct console *co, char *options)
 {
-        struct uart_port *port;
+        struct uart_amba_port *uap;
         int baud = 38400;
         int bits = 8;
         int parity = 'n';
@@ -589,16 +626,18 @@ static int __init pl010_console_setup(struct console *co, char *options)
          */
         if (co->index >= UART_NR)
                 co->index = 0;
-        if (!amba_ports[co->index])
+        uap = amba_ports[co->index];
+        if (!uap)
                 return -ENODEV;
-        port = &amba_ports[co->index]->port;
+
+        uap->port.uartclk = clk_get_rate(uap->clk);
 
         if (options)
                 uart_parse_options(options, &baud, &parity, &bits, &flow);
         else
-                pl010_console_get_options(port, &baud, &parity, &bits);
+                pl010_console_get_options(uap, &baud, &parity, &bits);
 
-        return uart_set_options(port, co, baud, parity, bits, flow);
+        return uart_set_options(&uap->port, co, baud, parity, bits, flow);
 }
 
 static struct uart_driver amba_reg;
@@ -629,7 +668,7 @@ static struct uart_driver amba_reg = {
 
 static int pl010_probe(struct amba_device *dev, void *id)
 {
-        struct uart_amba_port *port;
+        struct uart_amba_port *uap;
         void __iomem *base;
         int i, ret;
 
@@ -642,8 +681,8 @@ static int pl010_probe(struct amba_device *dev, void *id)
                 goto out;
         }
 
-        port = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
-        if (!port) {
+        uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
+        if (!uap) {
                 ret = -ENOMEM;
                 goto out;
         }
@@ -654,51 +693,57 @@ static int pl010_probe(struct amba_device *dev, void *id)
                 goto free;
         }
 
-        port->port.dev = &dev->dev;
-        port->port.mapbase = dev->res.start;
-        port->port.membase = base;
-        port->port.iotype = UPIO_MEM;
-        port->port.irq = dev->irq[0];
-        port->port.uartclk = 14745600;
-        port->port.fifosize = 16;
-        port->port.ops = &amba_pl010_pops;
-        port->port.flags = UPF_BOOT_AUTOCONF;
-        port->port.line = i;
-        port->dev = dev;
-        port->data = dev->dev.platform_data;
-
-        amba_ports[i] = port;
-
-        amba_set_drvdata(dev, port);
-        ret = uart_add_one_port(&amba_reg, &port->port);
+        uap->clk = clk_get(&dev->dev, "UARTCLK");
+        if (IS_ERR(uap->clk)) {
+                ret = PTR_ERR(uap->clk);
+                goto unmap;
+        }
+
+        uap->port.dev = &dev->dev;
+        uap->port.mapbase = dev->res.start;
+        uap->port.membase = base;
+        uap->port.iotype = UPIO_MEM;
+        uap->port.irq = dev->irq[0];
+        uap->port.fifosize = 16;
+        uap->port.ops = &amba_pl010_pops;
+        uap->port.flags = UPF_BOOT_AUTOCONF;
+        uap->port.line = i;
+        uap->dev = dev;
+        uap->data = dev->dev.platform_data;
+
+        amba_ports[i] = uap;
+
+        amba_set_drvdata(dev, uap);
+        ret = uart_add_one_port(&amba_reg, &uap->port);
         if (ret) {
                 amba_set_drvdata(dev, NULL);
                 amba_ports[i] = NULL;
+                clk_put(uap->clk);
+ unmap:
                 iounmap(base);
  free:
-                kfree(port);
+                kfree(uap);
         }
-
  out:
         return ret;
 }
 
 static int pl010_remove(struct amba_device *dev)
 {
-        struct uart_amba_port *port = amba_get_drvdata(dev);
+        struct uart_amba_port *uap = amba_get_drvdata(dev);
         int i;
 
         amba_set_drvdata(dev, NULL);
 
-        uart_remove_one_port(&amba_reg, &port->port);
+        uart_remove_one_port(&amba_reg, &uap->port);
 
         for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
-                if (amba_ports[i] == port)
+                if (amba_ports[i] == uap)
                         amba_ports[i] = NULL;
 
-        iounmap(port->port.membase);
-        kfree(port);
-
+        iounmap(uap->port.membase);
+        clk_put(uap->clk);
+        kfree(uap);
         return 0;
 }
 
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c
index 935f48fa501d..3320bcd92c0a 100644
--- a/drivers/serial/atmel_serial.c
+++ b/drivers/serial/atmel_serial.c
@@ -484,11 +484,16 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios * termios,
         unsigned long flags;
         unsigned int mode, imr, quot, baud;
 
+        /* Get current mode register */
+        mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR);
+
         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
         quot = uart_get_divisor(port, baud);
 
-        /* Get current mode register */
-        mode = UART_GET_MR(port) & ~(ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR);
+        if (quot > 65535) {             /* BRGR is 16-bit, so switch to slower clock */
+                quot /= 8;
+                mode |= ATMEL_US_USCLKS_MCK_DIV8;
+        }
 
         /* byte size */
         switch (termios->c_cflag & CSIZE) {
diff --git a/drivers/serial/atmel_serial.h b/drivers/serial/atmel_serial.h
index 11b44360e108..e0141776517c 100644
--- a/drivers/serial/atmel_serial.h
+++ b/drivers/serial/atmel_serial.h
@@ -46,6 +46,9 @@
 #define                 ATMEL_US_USMODE_ISO7816_T1      6
 #define                 ATMEL_US_USMODE_IRDA            8
 #define         ATMEL_US_USCLKS         (3   <<  4)             /* Clock Selection */
+#define                 ATMEL_US_USCLKS_MCK             (0 <<  4)
+#define                 ATMEL_US_USCLKS_MCK_DIV8        (1 <<  4)
+#define                 ATMEL_US_USCLKS_SCK             (3 <<  4)
 #define         ATMEL_US_CHRL           (3   <<  6)             /* Character Length */
 #define                 ATMEL_US_CHRL_5                 (0 <<  6)
 #define                 ATMEL_US_CHRL_6                 (1 <<  6)
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
index 04cc88cc528c..e42faa4e4282 100644
--- a/drivers/serial/imx.c
+++ b/drivers/serial/imx.c
@@ -46,6 +46,122 @@
 #include <asm/hardware.h>
 #include <asm/arch/imx-uart.h>
 
+/* Register definitions */
+#define URXD0 0x0  /* Receiver Register */
+#define URTX0 0x40 /* Transmitter Register */
+#define UCR1  0x80 /* Control Register 1 */
+#define UCR2  0x84 /* Control Register 2 */
+#define UCR3  0x88 /* Control Register 3 */
+#define UCR4  0x8c /* Control Register 4 */
+#define UFCR  0x90 /* FIFO Control Register */
+#define USR1  0x94 /* Status Register 1 */
+#define USR2  0x98 /* Status Register 2 */
+#define UESC  0x9c /* Escape Character Register */
+#define UTIM  0xa0 /* Escape Timer Register */
+#define UBIR  0xa4 /* BRM Incremental Register */
+#define UBMR  0xa8 /* BRM Modulator Register */
+#define UBRC  0xac /* Baud Rate Count Register */
+#define BIPR1 0xb0 /* Incremental Preset Register 1 */
+#define BIPR2 0xb4 /* Incremental Preset Register 2 */
+#define BIPR3 0xb8 /* Incremental Preset Register 3 */
+#define BIPR4 0xbc /* Incremental Preset Register 4 */
+#define BMPR1 0xc0 /* BRM Modulator Register 1 */
+#define BMPR2 0xc4 /* BRM Modulator Register 2 */
+#define BMPR3 0xc8 /* BRM Modulator Register 3 */
+#define BMPR4 0xcc /* BRM Modulator Register 4 */
+#define UTS   0xd0 /* UART Test Register */
+
+/* UART Control Register Bit Fields.*/
+#define  URXD_CHARRDY    (1<<15)
+#define  URXD_ERR        (1<<14)
+#define  URXD_OVRRUN     (1<<13)
+#define  URXD_FRMERR     (1<<12)
+#define  URXD_BRK        (1<<11)
+#define  URXD_PRERR      (1<<10)
+#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
+#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
+#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
+#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
+#define  UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
+#define  UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
+#define  UCR1_IREN       (1<<7)  /* Infrared interface enable */
+#define  UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
+#define  UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
+#define  UCR1_SNDBRK     (1<<4)  /* Send break */
+#define  UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
+#define  UCR1_UARTCLKEN  (1<<2)  /* UART clock enabled */
+#define  UCR1_DOZE       (1<<1)  /* Doze */
+#define  UCR1_UARTEN     (1<<0)  /* UART enabled */
+#define  UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
+#define  UCR2_IRTS       (1<<14) /* Ignore RTS pin */
+#define  UCR2_CTSC       (1<<13) /* CTS pin control */
+#define  UCR2_CTS        (1<<12) /* Clear to send */
+#define  UCR2_ESCEN      (1<<11) /* Escape enable */
+#define  UCR2_PREN       (1<<8)  /* Parity enable */
+#define  UCR2_PROE       (1<<7)  /* Parity odd/even */
+#define  UCR2_STPB       (1<<6)  /* Stop */
+#define  UCR2_WS         (1<<5)  /* Word size */
+#define  UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
+#define  UCR2_TXEN       (1<<2)  /* Transmitter enabled */
+#define  UCR2_RXEN       (1<<1)  /* Receiver enabled */
+#define  UCR2_SRST       (1<<0)  /* SW reset */
+#define  UCR3_DTREN      (1<<13) /* DTR interrupt enable */
+#define  UCR3_PARERREN   (1<<12) /* Parity enable */
+#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
+#define  UCR3_DSR        (1<<10) /* Data set ready */
+#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
+#define  UCR3_RI         (1<<8)  /* Ring indicator */
+#define  UCR3_TIMEOUTEN  (1<<7)  /* Timeout interrupt enable */
+#define  UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
+#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
+#define  UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
+#define  UCR3_REF25      (1<<3)  /* Ref freq 25 MHz */
+#define  UCR3_REF30      (1<<2)  /* Ref Freq 30 MHz */
+#define  UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
+#define  UCR3_BPEN       (1<<0)  /* Preset registers enable */
+#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
+#define  UCR4_INVR       (1<<9)  /* Inverted infrared reception */
+#define  UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
+#define  UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
+#define  UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
+#define  UCR4_IRSC       (1<<5)  /* IR special case */
+#define  UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
+#define  UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
+#define  UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
+#define  UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
+#define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
+#define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
+#define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
+#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
+#define  USR1_RTSS       (1<<14) /* RTS pin status */
+#define  USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
+#define  USR1_RTSD       (1<<12) /* RTS delta */
+#define  USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
+#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
+#define  USR1_RRDY       (1<<9)  /* Receiver ready interrupt/dma flag */
+#define  USR1_TIMEOUT    (1<<7)  /* Receive timeout interrupt status */
+#define  USR1_RXDS       (1<<6)  /* Receiver idle interrupt flag */
+#define  USR1_AIRINT     (1<<5)  /* Async IR wake interrupt flag */
+#define  USR1_AWAKE      (1<<4)  /* Aysnc wake interrupt flag */
+#define  USR2_ADET       (1<<15) /* Auto baud rate detect complete */
+#define  USR2_TXFE       (1<<14) /* Transmit buffer FIFO empty */
+#define  USR2_DTRF       (1<<13) /* DTR edge interrupt flag */
+#define  USR2_IDLE       (1<<12) /* Idle condition */
+#define  USR2_IRINT      (1<<8)  /* Serial infrared interrupt flag */
+#define  USR2_WAKE       (1<<7)  /* Wake */
+#define  USR2_RTSF       (1<<4)  /* RTS edge interrupt flag */
+#define  USR2_TXDC       (1<<3)  /* Transmitter complete */
+#define  USR2_BRCD       (1<<2)  /* Break condition */
+#define  USR2_ORE        (1<<1)  /* Overrun error */
+#define  USR2_RDR        (1<<0)  /* Recv data ready */
+#define  UTS_FRCPERR     (1<<13) /* Force parity error */
+#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
+#define  UTS_TXEMPTY     (1<<6)  /* TxFIFO empty */
+#define  UTS_RXEMPTY     (1<<5)  /* RxFIFO empty */
+#define  UTS_TXFULL      (1<<4)  /* TxFIFO full */
+#define  UTS_RXFULL      (1<<3)  /* RxFIFO full */
+#define  UTS_SOFTRST     (1<<0)  /* Software reset */
+
 /* We've been assigned a range on the "Low-density serial ports" major */
 #define SERIAL_IMX_MAJOR        204
 #define MINOR_START             41
@@ -128,7 +244,10 @@ static void imx_timeout(unsigned long data)
 static void imx_stop_tx(struct uart_port *port)
 {
         struct imx_port *sport = (struct imx_port *)port;
-        UCR1((u32)sport->port.membase) &= ~UCR1_TXMPTYEN;
+        unsigned long temp;
+
+        temp = readl(sport->port.membase + UCR1);
+        writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
 }
 
 /*
@@ -137,7 +256,10 @@ static void imx_stop_tx(struct uart_port *port)
 static void imx_stop_rx(struct uart_port *port)
 {
         struct imx_port *sport = (struct imx_port *)port;
-        UCR2((u32)sport->port.membase) &= ~UCR2_RXEN;
+        unsigned long temp;
+
+        temp = readl(sport->port.membase + UCR2);
+        writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
 }
 
 /*
@@ -154,10 +276,10 @@ static inline void imx_transmit_buffer(struct imx_port *sport)
 {
         struct circ_buf *xmit = &sport->port.info->xmit;
 
-        while (!(UTS((u32)sport->port.membase) & UTS_TXFULL)) {
+        while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
                 /* send xmit->buf[xmit->tail]
                  * out the port here */
-                URTX0((u32)sport->port.membase) = xmit->buf[xmit->tail];
+                writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
                 xmit->tail = (xmit->tail + 1) &
                          (UART_XMIT_SIZE - 1);
                 sport->port.icount.tx++;
@@ -175,21 +297,24 @@ static inline void imx_transmit_buffer(struct imx_port *sport)
 static void imx_start_tx(struct uart_port *port)
 {
         struct imx_port *sport = (struct imx_port *)port;
+        unsigned long temp;
 
-        UCR1((u32)sport->port.membase) |= UCR1_TXMPTYEN;
+        temp = readl(sport->port.membase + UCR1);
+        writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
 
-        imx_transmit_buffer(sport);
+        if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
+                imx_transmit_buffer(sport);
 }
 
 static irqreturn_t imx_rtsint(int irq, void *dev_id)
 {
         struct imx_port *sport = (struct imx_port *)dev_id;
-        unsigned int val = USR1((u32)sport->port.membase)&USR1_RTSS;
+        unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
         unsigned long flags;
 
         spin_lock_irqsave(&sport->port.lock, flags);
 
-        USR1((u32)sport->port.membase) = USR1_RTSD;
+        writel(USR1_RTSD, sport->port.membase + USR1);
         uart_handle_cts_change(&sport->port, !!val);
         wake_up_interruptible(&sport->port.info->delta_msr_wait);
 
@@ -207,7 +332,7 @@ static irqreturn_t imx_txint(int irq, void *dev_id)
         if (sport->port.x_char)
         {
                 /* Send next char */
-                URTX0((u32)sport->port.membase) = sport->port.x_char;
+                writel(sport->port.x_char, sport->port.membase + URTX0);
                 goto out;
         }
 
@@ -231,17 +356,18 @@ static irqreturn_t imx_rxint(int irq, void *dev_id)
         struct imx_port *sport = dev_id;
         unsigned int rx,flg,ignored = 0;
         struct tty_struct *tty = sport->port.info->tty;
-        unsigned long flags;
+        unsigned long flags, temp;
 
-        rx = URXD0((u32)sport->port.membase);
+        rx = readl(sport->port.membase + URXD0);
         spin_lock_irqsave(&sport->port.lock,flags);
 
         do {
                 flg = TTY_NORMAL;
                 sport->port.icount.rx++;
 
-                if( USR2((u32)sport->port.membase) & USR2_BRCD ) {
-                        USR2((u32)sport->port.membase) |= USR2_BRCD;
+                temp = readl(sport->port.membase + USR2);
+                if( temp & USR2_BRCD ) {
+                        writel(temp | USR2_BRCD, sport->port.membase + USR2);
                         if(uart_handle_break(&sport->port))
                                 goto ignore_char;
                 }
@@ -257,7 +383,7 @@ static irqreturn_t imx_rxint(int irq, void *dev_id)
                 tty_insert_flip_char(tty, rx, flg);
 
         ignore_char:
-                rx = URXD0((u32)sport->port.membase);
+                rx = readl(sport->port.membase + URXD0);
         } while(rx & URXD_CHARRDY);
 
 out:
@@ -301,7 +427,7 @@ static unsigned int imx_tx_empty(struct uart_port *port)
 {
         struct imx_port *sport = (struct imx_port *)port;
 
-        return USR2((u32)sport->port.membase) & USR2_TXDC ?  TIOCSER_TEMT : 0;
+        return (readl(sport->port.membase + USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
 }
 
 /*
@@ -312,10 +438,10 @@ static unsigned int imx_get_mctrl(struct uart_port *port)
         struct imx_port *sport = (struct imx_port *)port;
         unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
 
-        if (USR1((u32)sport->port.membase) & USR1_RTSS)
+        if (readl(sport->port.membase + USR1) & USR1_RTSS)
                 tmp |= TIOCM_CTS;
 
-        if (UCR2((u32)sport->port.membase) & UCR2_CTS)
+        if (readl(sport->port.membase + UCR2) & UCR2_CTS)
                 tmp |= TIOCM_RTS;
 
         return tmp;
@@ -324,11 +450,14 @@ static unsigned int imx_get_mctrl(struct uart_port *port)
 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
 {
         struct imx_port *sport = (struct imx_port *)port;
+        unsigned long temp;
+
+        temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
 
         if (mctrl & TIOCM_RTS)
-                UCR2((u32)sport->port.membase) |= UCR2_CTS;
-        else
-                UCR2((u32)sport->port.membase) &= ~UCR2_CTS;
+                temp |= UCR2_CTS;
+
+        writel(temp, sport->port.membase + UCR2);
 }
 
 /*
@@ -337,14 +466,16 @@ static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
 static void imx_break_ctl(struct uart_port *port, int break_state)
 {
         struct imx_port *sport = (struct imx_port *)port;
-        unsigned long flags;
+        unsigned long flags, temp;
 
         spin_lock_irqsave(&sport->port.lock, flags);
 
+        temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
+
         if ( break_state != 0 )
-                UCR1((u32)sport->port.membase) |= UCR1_SNDBRK;
-        else
-                UCR1((u32)sport->port.membase) &= ~UCR1_SNDBRK;
+                temp |= UCR1_SNDBRK;
+
+        writel(temp, sport->port.membase + UCR1);
 
         spin_unlock_irqrestore(&sport->port.lock, flags);
 }
@@ -360,7 +491,7 @@ static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
         /* set receiver / transmitter trigger level.
          * RFDIV is set such way to satisfy requested uartclk value
          */
-        val = TXTL<<10 | RXTL;
+        val = TXTL << 10 | RXTL;
         ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk;
 
         if(!ufcr_rfdiv)
@@ -373,7 +504,7 @@ static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
 
         val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
 
-        UFCR((u32)sport->port.membase) = val;
+        writel(val, sport->port.membase + UFCR);
 
         return 0;
 }
@@ -382,14 +513,15 @@ static int imx_startup(struct uart_port *port)
 {
         struct imx_port *sport = (struct imx_port *)port;
         int retval;
-        unsigned long flags;
+        unsigned long flags, temp;
 
         imx_setup_ufcr(sport, 0);
 
         /* disable the DREN bit (Data Ready interrupt enable) before
          * requesting IRQs
          */
-        UCR4((u32)sport->port.membase) &= ~UCR4_DREN;
+        temp = readl(sport->port.membase + UCR4);
+        writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
 
         /*
          * Allocate the IRQ
@@ -411,12 +543,16 @@ static int imx_startup(struct uart_port *port)
         /*
          * Finally, clear and enable interrupts
          */
+        writel(USR1_RTSD, sport->port.membase + USR1);
+
+        temp = readl(sport->port.membase + UCR1);
+        temp |= (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
+        writel(temp, sport->port.membase + UCR1);
 
-        USR1((u32)sport->port.membase) = USR1_RTSD;
-        UCR1((u32)sport->port.membase) |=
-                         (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
+        temp = readl(sport->port.membase + UCR2);
+        temp |= (UCR2_RXEN | UCR2_TXEN);
+        writel(temp, sport->port.membase + UCR2);
 
-        UCR2((u32)sport->port.membase) |= (UCR2_RXEN | UCR2_TXEN);
         /*
          * Enable modem status interrupts
          */
@@ -437,6 +573,7 @@ error_out1:
 static void imx_shutdown(struct uart_port *port)
 {
         struct imx_port *sport = (struct imx_port *)port;
+        unsigned long temp;
 
         /*
          * Stop our timer.
@@ -454,8 +591,9 @@ static void imx_shutdown(struct uart_port *port)
          * Disable all interrupts, port and break condition.
          */
 
-        UCR1((u32)sport->port.membase) &=
-                         ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
+        temp = readl(sport->port.membase + UCR1);
+        temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
+        writel(temp, sport->port.membase + UCR1);
 }
 
 static void
@@ -548,18 +686,18 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
         /*
          * disable interrupts and drain transmitter
          */
-        old_ucr1 = UCR1((u32)sport->port.membase);
-        UCR1((u32)sport->port.membase) &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
+        old_ucr1 = readl(sport->port.membase + UCR1);
+        writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
+                        sport->port.membase + UCR1);
 
-        while ( !(USR2((u32)sport->port.membase) & USR2_TXDC))
+        while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
                 barrier();
 
         /* then, disable everything */
-        old_txrxen = UCR2((u32)sport->port.membase) & ( UCR2_TXEN | UCR2_RXEN );
-        UCR2((u32)sport->port.membase) &= ~( UCR2_TXEN | UCR2_RXEN);
-
-        /* set the parity, stop bits and data size */
-        UCR2((u32)sport->port.membase) = ucr2;
+        old_txrxen = readl(sport->port.membase + UCR2);
+        writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
+                        sport->port.membase + UCR2);
+        old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
 
         /* set the baud rate. We assume uartclk = 16 MHz
          *
@@ -567,11 +705,13 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
          * --------- = --------
          *  uartclk    UBMR - 1
          */
-        UBIR((u32)sport->port.membase) = (baud / 100) - 1;
-        UBMR((u32)sport->port.membase) = 10000 - 1;
+        writel((baud / 100) - 1, sport->port.membase + UBIR);
+        writel(10000 - 1, sport->port.membase + UBMR);
+
+        writel(old_ucr1, sport->port.membase + UCR1);
 
-        UCR1((u32)sport->port.membase) = old_ucr1;
-        UCR2((u32)sport->port.membase) |= old_txrxen;
+        /* set the parity, stop bits and data size */
+        writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
 
         if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
                 imx_enable_ms(&sport->port);
@@ -730,9 +870,11 @@ static void __init imx_init_ports(void)
 static void imx_console_putchar(struct uart_port *port, int ch)
 {
         struct imx_port *sport = (struct imx_port *)port;
-        while ((UTS((u32)sport->port.membase) & UTS_TXFULL))
+
+        while (readl(sport->port.membase + UTS) & UTS_TXFULL)
                 barrier();
-        URTX0((u32)sport->port.membase) = ch;
+
+        writel(ch, sport->port.membase + URTX0);
 }
 
 /*
@@ -747,13 +889,14 @@ imx_console_write(struct console *co, const char *s, unsigned int count)
         /*
          *      First, save UCR1/2 and then disable interrupts
          */
-        old_ucr1 = UCR1((u32)sport->port.membase);
-        old_ucr2 = UCR2((u32)sport->port.membase);
+        old_ucr1 = readl(sport->port.membase + UCR1);
+        old_ucr2 = readl(sport->port.membase + UCR2);
 
-        UCR1((u32)sport->port.membase) =
-                           (old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN)
-                           & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
-        UCR2((u32)sport->port.membase) = old_ucr2 | UCR2_TXEN;
+        writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
+                ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
+                sport->port.membase + UCR1);
+
+        writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
 
         uart_console_write(&sport->port, s, count, imx_console_putchar);
 
@@ -761,10 +904,10 @@ imx_console_write(struct console *co, const char *s, unsigned int count)
          *      Finally, wait for transmitter to become empty
          *      and restore UCR1/2
          */
-        while (!(USR2((u32)sport->port.membase) & USR2_TXDC));
+        while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
 
-        UCR1((u32)sport->port.membase) = old_ucr1;
-        UCR2((u32)sport->port.membase) = old_ucr2;
+        writel(old_ucr1, sport->port.membase + UCR1);
+        writel(old_ucr2, sport->port.membase + UCR2);
 }
 
 /*
@@ -776,13 +919,13 @@ imx_console_get_options(struct imx_port *sport, int *baud,
                            int *parity, int *bits)
 {
 
-        if ( UCR1((u32)sport->port.membase) | UCR1_UARTEN ) {
+        if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
                 /* ok, the port was enabled */
                 unsigned int ucr2, ubir,ubmr, uartclk;
                 unsigned int baud_raw;
                 unsigned int ucfr_rfdiv;
 
-                ucr2 = UCR2((u32)sport->port.membase);
+                ucr2 = readl(sport->port.membase + UCR2);
 
                 *parity = 'n';
                 if (ucr2 & UCR2_PREN) {
@@ -797,11 +940,10 @@ imx_console_get_options(struct imx_port *sport, int *baud,
                 else
                         *bits = 7;
 
-                ubir = UBIR((u32)sport->port.membase) & 0xffff;
-                ubmr = UBMR((u32)sport->port.membase) & 0xffff;
-
+                ubir = readl(sport->port.membase + UBIR) & 0xffff;
+                ubmr = readl(sport->port.membase + UBMR) & 0xffff;
 
-                ucfr_rfdiv = (UFCR((u32)sport->port.membase) & UFCR_RFDIV) >> 7;
+                ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
                 if (ucfr_rfdiv == 6)
                         ucfr_rfdiv = 7;
                 else
diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c
index d403aaa55092..e9c6cb391a23 100644
--- a/drivers/serial/pxa.c
+++ b/drivers/serial/pxa.c
@@ -717,7 +717,7 @@ struct uart_ops serial_pxa_pops = {
 static struct uart_pxa_port serial_pxa_ports[] = {
      {  /* FFUART */
         .name   = "FFUART",
-        .cken   = CKEN6_FFUART,
+        .cken   = CKEN_FFUART,
         .port   = {
                 .type           = PORT_PXA,
                 .iotype         = UPIO_MEM,
@@ -731,7 +731,7 @@ static struct uart_pxa_port serial_pxa_ports[] = {
         },
   }, {  /* BTUART */
         .name   = "BTUART",
-        .cken   = CKEN7_BTUART,
+        .cken   = CKEN_BTUART,
         .port   = {
                 .type           = PORT_PXA,
                 .iotype         = UPIO_MEM,
@@ -745,7 +745,7 @@ static struct uart_pxa_port serial_pxa_ports[] = {
         },
   }, {  /* STUART */
         .name   = "STUART",
-        .cken   = CKEN5_STUART,
+        .cken   = CKEN_STUART,
         .port   = {
                 .type           = PORT_PXA,
                 .iotype         = UPIO_MEM,
@@ -759,7 +759,7 @@ static struct uart_pxa_port serial_pxa_ports[] = {
         },
   }, {  /* HWUART */
         .name   = "HWUART",
-        .cken   = CKEN4_HWUART,
+        .cken   = CKEN_HWUART,
         .port = {
                 .type           = PORT_PXA,
                 .iotype         = UPIO_MEM,