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-rw-r--r--drivers/serial/sunsab.h321
1 files changed, 321 insertions, 0 deletions
diff --git a/drivers/serial/sunsab.h b/drivers/serial/sunsab.h
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1/* sunsab.h: Register Definitions for the Siemens SAB82532 DUSCC
2 *
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 */
5
6#ifndef _SUNSAB_H
7#define _SUNSAB_H
8
9struct sab82532_async_rd_regs {
10 u8 rfifo[0x20]; /* Receive FIFO */
11 u8 star; /* Status Register */
12 u8 __pad1;
13 u8 mode; /* Mode Register */
14 u8 timr; /* Timer Register */
15 u8 xon; /* XON Character */
16 u8 xoff; /* XOFF Character */
17 u8 tcr; /* Termination Character Register */
18 u8 dafo; /* Data Format */
19 u8 rfc; /* RFIFO Control Register */
20 u8 __pad2;
21 u8 rbcl; /* Receive Byte Count Low */
22 u8 rbch; /* Receive Byte Count High */
23 u8 ccr0; /* Channel Configuration Register 0 */
24 u8 ccr1; /* Channel Configuration Register 1 */
25 u8 ccr2; /* Channel Configuration Register 2 */
26 u8 ccr3; /* Channel Configuration Register 3 */
27 u8 __pad3[4];
28 u8 vstr; /* Version Status Register */
29 u8 __pad4[3];
30 u8 gis; /* Global Interrupt Status */
31 u8 ipc; /* Interrupt Port Configuration */
32 u8 isr0; /* Interrupt Status 0 */
33 u8 isr1; /* Interrupt Status 1 */
34 u8 pvr; /* Port Value Register */
35 u8 pis; /* Port Interrupt Status */
36 u8 pcr; /* Port Configuration Register */
37 u8 ccr4; /* Channel Configuration Register 4 */
38};
39
40struct sab82532_async_wr_regs {
41 u8 xfifo[0x20]; /* Transmit FIFO */
42 u8 cmdr; /* Command Register */
43 u8 __pad1;
44 u8 mode;
45 u8 timr;
46 u8 xon;
47 u8 xoff;
48 u8 tcr;
49 u8 dafo;
50 u8 rfc;
51 u8 __pad2;
52 u8 xbcl; /* Transmit Byte Count Low */
53 u8 xbch; /* Transmit Byte Count High */
54 u8 ccr0;
55 u8 ccr1;
56 u8 ccr2;
57 u8 ccr3;
58 u8 tsax; /* Time-Slot Assignment Reg. Transmit */
59 u8 tsar; /* Time-Slot Assignment Reg. Receive */
60 u8 xccr; /* Transmit Channel Capacity Register */
61 u8 rccr; /* Receive Channel Capacity Register */
62 u8 bgr; /* Baud Rate Generator Register */
63 u8 tic; /* Transmit Immediate Character */
64 u8 mxn; /* Mask XON Character */
65 u8 mxf; /* Mask XOFF Character */
66 u8 iva; /* Interrupt Vector Address */
67 u8 ipc;
68 u8 imr0; /* Interrupt Mask Register 0 */
69 u8 imr1; /* Interrupt Mask Register 1 */
70 u8 pvr;
71 u8 pim; /* Port Interrupt Mask */
72 u8 pcr;
73 u8 ccr4;
74};
75
76struct sab82532_async_rw_regs { /* Read/Write registers */
77 u8 __pad1[0x20];
78 u8 __pad2;
79 u8 __pad3;
80 u8 mode;
81 u8 timr;
82 u8 xon;
83 u8 xoff;
84 u8 tcr;
85 u8 dafo;
86 u8 rfc;
87 u8 __pad4;
88 u8 __pad5;
89 u8 __pad6;
90 u8 ccr0;
91 u8 ccr1;
92 u8 ccr2;
93 u8 ccr3;
94 u8 __pad7;
95 u8 __pad8;
96 u8 __pad9;
97 u8 __pad10;
98 u8 __pad11;
99 u8 __pad12;
100 u8 __pad13;
101 u8 __pad14;
102 u8 __pad15;
103 u8 ipc;
104 u8 __pad16;
105 u8 __pad17;
106 u8 pvr;
107 u8 __pad18;
108 u8 pcr;
109 u8 ccr4;
110};
111
112union sab82532_async_regs {
113 __volatile__ struct sab82532_async_rd_regs r;
114 __volatile__ struct sab82532_async_wr_regs w;
115 __volatile__ struct sab82532_async_rw_regs rw;
116};
117
118union sab82532_irq_status {
119 unsigned short stat;
120 struct {
121 unsigned char isr0;
122 unsigned char isr1;
123 } sreg;
124};
125
126/* irqflags bits */
127#define SAB82532_ALLS 0x00000001
128#define SAB82532_XPR 0x00000002
129
130/* RFIFO Status Byte */
131#define SAB82532_RSTAT_PE 0x80
132#define SAB82532_RSTAT_FE 0x40
133#define SAB82532_RSTAT_PARITY 0x01
134
135/* Status Register (STAR) */
136#define SAB82532_STAR_XDOV 0x80
137#define SAB82532_STAR_XFW 0x40
138#define SAB82532_STAR_RFNE 0x20
139#define SAB82532_STAR_FCS 0x10
140#define SAB82532_STAR_TEC 0x08
141#define SAB82532_STAR_CEC 0x04
142#define SAB82532_STAR_CTS 0x02
143
144/* Command Register (CMDR) */
145#define SAB82532_CMDR_RMC 0x80
146#define SAB82532_CMDR_RRES 0x40
147#define SAB82532_CMDR_RFRD 0x20
148#define SAB82532_CMDR_STI 0x10
149#define SAB82532_CMDR_XF 0x08
150#define SAB82532_CMDR_XRES 0x01
151
152/* Mode Register (MODE) */
153#define SAB82532_MODE_FRTS 0x40
154#define SAB82532_MODE_FCTS 0x20
155#define SAB82532_MODE_FLON 0x10
156#define SAB82532_MODE_RAC 0x08
157#define SAB82532_MODE_RTS 0x04
158#define SAB82532_MODE_TRS 0x02
159#define SAB82532_MODE_TLP 0x01
160
161/* Timer Register (TIMR) */
162#define SAB82532_TIMR_CNT_MASK 0xe0
163#define SAB82532_TIMR_VALUE_MASK 0x1f
164
165/* Data Format (DAFO) */
166#define SAB82532_DAFO_XBRK 0x40
167#define SAB82532_DAFO_STOP 0x20
168#define SAB82532_DAFO_PAR_SPACE 0x00
169#define SAB82532_DAFO_PAR_ODD 0x08
170#define SAB82532_DAFO_PAR_EVEN 0x10
171#define SAB82532_DAFO_PAR_MARK 0x18
172#define SAB82532_DAFO_PARE 0x04
173#define SAB82532_DAFO_CHL8 0x00
174#define SAB82532_DAFO_CHL7 0x01
175#define SAB82532_DAFO_CHL6 0x02
176#define SAB82532_DAFO_CHL5 0x03
177
178/* RFIFO Control Register (RFC) */
179#define SAB82532_RFC_DPS 0x40
180#define SAB82532_RFC_DXS 0x20
181#define SAB82532_RFC_RFDF 0x10
182#define SAB82532_RFC_RFTH_1 0x00
183#define SAB82532_RFC_RFTH_4 0x04
184#define SAB82532_RFC_RFTH_16 0x08
185#define SAB82532_RFC_RFTH_32 0x0c
186#define SAB82532_RFC_TCDE 0x01
187
188/* Received Byte Count High (RBCH) */
189#define SAB82532_RBCH_DMA 0x80
190#define SAB82532_RBCH_CAS 0x20
191
192/* Transmit Byte Count High (XBCH) */
193#define SAB82532_XBCH_DMA 0x80
194#define SAB82532_XBCH_CAS 0x20
195#define SAB82532_XBCH_XC 0x10
196
197/* Channel Configuration Register 0 (CCR0) */
198#define SAB82532_CCR0_PU 0x80
199#define SAB82532_CCR0_MCE 0x40
200#define SAB82532_CCR0_SC_NRZ 0x00
201#define SAB82532_CCR0_SC_NRZI 0x08
202#define SAB82532_CCR0_SC_FM0 0x10
203#define SAB82532_CCR0_SC_FM1 0x14
204#define SAB82532_CCR0_SC_MANCH 0x18
205#define SAB82532_CCR0_SM_HDLC 0x00
206#define SAB82532_CCR0_SM_SDLC_LOOP 0x01
207#define SAB82532_CCR0_SM_BISYNC 0x02
208#define SAB82532_CCR0_SM_ASYNC 0x03
209
210/* Channel Configuration Register 1 (CCR1) */
211#define SAB82532_CCR1_ODS 0x10
212#define SAB82532_CCR1_BCR 0x08
213#define SAB82532_CCR1_CM_MASK 0x07
214
215/* Channel Configuration Register 2 (CCR2) */
216#define SAB82532_CCR2_SOC1 0x80
217#define SAB82532_CCR2_SOC0 0x40
218#define SAB82532_CCR2_BR9 0x80
219#define SAB82532_CCR2_BR8 0x40
220#define SAB82532_CCR2_BDF 0x20
221#define SAB82532_CCR2_SSEL 0x10
222#define SAB82532_CCR2_XCS0 0x20
223#define SAB82532_CCR2_RCS0 0x10
224#define SAB82532_CCR2_TOE 0x08
225#define SAB82532_CCR2_RWX 0x04
226#define SAB82532_CCR2_DIV 0x01
227
228/* Channel Configuration Register 3 (CCR3) */
229#define SAB82532_CCR3_PSD 0x01
230
231/* Time Slot Assignment Register Transmit (TSAX) */
232#define SAB82532_TSAX_TSNX_MASK 0xfc
233#define SAB82532_TSAX_XCS2 0x02 /* see also CCR2 */
234#define SAB82532_TSAX_XCS1 0x01
235
236/* Time Slot Assignment Register Receive (TSAR) */
237#define SAB82532_TSAR_TSNR_MASK 0xfc
238#define SAB82532_TSAR_RCS2 0x02 /* see also CCR2 */
239#define SAB82532_TSAR_RCS1 0x01
240
241/* Version Status Register (VSTR) */
242#define SAB82532_VSTR_CD 0x80
243#define SAB82532_VSTR_DPLA 0x40
244#define SAB82532_VSTR_VN_MASK 0x0f
245#define SAB82532_VSTR_VN_1 0x00
246#define SAB82532_VSTR_VN_2 0x01
247#define SAB82532_VSTR_VN_3_2 0x02
248
249/* Global Interrupt Status Register (GIS) */
250#define SAB82532_GIS_PI 0x80
251#define SAB82532_GIS_ISA1 0x08
252#define SAB82532_GIS_ISA0 0x04
253#define SAB82532_GIS_ISB1 0x02
254#define SAB82532_GIS_ISB0 0x01
255
256/* Interrupt Vector Address (IVA) */
257#define SAB82532_IVA_MASK 0xf1
258
259/* Interrupt Port Configuration (IPC) */
260#define SAB82532_IPC_VIS 0x80
261#define SAB82532_IPC_SLA1 0x10
262#define SAB82532_IPC_SLA0 0x08
263#define SAB82532_IPC_CASM 0x04
264#define SAB82532_IPC_IC_OPEN_DRAIN 0x00
265#define SAB82532_IPC_IC_ACT_LOW 0x01
266#define SAB82532_IPC_IC_ACT_HIGH 0x03
267
268/* Interrupt Status Register 0 (ISR0) */
269#define SAB82532_ISR0_TCD 0x80
270#define SAB82532_ISR0_TIME 0x40
271#define SAB82532_ISR0_PERR 0x20
272#define SAB82532_ISR0_FERR 0x10
273#define SAB82532_ISR0_PLLA 0x08
274#define SAB82532_ISR0_CDSC 0x04
275#define SAB82532_ISR0_RFO 0x02
276#define SAB82532_ISR0_RPF 0x01
277
278/* Interrupt Status Register 1 (ISR1) */
279#define SAB82532_ISR1_BRK 0x80
280#define SAB82532_ISR1_BRKT 0x40
281#define SAB82532_ISR1_ALLS 0x20
282#define SAB82532_ISR1_XOFF 0x10
283#define SAB82532_ISR1_TIN 0x08
284#define SAB82532_ISR1_CSC 0x04
285#define SAB82532_ISR1_XON 0x02
286#define SAB82532_ISR1_XPR 0x01
287
288/* Interrupt Mask Register 0 (IMR0) */
289#define SAB82532_IMR0_TCD 0x80
290#define SAB82532_IMR0_TIME 0x40
291#define SAB82532_IMR0_PERR 0x20
292#define SAB82532_IMR0_FERR 0x10
293#define SAB82532_IMR0_PLLA 0x08
294#define SAB82532_IMR0_CDSC 0x04
295#define SAB82532_IMR0_RFO 0x02
296#define SAB82532_IMR0_RPF 0x01
297
298/* Interrupt Mask Register 1 (IMR1) */
299#define SAB82532_IMR1_BRK 0x80
300#define SAB82532_IMR1_BRKT 0x40
301#define SAB82532_IMR1_ALLS 0x20
302#define SAB82532_IMR1_XOFF 0x10
303#define SAB82532_IMR1_TIN 0x08
304#define SAB82532_IMR1_CSC 0x04
305#define SAB82532_IMR1_XON 0x02
306#define SAB82532_IMR1_XPR 0x01
307
308/* Port Interrupt Status Register (PIS) */
309#define SAB82532_PIS_SYNC_B 0x08
310#define SAB82532_PIS_DTR_B 0x04
311#define SAB82532_PIS_DTR_A 0x02
312#define SAB82532_PIS_SYNC_A 0x01
313
314/* Channel Configuration Register 4 (CCR4) */
315#define SAB82532_CCR4_MCK4 0x80
316#define SAB82532_CCR4_EBRG 0x40
317#define SAB82532_CCR4_TST1 0x20
318#define SAB82532_CCR4_ICD 0x10
319
320
321#endif /* !(_SUNSAB_H) */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 06:08:44 -0500