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Diffstat (limited to 'drivers/serial/sh-sci.h')
-rw-r--r--drivers/serial/sh-sci.h90
1 files changed, 46 insertions, 44 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index ab320fa3237c..28643c4dc850 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -10,7 +10,9 @@
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003). 10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004). 11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
12 */ 12 */
13#include <linux/config.h>
13#include <linux/serial_core.h> 14#include <linux/serial_core.h>
15#include <asm/io.h>
14 16
15#if defined(__H8300H__) || defined(__H8300S__) 17#if defined(__H8300H__) || defined(__H8300S__)
16#include <asm/gpio.h> 18#include <asm/gpio.h>
@@ -22,40 +24,13 @@
22#endif 24#endif
23#endif 25#endif
24 26
25/* Offsets into the sci_port->irqs array */
26#define SCIx_ERI_IRQ 0
27#define SCIx_RXI_IRQ 1
28#define SCIx_TXI_IRQ 2
29
30/* ERI, RXI, TXI, BRI */
31#define SCI_IRQS { 23, 24, 25, 0 }
32#define SH3_SCIF_IRQS { 56, 57, 59, 58 }
33#define SH3_IRDA_IRQS { 52, 53, 55, 54 }
34#define SH4_SCIF_IRQS { 40, 41, 43, 42 }
35#define STB1_SCIF1_IRQS {23, 24, 26, 25 }
36#define SH7760_SCIF0_IRQS { 52, 53, 55, 54 }
37#define SH7760_SCIF1_IRQS { 72, 73, 75, 74 }
38#define SH7760_SCIF2_IRQS { 76, 77, 79, 78 }
39#define SH7300_SCIF0_IRQS {80, 80, 80, 80 }
40#define SH73180_SCIF_IRQS {80, 81, 83, 82 }
41#define H8300H_SCI_IRQS0 {52, 53, 54, 0 }
42#define H8300H_SCI_IRQS1 {56, 57, 58, 0 }
43#define H8300H_SCI_IRQS2 {60, 61, 62, 0 }
44#define H8S_SCI_IRQS0 {88, 89, 90, 0 }
45#define H8S_SCI_IRQS1 {92, 93, 94, 0 }
46#define H8S_SCI_IRQS2 {96, 97, 98, 0 }
47#define SH5_SCIF_IRQS {39, 40, 42, 0 }
48#define SH7770_SCIF0_IRQS {61, 61, 61, 61 }
49#define SH7770_SCIF1_IRQS {62, 62, 62, 62 }
50#define SH7770_SCIF2_IRQS {63, 63, 63, 63 }
51#define SH7780_SCIF0_IRQS {40, 41, 43, 42 }
52#define SH7780_SCIF1_IRQS {76, 77, 79, 78 }
53
54#if defined(CONFIG_CPU_SUBTYPE_SH7708) 27#if defined(CONFIG_CPU_SUBTYPE_SH7708)
55# define SCSPTR 0xffffff7c /* 8 bit */ 28# define SCSPTR 0xffffff7c /* 8 bit */
56# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 29# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
57# define SCI_ONLY 30# define SCI_ONLY
58#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) 31#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7706)
59# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 34# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
60# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 35# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
61# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 36# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
@@ -99,12 +74,23 @@
99# define SCPDR 0xA4050136 /* 16 bit SCIF */ 74# define SCPDR 0xA4050136 /* 16 bit SCIF */
100# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 75# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
101# define SCIF_ONLY 76# define SCIF_ONLY
77#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
78# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
79# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
80# define SCIF_ONLY
102#elif defined(CONFIG_CPU_SUBTYPE_SH73180) 81#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
103# define SCPDR 0xA4050138 /* 16 bit SCIF */ 82# define SCPDR 0xA4050138 /* 16 bit SCIF */
104# define SCSPTR2 SCPDR 83# define SCSPTR2 SCPDR
105# define SCIF_ORER 0x0001 /* overrun error bit */ 84# define SCIF_ORER 0x0001 /* overrun error bit */
106# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */ 85# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
107# define SCIF_ONLY 86# define SCIF_ONLY
87#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
88# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
89# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
90# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
91# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
92# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
93# define SCIF_ONLY
108#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 94#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
109# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 95# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
110# define SCIF_ORER 0x0001 /* overrun error bit */ 96# define SCIF_ORER 0x0001 /* overrun error bit */
@@ -145,7 +131,7 @@
145#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 131#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
146# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 132# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
147# define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 133# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
148# define SCIF_OPER 0x0001 /* Overrun error bit */ 134# define SCIF_ORER 0x0001 /* Overrun error bit */
149# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 135# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
150# define SCIF_ONLY 136# define SCIF_ONLY
151#else 137#else
@@ -273,15 +259,6 @@
273 */ 259 */
274#define SCI_EVENT_WRITE_WAKEUP 0 260#define SCI_EVENT_WRITE_WAKEUP 0
275 261
276struct sci_port {
277 struct uart_port port;
278 int type;
279 unsigned char irqs[4]; /* ERI, RXI, TXI, BRI */
280 void (*init_pins)(struct uart_port *port, unsigned int cflag);
281 int break_flag;
282 struct timer_list break_timer;
283};
284
285#define SCI_IN(size, offset) \ 262#define SCI_IN(size, offset) \
286 unsigned int addr = port->mapbase + (offset); \ 263 unsigned int addr = port->mapbase + (offset); \
287 if ((size) == 8) { \ 264 if ((size) == 8) { \
@@ -336,7 +313,9 @@ struct sci_port {
336 } 313 }
337 314
338#ifdef CONFIG_CPU_SH3 315#ifdef CONFIG_CPU_SH3
339#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 316#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
317 defined(CONFIG_CPU_SUBTYPE_SH7705) || \
318 defined(CONFIG_CPU_SUBTYPE_SH7710)
340#define SCIF_FNS(name, scif_offset, scif_size) \ 319#define SCIF_FNS(name, scif_offset, scif_size) \
341 CPU_SCIF_FNS(name, scif_offset, scif_size) 320 CPU_SCIF_FNS(name, scif_offset, scif_size)
342#else 321#else
@@ -362,7 +341,9 @@ struct sci_port {
362 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 341 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
363#endif 342#endif
364 343
365#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 344#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
345 defined(CONFIG_CPU_SUBTYPE_SH7705) || \
346 defined(CONFIG_CPU_SUBTYPE_SH7710)
366SCIF_FNS(SCSMR, 0x00, 16) 347SCIF_FNS(SCSMR, 0x00, 16)
367SCIF_FNS(SCBRR, 0x04, 8) 348SCIF_FNS(SCBRR, 0x04, 8)
368SCIF_FNS(SCSCR, 0x08, 16) 349SCIF_FNS(SCSCR, 0x08, 16)
@@ -447,7 +428,9 @@ static inline int sci_rxd_in(struct uart_port *port)
447 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */ 428 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
448 return 1; 429 return 1;
449} 430}
450#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) 431#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
432 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
433 defined(CONFIG_CPU_SUBTYPE_SH7706)
451static inline int sci_rxd_in(struct uart_port *port) 434static inline int sci_rxd_in(struct uart_port *port)
452{ 435{
453 if (port->mapbase == 0xfffffe80) 436 if (port->mapbase == 0xfffffe80)
@@ -467,6 +450,13 @@ static inline int sci_rxd_in(struct uart_port *port)
467 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ 450 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
468 return 1; 451 return 1;
469} 452}
453#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
454static inline int sci_rxd_in(struct uart_port *port)
455{
456 if (port->mapbase == SCSPTR0)
457 return ctrl_inw(SCSPTR0 + 0x10) & 0x01 ? 1 : 0;
458 return 1;
459}
470#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 460#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
471 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 461 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
472 defined(CONFIG_CPU_SUBTYPE_SH4_202) 462 defined(CONFIG_CPU_SUBTYPE_SH4_202)
@@ -504,6 +494,19 @@ static inline int sci_rxd_in(struct uart_port *port)
504{ 494{
505 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */ 495 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
506} 496}
497#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
498static inline int sci_rxd_in(struct uart_port *port)
499{
500 if (port->mapbase == 0xffe00000)
501 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
502 if (port->mapbase == 0xffe10000)
503 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
504 if (port->mapbase == 0xffe20000)
505 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
506 if (port->mapbase == 0xffe30000)
507 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
508 return 1;
509}
507#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) 510#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
508static inline int sci_rxd_in(struct uart_port *port) 511static inline int sci_rxd_in(struct uart_port *port)
509{ 512{
@@ -587,4 +590,3 @@ static inline int sci_rxd_in(struct uart_port *port)
587#else /* Generic SH */ 590#else /* Generic SH */
588#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 591#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
589#endif 592#endif
590
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