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Diffstat (limited to 'drivers/serial/sh-sci.h')
-rw-r--r--drivers/serial/sh-sci.h50
1 files changed, 42 insertions, 8 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index fb04fb5f9843..247fb66bf0f4 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -53,7 +53,12 @@
53# define SCIF_ORER 0x0001 /* overrun error bit */ 53# define SCIF_ORER 0x0001 /* overrun error bit */
54# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 54# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
55# define SCIF_ONLY 55# define SCIF_ONLY
56#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) 56#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
57 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
58 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
59 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
60 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
61 defined(CONFIG_CPU_SUBTYPE_SH7751R)
57# define SCSPTR1 0xffe0001c /* 8 bit SCI */ 62# define SCSPTR1 0xffe0001c /* 8 bit SCI */
58# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 63# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
59# define SCIF_ORER 0x0001 /* overrun error bit */ 64# define SCIF_ORER 0x0001 /* overrun error bit */
@@ -73,7 +78,7 @@
73# define SCPDR 0xA4050136 /* 16 bit SCIF */ 78# define SCPDR 0xA4050136 /* 16 bit SCIF */
74# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 79# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
75# define SCIF_ONLY 80# define SCIF_ONLY
76#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 81#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
77# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 82# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
78# define SCI_NPORTS 2 83# define SCI_NPORTS 2
79# define SCIF_ORER 0x0001 /* overrun error bit */ 84# define SCIF_ORER 0x0001 /* overrun error bit */
@@ -168,6 +173,14 @@
168# define SCIF_ORER 0x0001 /* overrun error bit */ 173# define SCIF_ORER 0x0001 /* overrun error bit */
169# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 174# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
170# define SCIF_ONLY 175# define SCIF_ONLY
176#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
177# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
178# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
179# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
180# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
181# define SCIF_ORER 0x0001 /* Overrun error bit */
182# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
183# define SCIF_ONLY
171#else 184#else
172# error CPU subtype not defined 185# error CPU subtype not defined
173#endif 186#endif
@@ -177,10 +190,15 @@
177#define SCI_CTRL_FLAGS_RIE 0x40 /* all */ 190#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
178#define SCI_CTRL_FLAGS_TE 0x20 /* all */ 191#define SCI_CTRL_FLAGS_TE 0x20 /* all */
179#define SCI_CTRL_FLAGS_RE 0x10 /* all */ 192#define SCI_CTRL_FLAGS_RE 0x10 /* all */
180#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 193#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
181 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 194 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
182 defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 195 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
183 defined(CONFIG_CPU_SUBTYPE_SH7785) 196 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
197 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
198 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
199 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
200 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
201 defined(CONFIG_CPU_SUBTYPE_SHX3)
184#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 202#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
185#else 203#else
186#define SCI_CTRL_FLAGS_REIE 0 204#define SCI_CTRL_FLAGS_REIE 0
@@ -514,8 +532,12 @@ static inline void set_sh771x_scif_pfc(struct uart_port *port)
514 } 532 }
515} 533}
516 534
517#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 535#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
518 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 536 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
537 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
538 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
539 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
540 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
519 defined(CONFIG_CPU_SUBTYPE_SH4_202) 541 defined(CONFIG_CPU_SUBTYPE_SH4_202)
520static inline int sci_rxd_in(struct uart_port *port) 542static inline int sci_rxd_in(struct uart_port *port)
521{ 543{
@@ -653,6 +675,18 @@ static inline int sci_rxd_in(struct uart_port *port)
653 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 675 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
654 return 1; 676 return 1;
655} 677}
678#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
679static inline int sci_rxd_in(struct uart_port *port)
680{
681 if (port->mapbase == 0xffc30000)
682 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
683 if (port->mapbase == 0xffc40000)
684 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
685 if (port->mapbase == 0xffc50000)
686 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
687 if (port->mapbase == 0xffc60000)
688 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
689}
656#endif 690#endif
657 691
658/* 692/*