diff options
Diffstat (limited to 'drivers/serial/sh-sci.h')
-rw-r--r-- | drivers/serial/sh-sci.h | 42 |
1 files changed, 36 insertions, 6 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index d0aa82d7fce0..38072c15b845 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h | |||
@@ -91,6 +91,9 @@ | |||
91 | # define SCSPTR5 0xa4050128 | 91 | # define SCSPTR5 0xa4050128 |
92 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 92 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
93 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 93 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
94 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) | ||
95 | # define SCIF_ORER 0x0001 /* overrun error bit */ | ||
96 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
94 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) | 97 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
95 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ | 98 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ |
96 | # define SCIF_ORER 0x0001 /* overrun error bit */ | 99 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
@@ -314,7 +317,18 @@ | |||
314 | } \ | 317 | } \ |
315 | } | 318 | } |
316 | 319 | ||
317 | #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ | 320 | #ifdef CONFIG_H8300 |
321 | /* h8300 don't have SCIF */ | ||
322 | #define CPU_SCIF_FNS(name) \ | ||
323 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | ||
324 | { \ | ||
325 | return 0; \ | ||
326 | } \ | ||
327 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | ||
328 | { \ | ||
329 | } | ||
330 | #else | ||
331 | #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ | ||
318 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | 332 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ |
319 | { \ | 333 | { \ |
320 | SCI_IN(scif_size, scif_offset); \ | 334 | SCI_IN(scif_size, scif_offset); \ |
@@ -323,6 +337,7 @@ | |||
323 | { \ | 337 | { \ |
324 | SCI_OUT(scif_size, scif_offset, value); \ | 338 | SCI_OUT(scif_size, scif_offset, value); \ |
325 | } | 339 | } |
340 | #endif | ||
326 | 341 | ||
327 | #define CPU_SCI_FNS(name, sci_offset, sci_size) \ | 342 | #define CPU_SCI_FNS(name, sci_offset, sci_size) \ |
328 | static inline unsigned int sci_##name##_in(struct uart_port* port) \ | 343 | static inline unsigned int sci_##name##_in(struct uart_port* port) \ |
@@ -360,8 +375,10 @@ | |||
360 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | 375 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ |
361 | h8_sci_offset, h8_sci_size) \ | 376 | h8_sci_offset, h8_sci_size) \ |
362 | CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) | 377 | CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) |
363 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) | 378 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ |
364 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) | 379 | CPU_SCIF_FNS(name) |
380 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ | ||
381 | defined(CONFIG_CPU_SUBTYPE_SH7724) | ||
365 | #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \ | 382 | #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \ |
366 | CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) | 383 | CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) |
367 | #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ | 384 | #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ |
@@ -390,7 +407,8 @@ SCIF_FNS(SCFDR, 0x1c, 16) | |||
390 | SCIF_FNS(SCxTDR, 0x20, 8) | 407 | SCIF_FNS(SCxTDR, 0x20, 8) |
391 | SCIF_FNS(SCxRDR, 0x24, 8) | 408 | SCIF_FNS(SCxRDR, 0x24, 8) |
392 | SCIF_FNS(SCLSR, 0x24, 16) | 409 | SCIF_FNS(SCLSR, 0x24, 16) |
393 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) | 410 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ |
411 | defined(CONFIG_CPU_SUBTYPE_SH7724) | ||
394 | SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) | 412 | SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) |
395 | SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) | 413 | SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) |
396 | SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) | 414 | SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) |
@@ -604,10 +622,21 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
604 | return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ | 622 | return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ |
605 | return 1; | 623 | return 1; |
606 | } | 624 | } |
625 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) | ||
626 | # define SCFSR 0x0010 | ||
627 | # define SCASSR 0x0014 | ||
628 | static inline int sci_rxd_in(struct uart_port *port) | ||
629 | { | ||
630 | if (port->type == PORT_SCIF) | ||
631 | return ctrl_inw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0; | ||
632 | if (port->type == PORT_SCIFA) | ||
633 | return ctrl_inw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0; | ||
634 | return 1; | ||
635 | } | ||
607 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | 636 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
608 | static inline int sci_rxd_in(struct uart_port *port) | 637 | static inline int sci_rxd_in(struct uart_port *port) |
609 | { | 638 | { |
610 | return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | 639 | return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */ |
611 | } | 640 | } |
612 | #elif defined(__H8300H__) || defined(__H8300S__) | 641 | #elif defined(__H8300H__) || defined(__H8300S__) |
613 | static inline int sci_rxd_in(struct uart_port *port) | 642 | static inline int sci_rxd_in(struct uart_port *port) |
@@ -757,7 +786,8 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
757 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 786 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
758 | defined(CONFIG_CPU_SUBTYPE_SH7721) | 787 | defined(CONFIG_CPU_SUBTYPE_SH7721) |
759 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) | 788 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) |
760 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) | 789 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ |
790 | defined(CONFIG_CPU_SUBTYPE_SH7724) | ||
761 | static inline int scbrr_calc(struct uart_port *port, int bps, int clk) | 791 | static inline int scbrr_calc(struct uart_port *port, int bps, int clk) |
762 | { | 792 | { |
763 | if (port->type == PORT_SCIF) | 793 | if (port->type == PORT_SCIF) |