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-rw-r--r--drivers/serial/sh-sci.h83
1 files changed, 69 insertions, 14 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 77f7d6351ab1..fb04fb5f9843 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -73,9 +73,13 @@
73# define SCPDR 0xA4050136 /* 16 bit SCIF */ 73# define SCPDR 0xA4050136 /* 16 bit SCIF */
74# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 74# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
75# define SCIF_ONLY 75# define SCIF_ONLY
76#elif defined(CONFIG_CPU_SUBTYPE_SH7710) 76#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
77# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 77# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
78# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 78# define SCI_NPORTS 2
79# define SCIF_ORER 0x0001 /* overrun error bit */
80# define PACR 0xa4050100
81# define PBCR 0xa4050102
82# define SCSCR_INIT(port) 0x3B
79# define SCIF_ONLY 83# define SCIF_ONLY
80#elif defined(CONFIG_CPU_SUBTYPE_SH73180) 84#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
81# define SCPDR 0xA4050138 /* 16 bit SCIF */ 85# define SCPDR 0xA4050138 /* 16 bit SCIF */
@@ -140,6 +144,16 @@
140# define SCIF_ORER 0x0001 /* Overrun error bit */ 144# define SCIF_ORER 0x0001 /* Overrun error bit */
141# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 145# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
142# define SCIF_ONLY 146# define SCIF_ONLY
147#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
148# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
149# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
150# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
151# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
152# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
153# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
154# define SCIF_OPER 0x0001 /* Overrun error bit */
155# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
156# define SCIF_ONLY
143#elif defined(CONFIG_CPU_SUBTYPE_SH7206) 157#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
144# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ 158# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
145# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ 159# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
@@ -163,7 +177,10 @@
163#define SCI_CTRL_FLAGS_RIE 0x40 /* all */ 177#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
164#define SCI_CTRL_FLAGS_TE 0x20 /* all */ 178#define SCI_CTRL_FLAGS_TE 0x20 /* all */
165#define SCI_CTRL_FLAGS_RE 0x10 /* all */ 179#define SCI_CTRL_FLAGS_RE 0x10 /* all */
166#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7780) 180#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
181 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
182 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
183 defined(CONFIG_CPU_SUBTYPE_SH7785)
167#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 184#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
168#else 185#else
169#define SCI_CTRL_FLAGS_REIE 0 186#define SCI_CTRL_FLAGS_REIE 0
@@ -333,9 +350,15 @@
333 } 350 }
334 351
335#ifdef CONFIG_CPU_SH3 352#ifdef CONFIG_CPU_SH3
336#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ 353#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
337 defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 354#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
338 defined(CONFIG_CPU_SUBTYPE_SH7710) 355 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
356 h8_sci_offset, h8_sci_size) \
357 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
358#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
359 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
360#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
361 defined(CONFIG_CPU_SUBTYPE_SH7705)
339#define SCIF_FNS(name, scif_offset, scif_size) \ 362#define SCIF_FNS(name, scif_offset, scif_size) \
340 CPU_SCIF_FNS(name, scif_offset, scif_size) 363 CPU_SCIF_FNS(name, scif_offset, scif_size)
341#else 364#else
@@ -362,8 +385,8 @@
362#endif 385#endif
363 386
364#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ 387#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
365 defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 388 defined(CONFIG_CPU_SUBTYPE_SH7705)
366 defined(CONFIG_CPU_SUBTYPE_SH7710) 389
367SCIF_FNS(SCSMR, 0x00, 16) 390SCIF_FNS(SCSMR, 0x00, 16)
368SCIF_FNS(SCBRR, 0x04, 8) 391SCIF_FNS(SCBRR, 0x04, 8)
369SCIF_FNS(SCSCR, 0x08, 16) 392SCIF_FNS(SCSCR, 0x08, 16)
@@ -385,7 +408,9 @@ SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
385SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) 408SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
386SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) 409SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
387SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) 410SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
388#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) 411#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
412 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
413 defined(CONFIG_CPU_SUBTYPE_SH7785)
389SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 414SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
390SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 415SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
391SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 416SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
@@ -471,13 +496,24 @@ static inline int sci_rxd_in(struct uart_port *port)
471 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ 496 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
472 return 1; 497 return 1;
473} 498}
474#elif defined(CONFIG_CPU_SUBTYPE_SH7710) 499#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
475static inline int sci_rxd_in(struct uart_port *port) 500static inline int sci_rxd_in(struct uart_port *port)
476{ 501{
477 if (port->mapbase == SCSPTR0) 502 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
478 return ctrl_inw(SCSPTR0 + 0x10) & 0x01 ? 1 : 0; 503}
479 return 1; 504static inline void set_sh771x_scif_pfc(struct uart_port *port)
505{
506 if (port->mapbase == 0xA4400000){
507 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
508 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
509 return;
510 }
511 if (port->mapbase == 0xA4410000){
512 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
513 return;
514 }
480} 515}
516
481#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 517#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
482 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 518 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
483 defined(CONFIG_CPU_SUBTYPE_SH4_202) 519 defined(CONFIG_CPU_SUBTYPE_SH4_202)
@@ -576,6 +612,23 @@ static inline int sci_rxd_in(struct uart_port *port)
576 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 612 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
577 return 1; 613 return 1;
578} 614}
615#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
616static inline int sci_rxd_in(struct uart_port *port)
617{
618 if (port->mapbase == 0xffea0000)
619 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
620 if (port->mapbase == 0xffeb0000)
621 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
622 if (port->mapbase == 0xffec0000)
623 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
624 if (port->mapbase == 0xffed0000)
625 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
626 if (port->mapbase == 0xffee0000)
627 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
628 if (port->mapbase == 0xffef0000)
629 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
630 return 1;
631}
579#elif defined(CONFIG_CPU_SUBTYPE_SH7206) 632#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
580static inline int sci_rxd_in(struct uart_port *port) 633static inline int sci_rxd_in(struct uart_port *port)
581{ 634{
@@ -634,7 +687,9 @@ static inline int sci_rxd_in(struct uart_port *port)
634 * -- Mitch Davis - 15 Jul 2000 687 * -- Mitch Davis - 15 Jul 2000
635 */ 688 */
636 689
637#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7780) 690#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
691 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
692 defined(CONFIG_CPU_SUBTYPE_SH7785)
638#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 693#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
639#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 694#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
640#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 695#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)