diff options
Diffstat (limited to 'drivers/serial/sh-sci.h')
-rw-r--r-- | drivers/serial/sh-sci.h | 40 |
1 files changed, 37 insertions, 3 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index 77f7d6351ab1..854153a1d60a 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h | |||
@@ -140,6 +140,16 @@ | |||
140 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | 140 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
141 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | 141 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
142 | # define SCIF_ONLY | 142 | # define SCIF_ONLY |
143 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) | ||
144 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ | ||
145 | # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ | ||
146 | # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ | ||
147 | # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ | ||
148 | # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ | ||
149 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ | ||
150 | # define SCIF_OPER 0x0001 /* Overrun error bit */ | ||
151 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
152 | # define SCIF_ONLY | ||
143 | #elif defined(CONFIG_CPU_SUBTYPE_SH7206) | 153 | #elif defined(CONFIG_CPU_SUBTYPE_SH7206) |
144 | # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ | 154 | # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ |
145 | # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ | 155 | # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ |
@@ -163,7 +173,10 @@ | |||
163 | #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ | 173 | #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ |
164 | #define SCI_CTRL_FLAGS_TE 0x20 /* all */ | 174 | #define SCI_CTRL_FLAGS_TE 0x20 /* all */ |
165 | #define SCI_CTRL_FLAGS_RE 0x10 /* all */ | 175 | #define SCI_CTRL_FLAGS_RE 0x10 /* all */ |
166 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7780) | 176 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
177 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | ||
178 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | ||
179 | defined(CONFIG_CPU_SUBTYPE_SH7785) | ||
167 | #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ | 180 | #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ |
168 | #else | 181 | #else |
169 | #define SCI_CTRL_FLAGS_REIE 0 | 182 | #define SCI_CTRL_FLAGS_REIE 0 |
@@ -385,7 +398,9 @@ SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) | |||
385 | SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) | 398 | SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) |
386 | SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) | 399 | SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) |
387 | SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) | 400 | SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) |
388 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) | 401 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
402 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | ||
403 | defined(CONFIG_CPU_SUBTYPE_SH7785) | ||
389 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) | 404 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
390 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) | 405 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) |
391 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | 406 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) |
@@ -576,6 +591,23 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
576 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | 591 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ |
577 | return 1; | 592 | return 1; |
578 | } | 593 | } |
594 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) | ||
595 | static inline int sci_rxd_in(struct uart_port *port) | ||
596 | { | ||
597 | if (port->mapbase == 0xffea0000) | ||
598 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
599 | if (port->mapbase == 0xffeb0000) | ||
600 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
601 | if (port->mapbase == 0xffec0000) | ||
602 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
603 | if (port->mapbase == 0xffed0000) | ||
604 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | ||
605 | if (port->mapbase == 0xffee0000) | ||
606 | return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ | ||
607 | if (port->mapbase == 0xffef0000) | ||
608 | return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ | ||
609 | return 1; | ||
610 | } | ||
579 | #elif defined(CONFIG_CPU_SUBTYPE_SH7206) | 611 | #elif defined(CONFIG_CPU_SUBTYPE_SH7206) |
580 | static inline int sci_rxd_in(struct uart_port *port) | 612 | static inline int sci_rxd_in(struct uart_port *port) |
581 | { | 613 | { |
@@ -634,7 +666,9 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
634 | * -- Mitch Davis - 15 Jul 2000 | 666 | * -- Mitch Davis - 15 Jul 2000 |
635 | */ | 667 | */ |
636 | 668 | ||
637 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7780) | 669 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ |
670 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | ||
671 | defined(CONFIG_CPU_SUBTYPE_SH7785) | ||
638 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) | 672 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) |
639 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | 673 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) |
640 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) | 674 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) |