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-rw-r--r--drivers/serial/sh-sci.c1148
1 files changed, 420 insertions, 728 deletions
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 44f6bf79bbe1..f336ba6778dd 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * 5 *
6 * Copyright (C) 2002, 2003, 2004 Paul Mundt 6 * Copyright (C) 2002 - 2006 Paul Mundt
7 * 7 *
8 * based off of the old drivers/char/sh-sci.c by: 8 * based off of the old drivers/char/sh-sci.c by:
9 * 9 *
@@ -23,8 +23,6 @@
23#include <linux/config.h> 23#include <linux/config.h>
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/errno.h> 25#include <linux/errno.h>
26#include <linux/signal.h>
27#include <linux/sched.h>
28#include <linux/timer.h> 26#include <linux/timer.h>
29#include <linux/interrupt.h> 27#include <linux/interrupt.h>
30#include <linux/tty.h> 28#include <linux/tty.h>
@@ -33,71 +31,77 @@
33#include <linux/major.h> 31#include <linux/major.h>
34#include <linux/string.h> 32#include <linux/string.h>
35#include <linux/sysrq.h> 33#include <linux/sysrq.h>
36#include <linux/fcntl.h>
37#include <linux/ptrace.h>
38#include <linux/ioport.h> 34#include <linux/ioport.h>
39#include <linux/mm.h> 35#include <linux/mm.h>
40#include <linux/slab.h>
41#include <linux/init.h> 36#include <linux/init.h>
42#include <linux/delay.h> 37#include <linux/delay.h>
43#include <linux/console.h> 38#include <linux/console.h>
44#include <linux/bitops.h> 39#include <linux/platform_device.h>
45#include <linux/generic_serial.h>
46 40
47#ifdef CONFIG_CPU_FREQ 41#ifdef CONFIG_CPU_FREQ
48#include <linux/notifier.h> 42#include <linux/notifier.h>
49#include <linux/cpufreq.h> 43#include <linux/cpufreq.h>
50#endif 44#endif
51 45
52#include <asm/system.h>
53#include <asm/io.h>
54#include <asm/irq.h>
55#include <asm/uaccess.h>
56
57#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64) 46#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
58#include <asm/clock.h> 47#include <asm/clock.h>
59#endif
60
61#ifdef CONFIG_SH_STANDARD_BIOS
62#include <asm/sh_bios.h> 48#include <asm/sh_bios.h>
49#include <asm/kgdb.h>
63#endif 50#endif
64 51
52#include <asm/sci.h>
53
65#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 54#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
66#define SUPPORT_SYSRQ 55#define SUPPORT_SYSRQ
67#endif 56#endif
68 57
69#include "sh-sci.h" 58#include "sh-sci.h"
70 59
71#ifdef CONFIG_SH_KGDB 60struct sci_port {
72#include <asm/kgdb.h> 61 struct uart_port port;
62
63 /* Port type */
64 unsigned int type;
65
66 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
67 unsigned int irqs[SCIx_NR_IRQS];
68
69 /* Port pin configuration */
70 void (*init_pins)(struct uart_port *port,
71 unsigned int cflag);
73 72
74static int kgdb_get_char(struct sci_port *port); 73 /* Port enable callback */
75static void kgdb_put_char(struct sci_port *port, char c); 74 void (*enable)(struct uart_port *port);
76static void kgdb_handle_error(struct sci_port *port); 75
76 /* Port disable callback */
77 void (*disable)(struct uart_port *port);
78
79 /* Break timer */
80 struct timer_list break_timer;
81 int break_flag;
82};
83
84#ifdef CONFIG_SH_KGDB
77static struct sci_port *kgdb_sci_port; 85static struct sci_port *kgdb_sci_port;
78#endif /* CONFIG_SH_KGDB */ 86#endif
79 87
80#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 88#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
81static struct sci_port *serial_console_port = 0; 89static struct sci_port *serial_console_port;
82#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 90#endif
83 91
84/* Function prototypes */ 92/* Function prototypes */
85static void sci_stop_tx(struct uart_port *port); 93static void sci_stop_tx(struct uart_port *port);
86static void sci_start_tx(struct uart_port *port);
87static void sci_start_rx(struct uart_port *port, unsigned int tty_start);
88static void sci_stop_rx(struct uart_port *port);
89static int sci_request_irq(struct sci_port *port);
90static void sci_free_irq(struct sci_port *port);
91
92static struct sci_port sci_ports[];
93static struct uart_driver sci_uart_driver;
94 94
95#define SCI_NPORTS sci_uart_driver.nr 95#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
96 96
97#if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) 97static struct sci_port sci_ports[SCI_NPORTS];
98static struct uart_driver sci_uart_driver;
98 99
99static void handle_error(struct uart_port *port) 100#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
100{ /* Clear error flags */ 101 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
102static inline void handle_error(struct uart_port *port)
103{
104 /* Clear error flags */
101 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 105 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
102} 106}
103 107
@@ -107,8 +111,8 @@ static int get_char(struct uart_port *port)
107 unsigned short status; 111 unsigned short status;
108 int c; 112 int c;
109 113
110 local_irq_save(flags); 114 spin_lock_irqsave(&port->lock, flags);
111 do { 115 do {
112 status = sci_in(port, SCxSR); 116 status = sci_in(port, SCxSR);
113 if (status & SCxSR_ERRORS(port)) { 117 if (status & SCxSR_ERRORS(port)) {
114 handle_error(port); 118 handle_error(port);
@@ -118,38 +122,19 @@ static int get_char(struct uart_port *port)
118 c = sci_in(port, SCxRDR); 122 c = sci_in(port, SCxRDR);
119 sci_in(port, SCxSR); /* Dummy read */ 123 sci_in(port, SCxSR); /* Dummy read */
120 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 124 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
121 local_irq_restore(flags); 125 spin_unlock_irqrestore(&port->lock, flags);
122 126
123 return c; 127 return c;
124} 128}
125
126/* Taken from sh-stub.c of GDB 4.18 */
127static const char hexchars[] = "0123456789abcdef";
128
129static __inline__ char highhex(int x)
130{
131 return hexchars[(x >> 4) & 0xf];
132}
133
134static __inline__ char lowhex(int x)
135{
136 return hexchars[x & 0xf];
137}
138
139#endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */ 129#endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
140 130
141/* 131#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
142 * Send the packet in buffer. The host gets one chance to read it.
143 * This routine does not wait for a positive acknowledge.
144 */
145
146#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
147static void put_char(struct uart_port *port, char c) 132static void put_char(struct uart_port *port, char c)
148{ 133{
149 unsigned long flags; 134 unsigned long flags;
150 unsigned short status; 135 unsigned short status;
151 136
152 local_irq_save(flags); 137 spin_lock_irqsave(&port->lock, flags);
153 138
154 do { 139 do {
155 status = sci_in(port, SCxSR); 140 status = sci_in(port, SCxSR);
@@ -159,9 +144,11 @@ static void put_char(struct uart_port *port, char c)
159 sci_in(port, SCxSR); /* Dummy read */ 144 sci_in(port, SCxSR); /* Dummy read */
160 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 145 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
161 146
162 local_irq_restore(flags); 147 spin_unlock_irqrestore(&port->lock, flags);
163} 148}
149#endif
164 150
151#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
165static void put_string(struct sci_port *sci_port, const char *buffer, int count) 152static void put_string(struct sci_port *sci_port, const char *buffer, int count)
166{ 153{
167 struct uart_port *port = &sci_port->port; 154 struct uart_port *port = &sci_port->port;
@@ -214,96 +201,28 @@ static void put_string(struct sci_port *sci_port, const char *buffer, int count)
214} 201}
215#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 202#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
216 203
217
218#ifdef CONFIG_SH_KGDB 204#ifdef CONFIG_SH_KGDB
219
220/* Is the SCI ready, ie is there a char waiting? */
221static int kgdb_is_char_ready(struct sci_port *port)
222{
223 unsigned short status = sci_in(port, SCxSR);
224
225 if (status & (SCxSR_ERRORS(port) | SCxSR_BRK(port)))
226 kgdb_handle_error(port);
227
228 return (status & SCxSR_RDxF(port));
229}
230
231/* Write a char */
232static void kgdb_put_char(struct sci_port *port, char c)
233{
234 unsigned short status;
235
236 do
237 status = sci_in(port, SCxSR);
238 while (!(status & SCxSR_TDxE(port)));
239
240 sci_out(port, SCxTDR, c);
241 sci_in(port, SCxSR); /* Dummy read */
242 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
243}
244
245/* Get a char if there is one, else ret -1 */
246static int kgdb_get_char(struct sci_port *port)
247{
248 int c;
249
250 if (kgdb_is_char_ready(port) == 0)
251 c = -1;
252 else {
253 c = sci_in(port, SCxRDR);
254 sci_in(port, SCxSR); /* Dummy read */
255 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
256 }
257
258 return c;
259}
260
261/* Called from kgdbstub.c to get a character, i.e. is blocking */
262static int kgdb_sci_getchar(void) 205static int kgdb_sci_getchar(void)
263{ 206{
264 volatile int c; 207 int c;
265 208
266 /* Keep trying to read a character, this could be neater */ 209 /* Keep trying to read a character, this could be neater */
267 while ((c = kgdb_get_char(kgdb_sci_port)) < 0); 210 while ((c = get_char(kgdb_sci_port)) < 0)
211 cpu_relax();
268 212
269 return c; 213 return c;
270} 214}
271 215
272/* Called from kgdbstub.c to put a character, just a wrapper */ 216static inline void kgdb_sci_putchar(int c)
273static void kgdb_sci_putchar(int c)
274{
275
276 kgdb_put_char(kgdb_sci_port, c);
277}
278
279/* Clear any errors on the SCI */
280static void kgdb_handle_error(struct sci_port *port)
281{ 217{
282 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); /* Clear error flags */ 218 put_char(kgdb_sci_port, c);
283} 219}
284
285/* Breakpoint if there's a break sent on the serial port */
286static void kgdb_break_interrupt(int irq, void *ptr, struct pt_regs *regs)
287{
288 struct sci_port *port = ptr;
289 unsigned short status = sci_in(port, SCxSR);
290
291 if (status & SCxSR_BRK(port)) {
292
293 /* Break into the debugger if a break is detected */
294 BREAKPOINT();
295
296 /* Clear */
297 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
298 }
299}
300
301#endif /* CONFIG_SH_KGDB */ 220#endif /* CONFIG_SH_KGDB */
302 221
303#if defined(__H8300S__) 222#if defined(__H8300S__)
304enum { sci_disable, sci_enable }; 223enum { sci_disable, sci_enable };
305 224
306static void h8300_sci_enable(struct uart_port* port, unsigned int ctrl) 225static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
307{ 226{
308 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL; 227 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
309 int ch = (port->mapbase - SMR0) >> 3; 228 int ch = (port->mapbase - SMR0) >> 3;
@@ -315,32 +234,66 @@ static void h8300_sci_enable(struct uart_port* port, unsigned int ctrl)
315 *mstpcrl &= ~mask; 234 *mstpcrl &= ~mask;
316 } 235 }
317} 236}
237
238static inline void h8300_sci_enable(struct uart_port *port)
239{
240 h8300_sci_config(port, sci_enable);
241}
242
243static inline void h8300_sci_disable(struct uart_port *port)
244{
245 h8300_sci_config(port, sci_disable);
246}
318#endif 247#endif
319 248
320#if defined(SCI_ONLY) || defined(SCI_AND_SCIF) 249#if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
321#if defined(__H8300H__) || defined(__H8300S__) 250 defined(__H8300H__) || defined(__H8300S__)
322static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag) 251static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
323{ 252{
324 int ch = (port->mapbase - SMR0) >> 3; 253 int ch = (port->mapbase - SMR0) >> 3;
325 254
326 /* set DDR regs */ 255 /* set DDR regs */
327 H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].rx,H8300_GPIO_INPUT); 256 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
328 H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].tx,H8300_GPIO_OUTPUT); 257 h8300_sci_pins[ch].rx,
258 H8300_GPIO_INPUT);
259 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
260 h8300_sci_pins[ch].tx,
261 H8300_GPIO_OUTPUT);
262
329 /* tx mark output*/ 263 /* tx mark output*/
330 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; 264 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
331} 265}
266#else
267#define sci_init_pins_sci NULL
268#endif
269
270#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
271static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
272{
273 unsigned int fcr_val = 0;
274
275 if (cflag & CRTSCTS)
276 fcr_val |= SCFCR_MCE;
277
278 sci_out(port, SCFCR, fcr_val);
279}
280#else
281#define sci_init_pins_irda NULL
332#endif 282#endif
283
284#ifdef SCI_ONLY
285#define sci_init_pins_scif NULL
333#endif 286#endif
334 287
335#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF) 288#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
336#if defined(CONFIG_CPU_SUBTYPE_SH7300) 289#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
337/* SH7300 doesn't use RTS/CTS */ 290/* SH7300 doesn't use RTS/CTS */
338static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 291static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
339{ 292{
340 sci_out(port, SCFCR, 0); 293 sci_out(port, SCFCR, 0);
341} 294}
342#elif defined(CONFIG_CPU_SH3) 295#elif defined(CONFIG_CPU_SH3)
343/* For SH7705, SH7707, SH7709, SH7709A, SH7729 */ 296/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
344static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 297static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
345{ 298{
346 unsigned int fcr_val = 0; 299 unsigned int fcr_val = 0;
@@ -367,20 +320,7 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
367 320
368 sci_out(port, SCFCR, fcr_val); 321 sci_out(port, SCFCR, fcr_val);
369} 322}
370
371#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
372static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
373{
374 unsigned int fcr_val = 0;
375
376 if (cflag & CRTSCTS)
377 fcr_val |= SCFCR_MCE;
378
379 sci_out(port, SCFCR, fcr_val);
380}
381#endif
382#else 323#else
383
384/* For SH7750 */ 324/* For SH7750 */
385static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 325static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
386{ 326{
@@ -389,7 +329,9 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
389 if (cflag & CRTSCTS) { 329 if (cflag & CRTSCTS) {
390 fcr_val |= SCFCR_MCE; 330 fcr_val |= SCFCR_MCE;
391 } else { 331 } else {
392#ifdef CONFIG_CPU_SUBTYPE_SH7780 332#ifdef CONFIG_CPU_SUBTYPE_SH7343
333 /* Nothing */
334#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
393 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */ 335 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
394#else 336#else
395 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */ 337 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
@@ -397,10 +339,41 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
397 } 339 }
398 sci_out(port, SCFCR, fcr_val); 340 sci_out(port, SCFCR, fcr_val);
399} 341}
342#endif
343
344#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
345static inline int scif_txroom(struct uart_port *port)
346{
347 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
348}
349
350static inline int scif_rxroom(struct uart_port *port)
351{
352 return sci_in(port, SCRFDR) & 0x7f;
353}
354#else
355static inline int scif_txroom(struct uart_port *port)
356{
357 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
358}
400 359
360static inline int scif_rxroom(struct uart_port *port)
361{
362 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
363}
401#endif 364#endif
402#endif /* SCIF_ONLY || SCI_AND_SCIF */ 365#endif /* SCIF_ONLY || SCI_AND_SCIF */
403 366
367static inline int sci_txroom(struct uart_port *port)
368{
369 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
370}
371
372static inline int sci_rxroom(struct uart_port *port)
373{
374 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
375}
376
404/* ********************************************************************** * 377/* ********************************************************************** *
405 * the interrupt related routines * 378 * the interrupt related routines *
406 * ********************************************************************** */ 379 * ********************************************************************** */
@@ -409,14 +382,12 @@ static void sci_transmit_chars(struct uart_port *port)
409{ 382{
410 struct circ_buf *xmit = &port->info->xmit; 383 struct circ_buf *xmit = &port->info->xmit;
411 unsigned int stopped = uart_tx_stopped(port); 384 unsigned int stopped = uart_tx_stopped(port);
412 unsigned long flags;
413 unsigned short status; 385 unsigned short status;
414 unsigned short ctrl; 386 unsigned short ctrl;
415 int count, txroom; 387 int count;
416 388
417 status = sci_in(port, SCxSR); 389 status = sci_in(port, SCxSR);
418 if (!(status & SCxSR_TDxE(port))) { 390 if (!(status & SCxSR_TDxE(port))) {
419 local_irq_save(flags);
420 ctrl = sci_in(port, SCSCR); 391 ctrl = sci_in(port, SCSCR);
421 if (uart_circ_empty(xmit)) { 392 if (uart_circ_empty(xmit)) {
422 ctrl &= ~SCI_CTRL_FLAGS_TIE; 393 ctrl &= ~SCI_CTRL_FLAGS_TIE;
@@ -424,25 +395,15 @@ static void sci_transmit_chars(struct uart_port *port)
424 ctrl |= SCI_CTRL_FLAGS_TIE; 395 ctrl |= SCI_CTRL_FLAGS_TIE;
425 } 396 }
426 sci_out(port, SCSCR, ctrl); 397 sci_out(port, SCSCR, ctrl);
427 local_irq_restore(flags);
428 return; 398 return;
429 } 399 }
430 400
431#if !defined(SCI_ONLY) 401#ifndef SCI_ONLY
432 if (port->type == PORT_SCIF) { 402 if (port->type == PORT_SCIF)
433#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) 403 count = scif_txroom(port);
434 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f); 404 else
435#else
436 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCFDR)>>8);
437#endif
438 } else {
439 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
440 }
441#else
442 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
443#endif 405#endif
444 406 count = sci_txroom(port);
445 count = txroom;
446 407
447 do { 408 do {
448 unsigned char c; 409 unsigned char c;
@@ -469,7 +430,6 @@ static void sci_transmit_chars(struct uart_port *port)
469 if (uart_circ_empty(xmit)) { 430 if (uart_circ_empty(xmit)) {
470 sci_stop_tx(port); 431 sci_stop_tx(port);
471 } else { 432 } else {
472 local_irq_save(flags);
473 ctrl = sci_in(port, SCSCR); 433 ctrl = sci_in(port, SCSCR);
474 434
475#if !defined(SCI_ONLY) 435#if !defined(SCI_ONLY)
@@ -481,7 +441,6 @@ static void sci_transmit_chars(struct uart_port *port)
481 441
482 ctrl |= SCI_CTRL_FLAGS_TIE; 442 ctrl |= SCI_CTRL_FLAGS_TIE;
483 sci_out(port, SCSCR, ctrl); 443 sci_out(port, SCSCR, ctrl);
484 local_irq_restore(flags);
485 } 444 }
486} 445}
487 446
@@ -491,6 +450,7 @@ static void sci_transmit_chars(struct uart_port *port)
491static inline void sci_receive_chars(struct uart_port *port, 450static inline void sci_receive_chars(struct uart_port *port,
492 struct pt_regs *regs) 451 struct pt_regs *regs)
493{ 452{
453 struct sci_port *sci_port = (struct sci_port *)port;
494 struct tty_struct *tty = port->info->tty; 454 struct tty_struct *tty = port->info->tty;
495 int i, count, copied = 0; 455 int i, count, copied = 0;
496 unsigned short status; 456 unsigned short status;
@@ -502,18 +462,11 @@ static inline void sci_receive_chars(struct uart_port *port,
502 462
503 while (1) { 463 while (1) {
504#if !defined(SCI_ONLY) 464#if !defined(SCI_ONLY)
505 if (port->type == PORT_SCIF) { 465 if (port->type == PORT_SCIF)
506#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) 466 count = scif_rxroom(port);
507 count = sci_in(port, SCRFDR) & 0x7f; 467 else
508#else
509 count = sci_in(port, SCFDR)&SCIF_RFDC_MASK ;
510#endif
511 } else {
512 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
513 }
514#else
515 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
516#endif 468#endif
469 count = sci_rxroom(port);
517 470
518 /* Don't copy more bytes than there is room for in the buffer */ 471 /* Don't copy more bytes than there is room for in the buffer */
519 count = tty_buffer_request_room(tty, count); 472 count = tty_buffer_request_room(tty, count);
@@ -524,11 +477,10 @@ static inline void sci_receive_chars(struct uart_port *port,
524 477
525 if (port->type == PORT_SCI) { 478 if (port->type == PORT_SCI) {
526 char c = sci_in(port, SCxRDR); 479 char c = sci_in(port, SCxRDR);
527 if(((struct sci_port *)port)->break_flag 480 if (uart_handle_sysrq_char(port, c, regs) || sci_port->break_flag)
528 || uart_handle_sysrq_char(port, c, regs)) {
529 count = 0; 481 count = 0;
530 } else { 482 else {
531 tty_insert_flip_char(tty, c, TTY_NORMAL); 483 tty_insert_flip_char(tty, c, TTY_NORMAL);
532 } 484 }
533 } else { 485 } else {
534 for (i=0; i<count; i++) { 486 for (i=0; i<count; i++) {
@@ -536,15 +488,17 @@ static inline void sci_receive_chars(struct uart_port *port,
536 status = sci_in(port, SCxSR); 488 status = sci_in(port, SCxSR);
537#if defined(CONFIG_CPU_SH3) 489#if defined(CONFIG_CPU_SH3)
538 /* Skip "chars" during break */ 490 /* Skip "chars" during break */
539 if (((struct sci_port *)port)->break_flag) { 491 if (sci_port->break_flag) {
540 if ((c == 0) && 492 if ((c == 0) &&
541 (status & SCxSR_FER(port))) { 493 (status & SCxSR_FER(port))) {
542 count--; i--; 494 count--; i--;
543 continue; 495 continue;
544 } 496 }
497
545 /* Nonzero => end-of-break */ 498 /* Nonzero => end-of-break */
546 pr_debug("scif: debounce<%02x>\n", c); 499 pr_debug("scif: debounce<%02x>\n", c);
547 ((struct sci_port *)port)->break_flag = 0; 500 sci_port->break_flag = 0;
501
548 if (STEPFN(c)) { 502 if (STEPFN(c)) {
549 count--; i--; 503 count--; i--;
550 continue; 504 continue;
@@ -601,15 +555,17 @@ static void sci_schedule_break_timer(struct sci_port *port)
601/* Ensure that two consecutive samples find the break over. */ 555/* Ensure that two consecutive samples find the break over. */
602static void sci_break_timer(unsigned long data) 556static void sci_break_timer(unsigned long data)
603{ 557{
604 struct sci_port * port = (struct sci_port *)data; 558 struct sci_port *port = (struct sci_port *)data;
605 if(sci_rxd_in(&port->port) == 0) { 559
560 if (sci_rxd_in(&port->port) == 0) {
606 port->break_flag = 1; 561 port->break_flag = 1;
607 sci_schedule_break_timer(port); 562 sci_schedule_break_timer(port);
608 } else if(port->break_flag == 1){ 563 } else if (port->break_flag == 1) {
609 /* break is over. */ 564 /* break is over. */
610 port->break_flag = 2; 565 port->break_flag = 2;
611 sci_schedule_break_timer(port); 566 sci_schedule_break_timer(port);
612 } else port->break_flag = 0; 567 } else
568 port->break_flag = 0;
613} 569}
614 570
615static inline int sci_handle_errors(struct uart_port *port) 571static inline int sci_handle_errors(struct uart_port *port)
@@ -618,40 +574,41 @@ static inline int sci_handle_errors(struct uart_port *port)
618 unsigned short status = sci_in(port, SCxSR); 574 unsigned short status = sci_in(port, SCxSR);
619 struct tty_struct *tty = port->info->tty; 575 struct tty_struct *tty = port->info->tty;
620 576
621 if (status&SCxSR_ORER(port)) { 577 if (status & SCxSR_ORER(port)) {
622 /* overrun error */ 578 /* overrun error */
623 if(tty_insert_flip_char(tty, 0, TTY_OVERRUN)) 579 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
624 copied++; 580 copied++;
625 pr_debug("sci: overrun error\n"); 581 pr_debug("sci: overrun error\n");
626 } 582 }
627 583
628 if (status&SCxSR_FER(port)) { 584 if (status & SCxSR_FER(port)) {
629 if (sci_rxd_in(port) == 0) { 585 if (sci_rxd_in(port) == 0) {
630 /* Notify of BREAK */ 586 /* Notify of BREAK */
631 struct sci_port * sci_port = (struct sci_port *)port; 587 struct sci_port *sci_port = (struct sci_port *)port;
632 if(!sci_port->break_flag) { 588
633 sci_port->break_flag = 1; 589 if (!sci_port->break_flag) {
634 sci_schedule_break_timer((struct sci_port *)port); 590 sci_port->break_flag = 1;
591 sci_schedule_break_timer(sci_port);
592
635 /* Do sysrq handling. */ 593 /* Do sysrq handling. */
636 if(uart_handle_break(port)) 594 if (uart_handle_break(port))
637 return 0; 595 return 0;
638 pr_debug("sci: BREAK detected\n"); 596 pr_debug("sci: BREAK detected\n");
639 if(tty_insert_flip_char(tty, 0, TTY_BREAK)) 597 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
640 copied++; 598 copied++;
641 } 599 }
642 } 600 } else {
643 else {
644 /* frame error */ 601 /* frame error */
645 if(tty_insert_flip_char(tty, 0, TTY_FRAME)) 602 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
646 copied++; 603 copied++;
647 pr_debug("sci: frame error\n"); 604 pr_debug("sci: frame error\n");
648 } 605 }
649 } 606 }
650 607
651 if (status&SCxSR_PER(port)) { 608 if (status & SCxSR_PER(port)) {
652 if(tty_insert_flip_char(tty, 0, TTY_PARITY))
653 copied++;
654 /* parity error */ 609 /* parity error */
610 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
611 copied++;
655 pr_debug("sci: parity error\n"); 612 pr_debug("sci: parity error\n");
656 } 613 }
657 614
@@ -674,7 +631,7 @@ static inline int sci_handle_breaks(struct uart_port *port)
674 s->break_flag = 1; 631 s->break_flag = 1;
675#endif 632#endif
676 /* Notify of BREAK */ 633 /* Notify of BREAK */
677 if(tty_insert_flip_char(tty, 0, TTY_BREAK)) 634 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
678 copied++; 635 copied++;
679 pr_debug("sci: BREAK detected\n"); 636 pr_debug("sci: BREAK detected\n");
680 } 637 }
@@ -683,7 +640,7 @@ static inline int sci_handle_breaks(struct uart_port *port)
683 /* XXX: Handle SCIF overrun error */ 640 /* XXX: Handle SCIF overrun error */
684 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) { 641 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
685 sci_out(port, SCLSR, 0); 642 sci_out(port, SCLSR, 0);
686 if(tty_insert_flip_char(tty, 0, TTY_OVERRUN)) { 643 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
687 copied++; 644 copied++;
688 pr_debug("sci: overrun error\n"); 645 pr_debug("sci: overrun error\n");
689 } 646 }
@@ -692,13 +649,12 @@ static inline int sci_handle_breaks(struct uart_port *port)
692 649
693 if (copied) 650 if (copied)
694 tty_flip_buffer_push(tty); 651 tty_flip_buffer_push(tty);
652
695 return copied; 653 return copied;
696} 654}
697 655
698static irqreturn_t sci_rx_interrupt(int irq, void *ptr, struct pt_regs *regs) 656static irqreturn_t sci_rx_interrupt(int irq, void *port, struct pt_regs *regs)
699{ 657{
700 struct uart_port *port = ptr;
701
702 /* I think sci_receive_chars has to be called irrespective 658 /* I think sci_receive_chars has to be called irrespective
703 * of whether the I_IXOFF is set, otherwise, how is the interrupt 659 * of whether the I_IXOFF is set, otherwise, how is the interrupt
704 * to be disabled? 660 * to be disabled?
@@ -712,7 +668,9 @@ static irqreturn_t sci_tx_interrupt(int irq, void *ptr, struct pt_regs *regs)
712{ 668{
713 struct uart_port *port = ptr; 669 struct uart_port *port = ptr;
714 670
671 spin_lock_irq(&port->lock);
715 sci_transmit_chars(port); 672 sci_transmit_chars(port);
673 spin_unlock_irq(&port->lock);
716 674
717 return IRQ_HANDLED; 675 return IRQ_HANDLED;
718} 676}
@@ -756,6 +714,12 @@ static irqreturn_t sci_br_interrupt(int irq, void *ptr, struct pt_regs *regs)
756 714
757 /* Handle BREAKs */ 715 /* Handle BREAKs */
758 sci_handle_breaks(port); 716 sci_handle_breaks(port);
717
718#ifdef CONFIG_SH_KGDB
719 /* Break into the debugger if a break is detected */
720 BREAKPOINT();
721#endif
722
759 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 723 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
760 724
761 return IRQ_HANDLED; 725 return IRQ_HANDLED;
@@ -770,16 +734,16 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr, struct pt_regs *regs)
770 scr_status = sci_in(port,SCSCR); 734 scr_status = sci_in(port,SCSCR);
771 735
772 /* Tx Interrupt */ 736 /* Tx Interrupt */
773 if ((ssr_status&0x0020) && (scr_status&0x0080)) 737 if ((ssr_status & 0x0020) && (scr_status & 0x0080))
774 sci_tx_interrupt(irq, ptr, regs); 738 sci_tx_interrupt(irq, ptr, regs);
775 /* Rx Interrupt */ 739 /* Rx Interrupt */
776 if ((ssr_status&0x0002) && (scr_status&0x0040)) 740 if ((ssr_status & 0x0002) && (scr_status & 0x0040))
777 sci_rx_interrupt(irq, ptr, regs); 741 sci_rx_interrupt(irq, ptr, regs);
778 /* Error Interrupt */ 742 /* Error Interrupt */
779 if ((ssr_status&0x0080) && (scr_status&0x0400)) 743 if ((ssr_status & 0x0080) && (scr_status & 0x0400))
780 sci_er_interrupt(irq, ptr, regs); 744 sci_er_interrupt(irq, ptr, regs);
781 /* Break Interrupt */ 745 /* Break Interrupt */
782 if ((ssr_status&0x0010) && (scr_status&0x0200)) 746 if ((ssr_status & 0x0010) && (scr_status & 0x0200))
783 sci_br_interrupt(irq, ptr, regs); 747 sci_br_interrupt(irq, ptr, regs);
784 748
785 return IRQ_HANDLED; 749 return IRQ_HANDLED;
@@ -790,7 +754,8 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr, struct pt_regs *regs)
790 * Here we define a transistion notifier so that we can update all of our 754 * Here we define a transistion notifier so that we can update all of our
791 * ports' baud rate when the peripheral clock changes. 755 * ports' baud rate when the peripheral clock changes.
792 */ 756 */
793static int sci_notifier(struct notifier_block *self, unsigned long phase, void *p) 757static int sci_notifier(struct notifier_block *self,
758 unsigned long phase, void *p)
794{ 759{
795 struct cpufreq_freqs *freqs = p; 760 struct cpufreq_freqs *freqs = p;
796 int i; 761 int i;
@@ -817,8 +782,9 @@ static int sci_notifier(struct notifier_block *self, unsigned long phase, void *
817 clk_put(clk); 782 clk_put(clk);
818 } 783 }
819 784
820 printk("%s: got a postchange notification for cpu %d (old %d, new %d)\n", 785 printk(KERN_INFO "%s: got a postchange notification "
821 __FUNCTION__, freqs->cpu, freqs->old, freqs->new); 786 "for cpu %d (old %d, new %d)\n",
787 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
822 } 788 }
823 789
824 return NOTIFY_OK; 790 return NOTIFY_OK;
@@ -842,8 +808,9 @@ static int sci_request_irq(struct sci_port *port)
842 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n"); 808 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
843 return -ENODEV; 809 return -ENODEV;
844 } 810 }
845 if (request_irq(port->irqs[0], sci_mpxed_interrupt, SA_INTERRUPT, 811
846 "sci", port)) { 812 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
813 SA_INTERRUPT, "sci", port)) {
847 printk(KERN_ERR "sci: Cannot allocate irq.\n"); 814 printk(KERN_ERR "sci: Cannot allocate irq.\n");
848 return -ENODEV; 815 return -ENODEV;
849 } 816 }
@@ -851,8 +818,8 @@ static int sci_request_irq(struct sci_port *port)
851 for (i = 0; i < ARRAY_SIZE(handlers); i++) { 818 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
852 if (!port->irqs[i]) 819 if (!port->irqs[i])
853 continue; 820 continue;
854 if (request_irq(port->irqs[i], handlers[i], SA_INTERRUPT, 821 if (request_irq(port->irqs[i], handlers[i],
855 desc[i], port)) { 822 SA_INTERRUPT, desc[i], port)) {
856 printk(KERN_ERR "sci: Cannot allocate irq.\n"); 823 printk(KERN_ERR "sci: Cannot allocate irq.\n");
857 return -ENODEV; 824 return -ENODEV;
858 } 825 }
@@ -904,50 +871,42 @@ static unsigned int sci_get_mctrl(struct uart_port *port)
904 871
905static void sci_start_tx(struct uart_port *port) 872static void sci_start_tx(struct uart_port *port)
906{ 873{
907 struct sci_port *s = &sci_ports[port->line]; 874 unsigned short ctrl;
908 875
909 disable_irq(s->irqs[SCIx_TXI_IRQ]); 876 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
910 sci_transmit_chars(port); 877 ctrl = sci_in(port, SCSCR);
911 enable_irq(s->irqs[SCIx_TXI_IRQ]); 878 ctrl |= SCI_CTRL_FLAGS_TIE;
879 sci_out(port, SCSCR, ctrl);
912} 880}
913 881
914static void sci_stop_tx(struct uart_port *port) 882static void sci_stop_tx(struct uart_port *port)
915{ 883{
916 unsigned long flags;
917 unsigned short ctrl; 884 unsigned short ctrl;
918 885
919 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 886 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
920 local_irq_save(flags);
921 ctrl = sci_in(port, SCSCR); 887 ctrl = sci_in(port, SCSCR);
922 ctrl &= ~SCI_CTRL_FLAGS_TIE; 888 ctrl &= ~SCI_CTRL_FLAGS_TIE;
923 sci_out(port, SCSCR, ctrl); 889 sci_out(port, SCSCR, ctrl);
924 local_irq_restore(flags);
925} 890}
926 891
927static void sci_start_rx(struct uart_port *port, unsigned int tty_start) 892static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
928{ 893{
929 unsigned long flags;
930 unsigned short ctrl; 894 unsigned short ctrl;
931 895
932 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ 896 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
933 local_irq_save(flags);
934 ctrl = sci_in(port, SCSCR); 897 ctrl = sci_in(port, SCSCR);
935 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE; 898 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
936 sci_out(port, SCSCR, ctrl); 899 sci_out(port, SCSCR, ctrl);
937 local_irq_restore(flags);
938} 900}
939 901
940static void sci_stop_rx(struct uart_port *port) 902static void sci_stop_rx(struct uart_port *port)
941{ 903{
942 unsigned long flags;
943 unsigned short ctrl; 904 unsigned short ctrl;
944 905
945 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ 906 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
946 local_irq_save(flags);
947 ctrl = sci_in(port, SCSCR); 907 ctrl = sci_in(port, SCSCR);
948 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); 908 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
949 sci_out(port, SCSCR, ctrl); 909 sci_out(port, SCSCR, ctrl);
950 local_irq_restore(flags);
951} 910}
952 911
953static void sci_enable_ms(struct uart_port *port) 912static void sci_enable_ms(struct uart_port *port)
@@ -964,9 +923,8 @@ static int sci_startup(struct uart_port *port)
964{ 923{
965 struct sci_port *s = &sci_ports[port->line]; 924 struct sci_port *s = &sci_ports[port->line];
966 925
967#if defined(__H8300S__) 926 if (s->enable)
968 h8300_sci_enable(port, sci_enable); 927 s->enable(port);
969#endif
970 928
971 sci_request_irq(s); 929 sci_request_irq(s);
972 sci_start_tx(port); 930 sci_start_tx(port);
@@ -983,9 +941,8 @@ static void sci_shutdown(struct uart_port *port)
983 sci_stop_tx(port); 941 sci_stop_tx(port);
984 sci_free_irq(s); 942 sci_free_irq(s);
985 943
986#if defined(__H8300S__) 944 if (s->disable)
987 h8300_sci_enable(port, sci_disable); 945 s->disable(port);
988#endif
989} 946}
990 947
991static void sci_set_termios(struct uart_port *port, struct termios *termios, 948static void sci_set_termios(struct uart_port *port, struct termios *termios,
@@ -998,6 +955,23 @@ static void sci_set_termios(struct uart_port *port, struct termios *termios,
998 955
999 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 956 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1000 957
958 switch (baud) {
959 case 0:
960 t = -1;
961 break;
962 default:
963 {
964#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
965 struct clk *clk = clk_get("module_clk");
966 t = SCBRR_VALUE(baud, clk_get_rate(clk));
967 clk_put(clk);
968#else
969 t = SCBRR_VALUE(baud);
970#endif
971 }
972 break;
973 }
974
1001 spin_lock_irqsave(&port->lock, flags); 975 spin_lock_irqsave(&port->lock, flags);
1002 976
1003 do { 977 do {
@@ -1007,9 +981,8 @@ static void sci_set_termios(struct uart_port *port, struct termios *termios,
1007 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 981 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1008 982
1009#if !defined(SCI_ONLY) 983#if !defined(SCI_ONLY)
1010 if (port->type == PORT_SCIF) { 984 if (port->type == PORT_SCIF)
1011 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 985 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1012 }
1013#endif 986#endif
1014 987
1015 smr_val = sci_in(port, SCSMR) & 3; 988 smr_val = sci_in(port, SCSMR) & 3;
@@ -1026,23 +999,6 @@ static void sci_set_termios(struct uart_port *port, struct termios *termios,
1026 999
1027 sci_out(port, SCSMR, smr_val); 1000 sci_out(port, SCSMR, smr_val);
1028 1001
1029 switch (baud) {
1030 case 0:
1031 t = -1;
1032 break;
1033 default:
1034 {
1035#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1036 struct clk *clk = clk_get("module_clk");
1037 t = SCBRR_VALUE(baud, clk_get_rate(clk));
1038 clk_put(clk);
1039#else
1040 t = SCBRR_VALUE(baud);
1041#endif
1042 }
1043 break;
1044 }
1045
1046 if (t > 0) { 1002 if (t > 0) {
1047 if(t >= 256) { 1003 if(t >= 256) {
1048 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); 1004 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
@@ -1093,11 +1049,23 @@ static void sci_config_port(struct uart_port *port, int flags)
1093 1049
1094 port->type = s->type; 1050 port->type = s->type;
1095 1051
1052 switch (port->type) {
1053 case PORT_SCI:
1054 s->init_pins = sci_init_pins_sci;
1055 break;
1056 case PORT_SCIF:
1057 s->init_pins = sci_init_pins_scif;
1058 break;
1059 case PORT_IRDA:
1060 s->init_pins = sci_init_pins_irda;
1061 break;
1062 }
1063
1096#if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 1064#if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1097 if (port->mapbase == 0) 1065 if (port->mapbase == 0)
1098 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF"); 1066 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1099 1067
1100 port->membase = (void *)port->mapbase; 1068 port->membase = (void __iomem *)port->mapbase;
1101#endif 1069#endif
1102} 1070}
1103 1071
@@ -1133,412 +1101,61 @@ static struct uart_ops sci_uart_ops = {
1133 .verify_port = sci_verify_port, 1101 .verify_port = sci_verify_port,
1134}; 1102};
1135 1103
1136static struct sci_port sci_ports[] = { 1104static void __init sci_init_ports(void)
1137#if defined(CONFIG_CPU_SUBTYPE_SH7708) 1105{
1138 { 1106 static int first = 1;
1139 .port = { 1107 int i;
1140 .membase = (void *)0xfffffe80, 1108
1141 .mapbase = 0xfffffe80, 1109 if (!first)
1142 .iotype = UPIO_MEM, 1110 return;
1143 .irq = 25, 1111
1144 .ops = &sci_uart_ops, 1112 first = 0;
1145 .flags = UPF_BOOT_AUTOCONF, 1113
1146 .line = 0, 1114 for (i = 0; i < SCI_NPORTS; i++) {
1147 }, 1115 sci_ports[i].port.ops = &sci_uart_ops;
1148 .type = PORT_SCI, 1116 sci_ports[i].port.iotype = UPIO_MEM;
1149 .irqs = SCI_IRQS, 1117 sci_ports[i].port.line = i;
1150 }, 1118 sci_ports[i].port.fifosize = 1;
1151#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 1119
1152 { 1120#if defined(__H8300H__) || defined(__H8300S__)
1153 .port = { 1121#ifdef __H8300S__
1154 .membase = (void *)SCIF0, 1122 sci_ports[i].enable = h8300_sci_enable;
1155 .mapbase = SCIF0, 1123 sci_ports[i].disable = h8300_sci_disable;
1156 .iotype = UPIO_MEM, 1124#endif
1157 .irq = 55, 1125 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1158 .ops = &sci_uart_ops, 1126#elif defined(CONFIG_SUPERH64)
1159 .flags = UPF_BOOT_AUTOCONF, 1127 sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
1160 .line = 0,
1161 },
1162 .type = PORT_SCIF,
1163 .irqs = SH3_IRDA_IRQS,
1164 .init_pins = sci_init_pins_scif,
1165 },
1166 {
1167 .port = {
1168 .membase = (void *)SCIF2,
1169 .mapbase = SCIF2,
1170 .iotype = UPIO_MEM,
1171 .irq = 59,
1172 .ops = &sci_uart_ops,
1173 .flags = UPF_BOOT_AUTOCONF,
1174 .line = 1,
1175 },
1176 .type = PORT_SCIF,
1177 .irqs = SH3_SCIF_IRQS,
1178 .init_pins = sci_init_pins_scif,
1179 }
1180#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
1181 {
1182 .port = {
1183 .membase = (void *)0xfffffe80,
1184 .mapbase = 0xfffffe80,
1185 .iotype = UPIO_MEM,
1186 .irq = 25,
1187 .ops = &sci_uart_ops,
1188 .flags = UPF_BOOT_AUTOCONF,
1189 .line = 0,
1190 },
1191 .type = PORT_SCI,
1192 .irqs = SCI_IRQS,
1193 },
1194 {
1195 .port = {
1196 .membase = (void *)0xa4000150,
1197 .mapbase = 0xa4000150,
1198 .iotype = UPIO_MEM,
1199 .irq = 59,
1200 .ops = &sci_uart_ops,
1201 .flags = UPF_BOOT_AUTOCONF,
1202 .line = 1,
1203 },
1204 .type = PORT_SCIF,
1205 .irqs = SH3_SCIF_IRQS,
1206 .init_pins = sci_init_pins_scif,
1207 },
1208 {
1209 .port = {
1210 .membase = (void *)0xa4000140,
1211 .mapbase = 0xa4000140,
1212 .iotype = UPIO_MEM,
1213 .irq = 55,
1214 .ops = &sci_uart_ops,
1215 .flags = UPF_BOOT_AUTOCONF,
1216 .line = 2,
1217 },
1218 .type = PORT_IRDA,
1219 .irqs = SH3_IRDA_IRQS,
1220 .init_pins = sci_init_pins_irda,
1221 }
1222#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
1223 {
1224 .port = {
1225 .membase = (void *)0xA4430000,
1226 .mapbase = 0xA4430000,
1227 .iotype = UPIO_MEM,
1228 .irq = 25,
1229 .ops = &sci_uart_ops,
1230 .flags = UPF_BOOT_AUTOCONF,
1231 .line = 0,
1232 },
1233 .type = PORT_SCIF,
1234 .irqs = SH7300_SCIF0_IRQS,
1235 .init_pins = sci_init_pins_scif,
1236 },
1237#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
1238 {
1239 .port = {
1240 .membase = (void *)0xffe00000,
1241 .mapbase = 0xffe00000,
1242 .iotype = UPIO_MEM,
1243 .irq = 25,
1244 .ops = &sci_uart_ops,
1245 .flags = UPF_BOOT_AUTOCONF,
1246 .line = 0,
1247 },
1248 .type = PORT_SCIF,
1249 .irqs = SH73180_SCIF_IRQS,
1250 .init_pins = sci_init_pins_scif,
1251 },
1252#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1253 {
1254 .port = {
1255 .membase = (void *)0xffe80000,
1256 .mapbase = 0xffe80000,
1257 .iotype = UPIO_MEM,
1258 .irq = 43,
1259 .ops = &sci_uart_ops,
1260 .flags = UPF_BOOT_AUTOCONF,
1261 .line = 0,
1262 },
1263 .type = PORT_SCIF,
1264 .irqs = SH4_SCIF_IRQS,
1265 .init_pins = sci_init_pins_scif,
1266 },
1267#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
1268 {
1269 .port = {
1270 .membase = (void *)0xffe00000,
1271 .mapbase = 0xffe00000,
1272 .iotype = UPIO_MEM,
1273 .irq = 25,
1274 .ops = &sci_uart_ops,
1275 .flags = UPF_BOOT_AUTOCONF,
1276 .line = 0,
1277 },
1278 .type = PORT_SCI,
1279 .irqs = SCI_IRQS,
1280 },
1281 {
1282 .port = {
1283 .membase = (void *)0xffe80000,
1284 .mapbase = 0xffe80000,
1285 .iotype = UPIO_MEM,
1286 .irq = 43,
1287 .ops = &sci_uart_ops,
1288 .flags = UPF_BOOT_AUTOCONF,
1289 .line = 1,
1290 },
1291 .type = PORT_SCIF,
1292 .irqs = SH4_SCIF_IRQS,
1293 .init_pins = sci_init_pins_scif,
1294 },
1295#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
1296 {
1297 .port = {
1298 .membase = (void *)0xfe600000,
1299 .mapbase = 0xfe600000,
1300 .iotype = UPIO_MEM,
1301 .irq = 55,
1302 .ops = &sci_uart_ops,
1303 .flags = UPF_BOOT_AUTOCONF,
1304 .line = 0,
1305 },
1306 .type = PORT_SCIF,
1307 .irqs = SH7760_SCIF0_IRQS,
1308 .init_pins = sci_init_pins_scif,
1309 },
1310 {
1311 .port = {
1312 .membase = (void *)0xfe610000,
1313 .mapbase = 0xfe610000,
1314 .iotype = UPIO_MEM,
1315 .irq = 75,
1316 .ops = &sci_uart_ops,
1317 .flags = UPF_BOOT_AUTOCONF,
1318 .line = 1,
1319 },
1320 .type = PORT_SCIF,
1321 .irqs = SH7760_SCIF1_IRQS,
1322 .init_pins = sci_init_pins_scif,
1323 },
1324 {
1325 .port = {
1326 .membase = (void *)0xfe620000,
1327 .mapbase = 0xfe620000,
1328 .iotype = UPIO_MEM,
1329 .irq = 79,
1330 .ops = &sci_uart_ops,
1331 .flags = UPF_BOOT_AUTOCONF,
1332 .line = 2,
1333 },
1334 .type = PORT_SCIF,
1335 .irqs = SH7760_SCIF2_IRQS,
1336 .init_pins = sci_init_pins_scif,
1337 },
1338#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
1339 {
1340 .port = {
1341 .membase = (void *)0xffe00000,
1342 .mapbase = 0xffe00000,
1343 .iotype = UPIO_MEM,
1344 .irq = 26,
1345 .ops = &sci_uart_ops,
1346 .flags = UPF_BOOT_AUTOCONF,
1347 .line = 0,
1348 },
1349 .type = PORT_SCIF,
1350 .irqs = STB1_SCIF1_IRQS,
1351 .init_pins = sci_init_pins_scif,
1352 },
1353 {
1354 .port = {
1355 .membase = (void *)0xffe80000,
1356 .mapbase = 0xffe80000,
1357 .iotype = UPIO_MEM,
1358 .irq = 43,
1359 .ops = &sci_uart_ops,
1360 .flags = UPF_BOOT_AUTOCONF,
1361 .line = 1,
1362 },
1363 .type = PORT_SCIF,
1364 .irqs = SH4_SCIF_IRQS,
1365 .init_pins = sci_init_pins_scif,
1366 },
1367#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1368 {
1369 .port = {
1370 .iotype = UPIO_MEM,
1371 .irq = 42,
1372 .ops = &sci_uart_ops,
1373 .flags = UPF_BOOT_AUTOCONF,
1374 .line = 0,
1375 },
1376 .type = PORT_SCIF,
1377 .irqs = SH5_SCIF_IRQS,
1378 .init_pins = sci_init_pins_scif,
1379 },
1380#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1381 {
1382 .port = {
1383 .membase = (void *)0x00ffffb0,
1384 .mapbase = 0x00ffffb0,
1385 .iotype = UPIO_MEM,
1386 .irq = 54,
1387 .ops = &sci_uart_ops,
1388 .flags = UPF_BOOT_AUTOCONF,
1389 .line = 0,
1390 },
1391 .type = PORT_SCI,
1392 .irqs = H8300H_SCI_IRQS0,
1393 .init_pins = sci_init_pins_sci,
1394 },
1395 {
1396 .port = {
1397 .membase = (void *)0x00ffffb8,
1398 .mapbase = 0x00ffffb8,
1399 .iotype = UPIO_MEM,
1400 .irq = 58,
1401 .ops = &sci_uart_ops,
1402 .flags = UPF_BOOT_AUTOCONF,
1403 .line = 1,
1404 },
1405 .type = PORT_SCI,
1406 .irqs = H8300H_SCI_IRQS1,
1407 .init_pins = sci_init_pins_sci,
1408 },
1409 {
1410 .port = {
1411 .membase = (void *)0x00ffffc0,
1412 .mapbase = 0x00ffffc0,
1413 .iotype = UPIO_MEM,
1414 .irq = 62,
1415 .ops = &sci_uart_ops,
1416 .flags = UPF_BOOT_AUTOCONF,
1417 .line = 2,
1418 },
1419 .type = PORT_SCI,
1420 .irqs = H8300H_SCI_IRQS2,
1421 .init_pins = sci_init_pins_sci,
1422 },
1423#elif defined(CONFIG_H8S2678)
1424 {
1425 .port = {
1426 .membase = (void *)0x00ffff78,
1427 .mapbase = 0x00ffff78,
1428 .iotype = UPIO_MEM,
1429 .irq = 90,
1430 .ops = &sci_uart_ops,
1431 .flags = UPF_BOOT_AUTOCONF,
1432 .line = 0,
1433 },
1434 .type = PORT_SCI,
1435 .irqs = H8S_SCI_IRQS0,
1436 .init_pins = sci_init_pins_sci,
1437 },
1438 {
1439 .port = {
1440 .membase = (void *)0x00ffff80,
1441 .mapbase = 0x00ffff80,
1442 .iotype = UPIO_MEM,
1443 .irq = 94,
1444 .ops = &sci_uart_ops,
1445 .flags = UPF_BOOT_AUTOCONF,
1446 .line = 1,
1447 },
1448 .type = PORT_SCI,
1449 .irqs = H8S_SCI_IRQS1,
1450 .init_pins = sci_init_pins_sci,
1451 },
1452 {
1453 .port = {
1454 .membase = (void *)0x00ffff88,
1455 .mapbase = 0x00ffff88,
1456 .iotype = UPIO_MEM,
1457 .irq = 98,
1458 .ops = &sci_uart_ops,
1459 .flags = UPF_BOOT_AUTOCONF,
1460 .line = 2,
1461 },
1462 .type = PORT_SCI,
1463 .irqs = H8S_SCI_IRQS2,
1464 .init_pins = sci_init_pins_sci,
1465 },
1466#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
1467 {
1468 .port = {
1469 .membase = (void *)0xff923000,
1470 .mapbase = 0xff923000,
1471 .iotype = UPIO_MEM,
1472 .irq = 61,
1473 .ops = &sci_uart_ops,
1474 .flags = UPF_BOOT_AUTOCONF,
1475 .line = 0,
1476 },
1477 .type = PORT_SCIF,
1478 .irqs = SH7770_SCIF0_IRQS,
1479 .init_pins = sci_init_pins_scif,
1480 },
1481 {
1482 .port = {
1483 .membase = (void *)0xff924000,
1484 .mapbase = 0xff924000,
1485 .iotype = UPIO_MEM,
1486 .irq = 62,
1487 .ops = &sci_uart_ops,
1488 .flags = UPF_BOOT_AUTOCONF,
1489 .line = 1,
1490 },
1491 .type = PORT_SCIF,
1492 .irqs = SH7770_SCIF1_IRQS,
1493 .init_pins = sci_init_pins_scif,
1494 },
1495 {
1496 .port = {
1497 .membase = (void *)0xff925000,
1498 .mapbase = 0xff925000,
1499 .iotype = UPIO_MEM,
1500 .irq = 63,
1501 .ops = &sci_uart_ops,
1502 .flags = UPF_BOOT_AUTOCONF,
1503 .line = 2,
1504 },
1505 .type = PORT_SCIF,
1506 .irqs = SH7770_SCIF2_IRQS,
1507 .init_pins = sci_init_pins_scif,
1508 },
1509#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
1510 {
1511 .port = {
1512 .membase = (void *)0xffe00000,
1513 .mapbase = 0xffe00000,
1514 .iotype = UPIO_MEM,
1515 .irq = 43,
1516 .ops = &sci_uart_ops,
1517 .flags = UPF_BOOT_AUTOCONF,
1518 .line = 0,
1519 },
1520 .type = PORT_SCIF,
1521 .irqs = SH7780_SCIF0_IRQS,
1522 .init_pins = sci_init_pins_scif,
1523 },
1524 {
1525 .port = {
1526 .membase = (void *)0xffe10000,
1527 .mapbase = 0xffe10000,
1528 .iotype = UPIO_MEM,
1529 .irq = 79,
1530 .ops = &sci_uart_ops,
1531 .flags = UPF_BOOT_AUTOCONF,
1532 .line = 1,
1533 },
1534 .type = PORT_SCIF,
1535 .irqs = SH7780_SCIF1_IRQS,
1536 .init_pins = sci_init_pins_scif,
1537 },
1538#else 1128#else
1539#error "CPU subtype not defined" 1129 /*
1130 * XXX: We should use a proper SCI/SCIF clock
1131 */
1132 {
1133 struct clk *clk = clk_get("module_clk");
1134 sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
1135 clk_put(clk);
1136 }
1540#endif 1137#endif
1541}; 1138
1139 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1140 sci_ports[i].break_timer.function = sci_break_timer;
1141
1142 init_timer(&sci_ports[i].break_timer);
1143 }
1144}
1145
1146int __init early_sci_setup(struct uart_port *port)
1147{
1148 if (unlikely(port->line > SCI_NPORTS))
1149 return -ENODEV;
1150
1151 sci_init_ports();
1152
1153 sci_ports[port->line].port.membase = port->membase;
1154 sci_ports[port->line].port.mapbase = port->mapbase;
1155 sci_ports[port->line].port.type = port->type;
1156
1157 return 0;
1158}
1542 1159
1543#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 1160#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1544/* 1161/*
@@ -1560,34 +1177,38 @@ static int __init serial_console_setup(struct console *co, char *options)
1560 int flow = 'n'; 1177 int flow = 'n';
1561 int ret; 1178 int ret;
1562 1179
1180 /*
1181 * Check whether an invalid uart number has been specified, and
1182 * if so, search for the first available port that does have
1183 * console support.
1184 */
1185 if (co->index >= SCI_NPORTS)
1186 co->index = 0;
1187
1563 serial_console_port = &sci_ports[co->index]; 1188 serial_console_port = &sci_ports[co->index];
1564 port = &serial_console_port->port; 1189 port = &serial_console_port->port;
1565 port->type = serial_console_port->type;
1566
1567#ifdef CONFIG_SUPERH64
1568 /* This is especially needed on sh64 to remap the SCIF */
1569 sci_config_port(port, 0);
1570#endif
1571 1190
1572 /* 1191 /*
1573 * We need to set the initial uartclk here, since otherwise it will 1192 * Also need to check port->type, we don't actually have any
1574 * only ever be setup at sci_init() time. 1193 * UPIO_PORT ports, but uart_report_port() handily misreports
1194 * it anyways if we don't have a port available by the time this is
1195 * called.
1575 */ 1196 */
1576#if defined(__H8300H__) || defined(__H8300S__) 1197 if (!port->type)
1577 port->uartclk = CONFIG_CPU_CLOCK; 1198 return -ENODEV;
1199 if (!port->membase || !port->mapbase)
1200 return -ENODEV;
1201
1202 spin_lock_init(&port->lock);
1203
1204 port->type = serial_console_port->type;
1205
1206 if (port->flags & UPF_IOREMAP)
1207 sci_config_port(port, 0);
1208
1209 if (serial_console_port->enable)
1210 serial_console_port->enable(port);
1578 1211
1579#if defined(__H8300S__)
1580 h8300_sci_enable(port, sci_enable);
1581#endif
1582#elif defined(CONFIG_SUPERH64)
1583 port->uartclk = current_cpu_info.module_clock * 16;
1584#else
1585 {
1586 struct clk *clk = clk_get("module_clk");
1587 port->uartclk = clk_get_rate(clk) * 16;
1588 clk_put(clk);
1589 }
1590#endif
1591 if (options) 1212 if (options)
1592 uart_parse_options(options, &baud, &parity, &bits, &flow); 1213 uart_parse_options(options, &baud, &parity, &bits, &flow);
1593 1214
@@ -1605,17 +1226,17 @@ static struct console serial_console = {
1605 .device = uart_console_device, 1226 .device = uart_console_device,
1606 .write = serial_console_write, 1227 .write = serial_console_write,
1607 .setup = serial_console_setup, 1228 .setup = serial_console_setup,
1608 .flags = CON_PRINTBUFFER, 1229 .flags = CON_PRINTBUFFER,
1609 .index = -1, 1230 .index = -1,
1610 .data = &sci_uart_driver, 1231 .data = &sci_uart_driver,
1611}; 1232};
1612 1233
1613static int __init sci_console_init(void) 1234static int __init sci_console_init(void)
1614{ 1235{
1236 sci_init_ports();
1615 register_console(&serial_console); 1237 register_console(&serial_console);
1616 return 0; 1238 return 0;
1617} 1239}
1618
1619console_initcall(sci_console_init); 1240console_initcall(sci_console_init);
1620#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 1241#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1621 1242
@@ -1650,6 +1271,8 @@ int __init kgdb_console_setup(struct console *co, char *options)
1650 int parity = 'n'; 1271 int parity = 'n';
1651 int flow = 'n'; 1272 int flow = 'n';
1652 1273
1274 spin_lock_init(&port->lock);
1275
1653 if (co->index != kgdb_portnum) 1276 if (co->index != kgdb_portnum)
1654 co->index = kgdb_portnum; 1277 co->index = kgdb_portnum;
1655 1278
@@ -1678,10 +1301,10 @@ static struct console kgdb_console = {
1678/* Register the KGDB console so we get messages (d'oh!) */ 1301/* Register the KGDB console so we get messages (d'oh!) */
1679static int __init kgdb_console_init(void) 1302static int __init kgdb_console_init(void)
1680{ 1303{
1304 sci_init_ports();
1681 register_console(&kgdb_console); 1305 register_console(&kgdb_console);
1682 return 0; 1306 return 0;
1683} 1307}
1684
1685console_initcall(kgdb_console_init); 1308console_initcall(kgdb_console_init);
1686#endif /* CONFIG_SH_KGDB_CONSOLE */ 1309#endif /* CONFIG_SH_KGDB_CONSOLE */
1687 1310
@@ -1699,66 +1322,135 @@ static char banner[] __initdata =
1699static struct uart_driver sci_uart_driver = { 1322static struct uart_driver sci_uart_driver = {
1700 .owner = THIS_MODULE, 1323 .owner = THIS_MODULE,
1701 .driver_name = "sci", 1324 .driver_name = "sci",
1702#ifdef CONFIG_DEVFS_FS
1703 .devfs_name = "ttsc/",
1704#endif
1705 .dev_name = "ttySC", 1325 .dev_name = "ttySC",
1706 .major = SCI_MAJOR, 1326 .major = SCI_MAJOR,
1707 .minor = SCI_MINOR_START, 1327 .minor = SCI_MINOR_START,
1328 .nr = SCI_NPORTS,
1708 .cons = SCI_CONSOLE, 1329 .cons = SCI_CONSOLE,
1709}; 1330};
1710 1331
1711static int __init sci_init(void) 1332/*
1333 * Register a set of serial devices attached to a platform device. The
1334 * list is terminated with a zero flags entry, which means we expect
1335 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1336 * remapping (such as sh64) should also set UPF_IOREMAP.
1337 */
1338static int __devinit sci_probe(struct platform_device *dev)
1712{ 1339{
1713 int chan, ret; 1340 struct plat_sci_port *p = dev->dev.platform_data;
1341 int i;
1714 1342
1715 printk("%s", banner); 1343 for (i = 0; p && p->flags != 0 && i < SCI_NPORTS; p++, i++) {
1344 struct sci_port *sciport = &sci_ports[i];
1716 1345
1717 sci_uart_driver.nr = ARRAY_SIZE(sci_ports); 1346 sciport->port.mapbase = p->mapbase;
1718 1347
1719 ret = uart_register_driver(&sci_uart_driver); 1348 /*
1720 if (ret == 0) { 1349 * For the simple (and majority of) cases where we don't need
1721 for (chan = 0; chan < SCI_NPORTS; chan++) { 1350 * to do any remapping, just cast the cookie directly.
1722 struct sci_port *sciport = &sci_ports[chan]; 1351 */
1352 if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
1353 p->membase = (void __iomem *)p->mapbase;
1723 1354
1724#if defined(__H8300H__) || defined(__H8300S__) 1355 sciport->port.membase = p->membase;
1725 sciport->port.uartclk = CONFIG_CPU_CLOCK; 1356
1726#elif defined(CONFIG_SUPERH64) 1357 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1727 sciport->port.uartclk = current_cpu_info.module_clock * 16; 1358 sciport->port.flags = p->flags;
1728#else 1359 sciport->port.dev = &dev->dev;
1729 struct clk *clk = clk_get("module_clk"); 1360
1730 sciport->port.uartclk = clk_get_rate(clk) * 16; 1361 sciport->type = sciport->port.type = p->type;
1731 clk_put(clk); 1362
1732#endif 1363 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1733 uart_add_one_port(&sci_uart_driver, &sciport->port); 1364
1734 sciport->break_timer.data = (unsigned long)sciport; 1365 uart_add_one_port(&sci_uart_driver, &sciport->port);
1735 sciport->break_timer.function = sci_break_timer;
1736 init_timer(&sciport->break_timer);
1737 }
1738 } 1366 }
1739 1367
1740#ifdef CONFIG_CPU_FREQ 1368#ifdef CONFIG_CPU_FREQ
1741 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER); 1369 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1742 printk("sci: CPU frequency notifier registered\n"); 1370 dev_info(&dev->dev, "sci: CPU frequency notifier registered\n");
1743#endif 1371#endif
1744 1372
1745#ifdef CONFIG_SH_STANDARD_BIOS 1373#ifdef CONFIG_SH_STANDARD_BIOS
1746 sh_bios_gdb_detach(); 1374 sh_bios_gdb_detach();
1747#endif 1375#endif
1748 1376
1749 return ret; 1377 return 0;
1750} 1378}
1751 1379
1752static void __exit sci_exit(void) 1380static int __devexit sci_remove(struct platform_device *dev)
1381{
1382 int i;
1383
1384 for (i = 0; i < SCI_NPORTS; i++)
1385 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1386
1387 return 0;
1388}
1389
1390static int sci_suspend(struct platform_device *dev, pm_message_t state)
1391{
1392 int i;
1393
1394 for (i = 0; i < SCI_NPORTS; i++) {
1395 struct sci_port *p = &sci_ports[i];
1396
1397 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1398 uart_suspend_port(&sci_uart_driver, &p->port);
1399 }
1400
1401 return 0;
1402}
1403
1404static int sci_resume(struct platform_device *dev)
1405{
1406 int i;
1407
1408 for (i = 0; i < SCI_NPORTS; i++) {
1409 struct sci_port *p = &sci_ports[i];
1410
1411 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1412 uart_resume_port(&sci_uart_driver, &p->port);
1413 }
1414
1415 return 0;
1416}
1417
1418static struct platform_driver sci_driver = {
1419 .probe = sci_probe,
1420 .remove = __devexit_p(sci_remove),
1421 .suspend = sci_suspend,
1422 .resume = sci_resume,
1423 .driver = {
1424 .name = "sh-sci",
1425 .owner = THIS_MODULE,
1426 },
1427};
1428
1429static int __init sci_init(void)
1753{ 1430{
1754 int chan; 1431 int ret;
1432
1433 printk(banner);
1755 1434
1756 for (chan = 0; chan < SCI_NPORTS; chan++) 1435 sci_init_ports();
1757 uart_remove_one_port(&sci_uart_driver, &sci_ports[chan].port); 1436
1437 ret = uart_register_driver(&sci_uart_driver);
1438 if (likely(ret == 0)) {
1439 ret = platform_driver_register(&sci_driver);
1440 if (unlikely(ret))
1441 uart_unregister_driver(&sci_uart_driver);
1442 }
1758 1443
1444 return ret;
1445}
1446
1447static void __exit sci_exit(void)
1448{
1449 platform_driver_unregister(&sci_driver);
1759 uart_unregister_driver(&sci_uart_driver); 1450 uart_unregister_driver(&sci_uart_driver);
1760} 1451}
1761 1452
1762module_init(sci_init); 1453module_init(sci_init);
1763module_exit(sci_exit); 1454module_exit(sci_exit);
1764 1455
1456MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-14 19:20:04 -0400