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Diffstat (limited to 'drivers/serial/pmac_zilog.h')
-rw-r--r--drivers/serial/pmac_zilog.h34
1 files changed, 24 insertions, 10 deletions
diff --git a/drivers/serial/pmac_zilog.h b/drivers/serial/pmac_zilog.h
index f6e77f12acd5..cbc34fbb1b20 100644
--- a/drivers/serial/pmac_zilog.h
+++ b/drivers/serial/pmac_zilog.h
@@ -1,7 +1,15 @@
1#ifndef __PMAC_ZILOG_H__ 1#ifndef __PMAC_ZILOG_H__
2#define __PMAC_ZILOG_H__ 2#define __PMAC_ZILOG_H__
3 3
4#define pmz_debug(fmt,arg...) dev_dbg(&uap->dev->ofdev.dev, fmt, ## arg) 4#ifdef CONFIG_PPC_PMAC
5#define pmz_debug(fmt, arg...) dev_dbg(&uap->dev->ofdev.dev, fmt, ## arg)
6#define pmz_error(fmt, arg...) dev_err(&uap->dev->ofdev.dev, fmt, ## arg)
7#define pmz_info(fmt, arg...) dev_info(&uap->dev->ofdev.dev, fmt, ## arg)
8#else
9#define pmz_debug(fmt, arg...) dev_dbg(&uap->node->dev, fmt, ## arg)
10#define pmz_error(fmt, arg...) dev_err(&uap->node->dev, fmt, ## arg)
11#define pmz_info(fmt, arg...) dev_info(&uap->node->dev, fmt, ## arg)
12#endif
5 13
6/* 14/*
7 * At most 2 ESCCs with 2 ports each 15 * At most 2 ESCCs with 2 ports each
@@ -17,6 +25,7 @@ struct uart_pmac_port {
17 struct uart_port port; 25 struct uart_port port;
18 struct uart_pmac_port *mate; 26 struct uart_pmac_port *mate;
19 27
28#ifdef CONFIG_PPC_PMAC
20 /* macio_dev for the escc holding this port (maybe be null on 29 /* macio_dev for the escc holding this port (maybe be null on
21 * early inited port) 30 * early inited port)
22 */ 31 */
@@ -25,6 +34,9 @@ struct uart_pmac_port {
25 * of "escc" node (ie. ch-a or ch-b) 34 * of "escc" node (ie. ch-a or ch-b)
26 */ 35 */
27 struct device_node *node; 36 struct device_node *node;
37#else
38 struct platform_device *node;
39#endif
28 40
29 /* Port type as obtained from device tree (IRDA, modem, ...) */ 41 /* Port type as obtained from device tree (IRDA, modem, ...) */
30 int port_type; 42 int port_type;
@@ -55,10 +67,12 @@ struct uart_pmac_port {
55 volatile u8 __iomem *control_reg; 67 volatile u8 __iomem *control_reg;
56 volatile u8 __iomem *data_reg; 68 volatile u8 __iomem *data_reg;
57 69
70#ifdef CONFIG_PPC_PMAC
58 unsigned int tx_dma_irq; 71 unsigned int tx_dma_irq;
59 unsigned int rx_dma_irq; 72 unsigned int rx_dma_irq;
60 volatile struct dbdma_regs __iomem *tx_dma_regs; 73 volatile struct dbdma_regs __iomem *tx_dma_regs;
61 volatile struct dbdma_regs __iomem *rx_dma_regs; 74 volatile struct dbdma_regs __iomem *rx_dma_regs;
75#endif
62 76
63 struct ktermios termios_cache; 77 struct ktermios termios_cache;
64}; 78};
@@ -113,7 +127,7 @@ static inline void zssync(struct uart_pmac_port *port)
113#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) 127#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
114#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) 128#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
115 129
116#define ZS_CLOCK 3686400 /* Z8530 RTxC input clock rate */ 130#define ZS_CLOCK 3686400 /* Z8530 RTxC input clock rate */
117 131
118/* The Zilog register set */ 132/* The Zilog register set */
119 133
@@ -171,7 +185,7 @@ static inline void zssync(struct uart_pmac_port *port)
171 185
172/* Write Register 3 */ 186/* Write Register 3 */
173 187
174#define RxENABLE 0x1 /* Rx Enable */ 188#define RxENABLE 0x1 /* Rx Enable */
175#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */ 189#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
176#define ADD_SM 0x4 /* Address Search Mode (SDLC) */ 190#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
177#define RxCRC_ENAB 0x8 /* Rx CRC Enable */ 191#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
@@ -185,7 +199,7 @@ static inline void zssync(struct uart_pmac_port *port)
185 199
186/* Write Register 4 */ 200/* Write Register 4 */
187 201
188#define PAR_ENAB 0x1 /* Parity Enable */ 202#define PAR_ENAB 0x1 /* Parity Enable */
189#define PAR_EVEN 0x2 /* Parity Even/Odd* */ 203#define PAR_EVEN 0x2 /* Parity Even/Odd* */
190 204
191#define SYNC_ENAB 0 /* Sync Modes Enable */ 205#define SYNC_ENAB 0 /* Sync Modes Enable */
@@ -210,7 +224,7 @@ static inline void zssync(struct uart_pmac_port *port)
210#define TxCRC_ENAB 0x1 /* Tx CRC Enable */ 224#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
211#define RTS 0x2 /* RTS */ 225#define RTS 0x2 /* RTS */
212#define SDLC_CRC 0x4 /* SDLC/CRC-16 */ 226#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
213#define TxENABLE 0x8 /* Tx Enable */ 227#define TxENABLE 0x8 /* Tx Enable */
214#define SND_BRK 0x10 /* Send Break */ 228#define SND_BRK 0x10 /* Send Break */
215#define Tx5 0x0 /* Tx 5 bits (or less)/character */ 229#define Tx5 0x0 /* Tx 5 bits (or less)/character */
216#define Tx7 0x20 /* Tx 7 bits/character */ 230#define Tx7 0x20 /* Tx 7 bits/character */
@@ -372,11 +386,11 @@ static inline void zssync(struct uart_pmac_port *port)
372#define ZS_TX_ACTIVE(UP) ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE) 386#define ZS_TX_ACTIVE(UP) ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
373#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS) 387#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
374#define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA) 388#define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
375#define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM) 389#define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
376#define ZS_HAS_DMA(UP) ((UP)->flags & PMACZILOG_FLAG_HAS_DMA) 390#define ZS_HAS_DMA(UP) ((UP)->flags & PMACZILOG_FLAG_HAS_DMA)
377#define ZS_IS_ASLEEP(UP) ((UP)->flags & PMACZILOG_FLAG_IS_ASLEEP) 391#define ZS_IS_ASLEEP(UP) ((UP)->flags & PMACZILOG_FLAG_IS_ASLEEP)
378#define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN) 392#define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
379#define ZS_IS_IRQ_ON(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRQ_ON) 393#define ZS_IS_IRQ_ON(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRQ_ON)
380#define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK) 394#define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)
381 395
382#endif /* __PMAC_ZILOG_H__ */ 396#endif /* __PMAC_ZILOG_H__ */