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-rw-r--r--drivers/serial/mfd.c47
1 files changed, 33 insertions, 14 deletions
diff --git a/drivers/serial/mfd.c b/drivers/serial/mfd.c
index dc0967fb9ea6..5fc699e929dc 100644
--- a/drivers/serial/mfd.c
+++ b/drivers/serial/mfd.c
@@ -172,6 +172,9 @@ static ssize_t port_show_regs(struct file *file, char __user *user_buf,
172 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 172 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
173 "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV)); 173 "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
174 174
175 if (len > HSU_REGS_BUFSIZE)
176 len = HSU_REGS_BUFSIZE;
177
175 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 178 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
176 kfree(buf); 179 kfree(buf);
177 return ret; 180 return ret;
@@ -219,6 +222,9 @@ static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
219 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 222 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
220 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR)); 223 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
221 224
225 if (len > HSU_REGS_BUFSIZE)
226 len = HSU_REGS_BUFSIZE;
227
222 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 228 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
223 kfree(buf); 229 kfree(buf);
224 return ret; 230 return ret;
@@ -925,39 +931,52 @@ serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
925 cval |= UART_LCR_EPAR; 931 cval |= UART_LCR_EPAR;
926 932
927 /* 933 /*
934 * The base clk is 50Mhz, and the baud rate come from:
935 * baud = 50M * MUL / (DIV * PS * DLAB)
936 *
928 * For those basic low baud rate we can get the direct 937 * For those basic low baud rate we can get the direct
929 * scalar from 2746800, like 115200 = 2746800/24, for those 938 * scalar from 2746800, like 115200 = 2746800/24. For those
930 * higher baud rate, we have to handle them case by case, 939 * higher baud rate, we handle them case by case, mainly by
931 * but DIV reg is never touched as its default value 0x3d09 940 * adjusting the MUL/PS registers, and DIV register is kept
941 * as default value 0x3d09 to make things simple
932 */ 942 */
933 baud = uart_get_baud_rate(port, termios, old, 0, 4000000); 943 baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
934 quot = uart_get_divisor(port, baud);
935 944
945 quot = 1;
936 switch (baud) { 946 switch (baud) {
937 case 3500000: 947 case 3500000:
938 mul = 0x3345; 948 mul = 0x3345;
939 ps = 0xC; 949 ps = 0xC;
940 quot = 1; 950 break;
951 case 3000000:
952 mul = 0x2EE0;
941 break; 953 break;
942 case 2500000: 954 case 2500000:
943 mul = 0x2710; 955 mul = 0x2710;
944 ps = 0x10;
945 quot = 1;
946 break; 956 break;
947 case 18432000: 957 case 2000000:
958 mul = 0x1F40;
959 break;
960 case 1843200:
948 mul = 0x2400; 961 mul = 0x2400;
949 ps = 0x10;
950 quot = 1;
951 break; 962 break;
952 case 1500000: 963 case 1500000:
953 mul = 0x1D4C; 964 mul = 0x1770;
954 ps = 0xc; 965 break;
955 quot = 1; 966 case 1000000:
967 mul = 0xFA0;
968 break;
969 case 500000:
970 mul = 0x7D0;
956 break; 971 break;
957 default: 972 default:
958 ; 973 /* Use uart_get_divisor to get quot for other baud rates */
974 quot = 0;
959 } 975 }
960 976
977 if (!quot)
978 quot = uart_get_divisor(port, baud);
979
961 if ((up->port.uartclk / quot) < (2400 * 16)) 980 if ((up->port.uartclk / quot) < (2400 * 16))
962 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B; 981 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
963 else if ((up->port.uartclk / quot) < (230400 * 16)) 982 else if ((up->port.uartclk / quot) < (230400 * 16))