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Diffstat (limited to 'drivers/serial/imx.c')
-rw-r--r--drivers/serial/imx.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
index 3f90f1bbbbcd..a50954612b60 100644
--- a/drivers/serial/imx.c
+++ b/drivers/serial/imx.c
@@ -66,7 +66,7 @@
66#define ONEMS 0xb0 /* One Millisecond register */ 66#define ONEMS 0xb0 /* One Millisecond register */
67#define UTS 0xb4 /* UART Test Register */ 67#define UTS 0xb4 /* UART Test Register */
68#endif 68#endif
69#ifdef CONFIG_ARCH_IMX 69#if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
70#define BIPR1 0xb0 /* Incremental Preset Register 1 */ 70#define BIPR1 0xb0 /* Incremental Preset Register 1 */
71#define BIPR2 0xb4 /* Incremental Preset Register 2 */ 71#define BIPR2 0xb4 /* Incremental Preset Register 2 */
72#define BIPR3 0xb8 /* Incremental Preset Register 3 */ 72#define BIPR3 0xb8 /* Incremental Preset Register 3 */
@@ -96,7 +96,7 @@
96#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 96#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
97#define UCR1_SNDBRK (1<<4) /* Send break */ 97#define UCR1_SNDBRK (1<<4) /* Send break */
98#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 98#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
99#ifdef CONFIG_ARCH_IMX 99#if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
100#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ 100#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
101#endif 101#endif
102#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 102#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
@@ -187,11 +187,11 @@
187#define MAX_INTERNAL_IRQ IMX_IRQS 187#define MAX_INTERNAL_IRQ IMX_IRQS
188#endif 188#endif
189 189
190#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 190#ifdef CONFIG_ARCH_MXC
191#define SERIAL_IMX_MAJOR 207 191#define SERIAL_IMX_MAJOR 207
192#define MINOR_START 16 192#define MINOR_START 16
193#define DEV_NAME "ttymxc" 193#define DEV_NAME "ttymxc"
194#define MAX_INTERNAL_IRQ MXC_MAX_INT_LINES 194#define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
195#endif 195#endif
196 196
197/* 197/*