diff options
Diffstat (limited to 'drivers/serial/imx.c')
-rw-r--r-- | drivers/serial/imx.c | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c index 7b5d1de9cfe3..285b414f3054 100644 --- a/drivers/serial/imx.c +++ b/drivers/serial/imx.c | |||
@@ -71,7 +71,7 @@ | |||
71 | #define ONEMS 0xb0 /* One Millisecond register */ | 71 | #define ONEMS 0xb0 /* One Millisecond register */ |
72 | #define UTS 0xb4 /* UART Test Register */ | 72 | #define UTS 0xb4 /* UART Test Register */ |
73 | #endif | 73 | #endif |
74 | #if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1) | 74 | #ifdef CONFIG_ARCH_MX1 |
75 | #define BIPR1 0xb0 /* Incremental Preset Register 1 */ | 75 | #define BIPR1 0xb0 /* Incremental Preset Register 1 */ |
76 | #define BIPR2 0xb4 /* Incremental Preset Register 2 */ | 76 | #define BIPR2 0xb4 /* Incremental Preset Register 2 */ |
77 | #define BIPR3 0xb8 /* Incremental Preset Register 3 */ | 77 | #define BIPR3 0xb8 /* Incremental Preset Register 3 */ |
@@ -101,7 +101,7 @@ | |||
101 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ | 101 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ |
102 | #define UCR1_SNDBRK (1<<4) /* Send break */ | 102 | #define UCR1_SNDBRK (1<<4) /* Send break */ |
103 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ | 103 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ |
104 | #if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1) | 104 | #ifdef CONFIG_ARCH_MX1 |
105 | #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ | 105 | #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ |
106 | #endif | 106 | #endif |
107 | #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 | 107 | #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 |
@@ -132,7 +132,7 @@ | |||
132 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ | 132 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ |
133 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ | 133 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ |
134 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ | 134 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ |
135 | #ifdef CONFIG_ARCH_IMX | 135 | #ifdef CONFIG_ARCH_MX1 |
136 | #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */ | 136 | #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */ |
137 | #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */ | 137 | #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */ |
138 | #endif | 138 | #endif |
@@ -186,13 +186,6 @@ | |||
186 | #define UTS_SOFTRST (1<<0) /* Software reset */ | 186 | #define UTS_SOFTRST (1<<0) /* Software reset */ |
187 | 187 | ||
188 | /* We've been assigned a range on the "Low-density serial ports" major */ | 188 | /* We've been assigned a range on the "Low-density serial ports" major */ |
189 | #ifdef CONFIG_ARCH_IMX | ||
190 | #define SERIAL_IMX_MAJOR 204 | ||
191 | #define MINOR_START 41 | ||
192 | #define DEV_NAME "ttySMX" | ||
193 | #define MAX_INTERNAL_IRQ IMX_IRQS | ||
194 | #endif | ||
195 | |||
196 | #ifdef CONFIG_ARCH_MXC | 189 | #ifdef CONFIG_ARCH_MXC |
197 | #define SERIAL_IMX_MAJOR 207 | 190 | #define SERIAL_IMX_MAJOR 207 |
198 | #define MINOR_START 16 | 191 | #define MINOR_START 16 |