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-rw-r--r--drivers/serial/8250_pci.c412
1 files changed, 412 insertions, 0 deletions
diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
index 533f82025adf..7ddff3f55087 100644
--- a/drivers/serial/8250_pci.c
+++ b/drivers/serial/8250_pci.c
@@ -306,6 +306,63 @@ static void __devexit pci_plx9050_exit(struct pci_dev *dev)
306 } 306 }
307} 307}
308 308
309#define NI8420_INT_ENABLE_REG 0x38
310#define NI8420_INT_ENABLE_BIT 0x2000
311
312static void __devexit pci_ni8420_exit(struct pci_dev *dev)
313{
314 void __iomem *p;
315 unsigned long base, len;
316 unsigned int bar = 0;
317
318 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
319 moan_device("no memory in bar", dev);
320 return;
321 }
322
323 base = pci_resource_start(dev, bar);
324 len = pci_resource_len(dev, bar);
325 p = ioremap_nocache(base, len);
326 if (p == NULL)
327 return;
328
329 /* Disable the CPU Interrupt */
330 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
331 p + NI8420_INT_ENABLE_REG);
332 iounmap(p);
333}
334
335
336/* MITE registers */
337#define MITE_IOWBSR1 0xc4
338#define MITE_IOWCR1 0xf4
339#define MITE_LCIMR1 0x08
340#define MITE_LCIMR2 0x10
341
342#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
343
344static void __devexit pci_ni8430_exit(struct pci_dev *dev)
345{
346 void __iomem *p;
347 unsigned long base, len;
348 unsigned int bar = 0;
349
350 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
351 moan_device("no memory in bar", dev);
352 return;
353 }
354
355 base = pci_resource_start(dev, bar);
356 len = pci_resource_len(dev, bar);
357 p = ioremap_nocache(base, len);
358 if (p == NULL)
359 return;
360
361 /* Disable the CPU Interrupt */
362 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
363 iounmap(p);
364}
365
309/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 366/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
310static int 367static int
311sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 368sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
@@ -597,6 +654,108 @@ static int pci_xircom_init(struct pci_dev *dev)
597 return 0; 654 return 0;
598} 655}
599 656
657static int pci_ni8420_init(struct pci_dev *dev)
658{
659 void __iomem *p;
660 unsigned long base, len;
661 unsigned int bar = 0;
662
663 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
664 moan_device("no memory in bar", dev);
665 return 0;
666 }
667
668 base = pci_resource_start(dev, bar);
669 len = pci_resource_len(dev, bar);
670 p = ioremap_nocache(base, len);
671 if (p == NULL)
672 return -ENOMEM;
673
674 /* Enable CPU Interrupt */
675 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
676 p + NI8420_INT_ENABLE_REG);
677
678 iounmap(p);
679 return 0;
680}
681
682#define MITE_IOWBSR1_WSIZE 0xa
683#define MITE_IOWBSR1_WIN_OFFSET 0x800
684#define MITE_IOWBSR1_WENAB (1 << 7)
685#define MITE_LCIMR1_IO_IE_0 (1 << 24)
686#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
687#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
688
689static int pci_ni8430_init(struct pci_dev *dev)
690{
691 void __iomem *p;
692 unsigned long base, len;
693 u32 device_window;
694 unsigned int bar = 0;
695
696 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
697 moan_device("no memory in bar", dev);
698 return 0;
699 }
700
701 base = pci_resource_start(dev, bar);
702 len = pci_resource_len(dev, bar);
703 p = ioremap_nocache(base, len);
704 if (p == NULL)
705 return -ENOMEM;
706
707 /* Set device window address and size in BAR0 */
708 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
709 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
710 writel(device_window, p + MITE_IOWBSR1);
711
712 /* Set window access to go to RAMSEL IO address space */
713 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
714 p + MITE_IOWCR1);
715
716 /* Enable IO Bus Interrupt 0 */
717 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
718
719 /* Enable CPU Interrupt */
720 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
721
722 iounmap(p);
723 return 0;
724}
725
726/* UART Port Control Register */
727#define NI8430_PORTCON 0x0f
728#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
729
730static int
731pci_ni8430_setup(struct serial_private *priv,
732 const struct pciserial_board *board,
733 struct uart_port *port, int idx)
734{
735 void __iomem *p;
736 unsigned long base, len;
737 unsigned int bar, offset = board->first_offset;
738
739 if (idx >= board->num_ports)
740 return 1;
741
742 bar = FL_GET_BASE(board->flags);
743 offset += idx * board->uart_offset;
744
745 base = pci_resource_start(priv->dev, bar);
746 len = pci_resource_len(priv->dev, bar);
747 p = ioremap_nocache(base, len);
748
749 /* enable the transciever */
750 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
751 p + offset + NI8430_PORTCON);
752
753 iounmap(p);
754
755 return setup_port(priv, port, bar, offset, board->reg_shift);
756}
757
758
600static int pci_netmos_init(struct pci_dev *dev) 759static int pci_netmos_init(struct pci_dev *dev)
601{ 760{
602 /* subdevice 0x00PS means <P> parallel, <S> serial */ 761 /* subdevice 0x00PS means <P> parallel, <S> serial */
@@ -913,6 +1072,126 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
913 .exit = __devexit_p(pci_ite887x_exit), 1072 .exit = __devexit_p(pci_ite887x_exit),
914 }, 1073 },
915 /* 1074 /*
1075 * National Instruments
1076 */
1077 {
1078 .vendor = PCI_VENDOR_ID_NI,
1079 .device = PCI_DEVICE_ID_NI_PCI23216,
1080 .subvendor = PCI_ANY_ID,
1081 .subdevice = PCI_ANY_ID,
1082 .init = pci_ni8420_init,
1083 .setup = pci_default_setup,
1084 .exit = __devexit_p(pci_ni8420_exit),
1085 },
1086 {
1087 .vendor = PCI_VENDOR_ID_NI,
1088 .device = PCI_DEVICE_ID_NI_PCI2328,
1089 .subvendor = PCI_ANY_ID,
1090 .subdevice = PCI_ANY_ID,
1091 .init = pci_ni8420_init,
1092 .setup = pci_default_setup,
1093 .exit = __devexit_p(pci_ni8420_exit),
1094 },
1095 {
1096 .vendor = PCI_VENDOR_ID_NI,
1097 .device = PCI_DEVICE_ID_NI_PCI2324,
1098 .subvendor = PCI_ANY_ID,
1099 .subdevice = PCI_ANY_ID,
1100 .init = pci_ni8420_init,
1101 .setup = pci_default_setup,
1102 .exit = __devexit_p(pci_ni8420_exit),
1103 },
1104 {
1105 .vendor = PCI_VENDOR_ID_NI,
1106 .device = PCI_DEVICE_ID_NI_PCI2322,
1107 .subvendor = PCI_ANY_ID,
1108 .subdevice = PCI_ANY_ID,
1109 .init = pci_ni8420_init,
1110 .setup = pci_default_setup,
1111 .exit = __devexit_p(pci_ni8420_exit),
1112 },
1113 {
1114 .vendor = PCI_VENDOR_ID_NI,
1115 .device = PCI_DEVICE_ID_NI_PCI2324I,
1116 .subvendor = PCI_ANY_ID,
1117 .subdevice = PCI_ANY_ID,
1118 .init = pci_ni8420_init,
1119 .setup = pci_default_setup,
1120 .exit = __devexit_p(pci_ni8420_exit),
1121 },
1122 {
1123 .vendor = PCI_VENDOR_ID_NI,
1124 .device = PCI_DEVICE_ID_NI_PCI2322I,
1125 .subvendor = PCI_ANY_ID,
1126 .subdevice = PCI_ANY_ID,
1127 .init = pci_ni8420_init,
1128 .setup = pci_default_setup,
1129 .exit = __devexit_p(pci_ni8420_exit),
1130 },
1131 {
1132 .vendor = PCI_VENDOR_ID_NI,
1133 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1134 .subvendor = PCI_ANY_ID,
1135 .subdevice = PCI_ANY_ID,
1136 .init = pci_ni8420_init,
1137 .setup = pci_default_setup,
1138 .exit = __devexit_p(pci_ni8420_exit),
1139 },
1140 {
1141 .vendor = PCI_VENDOR_ID_NI,
1142 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1143 .subvendor = PCI_ANY_ID,
1144 .subdevice = PCI_ANY_ID,
1145 .init = pci_ni8420_init,
1146 .setup = pci_default_setup,
1147 .exit = __devexit_p(pci_ni8420_exit),
1148 },
1149 {
1150 .vendor = PCI_VENDOR_ID_NI,
1151 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1152 .subvendor = PCI_ANY_ID,
1153 .subdevice = PCI_ANY_ID,
1154 .init = pci_ni8420_init,
1155 .setup = pci_default_setup,
1156 .exit = __devexit_p(pci_ni8420_exit),
1157 },
1158 {
1159 .vendor = PCI_VENDOR_ID_NI,
1160 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1161 .subvendor = PCI_ANY_ID,
1162 .subdevice = PCI_ANY_ID,
1163 .init = pci_ni8420_init,
1164 .setup = pci_default_setup,
1165 .exit = __devexit_p(pci_ni8420_exit),
1166 },
1167 {
1168 .vendor = PCI_VENDOR_ID_NI,
1169 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1170 .subvendor = PCI_ANY_ID,
1171 .subdevice = PCI_ANY_ID,
1172 .init = pci_ni8420_init,
1173 .setup = pci_default_setup,
1174 .exit = __devexit_p(pci_ni8420_exit),
1175 },
1176 {
1177 .vendor = PCI_VENDOR_ID_NI,
1178 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1179 .subvendor = PCI_ANY_ID,
1180 .subdevice = PCI_ANY_ID,
1181 .init = pci_ni8420_init,
1182 .setup = pci_default_setup,
1183 .exit = __devexit_p(pci_ni8420_exit),
1184 },
1185 {
1186 .vendor = PCI_VENDOR_ID_NI,
1187 .device = PCI_ANY_ID,
1188 .subvendor = PCI_ANY_ID,
1189 .subdevice = PCI_ANY_ID,
1190 .init = pci_ni8430_init,
1191 .setup = pci_ni8430_setup,
1192 .exit = __devexit_p(pci_ni8430_exit),
1193 },
1194 /*
916 * Panacom 1195 * Panacom
917 */ 1196 */
918 { 1197 {
@@ -1216,6 +1495,7 @@ enum pci_board_num_t {
1216 pbn_b1_2_115200, 1495 pbn_b1_2_115200,
1217 pbn_b1_4_115200, 1496 pbn_b1_4_115200,
1218 pbn_b1_8_115200, 1497 pbn_b1_8_115200,
1498 pbn_b1_16_115200,
1219 1499
1220 pbn_b1_1_921600, 1500 pbn_b1_1_921600,
1221 pbn_b1_2_921600, 1501 pbn_b1_2_921600,
@@ -1225,6 +1505,9 @@ enum pci_board_num_t {
1225 pbn_b1_2_1250000, 1505 pbn_b1_2_1250000,
1226 1506
1227 pbn_b1_bt_1_115200, 1507 pbn_b1_bt_1_115200,
1508 pbn_b1_bt_2_115200,
1509 pbn_b1_bt_4_115200,
1510
1228 pbn_b1_bt_2_921600, 1511 pbn_b1_bt_2_921600,
1229 1512
1230 pbn_b1_1_1382400, 1513 pbn_b1_1_1382400,
@@ -1280,6 +1563,10 @@ enum pci_board_num_t {
1280 pbn_exar_XR17C154, 1563 pbn_exar_XR17C154,
1281 pbn_exar_XR17C158, 1564 pbn_exar_XR17C158,
1282 pbn_pasemi_1682M, 1565 pbn_pasemi_1682M,
1566 pbn_ni8430_2,
1567 pbn_ni8430_4,
1568 pbn_ni8430_8,
1569 pbn_ni8430_16,
1283}; 1570};
1284 1571
1285/* 1572/*
@@ -1487,6 +1774,12 @@ static struct pciserial_board pci_boards[] __devinitdata = {
1487 .base_baud = 115200, 1774 .base_baud = 115200,
1488 .uart_offset = 8, 1775 .uart_offset = 8,
1489 }, 1776 },
1777 [pbn_b1_16_115200] = {
1778 .flags = FL_BASE1,
1779 .num_ports = 16,
1780 .base_baud = 115200,
1781 .uart_offset = 8,
1782 },
1490 1783
1491 [pbn_b1_1_921600] = { 1784 [pbn_b1_1_921600] = {
1492 .flags = FL_BASE1, 1785 .flags = FL_BASE1,
@@ -1525,6 +1818,18 @@ static struct pciserial_board pci_boards[] __devinitdata = {
1525 .base_baud = 115200, 1818 .base_baud = 115200,
1526 .uart_offset = 8, 1819 .uart_offset = 8,
1527 }, 1820 },
1821 [pbn_b1_bt_2_115200] = {
1822 .flags = FL_BASE1|FL_BASE_BARS,
1823 .num_ports = 2,
1824 .base_baud = 115200,
1825 .uart_offset = 8,
1826 },
1827 [pbn_b1_bt_4_115200] = {
1828 .flags = FL_BASE1|FL_BASE_BARS,
1829 .num_ports = 4,
1830 .base_baud = 115200,
1831 .uart_offset = 8,
1832 },
1528 1833
1529 [pbn_b1_bt_2_921600] = { 1834 [pbn_b1_bt_2_921600] = {
1530 .flags = FL_BASE1|FL_BASE_BARS, 1835 .flags = FL_BASE1|FL_BASE_BARS,
@@ -1850,6 +2155,37 @@ static struct pciserial_board pci_boards[] __devinitdata = {
1850 .num_ports = 1, 2155 .num_ports = 1,
1851 .base_baud = 8333333, 2156 .base_baud = 8333333,
1852 }, 2157 },
2158 /*
2159 * National Instruments 843x
2160 */
2161 [pbn_ni8430_16] = {
2162 .flags = FL_BASE0,
2163 .num_ports = 16,
2164 .base_baud = 3686400,
2165 .uart_offset = 0x10,
2166 .first_offset = 0x800,
2167 },
2168 [pbn_ni8430_8] = {
2169 .flags = FL_BASE0,
2170 .num_ports = 8,
2171 .base_baud = 3686400,
2172 .uart_offset = 0x10,
2173 .first_offset = 0x800,
2174 },
2175 [pbn_ni8430_4] = {
2176 .flags = FL_BASE0,
2177 .num_ports = 4,
2178 .base_baud = 3686400,
2179 .uart_offset = 0x10,
2180 .first_offset = 0x800,
2181 },
2182 [pbn_ni8430_2] = {
2183 .flags = FL_BASE0,
2184 .num_ports = 2,
2185 .base_baud = 3686400,
2186 .uart_offset = 0x10,
2187 .first_offset = 0x800,
2188 },
1853}; 2189};
1854 2190
1855static const struct pci_device_id softmodem_blacklist[] = { 2191static const struct pci_device_id softmodem_blacklist[] = {
@@ -3052,6 +3388,82 @@ static struct pci_device_id serial_pci_tbl[] = {
3052 pbn_pasemi_1682M }, 3388 pbn_pasemi_1682M },
3053 3389
3054 /* 3390 /*
3391 * National Instruments
3392 */
3393 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3395 pbn_b1_16_115200 },
3396 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3398 pbn_b1_8_115200 },
3399 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3401 pbn_b1_bt_4_115200 },
3402 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3404 pbn_b1_bt_2_115200 },
3405 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3407 pbn_b1_bt_4_115200 },
3408 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3410 pbn_b1_bt_2_115200 },
3411 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3413 pbn_b1_16_115200 },
3414 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3416 pbn_b1_8_115200 },
3417 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3419 pbn_b1_bt_4_115200 },
3420 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3422 pbn_b1_bt_2_115200 },
3423 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3425 pbn_b1_bt_4_115200 },
3426 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3428 pbn_b1_bt_2_115200 },
3429 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3431 pbn_ni8430_2 },
3432 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3434 pbn_ni8430_2 },
3435 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3437 pbn_ni8430_4 },
3438 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3440 pbn_ni8430_4 },
3441 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3443 pbn_ni8430_8 },
3444 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3446 pbn_ni8430_8 },
3447 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3449 pbn_ni8430_16 },
3450 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3452 pbn_ni8430_16 },
3453 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3455 pbn_ni8430_2 },
3456 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3458 pbn_ni8430_2 },
3459 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3461 pbn_ni8430_4 },
3462 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3464 pbn_ni8430_4 },
3465
3466 /*
3055 * ADDI-DATA GmbH communication cards <info@addi-data.com> 3467 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3056 */ 3468 */
3057 { PCI_VENDOR_ID_ADDIDATA, 3469 { PCI_VENDOR_ID_ADDIDATA,
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-22 15:07:13 -0500