aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/serial/8250.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/serial/8250.c')
-rw-r--r--drivers/serial/8250.c2632
1 files changed, 2632 insertions, 0 deletions
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
new file mode 100644
index 000000000000..201c3b9924f4
--- /dev/null
+++ b/drivers/serial/8250.c
@@ -0,0 +1,2632 @@
1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22#include <linux/config.h>
23
24#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/ioport.h>
31#include <linux/init.h>
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/mca.h>
35#include <linux/delay.h>
36#include <linux/device.h>
37#include <linux/tty.h>
38#include <linux/tty_flip.h>
39#include <linux/serial_reg.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/serial_8250.h>
43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
49/*
50 * Configuration:
51 * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option
52 * is unsafe when used on edge-triggered interrupts.
53 */
54unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
55
56/*
57 * Debugging.
58 */
59#if 0
60#define DEBUG_AUTOCONF(fmt...) printk(fmt)
61#else
62#define DEBUG_AUTOCONF(fmt...) do { } while (0)
63#endif
64
65#if 0
66#define DEBUG_INTR(fmt...) printk(fmt)
67#else
68#define DEBUG_INTR(fmt...) do { } while (0)
69#endif
70
71#define PASS_LIMIT 256
72
73/*
74 * We default to IRQ0 for the "no irq" hack. Some
75 * machine types want others as well - they're free
76 * to redefine this in their header file.
77 */
78#define is_real_interrupt(irq) ((irq) != 0)
79
80/*
81 * This converts from our new CONFIG_ symbols to the symbols
82 * that asm/serial.h expects. You _NEED_ to comment out the
83 * linux/config.h include contained inside asm/serial.h for
84 * this to work.
85 */
86#undef CONFIG_SERIAL_MANY_PORTS
87#undef CONFIG_SERIAL_DETECT_IRQ
88#undef CONFIG_SERIAL_MULTIPORT
89#undef CONFIG_HUB6
90
91#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
92#define CONFIG_SERIAL_DETECT_IRQ 1
93#endif
94#ifdef CONFIG_SERIAL_8250_MULTIPORT
95#define CONFIG_SERIAL_MULTIPORT 1
96#endif
97#ifdef CONFIG_SERIAL_8250_MANY_PORTS
98#define CONFIG_SERIAL_MANY_PORTS 1
99#endif
100
101/*
102 * HUB6 is always on. This will be removed once the header
103 * files have been cleaned.
104 */
105#define CONFIG_HUB6 1
106
107#include <asm/serial.h>
108
109/*
110 * SERIAL_PORT_DFNS tells us about built-in ports that have no
111 * standard enumeration mechanism. Platforms that can find all
112 * serial ports via mechanisms like ACPI or PCI need not supply it.
113 */
114#ifndef SERIAL_PORT_DFNS
115#define SERIAL_PORT_DFNS
116#endif
117
118static struct old_serial_port old_serial_port[] = {
119 SERIAL_PORT_DFNS /* defined in asm/serial.h */
120};
121
122#define UART_NR (ARRAY_SIZE(old_serial_port) + CONFIG_SERIAL_8250_NR_UARTS)
123
124#ifdef CONFIG_SERIAL_8250_RSA
125
126#define PORT_RSA_MAX 4
127static unsigned long probe_rsa[PORT_RSA_MAX];
128static unsigned int probe_rsa_count;
129#endif /* CONFIG_SERIAL_8250_RSA */
130
131struct uart_8250_port {
132 struct uart_port port;
133 struct timer_list timer; /* "no irq" timer */
134 struct list_head list; /* ports on this IRQ */
135 unsigned int capabilities; /* port capabilities */
136 unsigned int tx_loadsz; /* transmit fifo load size */
137 unsigned short rev;
138 unsigned char acr;
139 unsigned char ier;
140 unsigned char lcr;
141 unsigned char mcr;
142 unsigned char mcr_mask; /* mask of user bits */
143 unsigned char mcr_force; /* mask of forced bits */
144 unsigned char lsr_break_flag;
145
146 /*
147 * We provide a per-port pm hook.
148 */
149 void (*pm)(struct uart_port *port,
150 unsigned int state, unsigned int old);
151};
152
153struct irq_info {
154 spinlock_t lock;
155 struct list_head *head;
156};
157
158static struct irq_info irq_lists[NR_IRQS];
159
160/*
161 * Here we define the default xmit fifo size used for each type of UART.
162 */
163static const struct serial8250_config uart_config[] = {
164 [PORT_UNKNOWN] = {
165 .name = "unknown",
166 .fifo_size = 1,
167 .tx_loadsz = 1,
168 },
169 [PORT_8250] = {
170 .name = "8250",
171 .fifo_size = 1,
172 .tx_loadsz = 1,
173 },
174 [PORT_16450] = {
175 .name = "16450",
176 .fifo_size = 1,
177 .tx_loadsz = 1,
178 },
179 [PORT_16550] = {
180 .name = "16550",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 },
184 [PORT_16550A] = {
185 .name = "16550A",
186 .fifo_size = 16,
187 .tx_loadsz = 16,
188 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
189 .flags = UART_CAP_FIFO,
190 },
191 [PORT_CIRRUS] = {
192 .name = "Cirrus",
193 .fifo_size = 1,
194 .tx_loadsz = 1,
195 },
196 [PORT_16650] = {
197 .name = "ST16650",
198 .fifo_size = 1,
199 .tx_loadsz = 1,
200 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
201 },
202 [PORT_16650V2] = {
203 .name = "ST16650V2",
204 .fifo_size = 32,
205 .tx_loadsz = 16,
206 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
207 UART_FCR_T_TRIG_00,
208 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
209 },
210 [PORT_16750] = {
211 .name = "TI16750",
212 .fifo_size = 64,
213 .tx_loadsz = 64,
214 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
215 UART_FCR7_64BYTE,
216 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
217 },
218 [PORT_STARTECH] = {
219 .name = "Startech",
220 .fifo_size = 1,
221 .tx_loadsz = 1,
222 },
223 [PORT_16C950] = {
224 .name = "16C950/954",
225 .fifo_size = 128,
226 .tx_loadsz = 128,
227 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
228 .flags = UART_CAP_FIFO,
229 },
230 [PORT_16654] = {
231 .name = "ST16654",
232 .fifo_size = 64,
233 .tx_loadsz = 32,
234 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
235 UART_FCR_T_TRIG_10,
236 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
237 },
238 [PORT_16850] = {
239 .name = "XR16850",
240 .fifo_size = 128,
241 .tx_loadsz = 128,
242 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
244 },
245 [PORT_RSA] = {
246 .name = "RSA",
247 .fifo_size = 2048,
248 .tx_loadsz = 2048,
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
250 .flags = UART_CAP_FIFO,
251 },
252 [PORT_NS16550A] = {
253 .name = "NS16550A",
254 .fifo_size = 16,
255 .tx_loadsz = 16,
256 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
257 .flags = UART_CAP_FIFO | UART_NATSEMI,
258 },
259 [PORT_XSCALE] = {
260 .name = "XScale",
261 .fifo_size = 32,
262 .tx_loadsz = 32,
263 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
264 .flags = UART_CAP_FIFO | UART_CAP_UUE,
265 },
266};
267
268static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
269{
270 offset <<= up->port.regshift;
271
272 switch (up->port.iotype) {
273 case UPIO_HUB6:
274 outb(up->port.hub6 - 1 + offset, up->port.iobase);
275 return inb(up->port.iobase + 1);
276
277 case UPIO_MEM:
278 return readb(up->port.membase + offset);
279
280 case UPIO_MEM32:
281 return readl(up->port.membase + offset);
282
283 default:
284 return inb(up->port.iobase + offset);
285 }
286}
287
288static _INLINE_ void
289serial_out(struct uart_8250_port *up, int offset, int value)
290{
291 offset <<= up->port.regshift;
292
293 switch (up->port.iotype) {
294 case UPIO_HUB6:
295 outb(up->port.hub6 - 1 + offset, up->port.iobase);
296 outb(value, up->port.iobase + 1);
297 break;
298
299 case UPIO_MEM:
300 writeb(value, up->port.membase + offset);
301 break;
302
303 case UPIO_MEM32:
304 writel(value, up->port.membase + offset);
305 break;
306
307 default:
308 outb(value, up->port.iobase + offset);
309 }
310}
311
312/*
313 * We used to support using pause I/O for certain machines. We
314 * haven't supported this for a while, but just in case it's badly
315 * needed for certain old 386 machines, I've left these #define's
316 * in....
317 */
318#define serial_inp(up, offset) serial_in(up, offset)
319#define serial_outp(up, offset, value) serial_out(up, offset, value)
320
321
322/*
323 * For the 16C950
324 */
325static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
326{
327 serial_out(up, UART_SCR, offset);
328 serial_out(up, UART_ICR, value);
329}
330
331static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
332{
333 unsigned int value;
334
335 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
336 serial_out(up, UART_SCR, offset);
337 value = serial_in(up, UART_ICR);
338 serial_icr_write(up, UART_ACR, up->acr);
339
340 return value;
341}
342
343/*
344 * FIFO support.
345 */
346static inline void serial8250_clear_fifos(struct uart_8250_port *p)
347{
348 if (p->capabilities & UART_CAP_FIFO) {
349 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
350 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
351 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
352 serial_outp(p, UART_FCR, 0);
353 }
354}
355
356/*
357 * IER sleep support. UARTs which have EFRs need the "extended
358 * capability" bit enabled. Note that on XR16C850s, we need to
359 * reset LCR to write to IER.
360 */
361static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
362{
363 if (p->capabilities & UART_CAP_SLEEP) {
364 if (p->capabilities & UART_CAP_EFR) {
365 serial_outp(p, UART_LCR, 0xBF);
366 serial_outp(p, UART_EFR, UART_EFR_ECB);
367 serial_outp(p, UART_LCR, 0);
368 }
369 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
370 if (p->capabilities & UART_CAP_EFR) {
371 serial_outp(p, UART_LCR, 0xBF);
372 serial_outp(p, UART_EFR, 0);
373 serial_outp(p, UART_LCR, 0);
374 }
375 }
376}
377
378#ifdef CONFIG_SERIAL_8250_RSA
379/*
380 * Attempts to turn on the RSA FIFO. Returns zero on failure.
381 * We set the port uart clock rate if we succeed.
382 */
383static int __enable_rsa(struct uart_8250_port *up)
384{
385 unsigned char mode;
386 int result;
387
388 mode = serial_inp(up, UART_RSA_MSR);
389 result = mode & UART_RSA_MSR_FIFO;
390
391 if (!result) {
392 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
393 mode = serial_inp(up, UART_RSA_MSR);
394 result = mode & UART_RSA_MSR_FIFO;
395 }
396
397 if (result)
398 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
399
400 return result;
401}
402
403static void enable_rsa(struct uart_8250_port *up)
404{
405 if (up->port.type == PORT_RSA) {
406 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
407 spin_lock_irq(&up->port.lock);
408 __enable_rsa(up);
409 spin_unlock_irq(&up->port.lock);
410 }
411 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
412 serial_outp(up, UART_RSA_FRR, 0);
413 }
414}
415
416/*
417 * Attempts to turn off the RSA FIFO. Returns zero on failure.
418 * It is unknown why interrupts were disabled in here. However,
419 * the caller is expected to preserve this behaviour by grabbing
420 * the spinlock before calling this function.
421 */
422static void disable_rsa(struct uart_8250_port *up)
423{
424 unsigned char mode;
425 int result;
426
427 if (up->port.type == PORT_RSA &&
428 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
429 spin_lock_irq(&up->port.lock);
430
431 mode = serial_inp(up, UART_RSA_MSR);
432 result = !(mode & UART_RSA_MSR_FIFO);
433
434 if (!result) {
435 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
436 mode = serial_inp(up, UART_RSA_MSR);
437 result = !(mode & UART_RSA_MSR_FIFO);
438 }
439
440 if (result)
441 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
442 spin_unlock_irq(&up->port.lock);
443 }
444}
445#endif /* CONFIG_SERIAL_8250_RSA */
446
447/*
448 * This is a quickie test to see how big the FIFO is.
449 * It doesn't work at all the time, more's the pity.
450 */
451static int size_fifo(struct uart_8250_port *up)
452{
453 unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr;
454 int count;
455
456 old_lcr = serial_inp(up, UART_LCR);
457 serial_outp(up, UART_LCR, 0);
458 old_fcr = serial_inp(up, UART_FCR);
459 old_mcr = serial_inp(up, UART_MCR);
460 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
461 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
462 serial_outp(up, UART_MCR, UART_MCR_LOOP);
463 serial_outp(up, UART_LCR, UART_LCR_DLAB);
464 old_dll = serial_inp(up, UART_DLL);
465 old_dlm = serial_inp(up, UART_DLM);
466 serial_outp(up, UART_DLL, 0x01);
467 serial_outp(up, UART_DLM, 0x00);
468 serial_outp(up, UART_LCR, 0x03);
469 for (count = 0; count < 256; count++)
470 serial_outp(up, UART_TX, count);
471 mdelay(20);/* FIXME - schedule_timeout */
472 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
473 (count < 256); count++)
474 serial_inp(up, UART_RX);
475 serial_outp(up, UART_FCR, old_fcr);
476 serial_outp(up, UART_MCR, old_mcr);
477 serial_outp(up, UART_LCR, UART_LCR_DLAB);
478 serial_outp(up, UART_DLL, old_dll);
479 serial_outp(up, UART_DLM, old_dlm);
480 serial_outp(up, UART_LCR, old_lcr);
481
482 return count;
483}
484
485/*
486 * Read UART ID using the divisor method - set DLL and DLM to zero
487 * and the revision will be in DLL and device type in DLM. We
488 * preserve the device state across this.
489 */
490static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
491{
492 unsigned char old_dll, old_dlm, old_lcr;
493 unsigned int id;
494
495 old_lcr = serial_inp(p, UART_LCR);
496 serial_outp(p, UART_LCR, UART_LCR_DLAB);
497
498 old_dll = serial_inp(p, UART_DLL);
499 old_dlm = serial_inp(p, UART_DLM);
500
501 serial_outp(p, UART_DLL, 0);
502 serial_outp(p, UART_DLM, 0);
503
504 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
505
506 serial_outp(p, UART_DLL, old_dll);
507 serial_outp(p, UART_DLM, old_dlm);
508 serial_outp(p, UART_LCR, old_lcr);
509
510 return id;
511}
512
513/*
514 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
515 * When this function is called we know it is at least a StarTech
516 * 16650 V2, but it might be one of several StarTech UARTs, or one of
517 * its clones. (We treat the broken original StarTech 16650 V1 as a
518 * 16550, and why not? Startech doesn't seem to even acknowledge its
519 * existence.)
520 *
521 * What evil have men's minds wrought...
522 */
523static void autoconfig_has_efr(struct uart_8250_port *up)
524{
525 unsigned int id1, id2, id3, rev;
526
527 /*
528 * Everything with an EFR has SLEEP
529 */
530 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
531
532 /*
533 * First we check to see if it's an Oxford Semiconductor UART.
534 *
535 * If we have to do this here because some non-National
536 * Semiconductor clone chips lock up if you try writing to the
537 * LSR register (which serial_icr_read does)
538 */
539
540 /*
541 * Check for Oxford Semiconductor 16C950.
542 *
543 * EFR [4] must be set else this test fails.
544 *
545 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
546 * claims that it's needed for 952 dual UART's (which are not
547 * recommended for new designs).
548 */
549 up->acr = 0;
550 serial_out(up, UART_LCR, 0xBF);
551 serial_out(up, UART_EFR, UART_EFR_ECB);
552 serial_out(up, UART_LCR, 0x00);
553 id1 = serial_icr_read(up, UART_ID1);
554 id2 = serial_icr_read(up, UART_ID2);
555 id3 = serial_icr_read(up, UART_ID3);
556 rev = serial_icr_read(up, UART_REV);
557
558 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
559
560 if (id1 == 0x16 && id2 == 0xC9 &&
561 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
562 up->port.type = PORT_16C950;
563 up->rev = rev | (id3 << 8);
564 return;
565 }
566
567 /*
568 * We check for a XR16C850 by setting DLL and DLM to 0, and then
569 * reading back DLL and DLM. The chip type depends on the DLM
570 * value read back:
571 * 0x10 - XR16C850 and the DLL contains the chip revision.
572 * 0x12 - XR16C2850.
573 * 0x14 - XR16C854.
574 */
575 id1 = autoconfig_read_divisor_id(up);
576 DEBUG_AUTOCONF("850id=%04x ", id1);
577
578 id2 = id1 >> 8;
579 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
580 if (id2 == 0x10)
581 up->rev = id1 & 255;
582 up->port.type = PORT_16850;
583 return;
584 }
585
586 /*
587 * It wasn't an XR16C850.
588 *
589 * We distinguish between the '654 and the '650 by counting
590 * how many bytes are in the FIFO. I'm using this for now,
591 * since that's the technique that was sent to me in the
592 * serial driver update, but I'm not convinced this works.
593 * I've had problems doing this in the past. -TYT
594 */
595 if (size_fifo(up) == 64)
596 up->port.type = PORT_16654;
597 else
598 up->port.type = PORT_16650V2;
599}
600
601/*
602 * We detected a chip without a FIFO. Only two fall into
603 * this category - the original 8250 and the 16450. The
604 * 16450 has a scratch register (accessible with LCR=0)
605 */
606static void autoconfig_8250(struct uart_8250_port *up)
607{
608 unsigned char scratch, status1, status2;
609
610 up->port.type = PORT_8250;
611
612 scratch = serial_in(up, UART_SCR);
613 serial_outp(up, UART_SCR, 0xa5);
614 status1 = serial_in(up, UART_SCR);
615 serial_outp(up, UART_SCR, 0x5a);
616 status2 = serial_in(up, UART_SCR);
617 serial_outp(up, UART_SCR, scratch);
618
619 if (status1 == 0xa5 && status2 == 0x5a)
620 up->port.type = PORT_16450;
621}
622
623static int broken_efr(struct uart_8250_port *up)
624{
625 /*
626 * Exar ST16C2550 "A2" devices incorrectly detect as
627 * having an EFR, and report an ID of 0x0201. See
628 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
629 */
630 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
631 return 1;
632
633 return 0;
634}
635
636/*
637 * We know that the chip has FIFOs. Does it have an EFR? The
638 * EFR is located in the same register position as the IIR and
639 * we know the top two bits of the IIR are currently set. The
640 * EFR should contain zero. Try to read the EFR.
641 */
642static void autoconfig_16550a(struct uart_8250_port *up)
643{
644 unsigned char status1, status2;
645 unsigned int iersave;
646
647 up->port.type = PORT_16550A;
648 up->capabilities |= UART_CAP_FIFO;
649
650 /*
651 * Check for presence of the EFR when DLAB is set.
652 * Only ST16C650V1 UARTs pass this test.
653 */
654 serial_outp(up, UART_LCR, UART_LCR_DLAB);
655 if (serial_in(up, UART_EFR) == 0) {
656 serial_outp(up, UART_EFR, 0xA8);
657 if (serial_in(up, UART_EFR) != 0) {
658 DEBUG_AUTOCONF("EFRv1 ");
659 up->port.type = PORT_16650;
660 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
661 } else {
662 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
663 }
664 serial_outp(up, UART_EFR, 0);
665 return;
666 }
667
668 /*
669 * Maybe it requires 0xbf to be written to the LCR.
670 * (other ST16C650V2 UARTs, TI16C752A, etc)
671 */
672 serial_outp(up, UART_LCR, 0xBF);
673 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
674 DEBUG_AUTOCONF("EFRv2 ");
675 autoconfig_has_efr(up);
676 return;
677 }
678
679 /*
680 * Check for a National Semiconductor SuperIO chip.
681 * Attempt to switch to bank 2, read the value of the LOOP bit
682 * from EXCR1. Switch back to bank 0, change it in MCR. Then
683 * switch back to bank 2, read it from EXCR1 again and check
684 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
685 * On PowerPC we don't want to change baud_base, as we have
686 * a number of different divisors. -- Tom Rini
687 */
688 serial_outp(up, UART_LCR, 0);
689 status1 = serial_in(up, UART_MCR);
690 serial_outp(up, UART_LCR, 0xE0);
691 status2 = serial_in(up, 0x02); /* EXCR1 */
692
693 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
694 serial_outp(up, UART_LCR, 0);
695 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
696 serial_outp(up, UART_LCR, 0xE0);
697 status2 = serial_in(up, 0x02); /* EXCR1 */
698 serial_outp(up, UART_LCR, 0);
699 serial_outp(up, UART_MCR, status1);
700
701 if ((status2 ^ status1) & UART_MCR_LOOP) {
702#ifndef CONFIG_PPC
703 serial_outp(up, UART_LCR, 0xE0);
704 status1 = serial_in(up, 0x04); /* EXCR1 */
705 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
706 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
707 serial_outp(up, 0x04, status1);
708 serial_outp(up, UART_LCR, 0);
709 up->port.uartclk = 921600*16;
710#endif
711
712 up->port.type = PORT_NS16550A;
713 up->capabilities |= UART_NATSEMI;
714 return;
715 }
716 }
717
718 /*
719 * No EFR. Try to detect a TI16750, which only sets bit 5 of
720 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
721 * Try setting it with and without DLAB set. Cheap clones
722 * set bit 5 without DLAB set.
723 */
724 serial_outp(up, UART_LCR, 0);
725 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
726 status1 = serial_in(up, UART_IIR) >> 5;
727 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
728 serial_outp(up, UART_LCR, UART_LCR_DLAB);
729 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
730 status2 = serial_in(up, UART_IIR) >> 5;
731 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
732 serial_outp(up, UART_LCR, 0);
733
734 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
735
736 if (status1 == 6 && status2 == 7) {
737 up->port.type = PORT_16750;
738 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
739 return;
740 }
741
742 /*
743 * Try writing and reading the UART_IER_UUE bit (b6).
744 * If it works, this is probably one of the Xscale platform's
745 * internal UARTs.
746 * We're going to explicitly set the UUE bit to 0 before
747 * trying to write and read a 1 just to make sure it's not
748 * already a 1 and maybe locked there before we even start start.
749 */
750 iersave = serial_in(up, UART_IER);
751 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
752 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
753 /*
754 * OK it's in a known zero state, try writing and reading
755 * without disturbing the current state of the other bits.
756 */
757 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
758 if (serial_in(up, UART_IER) & UART_IER_UUE) {
759 /*
760 * It's an Xscale.
761 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
762 */
763 DEBUG_AUTOCONF("Xscale ");
764 up->port.type = PORT_XSCALE;
765 up->capabilities |= UART_CAP_UUE;
766 return;
767 }
768 } else {
769 /*
770 * If we got here we couldn't force the IER_UUE bit to 0.
771 * Log it and continue.
772 */
773 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
774 }
775 serial_outp(up, UART_IER, iersave);
776}
777
778/*
779 * This routine is called by rs_init() to initialize a specific serial
780 * port. It determines what type of UART chip this serial port is
781 * using: 8250, 16450, 16550, 16550A. The important question is
782 * whether or not this UART is a 16550A or not, since this will
783 * determine whether or not we can use its FIFO features or not.
784 */
785static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
786{
787 unsigned char status1, scratch, scratch2, scratch3;
788 unsigned char save_lcr, save_mcr;
789 unsigned long flags;
790
791 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
792 return;
793
794 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
795 up->port.line, up->port.iobase, up->port.membase);
796
797 /*
798 * We really do need global IRQs disabled here - we're going to
799 * be frobbing the chips IRQ enable register to see if it exists.
800 */
801 spin_lock_irqsave(&up->port.lock, flags);
802// save_flags(flags); cli();
803
804 up->capabilities = 0;
805
806 if (!(up->port.flags & UPF_BUGGY_UART)) {
807 /*
808 * Do a simple existence test first; if we fail this,
809 * there's no point trying anything else.
810 *
811 * 0x80 is used as a nonsense port to prevent against
812 * false positives due to ISA bus float. The
813 * assumption is that 0x80 is a non-existent port;
814 * which should be safe since include/asm/io.h also
815 * makes this assumption.
816 *
817 * Note: this is safe as long as MCR bit 4 is clear
818 * and the device is in "PC" mode.
819 */
820 scratch = serial_inp(up, UART_IER);
821 serial_outp(up, UART_IER, 0);
822#ifdef __i386__
823 outb(0xff, 0x080);
824#endif
825 scratch2 = serial_inp(up, UART_IER);
826 serial_outp(up, UART_IER, 0x0F);
827#ifdef __i386__
828 outb(0, 0x080);
829#endif
830 scratch3 = serial_inp(up, UART_IER);
831 serial_outp(up, UART_IER, scratch);
832 if (scratch2 != 0 || scratch3 != 0x0F) {
833 /*
834 * We failed; there's nothing here
835 */
836 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
837 scratch2, scratch3);
838 goto out;
839 }
840 }
841
842 save_mcr = serial_in(up, UART_MCR);
843 save_lcr = serial_in(up, UART_LCR);
844
845 /*
846 * Check to see if a UART is really there. Certain broken
847 * internal modems based on the Rockwell chipset fail this
848 * test, because they apparently don't implement the loopback
849 * test mode. So this test is skipped on the COM 1 through
850 * COM 4 ports. This *should* be safe, since no board
851 * manufacturer would be stupid enough to design a board
852 * that conflicts with COM 1-4 --- we hope!
853 */
854 if (!(up->port.flags & UPF_SKIP_TEST)) {
855 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
856 status1 = serial_inp(up, UART_MSR) & 0xF0;
857 serial_outp(up, UART_MCR, save_mcr);
858 if (status1 != 0x90) {
859 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
860 status1);
861 goto out;
862 }
863 }
864
865 /*
866 * We're pretty sure there's a port here. Lets find out what
867 * type of port it is. The IIR top two bits allows us to find
868 * out if its 8250 or 16450, 16550, 16550A or later. This
869 * determines what we test for next.
870 *
871 * We also initialise the EFR (if any) to zero for later. The
872 * EFR occupies the same register location as the FCR and IIR.
873 */
874 serial_outp(up, UART_LCR, 0xBF);
875 serial_outp(up, UART_EFR, 0);
876 serial_outp(up, UART_LCR, 0);
877
878 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
879 scratch = serial_in(up, UART_IIR) >> 6;
880
881 DEBUG_AUTOCONF("iir=%d ", scratch);
882
883 switch (scratch) {
884 case 0:
885 autoconfig_8250(up);
886 break;
887 case 1:
888 up->port.type = PORT_UNKNOWN;
889 break;
890 case 2:
891 up->port.type = PORT_16550;
892 break;
893 case 3:
894 autoconfig_16550a(up);
895 break;
896 }
897
898#ifdef CONFIG_SERIAL_8250_RSA
899 /*
900 * Only probe for RSA ports if we got the region.
901 */
902 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
903 int i;
904
905 for (i = 0 ; i < probe_rsa_count; ++i) {
906 if (probe_rsa[i] == up->port.iobase &&
907 __enable_rsa(up)) {
908 up->port.type = PORT_RSA;
909 break;
910 }
911 }
912 }
913#endif
914 serial_outp(up, UART_LCR, save_lcr);
915
916 if (up->capabilities != uart_config[up->port.type].flags) {
917 printk(KERN_WARNING
918 "ttyS%d: detected caps %08x should be %08x\n",
919 up->port.line, up->capabilities,
920 uart_config[up->port.type].flags);
921 }
922
923 up->port.fifosize = uart_config[up->port.type].fifo_size;
924 up->capabilities = uart_config[up->port.type].flags;
925 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
926
927 if (up->port.type == PORT_UNKNOWN)
928 goto out;
929
930 /*
931 * Reset the UART.
932 */
933#ifdef CONFIG_SERIAL_8250_RSA
934 if (up->port.type == PORT_RSA)
935 serial_outp(up, UART_RSA_FRR, 0);
936#endif
937 serial_outp(up, UART_MCR, save_mcr);
938 serial8250_clear_fifos(up);
939 (void)serial_in(up, UART_RX);
940 serial_outp(up, UART_IER, 0);
941
942 out:
943 spin_unlock_irqrestore(&up->port.lock, flags);
944// restore_flags(flags);
945 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
946}
947
948static void autoconfig_irq(struct uart_8250_port *up)
949{
950 unsigned char save_mcr, save_ier;
951 unsigned char save_ICP = 0;
952 unsigned int ICP = 0;
953 unsigned long irqs;
954 int irq;
955
956 if (up->port.flags & UPF_FOURPORT) {
957 ICP = (up->port.iobase & 0xfe0) | 0x1f;
958 save_ICP = inb_p(ICP);
959 outb_p(0x80, ICP);
960 (void) inb_p(ICP);
961 }
962
963 /* forget possible initially masked and pending IRQ */
964 probe_irq_off(probe_irq_on());
965 save_mcr = serial_inp(up, UART_MCR);
966 save_ier = serial_inp(up, UART_IER);
967 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
968
969 irqs = probe_irq_on();
970 serial_outp(up, UART_MCR, 0);
971 udelay (10);
972 if (up->port.flags & UPF_FOURPORT) {
973 serial_outp(up, UART_MCR,
974 UART_MCR_DTR | UART_MCR_RTS);
975 } else {
976 serial_outp(up, UART_MCR,
977 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
978 }
979 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
980 (void)serial_inp(up, UART_LSR);
981 (void)serial_inp(up, UART_RX);
982 (void)serial_inp(up, UART_IIR);
983 (void)serial_inp(up, UART_MSR);
984 serial_outp(up, UART_TX, 0xFF);
985 udelay (20);
986 irq = probe_irq_off(irqs);
987
988 serial_outp(up, UART_MCR, save_mcr);
989 serial_outp(up, UART_IER, save_ier);
990
991 if (up->port.flags & UPF_FOURPORT)
992 outb_p(save_ICP, ICP);
993
994 up->port.irq = (irq > 0) ? irq : 0;
995}
996
997static void serial8250_stop_tx(struct uart_port *port, unsigned int tty_stop)
998{
999 struct uart_8250_port *up = (struct uart_8250_port *)port;
1000
1001 if (up->ier & UART_IER_THRI) {
1002 up->ier &= ~UART_IER_THRI;
1003 serial_out(up, UART_IER, up->ier);
1004 }
1005
1006 /*
1007 * We only do this from uart_stop - if we run out of
1008 * characters to send, we don't want to prevent the
1009 * FIFO from emptying.
1010 */
1011 if (up->port.type == PORT_16C950 && tty_stop) {
1012 up->acr |= UART_ACR_TXDIS;
1013 serial_icr_write(up, UART_ACR, up->acr);
1014 }
1015}
1016
1017static void serial8250_start_tx(struct uart_port *port, unsigned int tty_start)
1018{
1019 struct uart_8250_port *up = (struct uart_8250_port *)port;
1020
1021 if (!(up->ier & UART_IER_THRI)) {
1022 up->ier |= UART_IER_THRI;
1023 serial_out(up, UART_IER, up->ier);
1024 }
1025 /*
1026 * We only do this from uart_start
1027 */
1028 if (tty_start && up->port.type == PORT_16C950) {
1029 up->acr &= ~UART_ACR_TXDIS;
1030 serial_icr_write(up, UART_ACR, up->acr);
1031 }
1032}
1033
1034static void serial8250_stop_rx(struct uart_port *port)
1035{
1036 struct uart_8250_port *up = (struct uart_8250_port *)port;
1037
1038 up->ier &= ~UART_IER_RLSI;
1039 up->port.read_status_mask &= ~UART_LSR_DR;
1040 serial_out(up, UART_IER, up->ier);
1041}
1042
1043static void serial8250_enable_ms(struct uart_port *port)
1044{
1045 struct uart_8250_port *up = (struct uart_8250_port *)port;
1046
1047 up->ier |= UART_IER_MSI;
1048 serial_out(up, UART_IER, up->ier);
1049}
1050
1051static _INLINE_ void
1052receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1053{
1054 struct tty_struct *tty = up->port.info->tty;
1055 unsigned char ch, lsr = *status;
1056 int max_count = 256;
1057 char flag;
1058
1059 do {
1060 /* The following is not allowed by the tty layer and
1061 unsafe. It should be fixed ASAP */
1062 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
1063 if (tty->low_latency) {
1064 spin_unlock(&up->port.lock);
1065 tty_flip_buffer_push(tty);
1066 spin_lock(&up->port.lock);
1067 }
1068 /* If this failed then we will throw away the
1069 bytes but must do so to clear interrupts */
1070 }
1071 ch = serial_inp(up, UART_RX);
1072 flag = TTY_NORMAL;
1073 up->port.icount.rx++;
1074
1075#ifdef CONFIG_SERIAL_8250_CONSOLE
1076 /*
1077 * Recover the break flag from console xmit
1078 */
1079 if (up->port.line == up->port.cons->index) {
1080 lsr |= up->lsr_break_flag;
1081 up->lsr_break_flag = 0;
1082 }
1083#endif
1084
1085 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1086 UART_LSR_FE | UART_LSR_OE))) {
1087 /*
1088 * For statistics only
1089 */
1090 if (lsr & UART_LSR_BI) {
1091 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1092 up->port.icount.brk++;
1093 /*
1094 * We do the SysRQ and SAK checking
1095 * here because otherwise the break
1096 * may get masked by ignore_status_mask
1097 * or read_status_mask.
1098 */
1099 if (uart_handle_break(&up->port))
1100 goto ignore_char;
1101 } else if (lsr & UART_LSR_PE)
1102 up->port.icount.parity++;
1103 else if (lsr & UART_LSR_FE)
1104 up->port.icount.frame++;
1105 if (lsr & UART_LSR_OE)
1106 up->port.icount.overrun++;
1107
1108 /*
1109 * Mask off conditions which should be ingored.
1110 */
1111 lsr &= up->port.read_status_mask;
1112
1113 if (lsr & UART_LSR_BI) {
1114 DEBUG_INTR("handling break....");
1115 flag = TTY_BREAK;
1116 } else if (lsr & UART_LSR_PE)
1117 flag = TTY_PARITY;
1118 else if (lsr & UART_LSR_FE)
1119 flag = TTY_FRAME;
1120 }
1121 if (uart_handle_sysrq_char(&up->port, ch, regs))
1122 goto ignore_char;
1123 if ((lsr & up->port.ignore_status_mask) == 0) {
1124 tty_insert_flip_char(tty, ch, flag);
1125 }
1126 if ((lsr & UART_LSR_OE) &&
1127 tty->flip.count < TTY_FLIPBUF_SIZE) {
1128 /*
1129 * Overrun is special, since it's reported
1130 * immediately, and doesn't affect the current
1131 * character.
1132 */
1133 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1134 }
1135 ignore_char:
1136 lsr = serial_inp(up, UART_LSR);
1137 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1138 spin_unlock(&up->port.lock);
1139 tty_flip_buffer_push(tty);
1140 spin_lock(&up->port.lock);
1141 *status = lsr;
1142}
1143
1144static _INLINE_ void transmit_chars(struct uart_8250_port *up)
1145{
1146 struct circ_buf *xmit = &up->port.info->xmit;
1147 int count;
1148
1149 if (up->port.x_char) {
1150 serial_outp(up, UART_TX, up->port.x_char);
1151 up->port.icount.tx++;
1152 up->port.x_char = 0;
1153 return;
1154 }
1155 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
1156 serial8250_stop_tx(&up->port, 0);
1157 return;
1158 }
1159
1160 count = up->tx_loadsz;
1161 do {
1162 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1163 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1164 up->port.icount.tx++;
1165 if (uart_circ_empty(xmit))
1166 break;
1167 } while (--count > 0);
1168
1169 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1170 uart_write_wakeup(&up->port);
1171
1172 DEBUG_INTR("THRE...");
1173
1174 if (uart_circ_empty(xmit))
1175 serial8250_stop_tx(&up->port, 0);
1176}
1177
1178static _INLINE_ void check_modem_status(struct uart_8250_port *up)
1179{
1180 int status;
1181
1182 status = serial_in(up, UART_MSR);
1183
1184 if ((status & UART_MSR_ANY_DELTA) == 0)
1185 return;
1186
1187 if (status & UART_MSR_TERI)
1188 up->port.icount.rng++;
1189 if (status & UART_MSR_DDSR)
1190 up->port.icount.dsr++;
1191 if (status & UART_MSR_DDCD)
1192 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1193 if (status & UART_MSR_DCTS)
1194 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1195
1196 wake_up_interruptible(&up->port.info->delta_msr_wait);
1197}
1198
1199/*
1200 * This handles the interrupt from one port.
1201 */
1202static inline void
1203serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1204{
1205 unsigned int status = serial_inp(up, UART_LSR);
1206
1207 DEBUG_INTR("status = %x...", status);
1208
1209 if (status & UART_LSR_DR)
1210 receive_chars(up, &status, regs);
1211 check_modem_status(up);
1212 if (status & UART_LSR_THRE)
1213 transmit_chars(up);
1214}
1215
1216/*
1217 * This is the serial driver's interrupt routine.
1218 *
1219 * Arjan thinks the old way was overly complex, so it got simplified.
1220 * Alan disagrees, saying that need the complexity to handle the weird
1221 * nature of ISA shared interrupts. (This is a special exception.)
1222 *
1223 * In order to handle ISA shared interrupts properly, we need to check
1224 * that all ports have been serviced, and therefore the ISA interrupt
1225 * line has been de-asserted.
1226 *
1227 * This means we need to loop through all ports. checking that they
1228 * don't have an interrupt pending.
1229 */
1230static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1231{
1232 struct irq_info *i = dev_id;
1233 struct list_head *l, *end = NULL;
1234 int pass_counter = 0, handled = 0;
1235
1236 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1237
1238 spin_lock(&i->lock);
1239
1240 l = i->head;
1241 do {
1242 struct uart_8250_port *up;
1243 unsigned int iir;
1244
1245 up = list_entry(l, struct uart_8250_port, list);
1246
1247 iir = serial_in(up, UART_IIR);
1248 if (!(iir & UART_IIR_NO_INT)) {
1249 spin_lock(&up->port.lock);
1250 serial8250_handle_port(up, regs);
1251 spin_unlock(&up->port.lock);
1252
1253 handled = 1;
1254
1255 end = NULL;
1256 } else if (end == NULL)
1257 end = l;
1258
1259 l = l->next;
1260
1261 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1262 /* If we hit this, we're dead. */
1263 printk(KERN_ERR "serial8250: too much work for "
1264 "irq%d\n", irq);
1265 break;
1266 }
1267 } while (l != end);
1268
1269 spin_unlock(&i->lock);
1270
1271 DEBUG_INTR("end.\n");
1272
1273 return IRQ_RETVAL(handled);
1274}
1275
1276/*
1277 * To support ISA shared interrupts, we need to have one interrupt
1278 * handler that ensures that the IRQ line has been deasserted
1279 * before returning. Failing to do this will result in the IRQ
1280 * line being stuck active, and, since ISA irqs are edge triggered,
1281 * no more IRQs will be seen.
1282 */
1283static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1284{
1285 spin_lock_irq(&i->lock);
1286
1287 if (!list_empty(i->head)) {
1288 if (i->head == &up->list)
1289 i->head = i->head->next;
1290 list_del(&up->list);
1291 } else {
1292 BUG_ON(i->head != &up->list);
1293 i->head = NULL;
1294 }
1295
1296 spin_unlock_irq(&i->lock);
1297}
1298
1299static int serial_link_irq_chain(struct uart_8250_port *up)
1300{
1301 struct irq_info *i = irq_lists + up->port.irq;
1302 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
1303
1304 spin_lock_irq(&i->lock);
1305
1306 if (i->head) {
1307 list_add(&up->list, i->head);
1308 spin_unlock_irq(&i->lock);
1309
1310 ret = 0;
1311 } else {
1312 INIT_LIST_HEAD(&up->list);
1313 i->head = &up->list;
1314 spin_unlock_irq(&i->lock);
1315
1316 ret = request_irq(up->port.irq, serial8250_interrupt,
1317 irq_flags, "serial", i);
1318 if (ret < 0)
1319 serial_do_unlink(i, up);
1320 }
1321
1322 return ret;
1323}
1324
1325static void serial_unlink_irq_chain(struct uart_8250_port *up)
1326{
1327 struct irq_info *i = irq_lists + up->port.irq;
1328
1329 BUG_ON(i->head == NULL);
1330
1331 if (list_empty(i->head))
1332 free_irq(up->port.irq, i);
1333
1334 serial_do_unlink(i, up);
1335}
1336
1337/*
1338 * This function is used to handle ports that do not have an
1339 * interrupt. This doesn't work very well for 16450's, but gives
1340 * barely passable results for a 16550A. (Although at the expense
1341 * of much CPU overhead).
1342 */
1343static void serial8250_timeout(unsigned long data)
1344{
1345 struct uart_8250_port *up = (struct uart_8250_port *)data;
1346 unsigned int timeout;
1347 unsigned int iir;
1348
1349 iir = serial_in(up, UART_IIR);
1350 if (!(iir & UART_IIR_NO_INT)) {
1351 spin_lock(&up->port.lock);
1352 serial8250_handle_port(up, NULL);
1353 spin_unlock(&up->port.lock);
1354 }
1355
1356 timeout = up->port.timeout;
1357 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1358 mod_timer(&up->timer, jiffies + timeout);
1359}
1360
1361static unsigned int serial8250_tx_empty(struct uart_port *port)
1362{
1363 struct uart_8250_port *up = (struct uart_8250_port *)port;
1364 unsigned long flags;
1365 unsigned int ret;
1366
1367 spin_lock_irqsave(&up->port.lock, flags);
1368 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1369 spin_unlock_irqrestore(&up->port.lock, flags);
1370
1371 return ret;
1372}
1373
1374static unsigned int serial8250_get_mctrl(struct uart_port *port)
1375{
1376 struct uart_8250_port *up = (struct uart_8250_port *)port;
1377 unsigned long flags;
1378 unsigned char status;
1379 unsigned int ret;
1380
1381 spin_lock_irqsave(&up->port.lock, flags);
1382 status = serial_in(up, UART_MSR);
1383 spin_unlock_irqrestore(&up->port.lock, flags);
1384
1385 ret = 0;
1386 if (status & UART_MSR_DCD)
1387 ret |= TIOCM_CAR;
1388 if (status & UART_MSR_RI)
1389 ret |= TIOCM_RNG;
1390 if (status & UART_MSR_DSR)
1391 ret |= TIOCM_DSR;
1392 if (status & UART_MSR_CTS)
1393 ret |= TIOCM_CTS;
1394 return ret;
1395}
1396
1397static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1398{
1399 struct uart_8250_port *up = (struct uart_8250_port *)port;
1400 unsigned char mcr = 0;
1401
1402 if (mctrl & TIOCM_RTS)
1403 mcr |= UART_MCR_RTS;
1404 if (mctrl & TIOCM_DTR)
1405 mcr |= UART_MCR_DTR;
1406 if (mctrl & TIOCM_OUT1)
1407 mcr |= UART_MCR_OUT1;
1408 if (mctrl & TIOCM_OUT2)
1409 mcr |= UART_MCR_OUT2;
1410 if (mctrl & TIOCM_LOOP)
1411 mcr |= UART_MCR_LOOP;
1412
1413 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1414
1415 serial_out(up, UART_MCR, mcr);
1416}
1417
1418static void serial8250_break_ctl(struct uart_port *port, int break_state)
1419{
1420 struct uart_8250_port *up = (struct uart_8250_port *)port;
1421 unsigned long flags;
1422
1423 spin_lock_irqsave(&up->port.lock, flags);
1424 if (break_state == -1)
1425 up->lcr |= UART_LCR_SBC;
1426 else
1427 up->lcr &= ~UART_LCR_SBC;
1428 serial_out(up, UART_LCR, up->lcr);
1429 spin_unlock_irqrestore(&up->port.lock, flags);
1430}
1431
1432static int serial8250_startup(struct uart_port *port)
1433{
1434 struct uart_8250_port *up = (struct uart_8250_port *)port;
1435 unsigned long flags;
1436 int retval;
1437
1438 up->capabilities = uart_config[up->port.type].flags;
1439 up->mcr = 0;
1440
1441 if (up->port.type == PORT_16C950) {
1442 /* Wake up and initialize UART */
1443 up->acr = 0;
1444 serial_outp(up, UART_LCR, 0xBF);
1445 serial_outp(up, UART_EFR, UART_EFR_ECB);
1446 serial_outp(up, UART_IER, 0);
1447 serial_outp(up, UART_LCR, 0);
1448 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1449 serial_outp(up, UART_LCR, 0xBF);
1450 serial_outp(up, UART_EFR, UART_EFR_ECB);
1451 serial_outp(up, UART_LCR, 0);
1452 }
1453
1454#ifdef CONFIG_SERIAL_8250_RSA
1455 /*
1456 * If this is an RSA port, see if we can kick it up to the
1457 * higher speed clock.
1458 */
1459 enable_rsa(up);
1460#endif
1461
1462 /*
1463 * Clear the FIFO buffers and disable them.
1464 * (they will be reeanbled in set_termios())
1465 */
1466 serial8250_clear_fifos(up);
1467
1468 /*
1469 * Clear the interrupt registers.
1470 */
1471 (void) serial_inp(up, UART_LSR);
1472 (void) serial_inp(up, UART_RX);
1473 (void) serial_inp(up, UART_IIR);
1474 (void) serial_inp(up, UART_MSR);
1475
1476 /*
1477 * At this point, there's no way the LSR could still be 0xff;
1478 * if it is, then bail out, because there's likely no UART
1479 * here.
1480 */
1481 if (!(up->port.flags & UPF_BUGGY_UART) &&
1482 (serial_inp(up, UART_LSR) == 0xff)) {
1483 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1484 return -ENODEV;
1485 }
1486
1487 /*
1488 * For a XR16C850, we need to set the trigger levels
1489 */
1490 if (up->port.type == PORT_16850) {
1491 unsigned char fctr;
1492
1493 serial_outp(up, UART_LCR, 0xbf);
1494
1495 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1496 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1497 serial_outp(up, UART_TRG, UART_TRG_96);
1498 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1499 serial_outp(up, UART_TRG, UART_TRG_96);
1500
1501 serial_outp(up, UART_LCR, 0);
1502 }
1503
1504 /*
1505 * If the "interrupt" for this port doesn't correspond with any
1506 * hardware interrupt, we use a timer-based system. The original
1507 * driver used to do this with IRQ0.
1508 */
1509 if (!is_real_interrupt(up->port.irq)) {
1510 unsigned int timeout = up->port.timeout;
1511
1512 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1513
1514 up->timer.data = (unsigned long)up;
1515 mod_timer(&up->timer, jiffies + timeout);
1516 } else {
1517 retval = serial_link_irq_chain(up);
1518 if (retval)
1519 return retval;
1520 }
1521
1522 /*
1523 * Now, initialize the UART
1524 */
1525 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1526
1527 spin_lock_irqsave(&up->port.lock, flags);
1528 if (up->port.flags & UPF_FOURPORT) {
1529 if (!is_real_interrupt(up->port.irq))
1530 up->port.mctrl |= TIOCM_OUT1;
1531 } else
1532 /*
1533 * Most PC uarts need OUT2 raised to enable interrupts.
1534 */
1535 if (is_real_interrupt(up->port.irq))
1536 up->port.mctrl |= TIOCM_OUT2;
1537
1538 serial8250_set_mctrl(&up->port, up->port.mctrl);
1539 spin_unlock_irqrestore(&up->port.lock, flags);
1540
1541 /*
1542 * Finally, enable interrupts. Note: Modem status interrupts
1543 * are set via set_termios(), which will be occurring imminently
1544 * anyway, so we don't enable them here.
1545 */
1546 up->ier = UART_IER_RLSI | UART_IER_RDI;
1547 serial_outp(up, UART_IER, up->ier);
1548
1549 if (up->port.flags & UPF_FOURPORT) {
1550 unsigned int icp;
1551 /*
1552 * Enable interrupts on the AST Fourport board
1553 */
1554 icp = (up->port.iobase & 0xfe0) | 0x01f;
1555 outb_p(0x80, icp);
1556 (void) inb_p(icp);
1557 }
1558
1559 /*
1560 * And clear the interrupt registers again for luck.
1561 */
1562 (void) serial_inp(up, UART_LSR);
1563 (void) serial_inp(up, UART_RX);
1564 (void) serial_inp(up, UART_IIR);
1565 (void) serial_inp(up, UART_MSR);
1566
1567 return 0;
1568}
1569
1570static void serial8250_shutdown(struct uart_port *port)
1571{
1572 struct uart_8250_port *up = (struct uart_8250_port *)port;
1573 unsigned long flags;
1574
1575 /*
1576 * Disable interrupts from this port
1577 */
1578 up->ier = 0;
1579 serial_outp(up, UART_IER, 0);
1580
1581 spin_lock_irqsave(&up->port.lock, flags);
1582 if (up->port.flags & UPF_FOURPORT) {
1583 /* reset interrupts on the AST Fourport board */
1584 inb((up->port.iobase & 0xfe0) | 0x1f);
1585 up->port.mctrl |= TIOCM_OUT1;
1586 } else
1587 up->port.mctrl &= ~TIOCM_OUT2;
1588
1589 serial8250_set_mctrl(&up->port, up->port.mctrl);
1590 spin_unlock_irqrestore(&up->port.lock, flags);
1591
1592 /*
1593 * Disable break condition and FIFOs
1594 */
1595 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1596 serial8250_clear_fifos(up);
1597
1598#ifdef CONFIG_SERIAL_8250_RSA
1599 /*
1600 * Reset the RSA board back to 115kbps compat mode.
1601 */
1602 disable_rsa(up);
1603#endif
1604
1605 /*
1606 * Read data port to reset things, and then unlink from
1607 * the IRQ chain.
1608 */
1609 (void) serial_in(up, UART_RX);
1610
1611 if (!is_real_interrupt(up->port.irq))
1612 del_timer_sync(&up->timer);
1613 else
1614 serial_unlink_irq_chain(up);
1615}
1616
1617static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1618{
1619 unsigned int quot;
1620
1621 /*
1622 * Handle magic divisors for baud rates above baud_base on
1623 * SMSC SuperIO chips.
1624 */
1625 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1626 baud == (port->uartclk/4))
1627 quot = 0x8001;
1628 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1629 baud == (port->uartclk/8))
1630 quot = 0x8002;
1631 else
1632 quot = uart_get_divisor(port, baud);
1633
1634 return quot;
1635}
1636
1637static void
1638serial8250_set_termios(struct uart_port *port, struct termios *termios,
1639 struct termios *old)
1640{
1641 struct uart_8250_port *up = (struct uart_8250_port *)port;
1642 unsigned char cval, fcr = 0;
1643 unsigned long flags;
1644 unsigned int baud, quot;
1645
1646 switch (termios->c_cflag & CSIZE) {
1647 case CS5:
1648 cval = 0x00;
1649 break;
1650 case CS6:
1651 cval = 0x01;
1652 break;
1653 case CS7:
1654 cval = 0x02;
1655 break;
1656 default:
1657 case CS8:
1658 cval = 0x03;
1659 break;
1660 }
1661
1662 if (termios->c_cflag & CSTOPB)
1663 cval |= 0x04;
1664 if (termios->c_cflag & PARENB)
1665 cval |= UART_LCR_PARITY;
1666 if (!(termios->c_cflag & PARODD))
1667 cval |= UART_LCR_EPAR;
1668#ifdef CMSPAR
1669 if (termios->c_cflag & CMSPAR)
1670 cval |= UART_LCR_SPAR;
1671#endif
1672
1673 /*
1674 * Ask the core to calculate the divisor for us.
1675 */
1676 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1677 quot = serial8250_get_divisor(port, baud);
1678
1679 /*
1680 * Work around a bug in the Oxford Semiconductor 952 rev B
1681 * chip which causes it to seriously miscalculate baud rates
1682 * when DLL is 0.
1683 */
1684 if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 &&
1685 up->rev == 0x5201)
1686 quot ++;
1687
1688 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1689 if (baud < 2400)
1690 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1691 else
1692 fcr = uart_config[up->port.type].fcr;
1693 }
1694
1695 /*
1696 * MCR-based auto flow control. When AFE is enabled, RTS will be
1697 * deasserted when the receive FIFO contains more characters than
1698 * the trigger, or the MCR RTS bit is cleared. In the case where
1699 * the remote UART is not using CTS auto flow control, we must
1700 * have sufficient FIFO entries for the latency of the remote
1701 * UART to respond. IOW, at least 32 bytes of FIFO.
1702 */
1703 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1704 up->mcr &= ~UART_MCR_AFE;
1705 if (termios->c_cflag & CRTSCTS)
1706 up->mcr |= UART_MCR_AFE;
1707 }
1708
1709 /*
1710 * Ok, we're now changing the port state. Do it with
1711 * interrupts disabled.
1712 */
1713 spin_lock_irqsave(&up->port.lock, flags);
1714
1715 /*
1716 * Update the per-port timeout.
1717 */
1718 uart_update_timeout(port, termios->c_cflag, baud);
1719
1720 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1721 if (termios->c_iflag & INPCK)
1722 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1723 if (termios->c_iflag & (BRKINT | PARMRK))
1724 up->port.read_status_mask |= UART_LSR_BI;
1725
1726 /*
1727 * Characteres to ignore
1728 */
1729 up->port.ignore_status_mask = 0;
1730 if (termios->c_iflag & IGNPAR)
1731 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1732 if (termios->c_iflag & IGNBRK) {
1733 up->port.ignore_status_mask |= UART_LSR_BI;
1734 /*
1735 * If we're ignoring parity and break indicators,
1736 * ignore overruns too (for real raw support).
1737 */
1738 if (termios->c_iflag & IGNPAR)
1739 up->port.ignore_status_mask |= UART_LSR_OE;
1740 }
1741
1742 /*
1743 * ignore all characters if CREAD is not set
1744 */
1745 if ((termios->c_cflag & CREAD) == 0)
1746 up->port.ignore_status_mask |= UART_LSR_DR;
1747
1748 /*
1749 * CTS flow control flag and modem status interrupts
1750 */
1751 up->ier &= ~UART_IER_MSI;
1752 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1753 up->ier |= UART_IER_MSI;
1754 if (up->capabilities & UART_CAP_UUE)
1755 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1756
1757 serial_out(up, UART_IER, up->ier);
1758
1759 if (up->capabilities & UART_CAP_EFR) {
1760 unsigned char efr = 0;
1761 /*
1762 * TI16C752/Startech hardware flow control. FIXME:
1763 * - TI16C752 requires control thresholds to be set.
1764 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1765 */
1766 if (termios->c_cflag & CRTSCTS)
1767 efr |= UART_EFR_CTS;
1768
1769 serial_outp(up, UART_LCR, 0xBF);
1770 serial_outp(up, UART_EFR, efr);
1771 }
1772
1773 if (up->capabilities & UART_NATSEMI) {
1774 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1775 serial_outp(up, UART_LCR, 0xe0);
1776 } else {
1777 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1778 }
1779
1780 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
1781 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
1782
1783 /*
1784 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1785 * is written without DLAB set, this mode will be disabled.
1786 */
1787 if (up->port.type == PORT_16750)
1788 serial_outp(up, UART_FCR, fcr);
1789
1790 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1791 up->lcr = cval; /* Save LCR */
1792 if (up->port.type != PORT_16750) {
1793 if (fcr & UART_FCR_ENABLE_FIFO) {
1794 /* emulated UARTs (Lucent Venus 167x) need two steps */
1795 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1796 }
1797 serial_outp(up, UART_FCR, fcr); /* set fcr */
1798 }
1799 serial8250_set_mctrl(&up->port, up->port.mctrl);
1800 spin_unlock_irqrestore(&up->port.lock, flags);
1801}
1802
1803static void
1804serial8250_pm(struct uart_port *port, unsigned int state,
1805 unsigned int oldstate)
1806{
1807 struct uart_8250_port *p = (struct uart_8250_port *)port;
1808
1809 serial8250_set_sleep(p, state != 0);
1810
1811 if (p->pm)
1812 p->pm(port, state, oldstate);
1813}
1814
1815/*
1816 * Resource handling.
1817 */
1818static int serial8250_request_std_resource(struct uart_8250_port *up)
1819{
1820 unsigned int size = 8 << up->port.regshift;
1821 int ret = 0;
1822
1823 switch (up->port.iotype) {
1824 case UPIO_MEM:
1825 if (!up->port.mapbase)
1826 break;
1827
1828 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1829 ret = -EBUSY;
1830 break;
1831 }
1832
1833 if (up->port.flags & UPF_IOREMAP) {
1834 up->port.membase = ioremap(up->port.mapbase, size);
1835 if (!up->port.membase) {
1836 release_mem_region(up->port.mapbase, size);
1837 ret = -ENOMEM;
1838 }
1839 }
1840 break;
1841
1842 case UPIO_HUB6:
1843 case UPIO_PORT:
1844 if (!request_region(up->port.iobase, size, "serial"))
1845 ret = -EBUSY;
1846 break;
1847 }
1848 return ret;
1849}
1850
1851static void serial8250_release_std_resource(struct uart_8250_port *up)
1852{
1853 unsigned int size = 8 << up->port.regshift;
1854
1855 switch (up->port.iotype) {
1856 case UPIO_MEM:
1857 if (!up->port.mapbase)
1858 break;
1859
1860 if (up->port.flags & UPF_IOREMAP) {
1861 iounmap(up->port.membase);
1862 up->port.membase = NULL;
1863 }
1864
1865 release_mem_region(up->port.mapbase, size);
1866 break;
1867
1868 case UPIO_HUB6:
1869 case UPIO_PORT:
1870 release_region(up->port.iobase, size);
1871 break;
1872 }
1873}
1874
1875static int serial8250_request_rsa_resource(struct uart_8250_port *up)
1876{
1877 unsigned long start = UART_RSA_BASE << up->port.regshift;
1878 unsigned int size = 8 << up->port.regshift;
1879 int ret = 0;
1880
1881 switch (up->port.iotype) {
1882 case UPIO_MEM:
1883 ret = -EINVAL;
1884 break;
1885
1886 case UPIO_HUB6:
1887 case UPIO_PORT:
1888 start += up->port.iobase;
1889 if (!request_region(start, size, "serial-rsa"))
1890 ret = -EBUSY;
1891 break;
1892 }
1893
1894 return ret;
1895}
1896
1897static void serial8250_release_rsa_resource(struct uart_8250_port *up)
1898{
1899 unsigned long offset = UART_RSA_BASE << up->port.regshift;
1900 unsigned int size = 8 << up->port.regshift;
1901
1902 switch (up->port.iotype) {
1903 case UPIO_MEM:
1904 break;
1905
1906 case UPIO_HUB6:
1907 case UPIO_PORT:
1908 release_region(up->port.iobase + offset, size);
1909 break;
1910 }
1911}
1912
1913static void serial8250_release_port(struct uart_port *port)
1914{
1915 struct uart_8250_port *up = (struct uart_8250_port *)port;
1916
1917 serial8250_release_std_resource(up);
1918 if (up->port.type == PORT_RSA)
1919 serial8250_release_rsa_resource(up);
1920}
1921
1922static int serial8250_request_port(struct uart_port *port)
1923{
1924 struct uart_8250_port *up = (struct uart_8250_port *)port;
1925 int ret = 0;
1926
1927 ret = serial8250_request_std_resource(up);
1928 if (ret == 0 && up->port.type == PORT_RSA) {
1929 ret = serial8250_request_rsa_resource(up);
1930 if (ret < 0)
1931 serial8250_release_std_resource(up);
1932 }
1933
1934 return ret;
1935}
1936
1937static void serial8250_config_port(struct uart_port *port, int flags)
1938{
1939 struct uart_8250_port *up = (struct uart_8250_port *)port;
1940 int probeflags = PROBE_ANY;
1941 int ret;
1942
1943 /*
1944 * Don't probe for MCA ports on non-MCA machines.
1945 */
1946 if (up->port.flags & UPF_BOOT_ONLYMCA && !MCA_bus)
1947 return;
1948
1949 /*
1950 * Find the region that we can probe for. This in turn
1951 * tells us whether we can probe for the type of port.
1952 */
1953 ret = serial8250_request_std_resource(up);
1954 if (ret < 0)
1955 return;
1956
1957 ret = serial8250_request_rsa_resource(up);
1958 if (ret < 0)
1959 probeflags &= ~PROBE_RSA;
1960
1961 if (flags & UART_CONFIG_TYPE)
1962 autoconfig(up, probeflags);
1963 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
1964 autoconfig_irq(up);
1965
1966 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
1967 serial8250_release_rsa_resource(up);
1968 if (up->port.type == PORT_UNKNOWN)
1969 serial8250_release_std_resource(up);
1970}
1971
1972static int
1973serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
1974{
1975 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
1976 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
1977 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
1978 ser->type == PORT_STARTECH)
1979 return -EINVAL;
1980 return 0;
1981}
1982
1983static const char *
1984serial8250_type(struct uart_port *port)
1985{
1986 int type = port->type;
1987
1988 if (type >= ARRAY_SIZE(uart_config))
1989 type = 0;
1990 return uart_config[type].name;
1991}
1992
1993static struct uart_ops serial8250_pops = {
1994 .tx_empty = serial8250_tx_empty,
1995 .set_mctrl = serial8250_set_mctrl,
1996 .get_mctrl = serial8250_get_mctrl,
1997 .stop_tx = serial8250_stop_tx,
1998 .start_tx = serial8250_start_tx,
1999 .stop_rx = serial8250_stop_rx,
2000 .enable_ms = serial8250_enable_ms,
2001 .break_ctl = serial8250_break_ctl,
2002 .startup = serial8250_startup,
2003 .shutdown = serial8250_shutdown,
2004 .set_termios = serial8250_set_termios,
2005 .pm = serial8250_pm,
2006 .type = serial8250_type,
2007 .release_port = serial8250_release_port,
2008 .request_port = serial8250_request_port,
2009 .config_port = serial8250_config_port,
2010 .verify_port = serial8250_verify_port,
2011};
2012
2013static struct uart_8250_port serial8250_ports[UART_NR];
2014
2015static void __init serial8250_isa_init_ports(void)
2016{
2017 struct uart_8250_port *up;
2018 static int first = 1;
2019 int i;
2020
2021 if (!first)
2022 return;
2023 first = 0;
2024
2025 for (i = 0; i < UART_NR; i++) {
2026 struct uart_8250_port *up = &serial8250_ports[i];
2027
2028 up->port.line = i;
2029 spin_lock_init(&up->port.lock);
2030
2031 init_timer(&up->timer);
2032 up->timer.function = serial8250_timeout;
2033
2034 /*
2035 * ALPHA_KLUDGE_MCR needs to be killed.
2036 */
2037 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2038 up->mcr_force = ALPHA_KLUDGE_MCR;
2039
2040 up->port.ops = &serial8250_pops;
2041 }
2042
2043 for (i = 0, up = serial8250_ports; i < ARRAY_SIZE(old_serial_port);
2044 i++, up++) {
2045 up->port.iobase = old_serial_port[i].port;
2046 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2047 up->port.uartclk = old_serial_port[i].baud_base * 16;
2048 up->port.flags = old_serial_port[i].flags;
2049 up->port.hub6 = old_serial_port[i].hub6;
2050 up->port.membase = old_serial_port[i].iomem_base;
2051 up->port.iotype = old_serial_port[i].io_type;
2052 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2053 if (share_irqs)
2054 up->port.flags |= UPF_SHARE_IRQ;
2055 }
2056}
2057
2058static void __init
2059serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2060{
2061 int i;
2062
2063 serial8250_isa_init_ports();
2064
2065 for (i = 0; i < UART_NR; i++) {
2066 struct uart_8250_port *up = &serial8250_ports[i];
2067
2068 up->port.dev = dev;
2069 uart_add_one_port(drv, &up->port);
2070 }
2071}
2072
2073#ifdef CONFIG_SERIAL_8250_CONSOLE
2074
2075#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2076
2077/*
2078 * Wait for transmitter & holding register to empty
2079 */
2080static inline void wait_for_xmitr(struct uart_8250_port *up)
2081{
2082 unsigned int status, tmout = 10000;
2083
2084 /* Wait up to 10ms for the character(s) to be sent. */
2085 do {
2086 status = serial_in(up, UART_LSR);
2087
2088 if (status & UART_LSR_BI)
2089 up->lsr_break_flag = UART_LSR_BI;
2090
2091 if (--tmout == 0)
2092 break;
2093 udelay(1);
2094 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
2095
2096 /* Wait up to 1s for flow control if necessary */
2097 if (up->port.flags & UPF_CONS_FLOW) {
2098 tmout = 1000000;
2099 while (--tmout &&
2100 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2101 udelay(1);
2102 }
2103}
2104
2105/*
2106 * Print a string to the serial port trying not to disturb
2107 * any possible real use of the port...
2108 *
2109 * The console_lock must be held when we get here.
2110 */
2111static void
2112serial8250_console_write(struct console *co, const char *s, unsigned int count)
2113{
2114 struct uart_8250_port *up = &serial8250_ports[co->index];
2115 unsigned int ier;
2116 int i;
2117
2118 /*
2119 * First save the UER then disable the interrupts
2120 */
2121 ier = serial_in(up, UART_IER);
2122
2123 if (up->capabilities & UART_CAP_UUE)
2124 serial_out(up, UART_IER, UART_IER_UUE);
2125 else
2126 serial_out(up, UART_IER, 0);
2127
2128 /*
2129 * Now, do each character
2130 */
2131 for (i = 0; i < count; i++, s++) {
2132 wait_for_xmitr(up);
2133
2134 /*
2135 * Send the character out.
2136 * If a LF, also do CR...
2137 */
2138 serial_out(up, UART_TX, *s);
2139 if (*s == 10) {
2140 wait_for_xmitr(up);
2141 serial_out(up, UART_TX, 13);
2142 }
2143 }
2144
2145 /*
2146 * Finally, wait for transmitter to become empty
2147 * and restore the IER
2148 */
2149 wait_for_xmitr(up);
2150 serial_out(up, UART_IER, ier);
2151}
2152
2153static int serial8250_console_setup(struct console *co, char *options)
2154{
2155 struct uart_port *port;
2156 int baud = 9600;
2157 int bits = 8;
2158 int parity = 'n';
2159 int flow = 'n';
2160
2161 /*
2162 * Check whether an invalid uart number has been specified, and
2163 * if so, search for the first available port that does have
2164 * console support.
2165 */
2166 if (co->index >= UART_NR)
2167 co->index = 0;
2168 port = &serial8250_ports[co->index].port;
2169 if (!port->iobase && !port->membase)
2170 return -ENODEV;
2171
2172 if (options)
2173 uart_parse_options(options, &baud, &parity, &bits, &flow);
2174
2175 return uart_set_options(port, co, baud, parity, bits, flow);
2176}
2177
2178static struct uart_driver serial8250_reg;
2179static struct console serial8250_console = {
2180 .name = "ttyS",
2181 .write = serial8250_console_write,
2182 .device = uart_console_device,
2183 .setup = serial8250_console_setup,
2184 .flags = CON_PRINTBUFFER,
2185 .index = -1,
2186 .data = &serial8250_reg,
2187};
2188
2189static int __init serial8250_console_init(void)
2190{
2191 serial8250_isa_init_ports();
2192 register_console(&serial8250_console);
2193 return 0;
2194}
2195console_initcall(serial8250_console_init);
2196
2197static int __init find_port(struct uart_port *p)
2198{
2199 int line;
2200 struct uart_port *port;
2201
2202 for (line = 0; line < UART_NR; line++) {
2203 port = &serial8250_ports[line].port;
2204 if (p->iotype == port->iotype &&
2205 p->iobase == port->iobase &&
2206 p->membase == port->membase)
2207 return line;
2208 }
2209 return -ENODEV;
2210}
2211
2212int __init serial8250_start_console(struct uart_port *port, char *options)
2213{
2214 int line;
2215
2216 line = find_port(port);
2217 if (line < 0)
2218 return -ENODEV;
2219
2220 add_preferred_console("ttyS", line, options);
2221 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2222 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2223 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2224 (unsigned long) port->iobase, options);
2225 if (!(serial8250_console.flags & CON_ENABLED)) {
2226 serial8250_console.flags &= ~CON_PRINTBUFFER;
2227 register_console(&serial8250_console);
2228 }
2229 return line;
2230}
2231
2232#define SERIAL8250_CONSOLE &serial8250_console
2233#else
2234#define SERIAL8250_CONSOLE NULL
2235#endif
2236
2237static struct uart_driver serial8250_reg = {
2238 .owner = THIS_MODULE,
2239 .driver_name = "serial",
2240 .devfs_name = "tts/",
2241 .dev_name = "ttyS",
2242 .major = TTY_MAJOR,
2243 .minor = 64,
2244 .nr = UART_NR,
2245 .cons = SERIAL8250_CONSOLE,
2246};
2247
2248int __init early_serial_setup(struct uart_port *port)
2249{
2250 if (port->line >= ARRAY_SIZE(serial8250_ports))
2251 return -ENODEV;
2252
2253 serial8250_isa_init_ports();
2254 serial8250_ports[port->line].port = *port;
2255 serial8250_ports[port->line].port.ops = &serial8250_pops;
2256 return 0;
2257}
2258
2259/**
2260 * serial8250_suspend_port - suspend one serial port
2261 * @line: serial line number
2262 * @level: the level of port suspension, as per uart_suspend_port
2263 *
2264 * Suspend one serial port.
2265 */
2266void serial8250_suspend_port(int line)
2267{
2268 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2269}
2270
2271/**
2272 * serial8250_resume_port - resume one serial port
2273 * @line: serial line number
2274 * @level: the level of port resumption, as per uart_resume_port
2275 *
2276 * Resume one serial port.
2277 */
2278void serial8250_resume_port(int line)
2279{
2280 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2281}
2282
2283/*
2284 * Register a set of serial devices attached to a platform device. The
2285 * list is terminated with a zero flags entry, which means we expect
2286 * all entries to have at least UPF_BOOT_AUTOCONF set.
2287 */
2288static int __devinit serial8250_probe(struct device *dev)
2289{
2290 struct plat_serial8250_port *p = dev->platform_data;
2291 struct uart_port port;
2292
2293 memset(&port, 0, sizeof(struct uart_port));
2294
2295 for (; p && p->flags != 0; p++) {
2296 port.iobase = p->iobase;
2297 port.membase = p->membase;
2298 port.irq = p->irq;
2299 port.uartclk = p->uartclk;
2300 port.regshift = p->regshift;
2301 port.iotype = p->iotype;
2302 port.flags = p->flags;
2303 port.mapbase = p->mapbase;
2304 port.dev = dev;
2305 if (share_irqs)
2306 port.flags |= UPF_SHARE_IRQ;
2307 serial8250_register_port(&port);
2308 }
2309 return 0;
2310}
2311
2312/*
2313 * Remove serial ports registered against a platform device.
2314 */
2315static int __devexit serial8250_remove(struct device *dev)
2316{
2317 int i;
2318
2319 for (i = 0; i < UART_NR; i++) {
2320 struct uart_8250_port *up = &serial8250_ports[i];
2321
2322 if (up->port.dev == dev)
2323 serial8250_unregister_port(i);
2324 }
2325 return 0;
2326}
2327
2328static int serial8250_suspend(struct device *dev, pm_message_t state, u32 level)
2329{
2330 int i;
2331
2332 if (level != SUSPEND_DISABLE)
2333 return 0;
2334
2335 for (i = 0; i < UART_NR; i++) {
2336 struct uart_8250_port *up = &serial8250_ports[i];
2337
2338 if (up->port.type != PORT_UNKNOWN && up->port.dev == dev)
2339 uart_suspend_port(&serial8250_reg, &up->port);
2340 }
2341
2342 return 0;
2343}
2344
2345static int serial8250_resume(struct device *dev, u32 level)
2346{
2347 int i;
2348
2349 if (level != RESUME_ENABLE)
2350 return 0;
2351
2352 for (i = 0; i < UART_NR; i++) {
2353 struct uart_8250_port *up = &serial8250_ports[i];
2354
2355 if (up->port.type != PORT_UNKNOWN && up->port.dev == dev)
2356 uart_resume_port(&serial8250_reg, &up->port);
2357 }
2358
2359 return 0;
2360}
2361
2362static struct device_driver serial8250_isa_driver = {
2363 .name = "serial8250",
2364 .bus = &platform_bus_type,
2365 .probe = serial8250_probe,
2366 .remove = __devexit_p(serial8250_remove),
2367 .suspend = serial8250_suspend,
2368 .resume = serial8250_resume,
2369};
2370
2371/*
2372 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2373 * in the table in include/asm/serial.h
2374 */
2375static struct platform_device *serial8250_isa_devs;
2376
2377/*
2378 * serial8250_register_port and serial8250_unregister_port allows for
2379 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2380 * modems and PCI multiport cards.
2381 */
2382static DECLARE_MUTEX(serial_sem);
2383
2384static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2385{
2386 int i;
2387
2388 /*
2389 * First, find a port entry which matches.
2390 */
2391 for (i = 0; i < UART_NR; i++)
2392 if (uart_match_port(&serial8250_ports[i].port, port))
2393 return &serial8250_ports[i];
2394
2395 /*
2396 * We didn't find a matching entry, so look for the first
2397 * free entry. We look for one which hasn't been previously
2398 * used (indicated by zero iobase).
2399 */
2400 for (i = 0; i < UART_NR; i++)
2401 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2402 serial8250_ports[i].port.iobase == 0)
2403 return &serial8250_ports[i];
2404
2405 /*
2406 * That also failed. Last resort is to find any entry which
2407 * doesn't have a real port associated with it.
2408 */
2409 for (i = 0; i < UART_NR; i++)
2410 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2411 return &serial8250_ports[i];
2412
2413 return NULL;
2414}
2415
2416/**
2417 * serial8250_register_port - register a serial port
2418 * @port: serial port template
2419 *
2420 * Configure the serial port specified by the request. If the
2421 * port exists and is in use, it is hung up and unregistered
2422 * first.
2423 *
2424 * The port is then probed and if necessary the IRQ is autodetected
2425 * If this fails an error is returned.
2426 *
2427 * On success the port is ready to use and the line number is returned.
2428 */
2429int serial8250_register_port(struct uart_port *port)
2430{
2431 struct uart_8250_port *uart;
2432 int ret = -ENOSPC;
2433
2434 if (port->uartclk == 0)
2435 return -EINVAL;
2436
2437 down(&serial_sem);
2438
2439 uart = serial8250_find_match_or_unused(port);
2440 if (uart) {
2441 uart_remove_one_port(&serial8250_reg, &uart->port);
2442
2443 uart->port.iobase = port->iobase;
2444 uart->port.membase = port->membase;
2445 uart->port.irq = port->irq;
2446 uart->port.uartclk = port->uartclk;
2447 uart->port.fifosize = port->fifosize;
2448 uart->port.regshift = port->regshift;
2449 uart->port.iotype = port->iotype;
2450 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2451 uart->port.mapbase = port->mapbase;
2452 if (port->dev)
2453 uart->port.dev = port->dev;
2454
2455 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2456 if (ret == 0)
2457 ret = uart->port.line;
2458 }
2459 up(&serial_sem);
2460
2461 return ret;
2462}
2463EXPORT_SYMBOL(serial8250_register_port);
2464
2465/**
2466 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2467 * @line: serial line number
2468 *
2469 * Remove one serial port. This may not be called from interrupt
2470 * context. We hand the port back to the our control.
2471 */
2472void serial8250_unregister_port(int line)
2473{
2474 struct uart_8250_port *uart = &serial8250_ports[line];
2475
2476 down(&serial_sem);
2477 uart_remove_one_port(&serial8250_reg, &uart->port);
2478 if (serial8250_isa_devs) {
2479 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2480 uart->port.type = PORT_UNKNOWN;
2481 uart->port.dev = &serial8250_isa_devs->dev;
2482 uart_add_one_port(&serial8250_reg, &uart->port);
2483 } else {
2484 uart->port.dev = NULL;
2485 }
2486 up(&serial_sem);
2487}
2488EXPORT_SYMBOL(serial8250_unregister_port);
2489
2490static int __init serial8250_init(void)
2491{
2492 int ret, i;
2493
2494 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2495 "%d ports, IRQ sharing %sabled\n", (int) UART_NR,
2496 share_irqs ? "en" : "dis");
2497
2498 for (i = 0; i < NR_IRQS; i++)
2499 spin_lock_init(&irq_lists[i].lock);
2500
2501 ret = uart_register_driver(&serial8250_reg);
2502 if (ret)
2503 goto out;
2504
2505 serial8250_isa_devs = platform_device_register_simple("serial8250",
2506 -1, NULL, 0);
2507 if (IS_ERR(serial8250_isa_devs)) {
2508 ret = PTR_ERR(serial8250_isa_devs);
2509 goto unreg;
2510 }
2511
2512 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2513
2514 ret = driver_register(&serial8250_isa_driver);
2515 if (ret == 0)
2516 goto out;
2517
2518 platform_device_unregister(serial8250_isa_devs);
2519 unreg:
2520 uart_unregister_driver(&serial8250_reg);
2521 out:
2522 return ret;
2523}
2524
2525static void __exit serial8250_exit(void)
2526{
2527 struct platform_device *isa_dev = serial8250_isa_devs;
2528
2529 /*
2530 * This tells serial8250_unregister_port() not to re-register
2531 * the ports (thereby making serial8250_isa_driver permanently
2532 * in use.)
2533 */
2534 serial8250_isa_devs = NULL;
2535
2536 driver_unregister(&serial8250_isa_driver);
2537 platform_device_unregister(isa_dev);
2538
2539 uart_unregister_driver(&serial8250_reg);
2540}
2541
2542module_init(serial8250_init);
2543module_exit(serial8250_exit);
2544
2545EXPORT_SYMBOL(serial8250_suspend_port);
2546EXPORT_SYMBOL(serial8250_resume_port);
2547
2548MODULE_LICENSE("GPL");
2549MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2550
2551module_param(share_irqs, uint, 0644);
2552MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2553 " (unsafe)");
2554
2555#ifdef CONFIG_SERIAL_8250_RSA
2556module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2557MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2558#endif
2559MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
2560
2561/**
2562 * register_serial - configure a 16x50 serial port at runtime
2563 * @req: request structure
2564 *
2565 * Configure the serial port specified by the request. If the
2566 * port exists and is in use an error is returned. If the port
2567 * is not currently in the table it is added.
2568 *
2569 * The port is then probed and if necessary the IRQ is autodetected
2570 * If this fails an error is returned.
2571 *
2572 * On success the port is ready to use and the line number is returned.
2573 */
2574int register_serial(struct serial_struct *req)
2575{
2576 struct uart_port port;
2577
2578 port.iobase = req->port;
2579 port.membase = req->iomem_base;
2580 port.irq = req->irq;
2581 port.uartclk = req->baud_base * 16;
2582 port.fifosize = req->xmit_fifo_size;
2583 port.regshift = req->iomem_reg_shift;
2584 port.iotype = req->io_type;
2585 port.flags = req->flags | UPF_BOOT_AUTOCONF;
2586 port.mapbase = req->iomap_base;
2587 port.dev = NULL;
2588
2589 if (share_irqs)
2590 port.flags |= UPF_SHARE_IRQ;
2591
2592 if (HIGH_BITS_OFFSET)
2593 port.iobase |= (long) req->port_high << HIGH_BITS_OFFSET;
2594
2595 /*
2596 * If a clock rate wasn't specified by the low level driver, then
2597 * default to the standard clock rate. This should be 115200 (*16)
2598 * and should not depend on the architecture's BASE_BAUD definition.
2599 * However, since this API will be deprecated, it's probably a
2600 * better idea to convert the drivers to use the new API
2601 * (serial8250_register_port and serial8250_unregister_port).
2602 */
2603 if (port.uartclk == 0) {
2604 printk(KERN_WARNING
2605 "Serial: registering port at [%08x,%08lx,%p] irq %d with zero baud_base\n",
2606 port.iobase, port.mapbase, port.membase, port.irq);
2607 printk(KERN_WARNING "Serial: see %s:%d for more information\n",
2608 __FILE__, __LINE__);
2609 dump_stack();
2610
2611 /*
2612 * Fix it up for now, but this is only a temporary measure.
2613 */
2614 port.uartclk = BASE_BAUD * 16;
2615 }
2616
2617 return serial8250_register_port(&port);
2618}
2619EXPORT_SYMBOL(register_serial);
2620
2621/**
2622 * unregister_serial - remove a 16x50 serial port at runtime
2623 * @line: serial line number
2624 *
2625 * Remove one serial port. This may not be called from interrupt
2626 * context. We hand the port back to our local PM control.
2627 */
2628void unregister_serial(int line)
2629{
2630 serial8250_unregister_port(line);
2631}
2632EXPORT_SYMBOL(unregister_serial);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 15:18:23 -0500