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-rw-r--r--drivers/scsi/Kconfig2
-rw-r--r--drivers/scsi/ahci.c30
-rw-r--r--drivers/scsi/ata_piix.c2
-rw-r--r--drivers/scsi/ide-scsi.c2
-rw-r--r--drivers/scsi/libata-core.c38
-rw-r--r--drivers/scsi/libata.h2
-rw-r--r--drivers/scsi/sata_mv.c994
-rw-r--r--drivers/scsi/sata_promise.c2
-rw-r--r--drivers/scsi/sata_qstor.c2
-rw-r--r--drivers/scsi/sata_sil24.c218
-rw-r--r--drivers/scsi/sata_svw.c2
-rw-r--r--drivers/scsi/sata_sx4.c2
-rw-r--r--drivers/scsi/sata_vsc.c2
13 files changed, 1061 insertions, 237 deletions
diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index 84c42c44e04d..20dd85a77813 100644
--- a/drivers/scsi/Kconfig
+++ b/drivers/scsi/Kconfig
@@ -497,7 +497,7 @@ config SCSI_ATA_PIIX
497 If unsure, say N. 497 If unsure, say N.
498 498
499config SCSI_SATA_MV 499config SCSI_SATA_MV
500 tristate "Marvell SATA support" 500 tristate "Marvell SATA support (HIGHLY EXPERIMENTAL)"
501 depends on SCSI_SATA && PCI && EXPERIMENTAL 501 depends on SCSI_SATA && PCI && EXPERIMENTAL
502 help 502 help
503 This option enables support for the Marvell Serial ATA family. 503 This option enables support for the Marvell Serial ATA family.
diff --git a/drivers/scsi/ahci.c b/drivers/scsi/ahci.c
index 894e7113e0b3..83467a05dc8e 100644
--- a/drivers/scsi/ahci.c
+++ b/drivers/scsi/ahci.c
@@ -48,7 +48,7 @@
48#include <asm/io.h> 48#include <asm/io.h>
49 49
50#define DRV_NAME "ahci" 50#define DRV_NAME "ahci"
51#define DRV_VERSION "1.01" 51#define DRV_VERSION "1.2"
52 52
53 53
54enum { 54enum {
@@ -558,23 +558,25 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc)
558 pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16); 558 pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16);
559} 559}
560 560
561static void ahci_intr_error(struct ata_port *ap, u32 irq_stat) 561static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
562{ 562{
563 void __iomem *mmio = ap->host_set->mmio_base; 563 void __iomem *mmio = ap->host_set->mmio_base;
564 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 564 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
565 u32 tmp; 565 u32 tmp;
566 int work; 566 int work;
567 567
568 printk(KERN_WARNING "ata%u: port reset, " 568 if ((ap->device[0].class != ATA_DEV_ATAPI) ||
569 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n", 569 ((irq_stat & PORT_IRQ_TF_ERR) == 0))
570 ap->id, 570 printk(KERN_WARNING "ata%u: port reset, "
571 irq_stat, 571 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
572 readl(mmio + HOST_IRQ_STAT), 572 ap->id,
573 readl(port_mmio + PORT_IRQ_STAT), 573 irq_stat,
574 readl(port_mmio + PORT_CMD), 574 readl(mmio + HOST_IRQ_STAT),
575 readl(port_mmio + PORT_TFDATA), 575 readl(port_mmio + PORT_IRQ_STAT),
576 readl(port_mmio + PORT_SCR_STAT), 576 readl(port_mmio + PORT_CMD),
577 readl(port_mmio + PORT_SCR_ERR)); 577 readl(port_mmio + PORT_TFDATA),
578 readl(port_mmio + PORT_SCR_STAT),
579 readl(port_mmio + PORT_SCR_ERR));
578 580
579 /* stop DMA */ 581 /* stop DMA */
580 tmp = readl(port_mmio + PORT_CMD); 582 tmp = readl(port_mmio + PORT_CMD);
@@ -632,7 +634,7 @@ static void ahci_eng_timeout(struct ata_port *ap)
632 printk(KERN_ERR "ata%u: BUG: timeout without command\n", 634 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
633 ap->id); 635 ap->id);
634 } else { 636 } else {
635 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT)); 637 ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT));
636 638
637 /* hack alert! We cannot use the supplied completion 639 /* hack alert! We cannot use the supplied completion
638 * function from inside the ->eh_strategy_handler() thread. 640 * function from inside the ->eh_strategy_handler() thread.
@@ -677,7 +679,7 @@ static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
677 err_mask = AC_ERR_HOST_BUS; 679 err_mask = AC_ERR_HOST_BUS;
678 680
679 /* command processing has stopped due to error; restart */ 681 /* command processing has stopped due to error; restart */
680 ahci_intr_error(ap, status); 682 ahci_restart_port(ap, status);
681 683
682 if (qc) 684 if (qc)
683 ata_qc_complete(qc, err_mask); 685 ata_qc_complete(qc, err_mask);
diff --git a/drivers/scsi/ata_piix.c b/drivers/scsi/ata_piix.c
index 855428ff37e9..333d69dd84ef 100644
--- a/drivers/scsi/ata_piix.c
+++ b/drivers/scsi/ata_piix.c
@@ -50,7 +50,7 @@
50#include <linux/libata.h> 50#include <linux/libata.h>
51 51
52#define DRV_NAME "ata_piix" 52#define DRV_NAME "ata_piix"
53#define DRV_VERSION "1.04" 53#define DRV_VERSION "1.05"
54 54
55enum { 55enum {
56 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 56 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
diff --git a/drivers/scsi/ide-scsi.c b/drivers/scsi/ide-scsi.c
index e1960d69fb90..4cb1f3ed9100 100644
--- a/drivers/scsi/ide-scsi.c
+++ b/drivers/scsi/ide-scsi.c
@@ -784,8 +784,8 @@ static ide_proc_entry_t idescsi_proc[] = {
784#endif 784#endif
785 785
786static ide_driver_t idescsi_driver = { 786static ide_driver_t idescsi_driver = {
787 .owner = THIS_MODULE,
788 .gen_driver = { 787 .gen_driver = {
788 .owner = THIS_MODULE,
789 .name = "ide-scsi", 789 .name = "ide-scsi",
790 .bus = &ide_bus_type, 790 .bus = &ide_bus_type,
791 .probe = ide_scsi_probe, 791 .probe = ide_scsi_probe,
diff --git a/drivers/scsi/libata-core.c b/drivers/scsi/libata-core.c
index ba1eb8b38e00..665ae79e1fd6 100644
--- a/drivers/scsi/libata-core.c
+++ b/drivers/scsi/libata-core.c
@@ -1046,6 +1046,30 @@ static unsigned int ata_pio_modes(const struct ata_device *adev)
1046 return modes; 1046 return modes;
1047} 1047}
1048 1048
1049static int ata_qc_wait_err(struct ata_queued_cmd *qc,
1050 struct completion *wait)
1051{
1052 int rc = 0;
1053
1054 if (wait_for_completion_timeout(wait, 30 * HZ) < 1) {
1055 /* timeout handling */
1056 unsigned int err_mask = ac_err_mask(ata_chk_status(qc->ap));
1057
1058 if (!err_mask) {
1059 printk(KERN_WARNING "ata%u: slow completion (cmd %x)\n",
1060 qc->ap->id, qc->tf.command);
1061 } else {
1062 printk(KERN_WARNING "ata%u: qc timeout (cmd %x)\n",
1063 qc->ap->id, qc->tf.command);
1064 rc = -EIO;
1065 }
1066
1067 ata_qc_complete(qc, err_mask);
1068 }
1069
1070 return rc;
1071}
1072
1049/** 1073/**
1050 * ata_dev_identify - obtain IDENTIFY x DEVICE page 1074 * ata_dev_identify - obtain IDENTIFY x DEVICE page
1051 * @ap: port on which device we wish to probe resides 1075 * @ap: port on which device we wish to probe resides
@@ -1125,7 +1149,7 @@ retry:
1125 if (rc) 1149 if (rc)
1126 goto err_out; 1150 goto err_out;
1127 else 1151 else
1128 wait_for_completion(&wait); 1152 ata_qc_wait_err(qc, &wait);
1129 1153
1130 spin_lock_irqsave(&ap->host_set->lock, flags); 1154 spin_lock_irqsave(&ap->host_set->lock, flags);
1131 ap->ops->tf_read(ap, &qc->tf); 1155 ap->ops->tf_read(ap, &qc->tf);
@@ -1570,11 +1594,13 @@ int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1570 1594
1571 /* 1595 /*
1572 * Find the mode. 1596 * Find the mode.
1573 */ 1597 */
1574 1598
1575 if (!(s = ata_timing_find_mode(speed))) 1599 if (!(s = ata_timing_find_mode(speed)))
1576 return -EINVAL; 1600 return -EINVAL;
1577 1601
1602 memcpy(t, s, sizeof(*s));
1603
1578 /* 1604 /*
1579 * If the drive is an EIDE drive, it can tell us it needs extended 1605 * If the drive is an EIDE drive, it can tell us it needs extended
1580 * PIO/MW_DMA cycle timing. 1606 * PIO/MW_DMA cycle timing.
@@ -1595,7 +1621,7 @@ int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1595 * Convert the timing to bus clock counts. 1621 * Convert the timing to bus clock counts.
1596 */ 1622 */
1597 1623
1598 ata_timing_quantize(s, t, T, UT); 1624 ata_timing_quantize(t, t, T, UT);
1599 1625
1600 /* 1626 /*
1601 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T 1627 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T
@@ -2267,7 +2293,7 @@ static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
2267 if (rc) 2293 if (rc)
2268 ata_port_disable(ap); 2294 ata_port_disable(ap);
2269 else 2295 else
2270 wait_for_completion(&wait); 2296 ata_qc_wait_err(qc, &wait);
2271 2297
2272 DPRINTK("EXIT\n"); 2298 DPRINTK("EXIT\n");
2273} 2299}
@@ -2315,7 +2341,7 @@ static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev)
2315 if (rc) 2341 if (rc)
2316 goto err_out; 2342 goto err_out;
2317 2343
2318 wait_for_completion(&wait); 2344 ata_qc_wait_err(qc, &wait);
2319 2345
2320 swap_buf_le16(dev->id, ATA_ID_WORDS); 2346 swap_buf_le16(dev->id, ATA_ID_WORDS);
2321 2347
@@ -2371,7 +2397,7 @@ static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev)
2371 if (rc) 2397 if (rc)
2372 ata_port_disable(ap); 2398 ata_port_disable(ap);
2373 else 2399 else
2374 wait_for_completion(&wait); 2400 ata_qc_wait_err(qc, &wait);
2375 2401
2376 DPRINTK("EXIT\n"); 2402 DPRINTK("EXIT\n");
2377} 2403}
diff --git a/drivers/scsi/libata.h b/drivers/scsi/libata.h
index 74a84e0ec0a4..8ebaa694d18e 100644
--- a/drivers/scsi/libata.h
+++ b/drivers/scsi/libata.h
@@ -29,7 +29,7 @@
29#define __LIBATA_H__ 29#define __LIBATA_H__
30 30
31#define DRV_NAME "libata" 31#define DRV_NAME "libata"
32#define DRV_VERSION "1.12" /* must be exactly four chars */ 32#define DRV_VERSION "1.20" /* must be exactly four chars */
33 33
34struct ata_scsi_args { 34struct ata_scsi_args {
35 u16 *id; 35 u16 *id;
diff --git a/drivers/scsi/sata_mv.c b/drivers/scsi/sata_mv.c
index 257c128f4aaa..ab7432a5778e 100644
--- a/drivers/scsi/sata_mv.c
+++ b/drivers/scsi/sata_mv.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * sata_mv.c - Marvell SATA support 2 * sata_mv.c - Marvell SATA support
3 * 3 *
4 * Copyright 2005: EMC Corporation, all rights reserved. 4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
5 * 6 *
6 * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
7 * 8 *
@@ -36,7 +37,7 @@
36#include <asm/io.h> 37#include <asm/io.h>
37 38
38#define DRV_NAME "sata_mv" 39#define DRV_NAME "sata_mv"
39#define DRV_VERSION "0.25" 40#define DRV_VERSION "0.5"
40 41
41enum { 42enum {
42 /* BAR's are enumerated in terms of pci_resource_start() terms */ 43 /* BAR's are enumerated in terms of pci_resource_start() terms */
@@ -50,6 +51,9 @@ enum {
50 MV_PCI_REG_BASE = 0, 51 MV_PCI_REG_BASE = 0,
51 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 52 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
52 MV_SATAHC0_REG_BASE = 0x20000, 53 MV_SATAHC0_REG_BASE = 0x20000,
54 MV_FLASH_CTL = 0x1046c,
55 MV_GPIO_PORT_CTL = 0x104f0,
56 MV_RESET_CFG = 0x180d8,
53 57
54 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 58 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
55 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 59 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
@@ -72,11 +76,6 @@ enum {
72 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 76 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
73 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ), 77 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
74 78
75 /* Our DMA boundary is determined by an ePRD being unable to handle
76 * anything larger than 64KB
77 */
78 MV_DMA_BOUNDARY = 0xffffU,
79
80 MV_PORTS_PER_HC = 4, 79 MV_PORTS_PER_HC = 4,
81 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ 80 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
82 MV_PORT_HC_SHIFT = 2, 81 MV_PORT_HC_SHIFT = 2,
@@ -86,16 +85,9 @@ enum {
86 /* Host Flags */ 85 /* Host Flags */
87 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 86 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
88 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 87 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
89 MV_FLAG_GLBL_SFT_RST = (1 << 28), /* Global Soft Reset support */
90 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 88 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
91 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO), 89 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO),
92 MV_6XXX_FLAGS = (MV_FLAG_IRQ_COALESCE | 90 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
93 MV_FLAG_GLBL_SFT_RST),
94
95 chip_504x = 0,
96 chip_508x = 1,
97 chip_604x = 2,
98 chip_608x = 3,
99 91
100 CRQB_FLAG_READ = (1 << 0), 92 CRQB_FLAG_READ = (1 << 0),
101 CRQB_TAG_SHIFT = 1, 93 CRQB_TAG_SHIFT = 1,
@@ -116,8 +108,19 @@ enum {
116 PCI_MASTER_EMPTY = (1 << 3), 108 PCI_MASTER_EMPTY = (1 << 3),
117 GLOB_SFT_RST = (1 << 4), 109 GLOB_SFT_RST = (1 << 4),
118 110
119 PCI_IRQ_CAUSE_OFS = 0x1d58, 111 MV_PCI_MODE = 0xd00,
120 PCI_IRQ_MASK_OFS = 0x1d5c, 112 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
113 MV_PCI_DISC_TIMER = 0xd04,
114 MV_PCI_MSI_TRIGGER = 0xc38,
115 MV_PCI_SERR_MASK = 0xc28,
116 MV_PCI_XBAR_TMOUT = 0x1d04,
117 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
118 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
119 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
120 MV_PCI_ERR_COMMAND = 0x1d50,
121
122 PCI_IRQ_CAUSE_OFS = 0x1d58,
123 PCI_IRQ_MASK_OFS = 0x1d5c,
121 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 124 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
122 125
123 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 126 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
@@ -134,7 +137,7 @@ enum {
134 SELF_INT = (1 << 23), 137 SELF_INT = (1 << 23),
135 TWSI_INT = (1 << 24), 138 TWSI_INT = (1 << 24),
136 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 139 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
137 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | 140 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
138 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | 141 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
139 HC_MAIN_RSVD), 142 HC_MAIN_RSVD),
140 143
@@ -153,6 +156,15 @@ enum {
153 /* SATA registers */ 156 /* SATA registers */
154 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 157 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
155 SATA_ACTIVE_OFS = 0x350, 158 SATA_ACTIVE_OFS = 0x350,
159 PHY_MODE3 = 0x310,
160 PHY_MODE4 = 0x314,
161 PHY_MODE2 = 0x330,
162 MV5_PHY_MODE = 0x74,
163 MV5_LT_MODE = 0x30,
164 MV5_PHY_CTL = 0x0C,
165 SATA_INTERFACE_CTL = 0x050,
166
167 MV_M2_PREAMP_MASK = 0x7e0,
156 168
157 /* Port registers */ 169 /* Port registers */
158 EDMA_CFG_OFS = 0, 170 EDMA_CFG_OFS = 0,
@@ -182,17 +194,16 @@ enum {
182 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), 194 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
183 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), 195 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
184 EDMA_ERR_TRANS_PROTO = (1 << 31), 196 EDMA_ERR_TRANS_PROTO = (1 << 31),
185 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 197 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
186 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR | 198 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
187 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR | 199 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
188 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 | 200 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
189 EDMA_ERR_LNK_DATA_RX | 201 EDMA_ERR_LNK_DATA_RX |
190 EDMA_ERR_LNK_DATA_TX | 202 EDMA_ERR_LNK_DATA_TX |
191 EDMA_ERR_TRANS_PROTO), 203 EDMA_ERR_TRANS_PROTO),
192 204
193 EDMA_REQ_Q_BASE_HI_OFS = 0x10, 205 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
194 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 206 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
195 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
196 207
197 EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 208 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
198 EDMA_REQ_Q_PTR_SHIFT = 5, 209 EDMA_REQ_Q_PTR_SHIFT = 5,
@@ -200,7 +211,6 @@ enum {
200 EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 211 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
201 EDMA_RSP_Q_IN_PTR_OFS = 0x20, 212 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
202 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 213 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
203 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
204 EDMA_RSP_Q_PTR_SHIFT = 3, 214 EDMA_RSP_Q_PTR_SHIFT = 3,
205 215
206 EDMA_CMD_OFS = 0x28, 216 EDMA_CMD_OFS = 0x28,
@@ -208,14 +218,44 @@ enum {
208 EDMA_DS = (1 << 1), 218 EDMA_DS = (1 << 1),
209 ATA_RST = (1 << 2), 219 ATA_RST = (1 << 2),
210 220
221 EDMA_IORDY_TMOUT = 0x34,
222 EDMA_ARB_CFG = 0x38,
223
211 /* Host private flags (hp_flags) */ 224 /* Host private flags (hp_flags) */
212 MV_HP_FLAG_MSI = (1 << 0), 225 MV_HP_FLAG_MSI = (1 << 0),
226 MV_HP_ERRATA_50XXB0 = (1 << 1),
227 MV_HP_ERRATA_50XXB2 = (1 << 2),
228 MV_HP_ERRATA_60X1B2 = (1 << 3),
229 MV_HP_ERRATA_60X1C0 = (1 << 4),
230 MV_HP_50XX = (1 << 5),
213 231
214 /* Port private flags (pp_flags) */ 232 /* Port private flags (pp_flags) */
215 MV_PP_FLAG_EDMA_EN = (1 << 0), 233 MV_PP_FLAG_EDMA_EN = (1 << 0),
216 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1), 234 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
217}; 235};
218 236
237#define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
238#define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
239
240enum {
241 /* Our DMA boundary is determined by an ePRD being unable to handle
242 * anything larger than 64KB
243 */
244 MV_DMA_BOUNDARY = 0xffffU,
245
246 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
247
248 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
249};
250
251enum chip_type {
252 chip_504x,
253 chip_508x,
254 chip_5080,
255 chip_604x,
256 chip_608x,
257};
258
219/* Command ReQuest Block: 32B */ 259/* Command ReQuest Block: 32B */
220struct mv_crqb { 260struct mv_crqb {
221 u32 sg_addr; 261 u32 sg_addr;
@@ -252,14 +292,37 @@ struct mv_port_priv {
252 u32 pp_flags; 292 u32 pp_flags;
253}; 293};
254 294
295struct mv_port_signal {
296 u32 amps;
297 u32 pre;
298};
299
300struct mv_host_priv;
301struct mv_hw_ops {
302 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
303 unsigned int port);
304 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
305 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
306 void __iomem *mmio);
307 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
308 unsigned int n_hc);
309 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
310 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
311};
312
255struct mv_host_priv { 313struct mv_host_priv {
256 u32 hp_flags; 314 u32 hp_flags;
315 struct mv_port_signal signal[8];
316 const struct mv_hw_ops *ops;
257}; 317};
258 318
259static void mv_irq_clear(struct ata_port *ap); 319static void mv_irq_clear(struct ata_port *ap);
260static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in); 320static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
261static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 321static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
322static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
323static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
262static void mv_phy_reset(struct ata_port *ap); 324static void mv_phy_reset(struct ata_port *ap);
325static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
263static void mv_host_stop(struct ata_host_set *host_set); 326static void mv_host_stop(struct ata_host_set *host_set);
264static int mv_port_start(struct ata_port *ap); 327static int mv_port_start(struct ata_port *ap);
265static void mv_port_stop(struct ata_port *ap); 328static void mv_port_stop(struct ata_port *ap);
@@ -270,6 +333,29 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance,
270static void mv_eng_timeout(struct ata_port *ap); 333static void mv_eng_timeout(struct ata_port *ap);
271static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 334static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
272 335
336static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
337 unsigned int port);
338static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
339static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
340 void __iomem *mmio);
341static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
342 unsigned int n_hc);
343static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
344static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
345
346static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
347 unsigned int port);
348static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
349static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
350 void __iomem *mmio);
351static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
352 unsigned int n_hc);
353static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
354static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
355static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
356 unsigned int port_no);
357static void mv_stop_and_reset(struct ata_port *ap);
358
273static struct scsi_host_template mv_sht = { 359static struct scsi_host_template mv_sht = {
274 .module = THIS_MODULE, 360 .module = THIS_MODULE,
275 .name = DRV_NAME, 361 .name = DRV_NAME,
@@ -278,7 +364,7 @@ static struct scsi_host_template mv_sht = {
278 .eh_strategy_handler = ata_scsi_error, 364 .eh_strategy_handler = ata_scsi_error,
279 .can_queue = MV_USE_Q_DEPTH, 365 .can_queue = MV_USE_Q_DEPTH,
280 .this_id = ATA_SHT_THIS_ID, 366 .this_id = ATA_SHT_THIS_ID,
281 .sg_tablesize = MV_MAX_SG_CT, 367 .sg_tablesize = MV_MAX_SG_CT / 2,
282 .max_sectors = ATA_MAX_SECTORS, 368 .max_sectors = ATA_MAX_SECTORS,
283 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 369 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
284 .emulated = ATA_SHT_EMULATED, 370 .emulated = ATA_SHT_EMULATED,
@@ -290,7 +376,34 @@ static struct scsi_host_template mv_sht = {
290 .ordered_flush = 1, 376 .ordered_flush = 1,
291}; 377};
292 378
293static const struct ata_port_operations mv_ops = { 379static const struct ata_port_operations mv5_ops = {
380 .port_disable = ata_port_disable,
381
382 .tf_load = ata_tf_load,
383 .tf_read = ata_tf_read,
384 .check_status = ata_check_status,
385 .exec_command = ata_exec_command,
386 .dev_select = ata_std_dev_select,
387
388 .phy_reset = mv_phy_reset,
389
390 .qc_prep = mv_qc_prep,
391 .qc_issue = mv_qc_issue,
392
393 .eng_timeout = mv_eng_timeout,
394
395 .irq_handler = mv_interrupt,
396 .irq_clear = mv_irq_clear,
397
398 .scr_read = mv5_scr_read,
399 .scr_write = mv5_scr_write,
400
401 .port_start = mv_port_start,
402 .port_stop = mv_port_stop,
403 .host_stop = mv_host_stop,
404};
405
406static const struct ata_port_operations mv6_ops = {
294 .port_disable = ata_port_disable, 407 .port_disable = ata_port_disable,
295 408
296 .tf_load = ata_tf_load, 409 .tf_load = ata_tf_load,
@@ -322,37 +435,44 @@ static struct ata_port_info mv_port_info[] = {
322 .sht = &mv_sht, 435 .sht = &mv_sht,
323 .host_flags = MV_COMMON_FLAGS, 436 .host_flags = MV_COMMON_FLAGS,
324 .pio_mask = 0x1f, /* pio0-4 */ 437 .pio_mask = 0x1f, /* pio0-4 */
325 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */ 438 .udma_mask = 0x7f, /* udma0-6 */
326 .port_ops = &mv_ops, 439 .port_ops = &mv5_ops,
327 }, 440 },
328 { /* chip_508x */ 441 { /* chip_508x */
329 .sht = &mv_sht, 442 .sht = &mv_sht,
330 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), 443 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
331 .pio_mask = 0x1f, /* pio0-4 */ 444 .pio_mask = 0x1f, /* pio0-4 */
332 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */ 445 .udma_mask = 0x7f, /* udma0-6 */
333 .port_ops = &mv_ops, 446 .port_ops = &mv5_ops,
447 },
448 { /* chip_5080 */
449 .sht = &mv_sht,
450 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
451 .pio_mask = 0x1f, /* pio0-4 */
452 .udma_mask = 0x7f, /* udma0-6 */
453 .port_ops = &mv5_ops,
334 }, 454 },
335 { /* chip_604x */ 455 { /* chip_604x */
336 .sht = &mv_sht, 456 .sht = &mv_sht,
337 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), 457 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
338 .pio_mask = 0x1f, /* pio0-4 */ 458 .pio_mask = 0x1f, /* pio0-4 */
339 .udma_mask = 0x7f, /* udma0-6 */ 459 .udma_mask = 0x7f, /* udma0-6 */
340 .port_ops = &mv_ops, 460 .port_ops = &mv6_ops,
341 }, 461 },
342 { /* chip_608x */ 462 { /* chip_608x */
343 .sht = &mv_sht, 463 .sht = &mv_sht,
344 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS | 464 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
345 MV_FLAG_DUAL_HC), 465 MV_FLAG_DUAL_HC),
346 .pio_mask = 0x1f, /* pio0-4 */ 466 .pio_mask = 0x1f, /* pio0-4 */
347 .udma_mask = 0x7f, /* udma0-6 */ 467 .udma_mask = 0x7f, /* udma0-6 */
348 .port_ops = &mv_ops, 468 .port_ops = &mv6_ops,
349 }, 469 },
350}; 470};
351 471
352static const struct pci_device_id mv_pci_tbl[] = { 472static const struct pci_device_id mv_pci_tbl[] = {
353 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x}, 473 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
354 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x}, 474 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
355 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_508x}, 475 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
356 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x}, 476 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
357 477
358 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x}, 478 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
@@ -371,6 +491,24 @@ static struct pci_driver mv_pci_driver = {
371 .remove = ata_pci_remove_one, 491 .remove = ata_pci_remove_one,
372}; 492};
373 493
494static const struct mv_hw_ops mv5xxx_ops = {
495 .phy_errata = mv5_phy_errata,
496 .enable_leds = mv5_enable_leds,
497 .read_preamp = mv5_read_preamp,
498 .reset_hc = mv5_reset_hc,
499 .reset_flash = mv5_reset_flash,
500 .reset_bus = mv5_reset_bus,
501};
502
503static const struct mv_hw_ops mv6xxx_ops = {
504 .phy_errata = mv6_phy_errata,
505 .enable_leds = mv6_enable_leds,
506 .read_preamp = mv6_read_preamp,
507 .reset_hc = mv6_reset_hc,
508 .reset_flash = mv6_reset_flash,
509 .reset_bus = mv_reset_pci_bus,
510};
511
374/* 512/*
375 * Functions 513 * Functions
376 */ 514 */
@@ -386,11 +524,27 @@ static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
386 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 524 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
387} 525}
388 526
527static inline unsigned int mv_hc_from_port(unsigned int port)
528{
529 return port >> MV_PORT_HC_SHIFT;
530}
531
532static inline unsigned int mv_hardport_from_port(unsigned int port)
533{
534 return port & MV_PORT_MASK;
535}
536
537static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
538 unsigned int port)
539{
540 return mv_hc_base(base, mv_hc_from_port(port));
541}
542
389static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 543static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
390{ 544{
391 return (mv_hc_base(base, port >> MV_PORT_HC_SHIFT) + 545 return mv_hc_base_from_port(base, port) +
392 MV_SATAHC_ARBTR_REG_SZ + 546 MV_SATAHC_ARBTR_REG_SZ +
393 ((port & MV_PORT_MASK) * MV_PORT_REG_SZ)); 547 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
394} 548}
395 549
396static inline void __iomem *mv_ap_base(struct ata_port *ap) 550static inline void __iomem *mv_ap_base(struct ata_port *ap)
@@ -398,9 +552,9 @@ static inline void __iomem *mv_ap_base(struct ata_port *ap)
398 return mv_port_base(ap->host_set->mmio_base, ap->port_no); 552 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
399} 553}
400 554
401static inline int mv_get_hc_count(unsigned long hp_flags) 555static inline int mv_get_hc_count(unsigned long host_flags)
402{ 556{
403 return ((hp_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 557 return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
404} 558}
405 559
406static void mv_irq_clear(struct ata_port *ap) 560static void mv_irq_clear(struct ata_port *ap)
@@ -452,7 +606,7 @@ static void mv_stop_dma(struct ata_port *ap)
452 } else { 606 } else {
453 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS))); 607 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
454 } 608 }
455 609
456 /* now properly wait for the eDMA to stop */ 610 /* now properly wait for the eDMA to stop */
457 for (i = 1000; i > 0; i--) { 611 for (i = 1000; i > 0; i--) {
458 reg = readl(port_mmio + EDMA_CMD_OFS); 612 reg = readl(port_mmio + EDMA_CMD_OFS);
@@ -503,7 +657,7 @@ static void mv_dump_all_regs(void __iomem *mmio_base, int port,
503 struct pci_dev *pdev) 657 struct pci_dev *pdev)
504{ 658{
505#ifdef ATA_DEBUG 659#ifdef ATA_DEBUG
506 void __iomem *hc_base = mv_hc_base(mmio_base, 660 void __iomem *hc_base = mv_hc_base(mmio_base,
507 port >> MV_PORT_HC_SHIFT); 661 port >> MV_PORT_HC_SHIFT);
508 void __iomem *port_base; 662 void __iomem *port_base;
509 int start_port, num_ports, p, start_hc, num_hcs, hc; 663 int start_port, num_ports, p, start_hc, num_hcs, hc;
@@ -517,7 +671,7 @@ static void mv_dump_all_regs(void __iomem *mmio_base, int port,
517 start_port = port; 671 start_port = port;
518 num_ports = num_hcs = 1; 672 num_ports = num_hcs = 1;
519 } 673 }
520 DPRINTK("All registers for port(s) %u-%u:\n", start_port, 674 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
521 num_ports > 1 ? num_ports - 1 : start_port); 675 num_ports > 1 ? num_ports - 1 : start_port);
522 676
523 if (NULL != pdev) { 677 if (NULL != pdev) {
@@ -585,70 +739,6 @@ static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
585} 739}
586 740
587/** 741/**
588 * mv_global_soft_reset - Perform the 6xxx global soft reset
589 * @mmio_base: base address of the HBA
590 *
591 * This routine only applies to 6xxx parts.
592 *
593 * LOCKING:
594 * Inherited from caller.
595 */
596static int mv_global_soft_reset(void __iomem *mmio_base)
597{
598 void __iomem *reg = mmio_base + PCI_MAIN_CMD_STS_OFS;
599 int i, rc = 0;
600 u32 t;
601
602 /* Following procedure defined in PCI "main command and status
603 * register" table.
604 */
605 t = readl(reg);
606 writel(t | STOP_PCI_MASTER, reg);
607
608 for (i = 0; i < 1000; i++) {
609 udelay(1);
610 t = readl(reg);
611 if (PCI_MASTER_EMPTY & t) {
612 break;
613 }
614 }
615 if (!(PCI_MASTER_EMPTY & t)) {
616 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
617 rc = 1;
618 goto done;
619 }
620
621 /* set reset */
622 i = 5;
623 do {
624 writel(t | GLOB_SFT_RST, reg);
625 t = readl(reg);
626 udelay(1);
627 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
628
629 if (!(GLOB_SFT_RST & t)) {
630 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
631 rc = 1;
632 goto done;
633 }
634
635 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
636 i = 5;
637 do {
638 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
639 t = readl(reg);
640 udelay(1);
641 } while ((GLOB_SFT_RST & t) && (i-- > 0));
642
643 if (GLOB_SFT_RST & t) {
644 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
645 rc = 1;
646 }
647done:
648 return rc;
649}
650
651/**
652 * mv_host_stop - Host specific cleanup/stop routine. 742 * mv_host_stop - Host specific cleanup/stop routine.
653 * @host_set: host data structure 743 * @host_set: host data structure
654 * 744 *
@@ -701,7 +791,7 @@ static int mv_port_start(struct ata_port *ap)
701 goto err_out; 791 goto err_out;
702 memset(pp, 0, sizeof(*pp)); 792 memset(pp, 0, sizeof(*pp));
703 793
704 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma, 794 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
705 GFP_KERNEL); 795 GFP_KERNEL);
706 if (!mem) 796 if (!mem)
707 goto err_out_pp; 797 goto err_out_pp;
@@ -711,7 +801,7 @@ static int mv_port_start(struct ata_port *ap)
711 if (rc) 801 if (rc)
712 goto err_out_priv; 802 goto err_out_priv;
713 803
714 /* First item in chunk of DMA memory: 804 /* First item in chunk of DMA memory:
715 * 32-slot command request table (CRQB), 32 bytes each in size 805 * 32-slot command request table (CRQB), 32 bytes each in size
716 */ 806 */
717 pp->crqb = mem; 807 pp->crqb = mem;
@@ -719,7 +809,7 @@ static int mv_port_start(struct ata_port *ap)
719 mem += MV_CRQB_Q_SZ; 809 mem += MV_CRQB_Q_SZ;
720 mem_dma += MV_CRQB_Q_SZ; 810 mem_dma += MV_CRQB_Q_SZ;
721 811
722 /* Second item: 812 /* Second item:
723 * 32-slot command response table (CRPB), 8 bytes each in size 813 * 32-slot command response table (CRPB), 8 bytes each in size
724 */ 814 */
725 pp->crpb = mem; 815 pp->crpb = mem;
@@ -733,18 +823,18 @@ static int mv_port_start(struct ata_port *ap)
733 pp->sg_tbl = mem; 823 pp->sg_tbl = mem;
734 pp->sg_tbl_dma = mem_dma; 824 pp->sg_tbl_dma = mem_dma;
735 825
736 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT | 826 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
737 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS); 827 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
738 828
739 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 829 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
740 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK, 830 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
741 port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 831 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
742 832
743 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 833 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
744 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 834 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
745 835
746 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 836 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
747 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK, 837 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
748 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 838 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
749 839
750 pp->req_producer = pp->rsp_consumer = 0; 840 pp->req_producer = pp->rsp_consumer = 0;
@@ -805,20 +895,30 @@ static void mv_fill_sg(struct ata_queued_cmd *qc)
805 struct scatterlist *sg; 895 struct scatterlist *sg;
806 896
807 ata_for_each_sg(sg, qc) { 897 ata_for_each_sg(sg, qc) {
808 u32 sg_len;
809 dma_addr_t addr; 898 dma_addr_t addr;
899 u32 sg_len, len, offset;
810 900
811 addr = sg_dma_address(sg); 901 addr = sg_dma_address(sg);
812 sg_len = sg_dma_len(sg); 902 sg_len = sg_dma_len(sg);
813 903
814 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff); 904 while (sg_len) {
815 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16); 905 offset = addr & MV_DMA_BOUNDARY;
816 assert(0 == (sg_len & ~MV_DMA_BOUNDARY)); 906 len = sg_len;
817 pp->sg_tbl[i].flags_size = cpu_to_le32(sg_len); 907 if ((offset + sg_len) > 0x10000)
818 if (ata_sg_is_last(sg, qc)) 908 len = 0x10000 - offset;
819 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 909
910 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
911 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
912 pp->sg_tbl[i].flags_size = cpu_to_le32(len);
913
914 sg_len -= len;
915 addr += len;
916
917 if (!sg_len && ata_sg_is_last(sg, qc))
918 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
820 919
821 i++; 920 i++;
921 }
822 } 922 }
823} 923}
824 924
@@ -859,7 +959,7 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
859 } 959 }
860 960
861 /* the req producer index should be the same as we remember it */ 961 /* the req producer index should be the same as we remember it */
862 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >> 962 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
863 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == 963 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
864 pp->req_producer); 964 pp->req_producer);
865 965
@@ -871,9 +971,9 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
871 assert(MV_MAX_Q_DEPTH > qc->tag); 971 assert(MV_MAX_Q_DEPTH > qc->tag);
872 flags |= qc->tag << CRQB_TAG_SHIFT; 972 flags |= qc->tag << CRQB_TAG_SHIFT;
873 973
874 pp->crqb[pp->req_producer].sg_addr = 974 pp->crqb[pp->req_producer].sg_addr =
875 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff); 975 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
876 pp->crqb[pp->req_producer].sg_addr_hi = 976 pp->crqb[pp->req_producer].sg_addr_hi =
877 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16); 977 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
878 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags); 978 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
879 979
@@ -896,7 +996,7 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
896#ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */ 996#ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
897 case ATA_CMD_FPDMA_READ: 997 case ATA_CMD_FPDMA_READ:
898 case ATA_CMD_FPDMA_WRITE: 998 case ATA_CMD_FPDMA_WRITE:
899 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 999 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
900 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 1000 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
901 break; 1001 break;
902#endif /* FIXME: remove this line when NCQ added */ 1002#endif /* FIXME: remove this line when NCQ added */
@@ -962,7 +1062,7 @@ static int mv_qc_issue(struct ata_queued_cmd *qc)
962 pp->req_producer); 1062 pp->req_producer);
963 /* until we do queuing, the queue should be empty at this point */ 1063 /* until we do queuing, the queue should be empty at this point */
964 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == 1064 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
965 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >> 1065 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
966 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK)); 1066 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
967 1067
968 mv_inc_q_index(&pp->req_producer); /* now incr producer index */ 1068 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
@@ -999,15 +1099,15 @@ static u8 mv_get_crpb_status(struct ata_port *ap)
999 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 1099 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1000 1100
1001 /* the response consumer index should be the same as we remember it */ 1101 /* the response consumer index should be the same as we remember it */
1002 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == 1102 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1003 pp->rsp_consumer); 1103 pp->rsp_consumer);
1004 1104
1005 /* increment our consumer index... */ 1105 /* increment our consumer index... */
1006 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer); 1106 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
1007 1107
1008 /* and, until we do NCQ, there should only be 1 CRPB waiting */ 1108 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1009 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >> 1109 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
1010 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == 1110 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1011 pp->rsp_consumer); 1111 pp->rsp_consumer);
1012 1112
1013 /* write out our inc'd consumer index so EDMA knows we're caught up */ 1113 /* write out our inc'd consumer index so EDMA knows we're caught up */
@@ -1055,7 +1155,7 @@ static void mv_err_intr(struct ata_port *ap)
1055 1155
1056 /* check for fatal here and recover if needed */ 1156 /* check for fatal here and recover if needed */
1057 if (EDMA_ERR_FATAL & edma_err_cause) { 1157 if (EDMA_ERR_FATAL & edma_err_cause) {
1058 mv_phy_reset(ap); 1158 mv_stop_and_reset(ap);
1059 } 1159 }
1060} 1160}
1061 1161
@@ -1120,6 +1220,10 @@ static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1120 handled++; 1220 handled++;
1121 } 1221 }
1122 1222
1223 if (ap &&
1224 (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR)))
1225 continue;
1226
1123 err_mask = ac_err_mask(ata_status); 1227 err_mask = ac_err_mask(ata_status);
1124 1228
1125 shift = port << 1; /* (port * 2) */ 1229 shift = port << 1; /* (port * 2) */
@@ -1131,14 +1235,15 @@ static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1131 err_mask |= AC_ERR_OTHER; 1235 err_mask |= AC_ERR_OTHER;
1132 handled++; 1236 handled++;
1133 } 1237 }
1134 1238
1135 if (handled && ap) { 1239 if (handled && ap) {
1136 qc = ata_qc_from_tag(ap, ap->active_tag); 1240 qc = ata_qc_from_tag(ap, ap->active_tag);
1137 if (NULL != qc) { 1241 if (NULL != qc) {
1138 VPRINTK("port %u IRQ found for qc, " 1242 VPRINTK("port %u IRQ found for qc, "
1139 "ata_status 0x%x\n", port,ata_status); 1243 "ata_status 0x%x\n", port,ata_status);
1140 /* mark qc status appropriately */ 1244 /* mark qc status appropriately */
1141 ata_qc_complete(qc, err_mask); 1245 if (!(qc->tf.ctl & ATA_NIEN))
1246 ata_qc_complete(qc, err_mask);
1142 } 1247 }
1143 } 1248 }
1144 } 1249 }
@@ -1146,7 +1251,7 @@ static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1146} 1251}
1147 1252
1148/** 1253/**
1149 * mv_interrupt - 1254 * mv_interrupt -
1150 * @irq: unused 1255 * @irq: unused
1151 * @dev_instance: private data; in this case the host structure 1256 * @dev_instance: private data; in this case the host structure
1152 * @regs: unused 1257 * @regs: unused
@@ -1156,7 +1261,7 @@ static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1156 * routine to handle. Also check for PCI errors which are only 1261 * routine to handle. Also check for PCI errors which are only
1157 * reported here. 1262 * reported here.
1158 * 1263 *
1159 * LOCKING: 1264 * LOCKING:
1160 * This routine holds the host_set lock while processing pending 1265 * This routine holds the host_set lock while processing pending
1161 * interrupts. 1266 * interrupts.
1162 */ 1267 */
@@ -1202,8 +1307,422 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1202 return IRQ_RETVAL(handled); 1307 return IRQ_RETVAL(handled);
1203} 1308}
1204 1309
1310static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1311{
1312 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1313 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1314
1315 return hc_mmio + ofs;
1316}
1317
1318static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1319{
1320 unsigned int ofs;
1321
1322 switch (sc_reg_in) {
1323 case SCR_STATUS:
1324 case SCR_ERROR:
1325 case SCR_CONTROL:
1326 ofs = sc_reg_in * sizeof(u32);
1327 break;
1328 default:
1329 ofs = 0xffffffffU;
1330 break;
1331 }
1332 return ofs;
1333}
1334
1335static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1336{
1337 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1338 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1339
1340 if (ofs != 0xffffffffU)
1341 return readl(mmio + ofs);
1342 else
1343 return (u32) ofs;
1344}
1345
1346static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1347{
1348 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1349 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1350
1351 if (ofs != 0xffffffffU)
1352 writelfl(val, mmio + ofs);
1353}
1354
1355static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1356{
1357 u8 rev_id;
1358 int early_5080;
1359
1360 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1361
1362 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1363
1364 if (!early_5080) {
1365 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1366 tmp |= (1 << 0);
1367 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1368 }
1369
1370 mv_reset_pci_bus(pdev, mmio);
1371}
1372
1373static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1374{
1375 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1376}
1377
1378static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1379 void __iomem *mmio)
1380{
1381 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1382 u32 tmp;
1383
1384 tmp = readl(phy_mmio + MV5_PHY_MODE);
1385
1386 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1387 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1388}
1389
1390static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1391{
1392 u32 tmp;
1393
1394 writel(0, mmio + MV_GPIO_PORT_CTL);
1395
1396 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1397
1398 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1399 tmp |= ~(1 << 0);
1400 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1401}
1402
1403static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1404 unsigned int port)
1405{
1406 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1407 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1408 u32 tmp;
1409 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1410
1411 if (fix_apm_sq) {
1412 tmp = readl(phy_mmio + MV5_LT_MODE);
1413 tmp |= (1 << 19);
1414 writel(tmp, phy_mmio + MV5_LT_MODE);
1415
1416 tmp = readl(phy_mmio + MV5_PHY_CTL);
1417 tmp &= ~0x3;
1418 tmp |= 0x1;
1419 writel(tmp, phy_mmio + MV5_PHY_CTL);
1420 }
1421
1422 tmp = readl(phy_mmio + MV5_PHY_MODE);
1423 tmp &= ~mask;
1424 tmp |= hpriv->signal[port].pre;
1425 tmp |= hpriv->signal[port].amps;
1426 writel(tmp, phy_mmio + MV5_PHY_MODE);
1427}
1428
1429
1430#undef ZERO
1431#define ZERO(reg) writel(0, port_mmio + (reg))
1432static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1433 unsigned int port)
1434{
1435 void __iomem *port_mmio = mv_port_base(mmio, port);
1436
1437 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1438
1439 mv_channel_reset(hpriv, mmio, port);
1440
1441 ZERO(0x028); /* command */
1442 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1443 ZERO(0x004); /* timer */
1444 ZERO(0x008); /* irq err cause */
1445 ZERO(0x00c); /* irq err mask */
1446 ZERO(0x010); /* rq bah */
1447 ZERO(0x014); /* rq inp */
1448 ZERO(0x018); /* rq outp */
1449 ZERO(0x01c); /* respq bah */
1450 ZERO(0x024); /* respq outp */
1451 ZERO(0x020); /* respq inp */
1452 ZERO(0x02c); /* test control */
1453 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1454}
1455#undef ZERO
1456
1457#define ZERO(reg) writel(0, hc_mmio + (reg))
1458static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1459 unsigned int hc)
1460{
1461 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1462 u32 tmp;
1463
1464 ZERO(0x00c);
1465 ZERO(0x010);
1466 ZERO(0x014);
1467 ZERO(0x018);
1468
1469 tmp = readl(hc_mmio + 0x20);
1470 tmp &= 0x1c1c1c1c;
1471 tmp |= 0x03030303;
1472 writel(tmp, hc_mmio + 0x20);
1473}
1474#undef ZERO
1475
1476static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1477 unsigned int n_hc)
1478{
1479 unsigned int hc, port;
1480
1481 for (hc = 0; hc < n_hc; hc++) {
1482 for (port = 0; port < MV_PORTS_PER_HC; port++)
1483 mv5_reset_hc_port(hpriv, mmio,
1484 (hc * MV_PORTS_PER_HC) + port);
1485
1486 mv5_reset_one_hc(hpriv, mmio, hc);
1487 }
1488
1489 return 0;
1490}
1491
1492#undef ZERO
1493#define ZERO(reg) writel(0, mmio + (reg))
1494static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1495{
1496 u32 tmp;
1497
1498 tmp = readl(mmio + MV_PCI_MODE);
1499 tmp &= 0xff00ffff;
1500 writel(tmp, mmio + MV_PCI_MODE);
1501
1502 ZERO(MV_PCI_DISC_TIMER);
1503 ZERO(MV_PCI_MSI_TRIGGER);
1504 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1505 ZERO(HC_MAIN_IRQ_MASK_OFS);
1506 ZERO(MV_PCI_SERR_MASK);
1507 ZERO(PCI_IRQ_CAUSE_OFS);
1508 ZERO(PCI_IRQ_MASK_OFS);
1509 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1510 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1511 ZERO(MV_PCI_ERR_ATTRIBUTE);
1512 ZERO(MV_PCI_ERR_COMMAND);
1513}
1514#undef ZERO
1515
1516static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1517{
1518 u32 tmp;
1519
1520 mv5_reset_flash(hpriv, mmio);
1521
1522 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1523 tmp &= 0x3;
1524 tmp |= (1 << 5) | (1 << 6);
1525 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1526}
1527
1528/**
1529 * mv6_reset_hc - Perform the 6xxx global soft reset
1530 * @mmio: base address of the HBA
1531 *
1532 * This routine only applies to 6xxx parts.
1533 *
1534 * LOCKING:
1535 * Inherited from caller.
1536 */
1537static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1538 unsigned int n_hc)
1539{
1540 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1541 int i, rc = 0;
1542 u32 t;
1543
1544 /* Following procedure defined in PCI "main command and status
1545 * register" table.
1546 */
1547 t = readl(reg);
1548 writel(t | STOP_PCI_MASTER, reg);
1549
1550 for (i = 0; i < 1000; i++) {
1551 udelay(1);
1552 t = readl(reg);
1553 if (PCI_MASTER_EMPTY & t) {
1554 break;
1555 }
1556 }
1557 if (!(PCI_MASTER_EMPTY & t)) {
1558 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1559 rc = 1;
1560 goto done;
1561 }
1562
1563 /* set reset */
1564 i = 5;
1565 do {
1566 writel(t | GLOB_SFT_RST, reg);
1567 t = readl(reg);
1568 udelay(1);
1569 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1570
1571 if (!(GLOB_SFT_RST & t)) {
1572 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1573 rc = 1;
1574 goto done;
1575 }
1576
1577 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1578 i = 5;
1579 do {
1580 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1581 t = readl(reg);
1582 udelay(1);
1583 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1584
1585 if (GLOB_SFT_RST & t) {
1586 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1587 rc = 1;
1588 }
1589done:
1590 return rc;
1591}
1592
1593static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1594 void __iomem *mmio)
1595{
1596 void __iomem *port_mmio;
1597 u32 tmp;
1598
1599 tmp = readl(mmio + MV_RESET_CFG);
1600 if ((tmp & (1 << 0)) == 0) {
1601 hpriv->signal[idx].amps = 0x7 << 8;
1602 hpriv->signal[idx].pre = 0x1 << 5;
1603 return;
1604 }
1605
1606 port_mmio = mv_port_base(mmio, idx);
1607 tmp = readl(port_mmio + PHY_MODE2);
1608
1609 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1610 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1611}
1612
1613static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1614{
1615 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1616}
1617
1618static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1619 unsigned int port)
1620{
1621 void __iomem *port_mmio = mv_port_base(mmio, port);
1622
1623 u32 hp_flags = hpriv->hp_flags;
1624 int fix_phy_mode2 =
1625 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1626 int fix_phy_mode4 =
1627 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1628 u32 m2, tmp;
1629
1630 if (fix_phy_mode2) {
1631 m2 = readl(port_mmio + PHY_MODE2);
1632 m2 &= ~(1 << 16);
1633 m2 |= (1 << 31);
1634 writel(m2, port_mmio + PHY_MODE2);
1635
1636 udelay(200);
1637
1638 m2 = readl(port_mmio + PHY_MODE2);
1639 m2 &= ~((1 << 16) | (1 << 31));
1640 writel(m2, port_mmio + PHY_MODE2);
1641
1642 udelay(200);
1643 }
1644
1645 /* who knows what this magic does */
1646 tmp = readl(port_mmio + PHY_MODE3);
1647 tmp &= ~0x7F800000;
1648 tmp |= 0x2A800000;
1649 writel(tmp, port_mmio + PHY_MODE3);
1650
1651 if (fix_phy_mode4) {
1652 u32 m4;
1653
1654 m4 = readl(port_mmio + PHY_MODE4);
1655
1656 if (hp_flags & MV_HP_ERRATA_60X1B2)
1657 tmp = readl(port_mmio + 0x310);
1658
1659 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1660
1661 writel(m4, port_mmio + PHY_MODE4);
1662
1663 if (hp_flags & MV_HP_ERRATA_60X1B2)
1664 writel(tmp, port_mmio + 0x310);
1665 }
1666
1667 /* Revert values of pre-emphasis and signal amps to the saved ones */
1668 m2 = readl(port_mmio + PHY_MODE2);
1669
1670 m2 &= ~MV_M2_PREAMP_MASK;
1671 m2 |= hpriv->signal[port].amps;
1672 m2 |= hpriv->signal[port].pre;
1673 m2 &= ~(1 << 16);
1674
1675 writel(m2, port_mmio + PHY_MODE2);
1676}
1677
1678static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1679 unsigned int port_no)
1680{
1681 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1682
1683 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1684
1685 if (IS_60XX(hpriv)) {
1686 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1687 ifctl |= (1 << 12) | (1 << 7);
1688 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1689 }
1690
1691 udelay(25); /* allow reset propagation */
1692
1693 /* Spec never mentions clearing the bit. Marvell's driver does
1694 * clear the bit, however.
1695 */
1696 writelfl(0, port_mmio + EDMA_CMD_OFS);
1697
1698 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1699
1700 if (IS_50XX(hpriv))
1701 mdelay(1);
1702}
1703
1704static void mv_stop_and_reset(struct ata_port *ap)
1705{
1706 struct mv_host_priv *hpriv = ap->host_set->private_data;
1707 void __iomem *mmio = ap->host_set->mmio_base;
1708
1709 mv_stop_dma(ap);
1710
1711 mv_channel_reset(hpriv, mmio, ap->port_no);
1712
1713 __mv_phy_reset(ap, 0);
1714}
1715
1716static inline void __msleep(unsigned int msec, int can_sleep)
1717{
1718 if (can_sleep)
1719 msleep(msec);
1720 else
1721 mdelay(msec);
1722}
1723
1205/** 1724/**
1206 * mv_phy_reset - Perform eDMA reset followed by COMRESET 1725 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1207 * @ap: ATA channel to manipulate 1726 * @ap: ATA channel to manipulate
1208 * 1727 *
1209 * Part of this is taken from __sata_phy_reset and modified to 1728 * Part of this is taken from __sata_phy_reset and modified to
@@ -1213,41 +1732,47 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1213 * Inherited from caller. This is coded to safe to call at 1732 * Inherited from caller. This is coded to safe to call at
1214 * interrupt level, i.e. it does not sleep. 1733 * interrupt level, i.e. it does not sleep.
1215 */ 1734 */
1216static void mv_phy_reset(struct ata_port *ap) 1735static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1217{ 1736{
1737 struct mv_port_priv *pp = ap->private_data;
1738 struct mv_host_priv *hpriv = ap->host_set->private_data;
1218 void __iomem *port_mmio = mv_ap_base(ap); 1739 void __iomem *port_mmio = mv_ap_base(ap);
1219 struct ata_taskfile tf; 1740 struct ata_taskfile tf;
1220 struct ata_device *dev = &ap->device[0]; 1741 struct ata_device *dev = &ap->device[0];
1221 unsigned long timeout; 1742 unsigned long timeout;
1743 int retry = 5;
1744 u32 sstatus;
1222 1745
1223 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio); 1746 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1224 1747
1225 mv_stop_dma(ap); 1748 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1226
1227 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1228 udelay(25); /* allow reset propagation */
1229
1230 /* Spec never mentions clearing the bit. Marvell's driver does
1231 * clear the bit, however.
1232 */
1233 writelfl(0, port_mmio + EDMA_CMD_OFS);
1234
1235 VPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1236 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), 1749 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1237 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); 1750 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1238 1751
1239 /* proceed to init communications via the scr_control reg */ 1752 /* Issue COMRESET via SControl */
1753comreset_retry:
1240 scr_write_flush(ap, SCR_CONTROL, 0x301); 1754 scr_write_flush(ap, SCR_CONTROL, 0x301);
1241 mdelay(1); 1755 __msleep(1, can_sleep);
1756
1242 scr_write_flush(ap, SCR_CONTROL, 0x300); 1757 scr_write_flush(ap, SCR_CONTROL, 0x300);
1243 timeout = jiffies + (HZ * 1); 1758 __msleep(20, can_sleep);
1759
1760 timeout = jiffies + msecs_to_jiffies(200);
1244 do { 1761 do {
1245 mdelay(10); 1762 sstatus = scr_read(ap, SCR_STATUS) & 0x3;
1246 if ((scr_read(ap, SCR_STATUS) & 0xf) != 1) 1763 if ((sstatus == 3) || (sstatus == 0))
1247 break; 1764 break;
1765
1766 __msleep(1, can_sleep);
1248 } while (time_before(jiffies, timeout)); 1767 } while (time_before(jiffies, timeout));
1249 1768
1250 VPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " 1769 /* work around errata */
1770 if (IS_60XX(hpriv) &&
1771 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1772 (retry-- > 0))
1773 goto comreset_retry;
1774
1775 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1251 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), 1776 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1252 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); 1777 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1253 1778
@@ -1261,6 +1786,21 @@ static void mv_phy_reset(struct ata_port *ap)
1261 } 1786 }
1262 ap->cbl = ATA_CBL_SATA; 1787 ap->cbl = ATA_CBL_SATA;
1263 1788
1789 /* even after SStatus reflects that device is ready,
1790 * it seems to take a while for link to be fully
1791 * established (and thus Status no longer 0x80/0x7F),
1792 * so we poll a bit for that, here.
1793 */
1794 retry = 20;
1795 while (1) {
1796 u8 drv_stat = ata_check_status(ap);
1797 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1798 break;
1799 __msleep(500, can_sleep);
1800 if (retry-- <= 0)
1801 break;
1802 }
1803
1264 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr); 1804 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1265 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr); 1805 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1266 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr); 1806 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
@@ -1271,9 +1811,19 @@ static void mv_phy_reset(struct ata_port *ap)
1271 VPRINTK("Port disabled post-sig: No device present.\n"); 1811 VPRINTK("Port disabled post-sig: No device present.\n");
1272 ata_port_disable(ap); 1812 ata_port_disable(ap);
1273 } 1813 }
1814
1815 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1816
1817 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1818
1274 VPRINTK("EXIT\n"); 1819 VPRINTK("EXIT\n");
1275} 1820}
1276 1821
1822static void mv_phy_reset(struct ata_port *ap)
1823{
1824 __mv_phy_reset(ap, 1);
1825}
1826
1277/** 1827/**
1278 * mv_eng_timeout - Routine called by libata when SCSI times out I/O 1828 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1279 * @ap: ATA channel to manipulate 1829 * @ap: ATA channel to manipulate
@@ -1291,16 +1841,16 @@ static void mv_eng_timeout(struct ata_port *ap)
1291 1841
1292 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id); 1842 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
1293 DPRINTK("All regs @ start of eng_timeout\n"); 1843 DPRINTK("All regs @ start of eng_timeout\n");
1294 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no, 1844 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
1295 to_pci_dev(ap->host_set->dev)); 1845 to_pci_dev(ap->host_set->dev));
1296 1846
1297 qc = ata_qc_from_tag(ap, ap->active_tag); 1847 qc = ata_qc_from_tag(ap, ap->active_tag);
1298 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n", 1848 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1299 ap->host_set->mmio_base, ap, qc, qc->scsicmd, 1849 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
1300 &qc->scsicmd->cmnd); 1850 &qc->scsicmd->cmnd);
1301 1851
1302 mv_err_intr(ap); 1852 mv_err_intr(ap);
1303 mv_phy_reset(ap); 1853 mv_stop_and_reset(ap);
1304 1854
1305 if (!qc) { 1855 if (!qc) {
1306 printk(KERN_ERR "ata%u: BUG: timeout without command\n", 1856 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
@@ -1336,17 +1886,17 @@ static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1336 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS; 1886 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
1337 unsigned serr_ofs; 1887 unsigned serr_ofs;
1338 1888
1339 /* PIO related setup 1889 /* PIO related setup
1340 */ 1890 */
1341 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 1891 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
1342 port->error_addr = 1892 port->error_addr =
1343 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 1893 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
1344 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 1894 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
1345 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 1895 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
1346 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 1896 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
1347 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 1897 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
1348 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 1898 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
1349 port->status_addr = 1899 port->status_addr =
1350 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 1900 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
1351 /* special case: control/altstatus doesn't have ATA_REG_ address */ 1901 /* special case: control/altstatus doesn't have ATA_REG_ address */
1352 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 1902 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
@@ -1362,14 +1912,92 @@ static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1362 /* unmask all EDMA error interrupts */ 1912 /* unmask all EDMA error interrupts */
1363 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 1913 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
1364 1914
1365 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 1915 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1366 readl(port_mmio + EDMA_CFG_OFS), 1916 readl(port_mmio + EDMA_CFG_OFS),
1367 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 1917 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
1368 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 1918 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
1369} 1919}
1370 1920
1921static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
1922 unsigned int board_idx)
1923{
1924 u8 rev_id;
1925 u32 hp_flags = hpriv->hp_flags;
1926
1927 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1928
1929 switch(board_idx) {
1930 case chip_5080:
1931 hpriv->ops = &mv5xxx_ops;
1932 hp_flags |= MV_HP_50XX;
1933
1934 switch (rev_id) {
1935 case 0x1:
1936 hp_flags |= MV_HP_ERRATA_50XXB0;
1937 break;
1938 case 0x3:
1939 hp_flags |= MV_HP_ERRATA_50XXB2;
1940 break;
1941 default:
1942 dev_printk(KERN_WARNING, &pdev->dev,
1943 "Applying 50XXB2 workarounds to unknown rev\n");
1944 hp_flags |= MV_HP_ERRATA_50XXB2;
1945 break;
1946 }
1947 break;
1948
1949 case chip_504x:
1950 case chip_508x:
1951 hpriv->ops = &mv5xxx_ops;
1952 hp_flags |= MV_HP_50XX;
1953
1954 switch (rev_id) {
1955 case 0x0:
1956 hp_flags |= MV_HP_ERRATA_50XXB0;
1957 break;
1958 case 0x3:
1959 hp_flags |= MV_HP_ERRATA_50XXB2;
1960 break;
1961 default:
1962 dev_printk(KERN_WARNING, &pdev->dev,
1963 "Applying B2 workarounds to unknown rev\n");
1964 hp_flags |= MV_HP_ERRATA_50XXB2;
1965 break;
1966 }
1967 break;
1968
1969 case chip_604x:
1970 case chip_608x:
1971 hpriv->ops = &mv6xxx_ops;
1972
1973 switch (rev_id) {
1974 case 0x7:
1975 hp_flags |= MV_HP_ERRATA_60X1B2;
1976 break;
1977 case 0x9:
1978 hp_flags |= MV_HP_ERRATA_60X1C0;
1979 break;
1980 default:
1981 dev_printk(KERN_WARNING, &pdev->dev,
1982 "Applying B2 workarounds to unknown rev\n");
1983 hp_flags |= MV_HP_ERRATA_60X1B2;
1984 break;
1985 }
1986 break;
1987
1988 default:
1989 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
1990 return 1;
1991 }
1992
1993 hpriv->hp_flags = hp_flags;
1994
1995 return 0;
1996}
1997
1371/** 1998/**
1372 * mv_host_init - Perform some early initialization of the host. 1999 * mv_init_host - Perform some early initialization of the host.
2000 * @pdev: host PCI device
1373 * @probe_ent: early data struct representing the host 2001 * @probe_ent: early data struct representing the host
1374 * 2002 *
1375 * If possible, do an early global reset of the host. Then do 2003 * If possible, do an early global reset of the host. Then do
@@ -1378,23 +2006,48 @@ static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1378 * LOCKING: 2006 * LOCKING:
1379 * Inherited from caller. 2007 * Inherited from caller.
1380 */ 2008 */
1381static int mv_host_init(struct ata_probe_ent *probe_ent) 2009static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2010 unsigned int board_idx)
1382{ 2011{
1383 int rc = 0, n_hc, port, hc; 2012 int rc = 0, n_hc, port, hc;
1384 void __iomem *mmio = probe_ent->mmio_base; 2013 void __iomem *mmio = probe_ent->mmio_base;
1385 void __iomem *port_mmio; 2014 struct mv_host_priv *hpriv = probe_ent->private_data;
1386 2015
1387 if ((MV_FLAG_GLBL_SFT_RST & probe_ent->host_flags) && 2016 /* global interrupt mask */
1388 mv_global_soft_reset(probe_ent->mmio_base)) { 2017 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
1389 rc = 1; 2018
2019 rc = mv_chip_id(pdev, hpriv, board_idx);
2020 if (rc)
1390 goto done; 2021 goto done;
1391 }
1392 2022
1393 n_hc = mv_get_hc_count(probe_ent->host_flags); 2023 n_hc = mv_get_hc_count(probe_ent->host_flags);
1394 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc; 2024 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
1395 2025
2026 for (port = 0; port < probe_ent->n_ports; port++)
2027 hpriv->ops->read_preamp(hpriv, port, mmio);
2028
2029 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2030 if (rc)
2031 goto done;
2032
2033 hpriv->ops->reset_flash(hpriv, mmio);
2034 hpriv->ops->reset_bus(pdev, mmio);
2035 hpriv->ops->enable_leds(hpriv, mmio);
2036
1396 for (port = 0; port < probe_ent->n_ports; port++) { 2037 for (port = 0; port < probe_ent->n_ports; port++) {
1397 port_mmio = mv_port_base(mmio, port); 2038 if (IS_60XX(hpriv)) {
2039 void __iomem *port_mmio = mv_port_base(mmio, port);
2040
2041 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2042 ifctl |= (1 << 12);
2043 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2044 }
2045
2046 hpriv->ops->phy_errata(hpriv, mmio, port);
2047 }
2048
2049 for (port = 0; port < probe_ent->n_ports; port++) {
2050 void __iomem *port_mmio = mv_port_base(mmio, port);
1398 mv_port_init(&probe_ent->port[port], port_mmio); 2051 mv_port_init(&probe_ent->port[port], port_mmio);
1399 } 2052 }
1400 2053
@@ -1418,11 +2071,12 @@ static int mv_host_init(struct ata_probe_ent *probe_ent)
1418 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS); 2071 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
1419 2072
1420 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " 2073 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
1421 "PCI int cause/mask=0x%08x/0x%08x\n", 2074 "PCI int cause/mask=0x%08x/0x%08x\n",
1422 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS), 2075 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
1423 readl(mmio + HC_MAIN_IRQ_MASK_OFS), 2076 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
1424 readl(mmio + PCI_IRQ_CAUSE_OFS), 2077 readl(mmio + PCI_IRQ_CAUSE_OFS),
1425 readl(mmio + PCI_IRQ_MASK_OFS)); 2078 readl(mmio + PCI_IRQ_MASK_OFS));
2079
1426done: 2080done:
1427 return rc; 2081 return rc;
1428} 2082}
@@ -1458,7 +2112,7 @@ static void mv_print_info(struct ata_probe_ent *probe_ent)
1458 2112
1459 dev_printk(KERN_INFO, &pdev->dev, 2113 dev_printk(KERN_INFO, &pdev->dev,
1460 "%u slots %u ports %s mode IRQ via %s\n", 2114 "%u slots %u ports %s mode IRQ via %s\n",
1461 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports, 2115 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
1462 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 2116 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
1463} 2117}
1464 2118
@@ -1528,7 +2182,7 @@ static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1528 probe_ent->private_data = hpriv; 2182 probe_ent->private_data = hpriv;
1529 2183
1530 /* initialize adapter */ 2184 /* initialize adapter */
1531 rc = mv_host_init(probe_ent); 2185 rc = mv_init_host(pdev, probe_ent, board_idx);
1532 if (rc) { 2186 if (rc) {
1533 goto err_out_hpriv; 2187 goto err_out_hpriv;
1534 } 2188 }
diff --git a/drivers/scsi/sata_promise.c b/drivers/scsi/sata_promise.c
index 242d906987ad..8a8e3e3ef0ed 100644
--- a/drivers/scsi/sata_promise.c
+++ b/drivers/scsi/sata_promise.c
@@ -46,7 +46,7 @@
46#include "sata_promise.h" 46#include "sata_promise.h"
47 47
48#define DRV_NAME "sata_promise" 48#define DRV_NAME "sata_promise"
49#define DRV_VERSION "1.02" 49#define DRV_VERSION "1.03"
50 50
51 51
52enum { 52enum {
diff --git a/drivers/scsi/sata_qstor.c b/drivers/scsi/sata_qstor.c
index 4a6d3067d23c..a8987f5ff5cc 100644
--- a/drivers/scsi/sata_qstor.c
+++ b/drivers/scsi/sata_qstor.c
@@ -41,7 +41,7 @@
41#include <linux/libata.h> 41#include <linux/libata.h>
42 42
43#define DRV_NAME "sata_qstor" 43#define DRV_NAME "sata_qstor"
44#define DRV_VERSION "0.04" 44#define DRV_VERSION "0.05"
45 45
46enum { 46enum {
47 QS_PORTS = 4, 47 QS_PORTS = 4,
diff --git a/drivers/scsi/sata_sil24.c b/drivers/scsi/sata_sil24.c
index 55e744d6db88..e0d6f194f54f 100644
--- a/drivers/scsi/sata_sil24.c
+++ b/drivers/scsi/sata_sil24.c
@@ -5,17 +5,6 @@
5 * 5 *
6 * Based on preview driver from Silicon Image. 6 * Based on preview driver from Silicon Image.
7 * 7 *
8 * NOTE: No NCQ/ATAPI support yet. The preview driver didn't support
9 * NCQ nor ATAPI, and, unfortunately, I couldn't find out how to make
10 * those work. Enabling those shouldn't be difficult. Basic
11 * structure is all there (in libata-dev tree). If you have any
12 * information about this hardware, please contact me or linux-ide.
13 * Info is needed on...
14 *
15 * - How to issue tagged commands and turn on sactive on issue accordingly.
16 * - Where to put an ATAPI command and how to tell the device to send it.
17 * - How to enable/use 64bit.
18 *
19 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2, or (at your option) any 10 * Free Software Foundation; either version 2, or (at your option) any
@@ -42,7 +31,7 @@
42#include <asm/io.h> 31#include <asm/io.h>
43 32
44#define DRV_NAME "sata_sil24" 33#define DRV_NAME "sata_sil24"
45#define DRV_VERSION "0.22" /* Silicon Image's preview driver was 0.10 */ 34#define DRV_VERSION "0.23"
46 35
47/* 36/*
48 * Port request block (PRB) 32 bytes 37 * Port request block (PRB) 32 bytes
@@ -139,6 +128,7 @@ enum {
139 PORT_CS_DEV_RST = (1 << 1), /* device reset */ 128 PORT_CS_DEV_RST = (1 << 1), /* device reset */
140 PORT_CS_INIT = (1 << 2), /* port initialize */ 129 PORT_CS_INIT = (1 << 2), /* port initialize */
141 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ 130 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
131 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
142 PORT_CS_RESUME = (1 << 6), /* port resume */ 132 PORT_CS_RESUME = (1 << 6), /* port resume */
143 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ 133 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
144 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */ 134 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
@@ -188,11 +178,29 @@ enum {
188 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ 178 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
189 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ 179 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
190 180
181 /* bits of PRB control field */
182 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
183 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
184 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
185 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
186 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
187
188 /* PRB protocol field */
189 PRB_PROT_PACKET = (1 << 0),
190 PRB_PROT_TCQ = (1 << 1),
191 PRB_PROT_NCQ = (1 << 2),
192 PRB_PROT_READ = (1 << 3),
193 PRB_PROT_WRITE = (1 << 4),
194 PRB_PROT_TRANSPARENT = (1 << 5),
195
191 /* 196 /*
192 * Other constants 197 * Other constants
193 */ 198 */
194 SGE_TRM = (1 << 31), /* Last SGE in chain */ 199 SGE_TRM = (1 << 31), /* Last SGE in chain */
195 PRB_SOFT_RST = (1 << 7), /* Soft reset request (ign BSY?) */ 200 SGE_LNK = (1 << 30), /* linked list
201 Points to SGT, not SGE */
202 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
203 data address ignored */
196 204
197 /* board id */ 205 /* board id */
198 BID_SIL3124 = 0, 206 BID_SIL3124 = 0,
@@ -202,11 +210,22 @@ enum {
202 IRQ_STAT_4PORTS = 0xf, 210 IRQ_STAT_4PORTS = 0xf,
203}; 211};
204 212
205struct sil24_cmd_block { 213struct sil24_ata_block {
206 struct sil24_prb prb; 214 struct sil24_prb prb;
207 struct sil24_sge sge[LIBATA_MAX_PRD]; 215 struct sil24_sge sge[LIBATA_MAX_PRD];
208}; 216};
209 217
218struct sil24_atapi_block {
219 struct sil24_prb prb;
220 u8 cdb[16];
221 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
222};
223
224union sil24_cmd_block {
225 struct sil24_ata_block ata;
226 struct sil24_atapi_block atapi;
227};
228
210/* 229/*
211 * ap->private_data 230 * ap->private_data
212 * 231 *
@@ -214,7 +233,7 @@ struct sil24_cmd_block {
214 * here from the previous interrupt. 233 * here from the previous interrupt.
215 */ 234 */
216struct sil24_port_priv { 235struct sil24_port_priv {
217 struct sil24_cmd_block *cmd_block; /* 32 cmd blocks */ 236 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
218 dma_addr_t cmd_block_dma; /* DMA base addr for them */ 237 dma_addr_t cmd_block_dma; /* DMA base addr for them */
219 struct ata_taskfile tf; /* Cached taskfile registers */ 238 struct ata_taskfile tf; /* Cached taskfile registers */
220}; 239};
@@ -225,6 +244,7 @@ struct sil24_host_priv {
225 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */ 244 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
226}; 245};
227 246
247static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev);
228static u8 sil24_check_status(struct ata_port *ap); 248static u8 sil24_check_status(struct ata_port *ap);
229static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); 249static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
230static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); 250static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
@@ -278,6 +298,8 @@ static struct scsi_host_template sil24_sht = {
278static const struct ata_port_operations sil24_ops = { 298static const struct ata_port_operations sil24_ops = {
279 .port_disable = ata_port_disable, 299 .port_disable = ata_port_disable,
280 300
301 .dev_config = sil24_dev_config,
302
281 .check_status = sil24_check_status, 303 .check_status = sil24_check_status,
282 .check_altstatus = sil24_check_status, 304 .check_altstatus = sil24_check_status,
283 .dev_select = ata_noop_dev_select, 305 .dev_select = ata_noop_dev_select,
@@ -314,7 +336,7 @@ static struct ata_port_info sil24_port_info[] = {
314 { 336 {
315 .sht = &sil24_sht, 337 .sht = &sil24_sht,
316 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 338 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
317 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO | 339 ATA_FLAG_SRST | ATA_FLAG_MMIO |
318 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(4), 340 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(4),
319 .pio_mask = 0x1f, /* pio0-4 */ 341 .pio_mask = 0x1f, /* pio0-4 */
320 .mwdma_mask = 0x07, /* mwdma0-2 */ 342 .mwdma_mask = 0x07, /* mwdma0-2 */
@@ -325,7 +347,7 @@ static struct ata_port_info sil24_port_info[] = {
325 { 347 {
326 .sht = &sil24_sht, 348 .sht = &sil24_sht,
327 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 349 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
328 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO | 350 ATA_FLAG_SRST | ATA_FLAG_MMIO |
329 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(2), 351 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(2),
330 .pio_mask = 0x1f, /* pio0-4 */ 352 .pio_mask = 0x1f, /* pio0-4 */
331 .mwdma_mask = 0x07, /* mwdma0-2 */ 353 .mwdma_mask = 0x07, /* mwdma0-2 */
@@ -336,7 +358,7 @@ static struct ata_port_info sil24_port_info[] = {
336 { 358 {
337 .sht = &sil24_sht, 359 .sht = &sil24_sht,
338 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 360 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
339 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO | 361 ATA_FLAG_SRST | ATA_FLAG_MMIO |
340 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(1), 362 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(1),
341 .pio_mask = 0x1f, /* pio0-4 */ 363 .pio_mask = 0x1f, /* pio0-4 */
342 .mwdma_mask = 0x07, /* mwdma0-2 */ 364 .mwdma_mask = 0x07, /* mwdma0-2 */
@@ -345,6 +367,16 @@ static struct ata_port_info sil24_port_info[] = {
345 }, 367 },
346}; 368};
347 369
370static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
371{
372 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
373
374 if (ap->cdb_len == 16)
375 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
376 else
377 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
378}
379
348static inline void sil24_update_tf(struct ata_port *ap) 380static inline void sil24_update_tf(struct ata_port *ap)
349{ 381{
350 struct sil24_port_priv *pp = ap->private_data; 382 struct sil24_port_priv *pp = ap->private_data;
@@ -396,22 +428,73 @@ static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
396 *tf = pp->tf; 428 *tf = pp->tf;
397} 429}
398 430
399static void sil24_phy_reset(struct ata_port *ap) 431static int sil24_issue_SRST(struct ata_port *ap)
400{ 432{
401 __sata_phy_reset(ap); 433 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
434 struct sil24_port_priv *pp = ap->private_data;
435 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
436 dma_addr_t paddr = pp->cmd_block_dma;
437 u32 irq_enable, irq_stat;
438 int cnt;
439
440 /* temporarily turn off IRQs during SRST */
441 irq_enable = readl(port + PORT_IRQ_ENABLE_SET);
442 writel(irq_enable, port + PORT_IRQ_ENABLE_CLR);
443
402 /* 444 /*
403 * No ATAPI yet. Just unconditionally indicate ATA device. 445 * XXX: Not sure whether the following sleep is needed or not.
404 * If ATAPI device is attached, it will fail ATA_CMD_ID_ATA 446 * The original driver had it. So....
405 * and libata core will ignore the device.
406 */ 447 */
407 if (!(ap->flags & ATA_FLAG_PORT_DISABLED)) 448 msleep(10);
408 ap->device[0].class = ATA_DEV_ATA; 449
450 prb->ctrl = PRB_CTRL_SRST;
451 prb->fis[1] = 0; /* no PM yet */
452
453 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
454
455 for (cnt = 0; cnt < 100; cnt++) {
456 irq_stat = readl(port + PORT_IRQ_STAT);
457 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
458
459 irq_stat >>= PORT_IRQ_RAW_SHIFT;
460 if (irq_stat & (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR))
461 break;
462
463 msleep(1);
464 }
465
466 /* restore IRQs */
467 writel(irq_enable, port + PORT_IRQ_ENABLE_SET);
468
469 if (!(irq_stat & PORT_IRQ_COMPLETE))
470 return -1;
471
472 /* update TF */
473 sil24_update_tf(ap);
474 return 0;
475}
476
477static void sil24_phy_reset(struct ata_port *ap)
478{
479 struct sil24_port_priv *pp = ap->private_data;
480
481 __sata_phy_reset(ap);
482 if (ap->flags & ATA_FLAG_PORT_DISABLED)
483 return;
484
485 if (sil24_issue_SRST(ap) < 0) {
486 printk(KERN_ERR DRV_NAME
487 " ata%u: SRST failed, disabling port\n", ap->id);
488 ap->ops->port_disable(ap);
489 return;
490 }
491
492 ap->device->class = ata_dev_classify(&pp->tf);
409} 493}
410 494
411static inline void sil24_fill_sg(struct ata_queued_cmd *qc, 495static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
412 struct sil24_cmd_block *cb) 496 struct sil24_sge *sge)
413{ 497{
414 struct sil24_sge *sge = cb->sge;
415 struct scatterlist *sg; 498 struct scatterlist *sg;
416 unsigned int idx = 0; 499 unsigned int idx = 0;
417 500
@@ -432,23 +515,47 @@ static void sil24_qc_prep(struct ata_queued_cmd *qc)
432{ 515{
433 struct ata_port *ap = qc->ap; 516 struct ata_port *ap = qc->ap;
434 struct sil24_port_priv *pp = ap->private_data; 517 struct sil24_port_priv *pp = ap->private_data;
435 struct sil24_cmd_block *cb = pp->cmd_block + qc->tag; 518 union sil24_cmd_block *cb = pp->cmd_block + qc->tag;
436 struct sil24_prb *prb = &cb->prb; 519 struct sil24_prb *prb;
520 struct sil24_sge *sge;
437 521
438 switch (qc->tf.protocol) { 522 switch (qc->tf.protocol) {
439 case ATA_PROT_PIO: 523 case ATA_PROT_PIO:
440 case ATA_PROT_DMA: 524 case ATA_PROT_DMA:
441 case ATA_PROT_NODATA: 525 case ATA_PROT_NODATA:
526 prb = &cb->ata.prb;
527 sge = cb->ata.sge;
528 prb->ctrl = 0;
529 break;
530
531 case ATA_PROT_ATAPI:
532 case ATA_PROT_ATAPI_DMA:
533 case ATA_PROT_ATAPI_NODATA:
534 prb = &cb->atapi.prb;
535 sge = cb->atapi.sge;
536 memset(cb->atapi.cdb, 0, 32);
537 memcpy(cb->atapi.cdb, qc->cdb, ap->cdb_len);
538
539 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
540 if (qc->tf.flags & ATA_TFLAG_WRITE)
541 prb->ctrl = PRB_CTRL_PACKET_WRITE;
542 else
543 prb->ctrl = PRB_CTRL_PACKET_READ;
544 } else
545 prb->ctrl = 0;
546
442 break; 547 break;
548
443 default: 549 default:
444 /* ATAPI isn't supported yet */ 550 prb = NULL; /* shut up, gcc */
551 sge = NULL;
445 BUG(); 552 BUG();
446 } 553 }
447 554
448 ata_tf_to_fis(&qc->tf, prb->fis, 0); 555 ata_tf_to_fis(&qc->tf, prb->fis, 0);
449 556
450 if (qc->flags & ATA_QCFLAG_DMAMAP) 557 if (qc->flags & ATA_QCFLAG_DMAMAP)
451 sil24_fill_sg(qc, cb); 558 sil24_fill_sg(qc, sge);
452} 559}
453 560
454static int sil24_qc_issue(struct ata_queued_cmd *qc) 561static int sil24_qc_issue(struct ata_queued_cmd *qc)
@@ -467,6 +574,31 @@ static void sil24_irq_clear(struct ata_port *ap)
467 /* unused */ 574 /* unused */
468} 575}
469 576
577static int __sil24_restart_controller(void __iomem *port)
578{
579 u32 tmp;
580 int cnt;
581
582 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
583
584 /* Max ~10ms */
585 for (cnt = 0; cnt < 10000; cnt++) {
586 tmp = readl(port + PORT_CTRL_STAT);
587 if (tmp & PORT_CS_RDY)
588 return 0;
589 udelay(1);
590 }
591
592 return -1;
593}
594
595static void sil24_restart_controller(struct ata_port *ap)
596{
597 if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr))
598 printk(KERN_ERR DRV_NAME
599 " ata%u: failed to restart controller\n", ap->id);
600}
601
470static int __sil24_reset_controller(void __iomem *port) 602static int __sil24_reset_controller(void __iomem *port)
471{ 603{
472 int cnt; 604 int cnt;
@@ -486,7 +618,11 @@ static int __sil24_reset_controller(void __iomem *port)
486 618
487 if (tmp & PORT_CS_DEV_RST) 619 if (tmp & PORT_CS_DEV_RST)
488 return -1; 620 return -1;
489 return 0; 621
622 if (tmp & PORT_CS_RDY)
623 return 0;
624
625 return __sil24_restart_controller(port);
490} 626}
491 627
492static void sil24_reset_controller(struct ata_port *ap) 628static void sil24_reset_controller(struct ata_port *ap)
@@ -548,9 +684,15 @@ static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
548 if (serror) 684 if (serror)
549 writel(serror, port + PORT_SERROR); 685 writel(serror, port + PORT_SERROR);
550 686
551 printk(KERN_ERR DRV_NAME " ata%u: error interrupt on port%d\n" 687 /*
552 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n", 688 * Don't log ATAPI device errors. They're supposed to happen
553 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror); 689 * and any serious errors will be logged using sense data by
690 * the SCSI layer.
691 */
692 if (ap->device[0].class != ATA_DEV_ATAPI || cmd_err > PORT_CERR_SDB)
693 printk("ata%u: error interrupt on port%d\n"
694 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
695 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
554 696
555 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) { 697 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
556 /* 698 /*
@@ -558,6 +700,7 @@ static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
558 */ 700 */
559 sil24_update_tf(ap); 701 sil24_update_tf(ap);
560 err_mask = ac_err_mask(pp->tf.command); 702 err_mask = ac_err_mask(pp->tf.command);
703 sil24_restart_controller(ap);
561 } else { 704 } else {
562 /* 705 /*
563 * Other errors. libata currently doesn't have any 706 * Other errors. libata currently doesn't have any
@@ -565,12 +708,11 @@ static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
565 * ATA_ERR. 708 * ATA_ERR.
566 */ 709 */
567 err_mask = AC_ERR_OTHER; 710 err_mask = AC_ERR_OTHER;
711 sil24_reset_controller(ap);
568 } 712 }
569 713
570 if (qc) 714 if (qc)
571 ata_qc_complete(qc, err_mask); 715 ata_qc_complete(qc, err_mask);
572
573 sil24_reset_controller(ap);
574} 716}
575 717
576static inline void sil24_host_intr(struct ata_port *ap) 718static inline void sil24_host_intr(struct ata_port *ap)
@@ -646,7 +788,7 @@ static int sil24_port_start(struct ata_port *ap)
646{ 788{
647 struct device *dev = ap->host_set->dev; 789 struct device *dev = ap->host_set->dev;
648 struct sil24_port_priv *pp; 790 struct sil24_port_priv *pp;
649 struct sil24_cmd_block *cb; 791 union sil24_cmd_block *cb;
650 size_t cb_size = sizeof(*cb); 792 size_t cb_size = sizeof(*cb);
651 dma_addr_t cb_dma; 793 dma_addr_t cb_dma;
652 int rc = -ENOMEM; 794 int rc = -ENOMEM;
diff --git a/drivers/scsi/sata_svw.c b/drivers/scsi/sata_svw.c
index 57e5a9d964c3..6e7f7c83a75a 100644
--- a/drivers/scsi/sata_svw.c
+++ b/drivers/scsi/sata_svw.c
@@ -54,7 +54,7 @@
54#endif /* CONFIG_PPC_OF */ 54#endif /* CONFIG_PPC_OF */
55 55
56#define DRV_NAME "sata_svw" 56#define DRV_NAME "sata_svw"
57#define DRV_VERSION "1.06" 57#define DRV_VERSION "1.07"
58 58
59/* Taskfile registers offsets */ 59/* Taskfile registers offsets */
60#define K2_SATA_TF_CMD_OFFSET 0x00 60#define K2_SATA_TF_CMD_OFFSET 0x00
diff --git a/drivers/scsi/sata_sx4.c b/drivers/scsi/sata_sx4.c
index b4bbe48acab0..dcc3ad9a9d6e 100644
--- a/drivers/scsi/sata_sx4.c
+++ b/drivers/scsi/sata_sx4.c
@@ -46,7 +46,7 @@
46#include "sata_promise.h" 46#include "sata_promise.h"
47 47
48#define DRV_NAME "sata_sx4" 48#define DRV_NAME "sata_sx4"
49#define DRV_VERSION "0.7" 49#define DRV_VERSION "0.8"
50 50
51 51
52enum { 52enum {
diff --git a/drivers/scsi/sata_vsc.c b/drivers/scsi/sata_vsc.c
index 77a6e4b9262d..fcfa486965b4 100644
--- a/drivers/scsi/sata_vsc.c
+++ b/drivers/scsi/sata_vsc.c
@@ -47,7 +47,7 @@
47#include <linux/libata.h> 47#include <linux/libata.h>
48 48
49#define DRV_NAME "sata_vsc" 49#define DRV_NAME "sata_vsc"
50#define DRV_VERSION "1.0" 50#define DRV_VERSION "1.1"
51 51
52/* Interrupt register offsets (from chip base address) */ 52/* Interrupt register offsets (from chip base address) */
53#define VSC_SATA_INT_STAT_OFFSET 0x00 53#define VSC_SATA_INT_STAT_OFFSET 0x00
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 05:13:52 -0500