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1/*
2 * Universal Flash Storage Host controller driver
3 *
4 * This code is based on drivers/scsi/ufs/ufshci.h
5 * Copyright (C) 2011-2012 Samsung India Software Operations
6 *
7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * NO WARRANTY
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
30
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
43 * USA.
44 */
45
46#ifndef _UFSHCI_H
47#define _UFSHCI_H
48
49enum {
50 TASK_REQ_UPIU_SIZE_DWORDS = 8,
51 TASK_RSP_UPIU_SIZE_DWORDS = 8,
52 ALIGNED_UPIU_SIZE = 128,
53};
54
55/* UFSHCI Registers */
56enum {
57 REG_CONTROLLER_CAPABILITIES = 0x00,
58 REG_UFS_VERSION = 0x08,
59 REG_CONTROLLER_DEV_ID = 0x10,
60 REG_CONTROLLER_PROD_ID = 0x14,
61 REG_INTERRUPT_STATUS = 0x20,
62 REG_INTERRUPT_ENABLE = 0x24,
63 REG_CONTROLLER_STATUS = 0x30,
64 REG_CONTROLLER_ENABLE = 0x34,
65 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
66 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
67 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
68 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
69 REG_UIC_ERROR_CODE_DME = 0x48,
70 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
71 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
72 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
73 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
74 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
75 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
76 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
77 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
78 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
79 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
80 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
81 REG_UIC_COMMAND = 0x90,
82 REG_UIC_COMMAND_ARG_1 = 0x94,
83 REG_UIC_COMMAND_ARG_2 = 0x98,
84 REG_UIC_COMMAND_ARG_3 = 0x9C,
85};
86
87/* Controller capability masks */
88enum {
89 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
90 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
91 MASK_64_ADDRESSING_SUPPORT = 0x01000000,
92 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
93 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
94};
95
96/* UFS Version 08h */
97#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
98#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
99
100/* Controller UFSHCI version */
101enum {
102 UFSHCI_VERSION_10 = 0x00010000,
103 UFSHCI_VERSION_11 = 0x00010100,
104};
105
106/*
107 * HCDDID - Host Controller Identification Descriptor
108 * - Device ID and Device Class 10h
109 */
110#define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
111#define DEVICE_ID UFS_MASK(0xFF, 24)
112
113/*
114 * HCPMID - Host Controller Identification Descriptor
115 * - Product/Manufacturer ID 14h
116 */
117#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
118#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
119
120#define UFS_BIT(x) (1L << (x))
121
122#define UTP_TRANSFER_REQ_COMPL UFS_BIT(0)
123#define UIC_DME_END_PT_RESET UFS_BIT(1)
124#define UIC_ERROR UFS_BIT(2)
125#define UIC_TEST_MODE UFS_BIT(3)
126#define UIC_POWER_MODE UFS_BIT(4)
127#define UIC_HIBERNATE_EXIT UFS_BIT(5)
128#define UIC_HIBERNATE_ENTER UFS_BIT(6)
129#define UIC_LINK_LOST UFS_BIT(7)
130#define UIC_LINK_STARTUP UFS_BIT(8)
131#define UTP_TASK_REQ_COMPL UFS_BIT(9)
132#define UIC_COMMAND_COMPL UFS_BIT(10)
133#define DEVICE_FATAL_ERROR UFS_BIT(11)
134#define CONTROLLER_FATAL_ERROR UFS_BIT(16)
135#define SYSTEM_BUS_FATAL_ERROR UFS_BIT(17)
136
137#define UFSHCD_ERROR_MASK (UIC_ERROR |\
138 DEVICE_FATAL_ERROR |\
139 CONTROLLER_FATAL_ERROR |\
140 SYSTEM_BUS_FATAL_ERROR)
141
142#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
143 CONTROLLER_FATAL_ERROR |\
144 SYSTEM_BUS_FATAL_ERROR)
145
146/* HCS - Host Controller Status 30h */
147#define DEVICE_PRESENT UFS_BIT(0)
148#define UTP_TRANSFER_REQ_LIST_READY UFS_BIT(1)
149#define UTP_TASK_REQ_LIST_READY UFS_BIT(2)
150#define UIC_COMMAND_READY UFS_BIT(3)
151#define HOST_ERROR_INDICATOR UFS_BIT(4)
152#define DEVICE_ERROR_INDICATOR UFS_BIT(5)
153#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
154
155/* HCE - Host Controller Enable 34h */
156#define CONTROLLER_ENABLE UFS_BIT(0)
157#define CONTROLLER_DISABLE 0x0
158
159/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
160#define UIC_PHY_ADAPTER_LAYER_ERROR UFS_BIT(31)
161#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
162
163/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
164#define UIC_DATA_LINK_LAYER_ERROR UFS_BIT(31)
165#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0x7FFF
166#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
167
168/* UECN - Host UIC Error Code Network Layer 40h */
169#define UIC_NETWORK_LAYER_ERROR UFS_BIT(31)
170#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
171
172/* UECT - Host UIC Error Code Transport Layer 44h */
173#define UIC_TRANSPORT_LAYER_ERROR UFS_BIT(31)
174#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
175
176/* UECDME - Host UIC Error Code DME 48h */
177#define UIC_DME_ERROR UFS_BIT(31)
178#define UIC_DME_ERROR_CODE_MASK 0x1
179
180#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
181#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
182#define INT_AGGR_COUNTER_AND_TIMER_RESET UFS_BIT(16)
183#define INT_AGGR_STATUS_BIT UFS_BIT(20)
184#define INT_AGGR_PARAM_WRITE UFS_BIT(24)
185#define INT_AGGR_ENABLE UFS_BIT(31)
186
187/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
188#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT UFS_BIT(0)
189
190/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
191#define UTP_TASK_REQ_LIST_RUN_STOP_BIT UFS_BIT(0)
192
193/* UICCMD - UIC Command */
194#define COMMAND_OPCODE_MASK 0xFF
195#define GEN_SELECTOR_INDEX_MASK 0xFFFF
196
197#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
198#define RESET_LEVEL 0xFF
199
200#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
201#define CONFIG_RESULT_CODE_MASK 0xFF
202#define GENERIC_ERROR_CODE_MASK 0xFF
203
204/* UIC Commands */
205enum {
206 UIC_CMD_DME_GET = 0x01,
207 UIC_CMD_DME_SET = 0x02,
208 UIC_CMD_DME_PEER_GET = 0x03,
209 UIC_CMD_DME_PEER_SET = 0x04,
210 UIC_CMD_DME_POWERON = 0x10,
211 UIC_CMD_DME_POWEROFF = 0x11,
212 UIC_CMD_DME_ENABLE = 0x12,
213 UIC_CMD_DME_RESET = 0x14,
214 UIC_CMD_DME_END_PT_RST = 0x15,
215 UIC_CMD_DME_LINK_STARTUP = 0x16,
216 UIC_CMD_DME_HIBER_ENTER = 0x17,
217 UIC_CMD_DME_HIBER_EXIT = 0x18,
218 UIC_CMD_DME_TEST_MODE = 0x1A,
219};
220
221/* UIC Config result code / Generic error code */
222enum {
223 UIC_CMD_RESULT_SUCCESS = 0x00,
224 UIC_CMD_RESULT_INVALID_ATTR = 0x01,
225 UIC_CMD_RESULT_FAILURE = 0x01,
226 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
227 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
228 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
229 UIC_CMD_RESULT_BAD_INDEX = 0x05,
230 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
231 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
232 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
233 UIC_CMD_RESULT_BUSY = 0x09,
234 UIC_CMD_RESULT_DME_FAILURE = 0x0A,
235};
236
237#define MASK_UIC_COMMAND_RESULT 0xFF
238
239#define INT_AGGR_COUNTER_THRESHOLD_VALUE (0x1F << 8)
240#define INT_AGGR_TIMEOUT_VALUE (0x02)
241
242/* Interrupt disable masks */
243enum {
244 /* Interrupt disable mask for UFSHCI v1.0 */
245 INTERRUPT_DISABLE_MASK_10 = 0xFFFF,
246
247 /* Interrupt disable mask for UFSHCI v1.1 */
248 INTERRUPT_DISABLE_MASK_11 = 0x0,
249};
250
251/*
252 * Request Descriptor Definitions
253 */
254
255/* Transfer request command type */
256enum {
257 UTP_CMD_TYPE_SCSI = 0x0,
258 UTP_CMD_TYPE_UFS = 0x1,
259 UTP_CMD_TYPE_DEV_MANAGE = 0x2,
260};
261
262enum {
263 UTP_SCSI_COMMAND = 0x00000000,
264 UTP_NATIVE_UFS_COMMAND = 0x10000000,
265 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
266 UTP_REQ_DESC_INT_CMD = 0x01000000,
267};
268
269/* UTP Transfer Request Data Direction (DD) */
270enum {
271 UTP_NO_DATA_TRANSFER = 0x00000000,
272 UTP_HOST_TO_DEVICE = 0x02000000,
273 UTP_DEVICE_TO_HOST = 0x04000000,
274};
275
276/* Overall command status values */
277enum {
278 OCS_SUCCESS = 0x0,
279 OCS_INVALID_CMD_TABLE_ATTR = 0x1,
280 OCS_INVALID_PRDT_ATTR = 0x2,
281 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
282 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
283 OCS_PEER_COMM_FAILURE = 0x5,
284 OCS_ABORTED = 0x6,
285 OCS_FATAL_ERROR = 0x7,
286 OCS_INVALID_COMMAND_STATUS = 0x0F,
287 MASK_OCS = 0x0F,
288};
289
290/**
291 * struct ufshcd_sg_entry - UFSHCI PRD Entry
292 * @base_addr: Lower 32bit physical address DW-0
293 * @upper_addr: Upper 32bit physical address DW-1
294 * @reserved: Reserved for future use DW-2
295 * @size: size of physical segment DW-3
296 */
297struct ufshcd_sg_entry {
298 u32 base_addr;
299 u32 upper_addr;
300 u32 reserved;
301 u32 size;
302};
303
304/**
305 * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
306 * @command_upiu: Command UPIU Frame address
307 * @response_upiu: Response UPIU Frame address
308 * @prd_table: Physical Region Descriptor
309 */
310struct utp_transfer_cmd_desc {
311 u8 command_upiu[ALIGNED_UPIU_SIZE];
312 u8 response_upiu[ALIGNED_UPIU_SIZE];
313 struct ufshcd_sg_entry prd_table[SG_ALL];
314};
315
316/**
317 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
318 * @dword0: Descriptor Header DW0
319 * @dword1: Descriptor Header DW1
320 * @dword2: Descriptor Header DW2
321 * @dword3: Descriptor Header DW3
322 */
323struct request_desc_header {
324 u32 dword_0;
325 u32 dword_1;
326 u32 dword_2;
327 u32 dword_3;
328};
329
330/**
331 * struct utp_transfer_req_desc - UTRD structure
332 * @header: UTRD header DW-0 to DW-3
333 * @command_desc_base_addr_lo: UCD base address low DW-4
334 * @command_desc_base_addr_hi: UCD base address high DW-5
335 * @response_upiu_length: response UPIU length DW-6
336 * @response_upiu_offset: response UPIU offset DW-6
337 * @prd_table_length: Physical region descriptor length DW-7
338 * @prd_table_offset: Physical region descriptor offset DW-7
339 */
340struct utp_transfer_req_desc {
341
342 /* DW 0-3 */
343 struct request_desc_header header;
344
345 /* DW 4-5*/
346 u32 command_desc_base_addr_lo;
347 u32 command_desc_base_addr_hi;
348
349 /* DW 6 */
350 u16 response_upiu_length;
351 u16 response_upiu_offset;
352
353 /* DW 7 */
354 u16 prd_table_length;
355 u16 prd_table_offset;
356};
357
358/**
359 * struct utp_task_req_desc - UTMRD structure
360 * @header: UTMRD header DW-0 to DW-3
361 * @task_req_upiu: Pointer to task request UPIU DW-4 to DW-11
362 * @task_rsp_upiu: Pointer to task response UPIU DW12 to DW-19
363 */
364struct utp_task_req_desc {
365
366 /* DW 0-3 */
367 struct request_desc_header header;
368
369 /* DW 4-11 */
370 u32 task_req_upiu[TASK_REQ_UPIU_SIZE_DWORDS];
371
372 /* DW 12-19 */
373 u32 task_rsp_upiu[TASK_RSP_UPIU_SIZE_DWORDS];
374};
375
376#endif /* End of Header */