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-rw-r--r--drivers/scsi/stex.c1252
1 files changed, 1252 insertions, 0 deletions
diff --git a/drivers/scsi/stex.c b/drivers/scsi/stex.c
new file mode 100644
index 000000000000..3cf3106a29b8
--- /dev/null
+++ b/drivers/scsi/stex.c
@@ -0,0 +1,1252 @@
1/*
2 * SuperTrak EX Series Storage Controller driver for Linux
3 *
4 * Copyright (C) 2005, 2006 Promise Technology Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Written By:
12 * Ed Lin <promise_linux@promise.com>
13 *
14 * Version: 2.9.0.13
15 *
16 */
17
18#include <linux/init.h>
19#include <linux/errno.h>
20#include <linux/kernel.h>
21#include <linux/delay.h>
22#include <linux/sched.h>
23#include <linux/time.h>
24#include <linux/pci.h>
25#include <linux/blkdev.h>
26#include <linux/interrupt.h>
27#include <linux/types.h>
28#include <linux/module.h>
29#include <linux/spinlock.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/byteorder.h>
33#include <scsi/scsi.h>
34#include <scsi/scsi_device.h>
35#include <scsi/scsi_cmnd.h>
36#include <scsi/scsi_host.h>
37#include <scsi/scsi_tcq.h>
38
39#define DRV_NAME "stex"
40#define ST_DRIVER_VERSION "2.9.0.13"
41#define ST_VER_MAJOR 2
42#define ST_VER_MINOR 9
43#define ST_OEM 0
44#define ST_BUILD_VER 13
45
46enum {
47 /* MU register offset */
48 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
49 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
50 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
51 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
52 IDBL = 0x20, /* MU_INBOUND_DOORBELL */
53 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
54 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
55 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
56 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
57 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
58
59 /* MU register value */
60 MU_INBOUND_DOORBELL_HANDSHAKE = 1,
61 MU_INBOUND_DOORBELL_REQHEADCHANGED = 2,
62 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4,
63 MU_INBOUND_DOORBELL_HMUSTOPPED = 8,
64 MU_INBOUND_DOORBELL_RESET = 16,
65
66 MU_OUTBOUND_DOORBELL_HANDSHAKE = 1,
67 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
68 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4,
69 MU_OUTBOUND_DOORBELL_BUSCHANGE = 8,
70 MU_OUTBOUND_DOORBELL_HASEVENT = 16,
71
72 /* MU status code */
73 MU_STATE_STARTING = 1,
74 MU_STATE_FMU_READY_FOR_HANDSHAKE = 2,
75 MU_STATE_SEND_HANDSHAKE_FRAME = 3,
76 MU_STATE_STARTED = 4,
77 MU_STATE_RESETTING = 5,
78
79 MU_MAX_DELAY_TIME = 240000,
80 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
81 HMU_PARTNER_TYPE = 2,
82
83 /* firmware returned values */
84 SRB_STATUS_SUCCESS = 0x01,
85 SRB_STATUS_ERROR = 0x04,
86 SRB_STATUS_BUSY = 0x05,
87 SRB_STATUS_INVALID_REQUEST = 0x06,
88 SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
89 SRB_SEE_SENSE = 0x80,
90
91 /* task attribute */
92 TASK_ATTRIBUTE_SIMPLE = 0x0,
93 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
94 TASK_ATTRIBUTE_ORDERED = 0x2,
95 TASK_ATTRIBUTE_ACA = 0x4,
96
97 /* request count, etc. */
98 MU_MAX_REQUEST = 32,
99
100 /* one message wasted, use MU_MAX_REQUEST+1
101 to handle MU_MAX_REQUEST messages */
102 MU_REQ_COUNT = (MU_MAX_REQUEST + 1),
103 MU_STATUS_COUNT = (MU_MAX_REQUEST + 1),
104
105 STEX_CDB_LENGTH = MAX_COMMAND_SIZE,
106 REQ_VARIABLE_LEN = 1024,
107 STATUS_VAR_LEN = 128,
108 ST_CAN_QUEUE = MU_MAX_REQUEST,
109 ST_CMD_PER_LUN = MU_MAX_REQUEST,
110 ST_MAX_SG = 32,
111
112 /* sg flags */
113 SG_CF_EOT = 0x80, /* end of table */
114 SG_CF_64B = 0x40, /* 64 bit item */
115 SG_CF_HOST = 0x20, /* sg in host memory */
116
117 ST_MAX_ARRAY_SUPPORTED = 16,
118 ST_MAX_TARGET_NUM = (ST_MAX_ARRAY_SUPPORTED+1),
119 ST_MAX_LUN_PER_TARGET = 16,
120
121 st_shasta = 0,
122 st_vsc = 1,
123
124 PASSTHRU_REQ_TYPE = 0x00000001,
125 PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
126 ST_INTERNAL_TIMEOUT = 30,
127
128 /* vendor specific commands of Promise */
129 ARRAY_CMD = 0xe0,
130 CONTROLLER_CMD = 0xe1,
131 DEBUGGING_CMD = 0xe2,
132 PASSTHRU_CMD = 0xe3,
133
134 PASSTHRU_GET_ADAPTER = 0x05,
135 PASSTHRU_GET_DRVVER = 0x10,
136 CTLR_POWER_STATE_CHANGE = 0x0e,
137 CTLR_POWER_SAVING = 0x01,
138
139 PASSTHRU_SIGNATURE = 0x4e415041,
140
141 INQUIRY_EVPD = 0x01,
142};
143
144struct st_sgitem {
145 u8 ctrl; /* SG_CF_xxx */
146 u8 reserved[3];
147 __le32 count;
148 __le32 addr;
149 __le32 addr_hi;
150};
151
152struct st_sgtable {
153 __le16 sg_count;
154 __le16 max_sg_count;
155 __le32 sz_in_byte;
156 struct st_sgitem table[ST_MAX_SG];
157};
158
159struct handshake_frame {
160 __le32 rb_phy; /* request payload queue physical address */
161 __le32 rb_phy_hi;
162 __le16 req_sz; /* size of each request payload */
163 __le16 req_cnt; /* count of reqs the buffer can hold */
164 __le16 status_sz; /* size of each status payload */
165 __le16 status_cnt; /* count of status the buffer can hold */
166 __le32 hosttime; /* seconds from Jan 1, 1970 (GMT) */
167 __le32 hosttime_hi;
168 u8 partner_type; /* who sends this frame */
169 u8 reserved0[7];
170 __le32 partner_ver_major;
171 __le32 partner_ver_minor;
172 __le32 partner_ver_oem;
173 __le32 partner_ver_build;
174 u32 reserved1[4];
175};
176
177struct req_msg {
178 __le16 tag;
179 u8 lun;
180 u8 target;
181 u8 task_attr;
182 u8 task_manage;
183 u8 prd_entry;
184 u8 payload_sz; /* payload size in 4-byte */
185 u8 cdb[STEX_CDB_LENGTH];
186 u8 variable[REQ_VARIABLE_LEN];
187};
188
189struct status_msg {
190 __le16 tag;
191 u8 lun;
192 u8 target;
193 u8 srb_status;
194 u8 scsi_status;
195 u8 reserved;
196 u8 payload_sz; /* payload size in 4-byte */
197 u8 variable[STATUS_VAR_LEN];
198};
199
200struct ver_info {
201 u32 major;
202 u32 minor;
203 u32 oem;
204 u32 build;
205 u32 reserved[2];
206};
207
208struct st_frame {
209 u32 base[6];
210 u32 rom_addr;
211
212 struct ver_info drv_ver;
213 struct ver_info bios_ver;
214
215 u32 bus;
216 u32 slot;
217 u32 irq_level;
218 u32 irq_vec;
219 u32 id;
220 u32 subid;
221
222 u32 dimm_size;
223 u8 dimm_type;
224 u8 reserved[3];
225
226 u32 channel;
227 u32 reserved1;
228};
229
230struct st_drvver {
231 u32 major;
232 u32 minor;
233 u32 oem;
234 u32 build;
235 u32 signature[2];
236 u8 console_id;
237 u8 host_no;
238 u8 reserved0[2];
239 u32 reserved[3];
240};
241
242#define MU_REQ_BUFFER_SIZE (MU_REQ_COUNT * sizeof(struct req_msg))
243#define MU_STATUS_BUFFER_SIZE (MU_STATUS_COUNT * sizeof(struct status_msg))
244#define MU_BUFFER_SIZE (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
245#define STEX_BUFFER_SIZE (MU_BUFFER_SIZE + sizeof(struct st_frame))
246
247struct st_ccb {
248 struct req_msg *req;
249 struct scsi_cmnd *cmd;
250
251 void *sense_buffer;
252 unsigned int sense_bufflen;
253 int sg_count;
254
255 u32 req_type;
256 u8 srb_status;
257 u8 scsi_status;
258};
259
260struct st_hba {
261 void __iomem *mmio_base; /* iomapped PCI memory space */
262 void *dma_mem;
263 dma_addr_t dma_handle;
264
265 struct Scsi_Host *host;
266 struct pci_dev *pdev;
267
268 u32 req_head;
269 u32 req_tail;
270 u32 status_head;
271 u32 status_tail;
272
273 struct status_msg *status_buffer;
274 void *copy_buffer; /* temp buffer for driver-handled commands */
275 struct st_ccb ccb[MU_MAX_REQUEST];
276 struct st_ccb *wait_ccb;
277 wait_queue_head_t waitq;
278
279 unsigned int mu_status;
280 int out_req_cnt;
281
282 unsigned int cardtype;
283};
284
285static const char console_inq_page[] =
286{
287 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
288 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
289 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
290 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
291 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
292 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
293 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
294 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
295};
296
297MODULE_AUTHOR("Ed Lin");
298MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
299MODULE_LICENSE("GPL");
300MODULE_VERSION(ST_DRIVER_VERSION);
301
302static void stex_gettime(__le32 *time)
303{
304 struct timeval tv;
305 do_gettimeofday(&tv);
306
307 *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
308 *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
309}
310
311static struct status_msg *stex_get_status(struct st_hba *hba)
312{
313 struct status_msg *status =
314 hba->status_buffer + hba->status_tail;
315
316 ++hba->status_tail;
317 hba->status_tail %= MU_STATUS_COUNT;
318
319 return status;
320}
321
322static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
323{
324 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
325
326 cmd->sense_buffer[0] = 0x70; /* fixed format, current */
327 cmd->sense_buffer[2] = sk;
328 cmd->sense_buffer[7] = 18 - 8; /* additional sense length */
329 cmd->sense_buffer[12] = asc;
330 cmd->sense_buffer[13] = ascq;
331}
332
333static void stex_invalid_field(struct scsi_cmnd *cmd,
334 void (*done)(struct scsi_cmnd *))
335{
336 /* "Invalid field in cbd" */
337 stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
338 done(cmd);
339}
340
341static struct req_msg *stex_alloc_req(struct st_hba *hba)
342{
343 struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
344 hba->req_head;
345
346 ++hba->req_head;
347 hba->req_head %= MU_REQ_COUNT;
348
349 return req;
350}
351
352static int stex_map_sg(struct st_hba *hba,
353 struct req_msg *req, struct st_ccb *ccb)
354{
355 struct pci_dev *pdev = hba->pdev;
356 struct scsi_cmnd *cmd;
357 dma_addr_t dma_handle;
358 struct scatterlist *src;
359 struct st_sgtable *dst;
360 int i;
361
362 cmd = ccb->cmd;
363 dst = (struct st_sgtable *)req->variable;
364 dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
365 dst->sz_in_byte = cpu_to_le32(cmd->request_bufflen);
366
367 if (cmd->use_sg) {
368 int n_elem;
369
370 src = (struct scatterlist *) cmd->request_buffer;
371 n_elem = pci_map_sg(pdev, src,
372 cmd->use_sg, cmd->sc_data_direction);
373 if (n_elem <= 0)
374 return -EIO;
375
376 ccb->sg_count = n_elem;
377 dst->sg_count = cpu_to_le16((u16)n_elem);
378
379 for (i = 0; i < n_elem; i++, src++) {
380 dst->table[i].count = cpu_to_le32((u32)sg_dma_len(src));
381 dst->table[i].addr =
382 cpu_to_le32(sg_dma_address(src) & 0xffffffff);
383 dst->table[i].addr_hi =
384 cpu_to_le32((sg_dma_address(src) >> 16) >> 16);
385 dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
386 }
387 dst->table[--i].ctrl |= SG_CF_EOT;
388 return 0;
389 }
390
391 dma_handle = pci_map_single(pdev, cmd->request_buffer,
392 cmd->request_bufflen, cmd->sc_data_direction);
393 cmd->SCp.dma_handle = dma_handle;
394
395 ccb->sg_count = 1;
396 dst->sg_count = cpu_to_le16(1);
397 dst->table[0].addr = cpu_to_le32(dma_handle & 0xffffffff);
398 dst->table[0].addr_hi = cpu_to_le32((dma_handle >> 16) >> 16);
399 dst->table[0].count = cpu_to_le32((u32)cmd->request_bufflen);
400 dst->table[0].ctrl = SG_CF_EOT | SG_CF_64B | SG_CF_HOST;
401
402 return 0;
403}
404
405static void stex_internal_copy(struct scsi_cmnd *cmd,
406 const void *src, size_t *count, int sg_count)
407{
408 size_t lcount;
409 size_t len;
410 void *s, *d, *base = NULL;
411 if (*count > cmd->request_bufflen)
412 *count = cmd->request_bufflen;
413 lcount = *count;
414 while (lcount) {
415 len = lcount;
416 s = (void *)src;
417 if (cmd->use_sg) {
418 size_t offset = *count - lcount;
419 s += offset;
420 base = scsi_kmap_atomic_sg(cmd->request_buffer,
421 sg_count, &offset, &len);
422 if (base == NULL) {
423 *count -= lcount;
424 return;
425 }
426 d = base + offset;
427 } else
428 d = cmd->request_buffer;
429
430 memcpy(d, s, len);
431
432 lcount -= len;
433 if (cmd->use_sg)
434 scsi_kunmap_atomic_sg(base);
435 }
436}
437
438static int stex_direct_copy(struct scsi_cmnd *cmd,
439 const void *src, size_t count)
440{
441 struct st_hba *hba = (struct st_hba *) &cmd->device->host->hostdata[0];
442 size_t cp_len = count;
443 int n_elem = 0;
444
445 if (cmd->use_sg) {
446 n_elem = pci_map_sg(hba->pdev, cmd->request_buffer,
447 cmd->use_sg, cmd->sc_data_direction);
448 if (n_elem <= 0)
449 return 0;
450 }
451
452 stex_internal_copy(cmd, src, &cp_len, n_elem);
453
454 if (cmd->use_sg)
455 pci_unmap_sg(hba->pdev, cmd->request_buffer,
456 cmd->use_sg, cmd->sc_data_direction);
457 return cp_len == count;
458}
459
460static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
461{
462 struct st_frame *p;
463 size_t count = sizeof(struct st_frame);
464
465 p = hba->copy_buffer;
466 memset(p->base, 0, sizeof(u32)*6);
467 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
468 p->rom_addr = 0;
469
470 p->drv_ver.major = ST_VER_MAJOR;
471 p->drv_ver.minor = ST_VER_MINOR;
472 p->drv_ver.oem = ST_OEM;
473 p->drv_ver.build = ST_BUILD_VER;
474
475 p->bus = hba->pdev->bus->number;
476 p->slot = hba->pdev->devfn;
477 p->irq_level = 0;
478 p->irq_vec = hba->pdev->irq;
479 p->id = hba->pdev->vendor << 16 | hba->pdev->device;
480 p->subid =
481 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
482
483 stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count);
484}
485
486static void
487stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
488{
489 req->tag = cpu_to_le16(tag);
490 req->task_attr = TASK_ATTRIBUTE_SIMPLE;
491 req->task_manage = 0; /* not supported yet */
492 req->payload_sz = (u8)(sizeof(struct req_msg)/sizeof(u32));
493
494 hba->ccb[tag].req = req;
495 hba->out_req_cnt++;
496
497 writel(hba->req_head, hba->mmio_base + IMR0);
498 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
499 readl(hba->mmio_base + IDBL); /* flush */
500}
501
502static int
503stex_slave_alloc(struct scsi_device *sdev)
504{
505 /* Cheat: usually extracted from Inquiry data */
506 sdev->tagged_supported = 1;
507
508 scsi_activate_tcq(sdev, sdev->host->can_queue);
509
510 return 0;
511}
512
513static int
514stex_slave_config(struct scsi_device *sdev)
515{
516 sdev->use_10_for_rw = 1;
517 sdev->use_10_for_ms = 1;
518 sdev->timeout = 60 * HZ;
519 sdev->tagged_supported = 1;
520
521 return 0;
522}
523
524static void
525stex_slave_destroy(struct scsi_device *sdev)
526{
527 scsi_deactivate_tcq(sdev, 1);
528}
529
530static int
531stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
532{
533 struct st_hba *hba;
534 struct Scsi_Host *host;
535 unsigned int id,lun;
536 struct req_msg *req;
537 u16 tag;
538 host = cmd->device->host;
539 id = cmd->device->id;
540 lun = cmd->device->channel; /* firmware lun issue work around */
541 hba = (struct st_hba *) &host->hostdata[0];
542
543 switch (cmd->cmnd[0]) {
544 case MODE_SENSE_10:
545 {
546 static char ms10_caching_page[12] =
547 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
548 unsigned char page;
549 page = cmd->cmnd[2] & 0x3f;
550 if (page == 0x8 || page == 0x3f) {
551 stex_direct_copy(cmd, ms10_caching_page,
552 sizeof(ms10_caching_page));
553 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
554 done(cmd);
555 } else
556 stex_invalid_field(cmd, done);
557 return 0;
558 }
559 case INQUIRY:
560 if (id != ST_MAX_ARRAY_SUPPORTED)
561 break;
562 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
563 stex_direct_copy(cmd, console_inq_page,
564 sizeof(console_inq_page));
565 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
566 done(cmd);
567 } else
568 stex_invalid_field(cmd, done);
569 return 0;
570 case PASSTHRU_CMD:
571 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
572 struct st_drvver ver;
573 ver.major = ST_VER_MAJOR;
574 ver.minor = ST_VER_MINOR;
575 ver.oem = ST_OEM;
576 ver.build = ST_BUILD_VER;
577 ver.signature[0] = PASSTHRU_SIGNATURE;
578 ver.console_id = ST_MAX_ARRAY_SUPPORTED;
579 ver.host_no = hba->host->host_no;
580 cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ?
581 DID_OK << 16 | COMMAND_COMPLETE << 8 :
582 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
583 done(cmd);
584 return 0;
585 }
586 default:
587 break;
588 }
589
590 cmd->scsi_done = done;
591
592 tag = cmd->request->tag;
593
594 if (unlikely(tag >= host->can_queue))
595 return SCSI_MLQUEUE_HOST_BUSY;
596
597 req = stex_alloc_req(hba);
598 req->lun = lun;
599 req->target = id;
600
601 /* cdb */
602 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
603
604 hba->ccb[tag].cmd = cmd;
605 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
606 hba->ccb[tag].sense_buffer = cmd->sense_buffer;
607 hba->ccb[tag].req_type = 0;
608
609 if (cmd->sc_data_direction != DMA_NONE)
610 stex_map_sg(hba, req, &hba->ccb[tag]);
611
612 stex_send_cmd(hba, req, tag);
613 return 0;
614}
615
616static void stex_unmap_sg(struct st_hba *hba, struct scsi_cmnd *cmd)
617{
618 if (cmd->sc_data_direction != DMA_NONE) {
619 if (cmd->use_sg)
620 pci_unmap_sg(hba->pdev, cmd->request_buffer,
621 cmd->use_sg, cmd->sc_data_direction);
622 else
623 pci_unmap_single(hba->pdev, cmd->SCp.dma_handle,
624 cmd->request_bufflen, cmd->sc_data_direction);
625 }
626}
627
628static void stex_scsi_done(struct st_ccb *ccb)
629{
630 struct scsi_cmnd *cmd = ccb->cmd;
631 int result;
632
633 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
634 result = ccb->scsi_status;
635 switch (ccb->scsi_status) {
636 case SAM_STAT_GOOD:
637 result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
638 break;
639 case SAM_STAT_CHECK_CONDITION:
640 result |= DRIVER_SENSE << 24;
641 break;
642 case SAM_STAT_BUSY:
643 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
644 break;
645 default:
646 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
647 break;
648 }
649 }
650 else if (ccb->srb_status & SRB_SEE_SENSE)
651 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
652 else switch (ccb->srb_status) {
653 case SRB_STATUS_SELECTION_TIMEOUT:
654 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
655 break;
656 case SRB_STATUS_BUSY:
657 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
658 break;
659 case SRB_STATUS_INVALID_REQUEST:
660 case SRB_STATUS_ERROR:
661 default:
662 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
663 break;
664 }
665
666 cmd->result = result;
667 cmd->scsi_done(cmd);
668}
669
670static void stex_copy_data(struct st_ccb *ccb,
671 struct status_msg *resp, unsigned int variable)
672{
673 size_t count = variable;
674 if (resp->scsi_status != SAM_STAT_GOOD) {
675 if (ccb->sense_buffer != NULL)
676 memcpy(ccb->sense_buffer, resp->variable,
677 min(variable, ccb->sense_bufflen));
678 return;
679 }
680
681 if (ccb->cmd == NULL)
682 return;
683 stex_internal_copy(ccb->cmd, resp->variable, &count, ccb->sg_count);
684}
685
686static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
687{
688 void __iomem *base = hba->mmio_base;
689 struct status_msg *resp;
690 struct st_ccb *ccb;
691 unsigned int size;
692 u16 tag;
693
694 if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
695 return;
696
697 /* status payloads */
698 hba->status_head = readl(base + OMR1);
699 if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
700 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
701 pci_name(hba->pdev));
702 return;
703 }
704
705 if (unlikely(hba->mu_status != MU_STATE_STARTED ||
706 hba->out_req_cnt <= 0)) {
707 hba->status_tail = hba->status_head;
708 goto update_status;
709 }
710
711 while (hba->status_tail != hba->status_head) {
712 resp = stex_get_status(hba);
713 tag = le16_to_cpu(resp->tag);
714 if (unlikely(tag >= hba->host->can_queue)) {
715 printk(KERN_WARNING DRV_NAME
716 "(%s): invalid tag\n", pci_name(hba->pdev));
717 continue;
718 }
719
720 ccb = &hba->ccb[tag];
721 if (hba->wait_ccb == ccb)
722 hba->wait_ccb = NULL;
723 if (unlikely(ccb->req == NULL)) {
724 printk(KERN_WARNING DRV_NAME
725 "(%s): lagging req\n", pci_name(hba->pdev));
726 continue;
727 }
728
729 size = resp->payload_sz * sizeof(u32); /* payload size */
730 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
731 size > sizeof(*resp))) {
732 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
733 pci_name(hba->pdev));
734 } else {
735 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
736 if (size)
737 stex_copy_data(ccb, resp, size);
738 }
739
740 ccb->srb_status = resp->srb_status;
741 ccb->scsi_status = resp->scsi_status;
742
743 if (likely(ccb->cmd != NULL)) {
744 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
745 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
746 stex_controller_info(hba, ccb);
747 stex_unmap_sg(hba, ccb->cmd);
748 stex_scsi_done(ccb);
749 hba->out_req_cnt--;
750 } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
751 hba->out_req_cnt--;
752 if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
753 ccb->req_type = 0;
754 continue;
755 }
756 ccb->req_type = 0;
757 if (waitqueue_active(&hba->waitq))
758 wake_up(&hba->waitq);
759 }
760 }
761
762update_status:
763 writel(hba->status_head, base + IMR1);
764 readl(base + IMR1); /* flush */
765}
766
767static irqreturn_t stex_intr(int irq, void *__hba, struct pt_regs *regs)
768{
769 struct st_hba *hba = __hba;
770 void __iomem *base = hba->mmio_base;
771 u32 data;
772 unsigned long flags;
773 int handled = 0;
774
775 spin_lock_irqsave(hba->host->host_lock, flags);
776
777 data = readl(base + ODBL);
778
779 if (data && data != 0xffffffff) {
780 /* clear the interrupt */
781 writel(data, base + ODBL);
782 readl(base + ODBL); /* flush */
783 stex_mu_intr(hba, data);
784 handled = 1;
785 }
786
787 spin_unlock_irqrestore(hba->host->host_lock, flags);
788
789 return IRQ_RETVAL(handled);
790}
791
792static int stex_handshake(struct st_hba *hba)
793{
794 void __iomem *base = hba->mmio_base;
795 struct handshake_frame *h;
796 dma_addr_t status_phys;
797 int i;
798
799 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
800 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
801 readl(base + IDBL);
802 for (i = 0; readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE
803 && i < MU_MAX_DELAY_TIME; i++) {
804 rmb();
805 msleep(1);
806 }
807
808 if (i == MU_MAX_DELAY_TIME) {
809 printk(KERN_ERR DRV_NAME
810 "(%s): no handshake signature\n",
811 pci_name(hba->pdev));
812 return -1;
813 }
814 }
815
816 udelay(10);
817
818 h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
819 h->rb_phy = cpu_to_le32(hba->dma_handle);
820 h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
821 h->req_sz = cpu_to_le16(sizeof(struct req_msg));
822 h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
823 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
824 h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
825 stex_gettime(&h->hosttime);
826 h->partner_type = HMU_PARTNER_TYPE;
827
828 status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
829 writel(status_phys, base + IMR0);
830 readl(base + IMR0);
831 writel((status_phys >> 16) >> 16, base + IMR1);
832 readl(base + IMR1);
833
834 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
835 readl(base + OMR0);
836 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
837 readl(base + IDBL); /* flush */
838
839 udelay(10);
840 for (i = 0; readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE
841 && i < MU_MAX_DELAY_TIME; i++) {
842 rmb();
843 msleep(1);
844 }
845
846 if (i == MU_MAX_DELAY_TIME) {
847 printk(KERN_ERR DRV_NAME
848 "(%s): no signature after handshake frame\n",
849 pci_name(hba->pdev));
850 return -1;
851 }
852
853 writel(0, base + IMR0);
854 readl(base + IMR0);
855 writel(0, base + OMR0);
856 readl(base + OMR0);
857 writel(0, base + IMR1);
858 readl(base + IMR1);
859 writel(0, base + OMR1);
860 readl(base + OMR1); /* flush */
861 hba->mu_status = MU_STATE_STARTED;
862 return 0;
863}
864
865static int stex_abort(struct scsi_cmnd *cmd)
866{
867 struct Scsi_Host *host = cmd->device->host;
868 struct st_hba *hba = (struct st_hba *)host->hostdata;
869 u16 tag = cmd->request->tag;
870 void __iomem *base;
871 u32 data;
872 int result = SUCCESS;
873 unsigned long flags;
874 base = hba->mmio_base;
875 spin_lock_irqsave(host->host_lock, flags);
876 if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
877 hba->wait_ccb = &hba->ccb[tag];
878 else {
879 for (tag = 0; tag < host->can_queue; tag++)
880 if (hba->ccb[tag].cmd == cmd) {
881 hba->wait_ccb = &hba->ccb[tag];
882 break;
883 }
884 if (tag >= host->can_queue)
885 goto out;
886 }
887
888 data = readl(base + ODBL);
889 if (data == 0 || data == 0xffffffff)
890 goto fail_out;
891
892 writel(data, base + ODBL);
893 readl(base + ODBL); /* flush */
894
895 stex_mu_intr(hba, data);
896
897 if (hba->wait_ccb == NULL) {
898 printk(KERN_WARNING DRV_NAME
899 "(%s): lost interrupt\n", pci_name(hba->pdev));
900 goto out;
901 }
902
903fail_out:
904 stex_unmap_sg(hba, cmd);
905 hba->wait_ccb->req = NULL; /* nullify the req's future return */
906 hba->wait_ccb = NULL;
907 result = FAILED;
908out:
909 spin_unlock_irqrestore(host->host_lock, flags);
910 return result;
911}
912
913static void stex_hard_reset(struct st_hba *hba)
914{
915 struct pci_bus *bus;
916 int i;
917 u16 pci_cmd;
918 u8 pci_bctl;
919
920 for (i = 0; i < 16; i++)
921 pci_read_config_dword(hba->pdev, i * 4,
922 &hba->pdev->saved_config_space[i]);
923
924 /* Reset secondary bus. Our controller(MU/ATU) is the only device on
925 secondary bus. Consult Intel 80331/3 developer's manual for detail */
926 bus = hba->pdev->bus;
927 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
928 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
929 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
930 msleep(1);
931 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
932 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
933
934 for (i = 0; i < MU_MAX_DELAY_TIME; i++) {
935 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
936 if (pci_cmd & PCI_COMMAND_MASTER)
937 break;
938 msleep(1);
939 }
940
941 ssleep(5);
942 for (i = 0; i < 16; i++)
943 pci_write_config_dword(hba->pdev, i * 4,
944 hba->pdev->saved_config_space[i]);
945}
946
947static int stex_reset(struct scsi_cmnd *cmd)
948{
949 struct st_hba *hba;
950 unsigned long flags;
951 hba = (struct st_hba *) &cmd->device->host->hostdata[0];
952
953 hba->mu_status = MU_STATE_RESETTING;
954
955 if (hba->cardtype == st_shasta)
956 stex_hard_reset(hba);
957
958 if (stex_handshake(hba)) {
959 printk(KERN_WARNING DRV_NAME
960 "(%s): resetting: handshake failed\n",
961 pci_name(hba->pdev));
962 return FAILED;
963 }
964 spin_lock_irqsave(hba->host->host_lock, flags);
965 hba->req_head = 0;
966 hba->req_tail = 0;
967 hba->status_head = 0;
968 hba->status_tail = 0;
969 hba->out_req_cnt = 0;
970 spin_unlock_irqrestore(hba->host->host_lock, flags);
971
972 return SUCCESS;
973}
974
975static int stex_biosparam(struct scsi_device *sdev,
976 struct block_device *bdev, sector_t capacity, int geom[])
977{
978 int heads = 255, sectors = 63, cylinders;
979
980 if (capacity < 0x200000) {
981 heads = 64;
982 sectors = 32;
983 }
984
985 cylinders = sector_div(capacity, heads * sectors);
986
987 geom[0] = heads;
988 geom[1] = sectors;
989 geom[2] = cylinders;
990
991 return 0;
992}
993
994static struct scsi_host_template driver_template = {
995 .module = THIS_MODULE,
996 .name = DRV_NAME,
997 .proc_name = DRV_NAME,
998 .bios_param = stex_biosparam,
999 .queuecommand = stex_queuecommand,
1000 .slave_alloc = stex_slave_alloc,
1001 .slave_configure = stex_slave_config,
1002 .slave_destroy = stex_slave_destroy,
1003 .eh_abort_handler = stex_abort,
1004 .eh_host_reset_handler = stex_reset,
1005 .can_queue = ST_CAN_QUEUE,
1006 .this_id = -1,
1007 .sg_tablesize = ST_MAX_SG,
1008 .cmd_per_lun = ST_CMD_PER_LUN,
1009};
1010
1011static int stex_set_dma_mask(struct pci_dev * pdev)
1012{
1013 int ret;
1014 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
1015 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1016 return 0;
1017 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1018 if (!ret)
1019 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1020 return ret;
1021}
1022
1023static int __devinit
1024stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1025{
1026 struct st_hba *hba;
1027 struct Scsi_Host *host;
1028 int err;
1029
1030 err = pci_enable_device(pdev);
1031 if (err)
1032 return err;
1033
1034 pci_set_master(pdev);
1035
1036 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1037
1038 if (!host) {
1039 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1040 pci_name(pdev));
1041 err = -ENOMEM;
1042 goto out_disable;
1043 }
1044
1045 hba = (struct st_hba *)host->hostdata;
1046 memset(hba, 0, sizeof(struct st_hba));
1047
1048 err = pci_request_regions(pdev, DRV_NAME);
1049 if (err < 0) {
1050 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1051 pci_name(pdev));
1052 goto out_scsi_host_put;
1053 }
1054
1055 hba->mmio_base = ioremap(pci_resource_start(pdev, 0),
1056 pci_resource_len(pdev, 0));
1057 if ( !hba->mmio_base) {
1058 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1059 pci_name(pdev));
1060 err = -ENOMEM;
1061 goto out_release_regions;
1062 }
1063
1064 err = stex_set_dma_mask(pdev);
1065 if (err) {
1066 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1067 pci_name(pdev));
1068 goto out_iounmap;
1069 }
1070
1071 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1072 STEX_BUFFER_SIZE, &hba->dma_handle, GFP_KERNEL);
1073 if (!hba->dma_mem) {
1074 err = -ENOMEM;
1075 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1076 pci_name(pdev));
1077 goto out_iounmap;
1078 }
1079
1080 hba->status_buffer =
1081 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
1082 hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
1083 hba->mu_status = MU_STATE_STARTING;
1084
1085 hba->cardtype = (unsigned int) id->driver_data;
1086
1087 /* firmware uses id/lun pair for a logical drive, but lun would be
1088 always 0 if CONFIG_SCSI_MULTI_LUN not configured, so we use
1089 channel to map lun here */
1090 host->max_channel = ST_MAX_LUN_PER_TARGET - 1;
1091 host->max_id = ST_MAX_TARGET_NUM;
1092 host->max_lun = 1;
1093 host->unique_id = host->host_no;
1094 host->max_cmd_len = STEX_CDB_LENGTH;
1095
1096 hba->host = host;
1097 hba->pdev = pdev;
1098 init_waitqueue_head(&hba->waitq);
1099
1100 err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
1101 if (err) {
1102 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1103 pci_name(pdev));
1104 goto out_pci_free;
1105 }
1106
1107 err = stex_handshake(hba);
1108 if (err)
1109 goto out_free_irq;
1110
1111 err = scsi_init_shared_tag_map(host, ST_CAN_QUEUE);
1112 if (err) {
1113 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1114 pci_name(pdev));
1115 goto out_free_irq;
1116 }
1117
1118 pci_set_drvdata(pdev, hba);
1119
1120 err = scsi_add_host(host, &pdev->dev);
1121 if (err) {
1122 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1123 pci_name(pdev));
1124 goto out_free_irq;
1125 }
1126
1127 scsi_scan_host(host);
1128
1129 return 0;
1130
1131out_free_irq:
1132 free_irq(pdev->irq, hba);
1133out_pci_free:
1134 dma_free_coherent(&pdev->dev, STEX_BUFFER_SIZE,
1135 hba->dma_mem, hba->dma_handle);
1136out_iounmap:
1137 iounmap(hba->mmio_base);
1138out_release_regions:
1139 pci_release_regions(pdev);
1140out_scsi_host_put:
1141 scsi_host_put(host);
1142out_disable:
1143 pci_disable_device(pdev);
1144
1145 return err;
1146}
1147
1148static void stex_hba_stop(struct st_hba *hba)
1149{
1150 struct req_msg *req;
1151 unsigned long flags;
1152 unsigned long before;
1153 u16 tag = 0;
1154
1155 spin_lock_irqsave(hba->host->host_lock, flags);
1156 req = stex_alloc_req(hba);
1157 memset(req->cdb, 0, STEX_CDB_LENGTH);
1158
1159 req->cdb[0] = CONTROLLER_CMD;
1160 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1161 req->cdb[2] = CTLR_POWER_SAVING;
1162
1163 hba->ccb[tag].cmd = NULL;
1164 hba->ccb[tag].sg_count = 0;
1165 hba->ccb[tag].sense_bufflen = 0;
1166 hba->ccb[tag].sense_buffer = NULL;
1167 hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
1168
1169 stex_send_cmd(hba, req, tag);
1170 spin_unlock_irqrestore(hba->host->host_lock, flags);
1171
1172 before = jiffies;
1173 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1174 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
1175 return;
1176 msleep(10);
1177 }
1178}
1179
1180static void stex_hba_free(struct st_hba *hba)
1181{
1182 free_irq(hba->pdev->irq, hba);
1183
1184 iounmap(hba->mmio_base);
1185
1186 pci_release_regions(hba->pdev);
1187
1188 dma_free_coherent(&hba->pdev->dev, STEX_BUFFER_SIZE,
1189 hba->dma_mem, hba->dma_handle);
1190}
1191
1192static void stex_remove(struct pci_dev *pdev)
1193{
1194 struct st_hba *hba = pci_get_drvdata(pdev);
1195
1196 scsi_remove_host(hba->host);
1197
1198 pci_set_drvdata(pdev, NULL);
1199
1200 stex_hba_stop(hba);
1201
1202 stex_hba_free(hba);
1203
1204 scsi_host_put(hba->host);
1205
1206 pci_disable_device(pdev);
1207}
1208
1209static void stex_shutdown(struct pci_dev *pdev)
1210{
1211 struct st_hba *hba = pci_get_drvdata(pdev);
1212
1213 stex_hba_stop(hba);
1214}
1215
1216static struct pci_device_id stex_pci_tbl[] = {
1217 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1218 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1219 { 0x105a, 0xf350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1220 { 0x105a, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1221 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1222 { 0x105a, 0x8301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1223 { 0x105a, 0x8302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1224 { 0x1725, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1225 { } /* terminate list */
1226};
1227MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1228
1229static struct pci_driver stex_pci_driver = {
1230 .name = DRV_NAME,
1231 .id_table = stex_pci_tbl,
1232 .probe = stex_probe,
1233 .remove = __devexit_p(stex_remove),
1234 .shutdown = stex_shutdown,
1235};
1236
1237static int __init stex_init(void)
1238{
1239 printk(KERN_INFO DRV_NAME
1240 ": Promise SuperTrak EX Driver version: %s\n",
1241 ST_DRIVER_VERSION);
1242
1243 return pci_register_driver(&stex_pci_driver);
1244}
1245
1246static void __exit stex_exit(void)
1247{
1248 pci_unregister_driver(&stex_pci_driver);
1249}
1250
1251module_init(stex_init);
1252module_exit(stex_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 14:16:00 -0500