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-rw-r--r--drivers/scsi/sata_sil24.c786
1 files changed, 786 insertions, 0 deletions
diff --git a/drivers/scsi/sata_sil24.c b/drivers/scsi/sata_sil24.c
new file mode 100644
index 000000000000..9958bc10a258
--- /dev/null
+++ b/drivers/scsi/sata_sil24.c
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1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * NOTE: No NCQ/ATAPI support yet. The preview driver didn't support
9 * NCQ nor ATAPI, and, unfortunately, I couldn't find out how to make
10 * those work. Enabling those shouldn't be difficult. Basic
11 * structure is all there (in libata-dev tree). If you have any
12 * information about this hardware, please contact me or linux-ide.
13 * Info is needed on...
14 *
15 * - How to issue tagged commands and turn on sactive on issue accordingly.
16 * - Where to put an ATAPI command and how to tell the device to send it.
17 * - How to enable/use 64bit.
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2, or (at your option) any
22 * later version.
23 *
24 * This program is distributed in the hope that it will be useful, but
25 * WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27 * General Public License for more details.
28 *
29 */
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/blkdev.h>
35#include <linux/delay.h>
36#include <linux/interrupt.h>
37#include <linux/dma-mapping.h>
38#include <scsi/scsi_host.h>
39#include "scsi.h"
40#include <linux/libata.h>
41#include <asm/io.h>
42
43#define DRV_NAME "sata_sil24"
44#define DRV_VERSION "0.20" /* Silicon Image's preview driver was 0.10 */
45
46#define NR_PORTS 4
47
48/*
49 * Port request block (PRB) 32 bytes
50 */
51struct sil24_prb {
52 u16 ctrl;
53 u16 prot;
54 u32 rx_cnt;
55 u8 fis[6 * 4];
56};
57
58/*
59 * Scatter gather entry (SGE) 16 bytes
60 */
61struct sil24_sge {
62 u64 addr;
63 u32 cnt;
64 u32 flags;
65};
66
67/*
68 * Port multiplier
69 */
70struct sil24_port_multiplier {
71 u32 diag;
72 u32 sactive;
73};
74
75enum {
76 /*
77 * Global controller registers (128 bytes @ BAR0)
78 */
79 /* 32 bit regs */
80 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
81 HOST_CTRL = 0x40,
82 HOST_IRQ_STAT = 0x44,
83 HOST_PHY_CFG = 0x48,
84 HOST_BIST_CTRL = 0x50,
85 HOST_BIST_PTRN = 0x54,
86 HOST_BIST_STAT = 0x58,
87 HOST_MEM_BIST_STAT = 0x5c,
88 HOST_FLASH_CMD = 0x70,
89 /* 8 bit regs */
90 HOST_FLASH_DATA = 0x74,
91 HOST_TRANSITION_DETECT = 0x75,
92 HOST_GPIO_CTRL = 0x76,
93 HOST_I2C_ADDR = 0x78, /* 32 bit */
94 HOST_I2C_DATA = 0x7c,
95 HOST_I2C_XFER_CNT = 0x7e,
96 HOST_I2C_CTRL = 0x7f,
97
98 /* HOST_SLOT_STAT bits */
99 HOST_SSTAT_ATTN = (1 << 31),
100
101 /*
102 * Port registers
103 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
104 */
105 PORT_REGS_SIZE = 0x2000,
106 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
107 /* TF is overlayed w/ PRB regs in the preview driver,
108 * but it doesn't seem to work. */
109 PORT_TF = 0x0000,
110
111 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
112 /* 32 bit regs */
113 PORT_CTRL_STAT = 0x1000, /* write:ctrl, read:stat */
114 PORT_CTRL_CLR = 0x1004,
115 PORT_IRQ_STAT = 0x1008,
116 PORT_IRQ_ENABLE_SET = 0x1010,
117 PORT_IRQ_ENABLE_CLR = 0x1014,
118 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
119 PORT_EXEC_FIFO = 0x1020,
120 PORT_CMD_ERR = 0x1024,
121 PORT_FIS_CFG = 0x1028,
122 PORT_FIFO_THRES = 0x102c,
123 /* 16 bit regs */
124 PORT_DECODE_ERR_CNT = 0x1040,
125 PORT_DECODE_ERR_THRESH = 0x1042,
126 PORT_CRC_ERR_CNT = 0x1044,
127 PORT_CRC_ERR_THRESH = 0x1046,
128 PORT_HSHK_ERR_CNT = 0x1048,
129 PORT_HSHK_ERR_THRESH = 0x104a,
130 /* 32 bit regs */
131 PORT_PHY_CFG = 0x1050,
132 PORT_SLOT_STAT = 0x1800,
133 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
134 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
135 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
136 PORT_SCONTROL = 0x1f00,
137 PORT_SSTATUS = 0x1f04,
138 PORT_SERROR = 0x1f08,
139 PORT_SACTIVE = 0x1f0c,
140
141 /* PORT_CTRL_STAT bits */
142 PORT_CS_PORT_RST = (1 << 0), /* port reset */
143 PORT_CS_DEV_RST = (1 << 1), /* device reset */
144 PORT_CS_INIT = (1 << 2), /* port initialize */
145 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
146 PORT_CS_RESUME = (1 << 4), /* port resume */
147 PORT_CS_32BIT_ACTV = (1 << 5), /* 32-bit activation */
148 PORT_CS_PM_EN = (1 << 6), /* port multiplier enable */
149 PORT_CS_RDY = (1 << 7), /* port ready to accept commands */
150
151 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
152 /* bits[11:0] are masked */
153 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
154 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
155 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
156 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
157 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
158 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
159 PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */
160 PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */
161
162 /* bits[27:16] are unmasked (raw) */
163 PORT_IRQ_RAW_SHIFT = 16,
164 PORT_IRQ_MASKED_MASK = 0x7ff,
165 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
166
167 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
168 PORT_IRQ_STEER_SHIFT = 30,
169 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
170
171 /* PORT_CMD_ERR constants */
172 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
173 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
174 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
175 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
176 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
177 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
178 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
179 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
180 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
181 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
182 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
183 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
184 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
185 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
186 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
187 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
188 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
189 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
190 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
191 PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */
192 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
193 PORT_CERR_SENDSERVICE = 36, /* FIS received whiel sending service */
194
195 /*
196 * Other constants
197 */
198 SGE_TRM = (1 << 31), /* Last SGE in chain */
199 PRB_SOFT_RST = (1 << 7), /* Soft reset request (ign BSY?) */
200
201 /* board id */
202 BID_SIL3124 = 0,
203 BID_SIL3132 = 1,
204
205 IRQ_STAT_4PORTS = 0xf,
206};
207
208struct sil24_cmd_block {
209 struct sil24_prb prb;
210 struct sil24_sge sge[LIBATA_MAX_PRD];
211};
212
213/*
214 * ap->private_data
215 *
216 * The preview driver always returned 0 for status. We emulate it
217 * here from the previous interrupt.
218 */
219struct sil24_port_priv {
220 void *port;
221 struct sil24_cmd_block *cmd_block; /* 32 cmd blocks */
222 dma_addr_t cmd_block_dma; /* DMA base addr for them */
223};
224
225/* ap->host_set->private_data */
226struct sil24_host_priv {
227 void *host_base; /* global controller control (128 bytes @BAR0) */
228 void *port_base; /* port registers (4 * 8192 bytes @BAR2) */
229};
230
231static u8 sil24_check_status(struct ata_port *ap);
232static u8 sil24_check_err(struct ata_port *ap);
233static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
234static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
235static void sil24_phy_reset(struct ata_port *ap);
236static void sil24_qc_prep(struct ata_queued_cmd *qc);
237static int sil24_qc_issue(struct ata_queued_cmd *qc);
238static void sil24_irq_clear(struct ata_port *ap);
239static void sil24_eng_timeout(struct ata_port *ap);
240static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
241static int sil24_port_start(struct ata_port *ap);
242static void sil24_port_stop(struct ata_port *ap);
243static void sil24_host_stop(struct ata_host_set *host_set);
244static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
245
246static struct pci_device_id sil24_pci_tbl[] = {
247 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
248 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
249};
250
251static struct pci_driver sil24_pci_driver = {
252 .name = DRV_NAME,
253 .id_table = sil24_pci_tbl,
254 .probe = sil24_init_one,
255 .remove = ata_pci_remove_one, /* safe? */
256};
257
258static Scsi_Host_Template sil24_sht = {
259 .module = THIS_MODULE,
260 .name = DRV_NAME,
261 .ioctl = ata_scsi_ioctl,
262 .queuecommand = ata_scsi_queuecmd,
263 .eh_strategy_handler = ata_scsi_error,
264 .can_queue = ATA_DEF_QUEUE,
265 .this_id = ATA_SHT_THIS_ID,
266 .sg_tablesize = LIBATA_MAX_PRD,
267 .max_sectors = ATA_MAX_SECTORS,
268 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
269 .emulated = ATA_SHT_EMULATED,
270 .use_clustering = ATA_SHT_USE_CLUSTERING,
271 .proc_name = DRV_NAME,
272 .dma_boundary = ATA_DMA_BOUNDARY,
273 .slave_configure = ata_scsi_slave_config,
274 .bios_param = ata_std_bios_param,
275 .ordered_flush = 1, /* NCQ not supported yet */
276};
277
278static struct ata_port_operations sil24_ops = {
279 .port_disable = ata_port_disable,
280
281 .check_status = sil24_check_status,
282 .check_altstatus = sil24_check_status,
283 .check_err = sil24_check_err,
284 .dev_select = ata_noop_dev_select,
285
286 .phy_reset = sil24_phy_reset,
287
288 .qc_prep = sil24_qc_prep,
289 .qc_issue = sil24_qc_issue,
290
291 .eng_timeout = sil24_eng_timeout,
292
293 .irq_handler = sil24_interrupt,
294 .irq_clear = sil24_irq_clear,
295
296 .scr_read = sil24_scr_read,
297 .scr_write = sil24_scr_write,
298
299 .port_start = sil24_port_start,
300 .port_stop = sil24_port_stop,
301 .host_stop = sil24_host_stop,
302};
303
304static struct ata_port_info sil24_port_info[] = {
305 /* sil_3124 */
306 {
307 .sht = &sil24_sht,
308 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
309 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
310 ATA_FLAG_PIO_DMA,
311 .pio_mask = 0x1f, /* pio0-4 */
312 .mwdma_mask = 0x07, /* mwdma0-2 */
313 .udma_mask = 0x3f, /* udma0-5 */
314 .port_ops = &sil24_ops,
315 },
316 /* sil_3132 */
317 {
318 .sht = &sil24_sht,
319 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
320 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
321 ATA_FLAG_PIO_DMA,
322 .pio_mask = 0x1f, /* pio0-4 */
323 .mwdma_mask = 0x07, /* mwdma0-2 */
324 .udma_mask = 0x3f, /* udma0-5 */
325 .port_ops = &sil24_ops,
326 },
327};
328
329static u8 sil24_check_status(struct ata_port *ap)
330{
331 return ATA_DRDY;
332}
333
334static u8 sil24_check_err(struct ata_port *ap)
335{
336 return 0;
337}
338
339static int sil24_scr_map[] = {
340 [SCR_CONTROL] = 0,
341 [SCR_STATUS] = 1,
342 [SCR_ERROR] = 2,
343 [SCR_ACTIVE] = 3,
344};
345
346static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
347{
348 void *scr_addr = (void *)ap->ioaddr.scr_addr;
349 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
350 void *addr;
351 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
352 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
353 }
354 return 0xffffffffU;
355}
356
357static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
358{
359 void *scr_addr = (void *)ap->ioaddr.scr_addr;
360 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
361 void *addr;
362 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
363 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
364 }
365}
366
367static void sil24_phy_reset(struct ata_port *ap)
368{
369 __sata_phy_reset(ap);
370 /*
371 * No ATAPI yet. Just unconditionally indicate ATA device.
372 * If ATAPI device is attached, it will fail ATA_CMD_ID_ATA
373 * and libata core will ignore the device.
374 */
375 if (!(ap->flags & ATA_FLAG_PORT_DISABLED))
376 ap->device[0].class = ATA_DEV_ATA;
377}
378
379static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
380 struct sil24_cmd_block *cb)
381{
382 struct scatterlist *sg = qc->sg;
383 struct sil24_sge *sge = cb->sge;
384 unsigned i;
385
386 for (i = 0; i < qc->n_elem; i++, sg++, sge++) {
387 sge->addr = cpu_to_le64(sg_dma_address(sg));
388 sge->cnt = cpu_to_le32(sg_dma_len(sg));
389 sge->flags = 0;
390 sge->flags = i < qc->n_elem - 1 ? 0 : cpu_to_le32(SGE_TRM);
391 }
392}
393
394static void sil24_qc_prep(struct ata_queued_cmd *qc)
395{
396 struct ata_port *ap = qc->ap;
397 struct sil24_port_priv *pp = ap->private_data;
398 struct sil24_cmd_block *cb = pp->cmd_block + qc->tag;
399 struct sil24_prb *prb = &cb->prb;
400
401 switch (qc->tf.protocol) {
402 case ATA_PROT_PIO:
403 case ATA_PROT_DMA:
404 case ATA_PROT_NODATA:
405 break;
406 default:
407 /* ATAPI isn't supported yet */
408 BUG();
409 }
410
411 ata_tf_to_fis(&qc->tf, prb->fis, 0);
412
413 if (qc->flags & ATA_QCFLAG_DMAMAP)
414 sil24_fill_sg(qc, cb);
415}
416
417static int sil24_qc_issue(struct ata_queued_cmd *qc)
418{
419 struct ata_port *ap = qc->ap;
420 struct sil24_port_priv *pp = ap->private_data;
421 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
422
423 writel((u32)paddr, pp->port + PORT_CMD_ACTIVATE);
424 return 0;
425}
426
427static void sil24_irq_clear(struct ata_port *ap)
428{
429 /* unused */
430}
431
432static void sil24_reset_controller(struct ata_port *ap)
433{
434 struct sil24_port_priv *pp = ap->private_data;
435 void *port = pp->port;
436 int cnt;
437 u32 tmp;
438
439 printk(KERN_NOTICE DRV_NAME
440 " ata%u: resetting controller...\n", ap->id);
441
442 /* Reset controller state. Is this correct? */
443 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
444 readl(port + PORT_CTRL_STAT); /* sync */
445
446 /* Max ~100ms */
447 for (cnt = 0; cnt < 1000; cnt++) {
448 udelay(100);
449 tmp = readl(port + PORT_CTRL_STAT);
450 if (!(tmp & PORT_CS_DEV_RST))
451 break;
452 }
453 if (tmp & PORT_CS_DEV_RST)
454 printk(KERN_ERR DRV_NAME
455 " ata%u: failed to reset controller\n", ap->id);
456}
457
458static void sil24_eng_timeout(struct ata_port *ap)
459{
460 struct ata_queued_cmd *qc;
461
462 qc = ata_qc_from_tag(ap, ap->active_tag);
463 if (!qc) {
464 printk(KERN_ERR "ata%u: BUG: tiemout without command\n",
465 ap->id);
466 return;
467 }
468
469 /*
470 * hack alert! We cannot use the supplied completion
471 * function from inside the ->eh_strategy_handler() thread.
472 * libata is the only user of ->eh_strategy_handler() in
473 * any kernel, so the default scsi_done() assumes it is
474 * not being called from the SCSI EH.
475 */
476 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
477 qc->scsidone = scsi_finish_command;
478 ata_qc_complete(qc, ATA_ERR);
479
480 sil24_reset_controller(ap);
481}
482
483static inline void sil24_host_intr(struct ata_port *ap)
484{
485 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
486 struct sil24_port_priv *pp = ap->private_data;
487 void *port = pp->port;
488 u32 slot_stat;
489
490 slot_stat = readl(port + PORT_SLOT_STAT);
491 if (!(slot_stat & HOST_SSTAT_ATTN)) {
492 if (qc)
493 ata_qc_complete(qc, 0);
494 } else {
495 u32 irq_stat, cmd_err, sstatus, serror;
496
497 irq_stat = readl(port + PORT_IRQ_STAT);
498 cmd_err = readl(port + PORT_CMD_ERR);
499 sstatus = readl(port + PORT_SSTATUS);
500 serror = readl(port + PORT_SERROR);
501
502 /* Clear IRQ/errors */
503 writel(irq_stat, port + PORT_IRQ_STAT);
504 if (cmd_err)
505 writel(cmd_err, port + PORT_CMD_ERR);
506 if (serror)
507 writel(serror, port + PORT_SERROR);
508
509 printk(KERN_ERR DRV_NAME " ata%u: error interrupt on port%d\n"
510 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
511 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
512
513 if (qc)
514 ata_qc_complete(qc, ATA_ERR);
515
516 sil24_reset_controller(ap);
517 }
518}
519
520static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
521{
522 struct ata_host_set *host_set = dev_instance;
523 struct sil24_host_priv *hpriv = host_set->private_data;
524 unsigned handled = 0;
525 u32 status;
526 int i;
527
528 status = readl(hpriv->host_base + HOST_IRQ_STAT);
529
530 if (!(status & IRQ_STAT_4PORTS))
531 goto out;
532
533 spin_lock(&host_set->lock);
534
535 for (i = 0; i < host_set->n_ports; i++)
536 if (status & (1 << i)) {
537 struct ata_port *ap = host_set->ports[i];
538 if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED))
539 sil24_host_intr(host_set->ports[i]);
540 else {
541 u32 tmp;
542 printk(KERN_WARNING DRV_NAME
543 ": spurious interrupt from port %d\n", i);
544 tmp = readl(hpriv->host_base + HOST_CTRL);
545 tmp &= ~(1 << i);
546 writel(tmp, hpriv->host_base + HOST_CTRL);
547 }
548 handled++;
549 }
550
551 spin_unlock(&host_set->lock);
552 out:
553 return IRQ_RETVAL(handled);
554}
555
556static int sil24_port_start(struct ata_port *ap)
557{
558 struct device *dev = ap->host_set->dev;
559 struct sil24_host_priv *hpriv = ap->host_set->private_data;
560 struct sil24_port_priv *pp;
561 struct sil24_cmd_block *cb;
562 size_t cb_size = sizeof(*cb);
563 dma_addr_t cb_dma;
564
565 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
566 if (!pp)
567 return -ENOMEM;
568 memset(pp, 0, sizeof(*pp));
569
570 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
571 if (!cb) {
572 kfree(pp);
573 return -ENOMEM;
574 }
575 memset(cb, 0, cb_size);
576
577 pp->port = hpriv->port_base + ap->port_no * PORT_REGS_SIZE;
578 pp->cmd_block = cb;
579 pp->cmd_block_dma = cb_dma;
580
581 ap->private_data = pp;
582
583 return 0;
584}
585
586static void sil24_port_stop(struct ata_port *ap)
587{
588 struct device *dev = ap->host_set->dev;
589 struct sil24_port_priv *pp = ap->private_data;
590 size_t cb_size = sizeof(*pp->cmd_block);
591
592 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
593 kfree(pp);
594}
595
596static void sil24_host_stop(struct ata_host_set *host_set)
597{
598 struct sil24_host_priv *hpriv = host_set->private_data;
599
600 iounmap(hpriv->host_base);
601 iounmap(hpriv->port_base);
602 kfree(hpriv);
603}
604
605static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
606{
607 static int printed_version = 0;
608 unsigned int board_id = (unsigned int)ent->driver_data;
609 struct ata_probe_ent *probe_ent = NULL;
610 struct sil24_host_priv *hpriv = NULL;
611 void *host_base = NULL, *port_base = NULL;
612 int i, rc;
613
614 if (!printed_version++)
615 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
616
617 rc = pci_enable_device(pdev);
618 if (rc)
619 return rc;
620
621 rc = pci_request_regions(pdev, DRV_NAME);
622 if (rc)
623 goto out_disable;
624
625 rc = -ENOMEM;
626 /* ioremap mmio registers */
627 host_base = ioremap(pci_resource_start(pdev, 0),
628 pci_resource_len(pdev, 0));
629 if (!host_base)
630 goto out_free;
631 port_base = ioremap(pci_resource_start(pdev, 2),
632 pci_resource_len(pdev, 2));
633 if (!port_base)
634 goto out_free;
635
636 /* allocate & init probe_ent and hpriv */
637 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
638 if (!probe_ent)
639 goto out_free;
640
641 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
642 if (!hpriv)
643 goto out_free;
644
645 memset(probe_ent, 0, sizeof(*probe_ent));
646 probe_ent->dev = pci_dev_to_dev(pdev);
647 INIT_LIST_HEAD(&probe_ent->node);
648
649 probe_ent->sht = sil24_port_info[board_id].sht;
650 probe_ent->host_flags = sil24_port_info[board_id].host_flags;
651 probe_ent->pio_mask = sil24_port_info[board_id].pio_mask;
652 probe_ent->udma_mask = sil24_port_info[board_id].udma_mask;
653 probe_ent->port_ops = sil24_port_info[board_id].port_ops;
654 probe_ent->n_ports = (board_id == BID_SIL3124) ? 4 : 2;
655
656 probe_ent->irq = pdev->irq;
657 probe_ent->irq_flags = SA_SHIRQ;
658 probe_ent->mmio_base = port_base;
659 probe_ent->private_data = hpriv;
660
661 memset(hpriv, 0, sizeof(*hpriv));
662 hpriv->host_base = host_base;
663 hpriv->port_base = port_base;
664
665 /*
666 * Configure the device
667 */
668 /*
669 * FIXME: This device is certainly 64-bit capable. We just
670 * don't know how to use it. After fixing 32bit activation in
671 * this function, enable 64bit masks here.
672 */
673 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
674 if (rc) {
675 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
676 pci_name(pdev));
677 goto out_free;
678 }
679 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
680 if (rc) {
681 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
682 pci_name(pdev));
683 goto out_free;
684 }
685
686 /* GPIO off */
687 writel(0, host_base + HOST_FLASH_CMD);
688
689 /* Mask interrupts during initialization */
690 writel(0, host_base + HOST_CTRL);
691
692 for (i = 0; i < probe_ent->n_ports; i++) {
693 void *port = port_base + i * PORT_REGS_SIZE;
694 unsigned long portu = (unsigned long)port;
695 u32 tmp;
696 int cnt;
697
698 probe_ent->port[i].cmd_addr = portu + PORT_TF;
699 probe_ent->port[i].ctl_addr = portu + PORT_TF + 0xa;
700 probe_ent->port[i].altstatus_addr = portu + PORT_TF + 0xa;
701 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
702
703 ata_std_ports(&probe_ent->port[i]);
704
705 /* Initial PHY setting */
706 writel(0x20c, port + PORT_PHY_CFG);
707
708 /* Clear port RST */
709 tmp = readl(port + PORT_CTRL_STAT);
710 if (tmp & PORT_CS_PORT_RST) {
711 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
712 readl(port + PORT_CTRL_STAT); /* sync */
713 for (cnt = 0; cnt < 10; cnt++) {
714 msleep(10);
715 tmp = readl(port + PORT_CTRL_STAT);
716 if (!(tmp & PORT_CS_PORT_RST))
717 break;
718 }
719 if (tmp & PORT_CS_PORT_RST)
720 printk(KERN_ERR DRV_NAME
721 "(%s): failed to clear port RST\n",
722 pci_name(pdev));
723 }
724
725 /* Zero error counters. */
726 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
727 writel(0x8000, port + PORT_CRC_ERR_THRESH);
728 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
729 writel(0x0000, port + PORT_DECODE_ERR_CNT);
730 writel(0x0000, port + PORT_CRC_ERR_CNT);
731 writel(0x0000, port + PORT_HSHK_ERR_CNT);
732
733 /* FIXME: 32bit activation? */
734 writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
735 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
736
737 /* Configure interrupts */
738 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
739 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS,
740 port + PORT_IRQ_ENABLE_SET);
741
742 /* Clear interrupts */
743 writel(0x0fff0fff, port + PORT_IRQ_STAT);
744 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
745 }
746
747 /* Turn on interrupts */
748 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
749
750 pci_set_master(pdev);
751
752 ata_device_add(probe_ent);
753
754 kfree(probe_ent);
755 return 0;
756
757 out_free:
758 if (host_base)
759 iounmap(host_base);
760 if (port_base)
761 iounmap(port_base);
762 kfree(probe_ent);
763 kfree(hpriv);
764 pci_release_regions(pdev);
765 out_disable:
766 pci_disable_device(pdev);
767 return rc;
768}
769
770static int __init sil24_init(void)
771{
772 return pci_module_init(&sil24_pci_driver);
773}
774
775static void __exit sil24_exit(void)
776{
777 pci_unregister_driver(&sil24_pci_driver);
778}
779
780MODULE_AUTHOR("Tejun Heo");
781MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
782MODULE_LICENSE("GPL");
783MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
784
785module_init(sil24_init);
786module_exit(sil24_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 08:46:00 -0500