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-rw-r--r--drivers/scsi/sata_promise.c837
1 files changed, 0 insertions, 837 deletions
diff --git a/drivers/scsi/sata_promise.c b/drivers/scsi/sata_promise.c
deleted file mode 100644
index b2b6ed5216e0..000000000000
--- a/drivers/scsi/sata_promise.c
+++ /dev/null
@@ -1,837 +0,0 @@
1/*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/init.h>
37#include <linux/blkdev.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
40#include <linux/sched.h>
41#include <linux/device.h>
42#include <scsi/scsi_host.h>
43#include <scsi/scsi_cmnd.h>
44#include <linux/libata.h>
45#include <asm/io.h>
46#include "sata_promise.h"
47
48#define DRV_NAME "sata_promise"
49#define DRV_VERSION "1.04"
50
51
52enum {
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_TBG_MODE = 0x41, /* TBG mode */
56 PDC_FLASH_CTL = 0x44, /* Flash control register */
57 PDC_PCI_CTL = 0x48, /* PCI control and status register */
58 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
59 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
61 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
62 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
63
64 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
65 (1<<8) | (1<<9) | (1<<10),
66
67 board_2037x = 0, /* FastTrak S150 TX2plus */
68 board_20319 = 1, /* FastTrak S150 TX4 */
69 board_20619 = 2, /* FastTrak TX4000 */
70 board_20771 = 3, /* FastTrak TX2300 */
71 board_2057x = 4, /* SATAII150 Tx2plus */
72 board_40518 = 5, /* SATAII150 Tx4 */
73
74 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
75
76 PDC_RESET = (1 << 11), /* HDMA reset */
77
78 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
79 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
80 ATA_FLAG_PIO_POLLING,
81};
82
83
84struct pdc_port_priv {
85 u8 *pkt;
86 dma_addr_t pkt_dma;
87};
88
89struct pdc_host_priv {
90 int hotplug_offset;
91};
92
93static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
94static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
95static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
96static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
97static void pdc_eng_timeout(struct ata_port *ap);
98static int pdc_port_start(struct ata_port *ap);
99static void pdc_port_stop(struct ata_port *ap);
100static void pdc_pata_phy_reset(struct ata_port *ap);
101static void pdc_sata_phy_reset(struct ata_port *ap);
102static void pdc_qc_prep(struct ata_queued_cmd *qc);
103static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
104static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
105static void pdc_irq_clear(struct ata_port *ap);
106static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
107static void pdc_host_stop(struct ata_host_set *host_set);
108
109
110static struct scsi_host_template pdc_ata_sht = {
111 .module = THIS_MODULE,
112 .name = DRV_NAME,
113 .ioctl = ata_scsi_ioctl,
114 .queuecommand = ata_scsi_queuecmd,
115 .can_queue = ATA_DEF_QUEUE,
116 .this_id = ATA_SHT_THIS_ID,
117 .sg_tablesize = LIBATA_MAX_PRD,
118 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
119 .emulated = ATA_SHT_EMULATED,
120 .use_clustering = ATA_SHT_USE_CLUSTERING,
121 .proc_name = DRV_NAME,
122 .dma_boundary = ATA_DMA_BOUNDARY,
123 .slave_configure = ata_scsi_slave_config,
124 .slave_destroy = ata_scsi_slave_destroy,
125 .bios_param = ata_std_bios_param,
126};
127
128static const struct ata_port_operations pdc_sata_ops = {
129 .port_disable = ata_port_disable,
130 .tf_load = pdc_tf_load_mmio,
131 .tf_read = ata_tf_read,
132 .check_status = ata_check_status,
133 .exec_command = pdc_exec_command_mmio,
134 .dev_select = ata_std_dev_select,
135
136 .phy_reset = pdc_sata_phy_reset,
137
138 .qc_prep = pdc_qc_prep,
139 .qc_issue = pdc_qc_issue_prot,
140 .eng_timeout = pdc_eng_timeout,
141 .data_xfer = ata_mmio_data_xfer,
142 .irq_handler = pdc_interrupt,
143 .irq_clear = pdc_irq_clear,
144
145 .scr_read = pdc_sata_scr_read,
146 .scr_write = pdc_sata_scr_write,
147 .port_start = pdc_port_start,
148 .port_stop = pdc_port_stop,
149 .host_stop = pdc_host_stop,
150};
151
152static const struct ata_port_operations pdc_pata_ops = {
153 .port_disable = ata_port_disable,
154 .tf_load = pdc_tf_load_mmio,
155 .tf_read = ata_tf_read,
156 .check_status = ata_check_status,
157 .exec_command = pdc_exec_command_mmio,
158 .dev_select = ata_std_dev_select,
159
160 .phy_reset = pdc_pata_phy_reset,
161
162 .qc_prep = pdc_qc_prep,
163 .qc_issue = pdc_qc_issue_prot,
164 .data_xfer = ata_mmio_data_xfer,
165 .eng_timeout = pdc_eng_timeout,
166 .irq_handler = pdc_interrupt,
167 .irq_clear = pdc_irq_clear,
168
169 .port_start = pdc_port_start,
170 .port_stop = pdc_port_stop,
171 .host_stop = pdc_host_stop,
172};
173
174static const struct ata_port_info pdc_port_info[] = {
175 /* board_2037x */
176 {
177 .sht = &pdc_ata_sht,
178 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
179 .pio_mask = 0x1f, /* pio0-4 */
180 .mwdma_mask = 0x07, /* mwdma0-2 */
181 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
182 .port_ops = &pdc_sata_ops,
183 },
184
185 /* board_20319 */
186 {
187 .sht = &pdc_ata_sht,
188 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
189 .pio_mask = 0x1f, /* pio0-4 */
190 .mwdma_mask = 0x07, /* mwdma0-2 */
191 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
192 .port_ops = &pdc_sata_ops,
193 },
194
195 /* board_20619 */
196 {
197 .sht = &pdc_ata_sht,
198 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
199 .pio_mask = 0x1f, /* pio0-4 */
200 .mwdma_mask = 0x07, /* mwdma0-2 */
201 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
202 .port_ops = &pdc_pata_ops,
203 },
204
205 /* board_20771 */
206 {
207 .sht = &pdc_ata_sht,
208 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
209 .pio_mask = 0x1f, /* pio0-4 */
210 .mwdma_mask = 0x07, /* mwdma0-2 */
211 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
212 .port_ops = &pdc_sata_ops,
213 },
214
215 /* board_2057x */
216 {
217 .sht = &pdc_ata_sht,
218 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
219 .pio_mask = 0x1f, /* pio0-4 */
220 .mwdma_mask = 0x07, /* mwdma0-2 */
221 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
222 .port_ops = &pdc_sata_ops,
223 },
224
225 /* board_40518 */
226 {
227 .sht = &pdc_ata_sht,
228 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
229 .pio_mask = 0x1f, /* pio0-4 */
230 .mwdma_mask = 0x07, /* mwdma0-2 */
231 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
232 .port_ops = &pdc_sata_ops,
233 },
234};
235
236static const struct pci_device_id pdc_ata_pci_tbl[] = {
237 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
238 board_2037x },
239 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
240 board_2037x },
241 { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
242 board_2037x },
243 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
244 board_2037x },
245 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
246 board_2037x },
247 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
248 board_2037x },
249 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
250 board_2057x },
251 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
252 board_2057x },
253 { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
254 board_2037x },
255
256 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
257 board_20319 },
258 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
259 board_20319 },
260 { PCI_VENDOR_ID_PROMISE, 0x3515, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 board_20319 },
262 { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_20319 },
264 { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_20319 },
266 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_40518 },
268
269 { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
270 board_20619 },
271
272 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 board_20771 },
274 { } /* terminate list */
275};
276
277
278static struct pci_driver pdc_ata_pci_driver = {
279 .name = DRV_NAME,
280 .id_table = pdc_ata_pci_tbl,
281 .probe = pdc_ata_init_one,
282 .remove = ata_pci_remove_one,
283};
284
285
286static int pdc_port_start(struct ata_port *ap)
287{
288 struct device *dev = ap->host_set->dev;
289 struct pdc_port_priv *pp;
290 int rc;
291
292 rc = ata_port_start(ap);
293 if (rc)
294 return rc;
295
296 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
297 if (!pp) {
298 rc = -ENOMEM;
299 goto err_out;
300 }
301
302 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
303 if (!pp->pkt) {
304 rc = -ENOMEM;
305 goto err_out_kfree;
306 }
307
308 ap->private_data = pp;
309
310 return 0;
311
312err_out_kfree:
313 kfree(pp);
314err_out:
315 ata_port_stop(ap);
316 return rc;
317}
318
319
320static void pdc_port_stop(struct ata_port *ap)
321{
322 struct device *dev = ap->host_set->dev;
323 struct pdc_port_priv *pp = ap->private_data;
324
325 ap->private_data = NULL;
326 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
327 kfree(pp);
328 ata_port_stop(ap);
329}
330
331
332static void pdc_host_stop(struct ata_host_set *host_set)
333{
334 struct pdc_host_priv *hp = host_set->private_data;
335
336 ata_pci_host_stop(host_set);
337
338 kfree(hp);
339}
340
341
342static void pdc_reset_port(struct ata_port *ap)
343{
344 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
345 unsigned int i;
346 u32 tmp;
347
348 for (i = 11; i > 0; i--) {
349 tmp = readl(mmio);
350 if (tmp & PDC_RESET)
351 break;
352
353 udelay(100);
354
355 tmp |= PDC_RESET;
356 writel(tmp, mmio);
357 }
358
359 tmp &= ~PDC_RESET;
360 writel(tmp, mmio);
361 readl(mmio); /* flush */
362}
363
364static void pdc_sata_phy_reset(struct ata_port *ap)
365{
366 pdc_reset_port(ap);
367 sata_phy_reset(ap);
368}
369
370static void pdc_pata_cbl_detect(struct ata_port *ap)
371{
372 u8 tmp;
373 void __iomem *mmio = (void *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
374
375 tmp = readb(mmio);
376
377 if (tmp & 0x01) {
378 ap->cbl = ATA_CBL_PATA40;
379 ap->udma_mask &= ATA_UDMA_MASK_40C;
380 } else
381 ap->cbl = ATA_CBL_PATA80;
382}
383
384static void pdc_pata_phy_reset(struct ata_port *ap)
385{
386 pdc_pata_cbl_detect(ap);
387 pdc_reset_port(ap);
388 ata_port_probe(ap);
389 ata_bus_reset(ap);
390}
391
392static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
393{
394 if (sc_reg > SCR_CONTROL)
395 return 0xffffffffU;
396 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
397}
398
399
400static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
401 u32 val)
402{
403 if (sc_reg > SCR_CONTROL)
404 return;
405 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
406}
407
408static void pdc_qc_prep(struct ata_queued_cmd *qc)
409{
410 struct pdc_port_priv *pp = qc->ap->private_data;
411 unsigned int i;
412
413 VPRINTK("ENTER\n");
414
415 switch (qc->tf.protocol) {
416 case ATA_PROT_DMA:
417 ata_qc_prep(qc);
418 /* fall through */
419
420 case ATA_PROT_NODATA:
421 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
422 qc->dev->devno, pp->pkt);
423
424 if (qc->tf.flags & ATA_TFLAG_LBA48)
425 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
426 else
427 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
428
429 pdc_pkt_footer(&qc->tf, pp->pkt, i);
430 break;
431
432 default:
433 break;
434 }
435}
436
437static void pdc_eng_timeout(struct ata_port *ap)
438{
439 struct ata_host_set *host_set = ap->host_set;
440 u8 drv_stat;
441 struct ata_queued_cmd *qc;
442 unsigned long flags;
443
444 DPRINTK("ENTER\n");
445
446 spin_lock_irqsave(&host_set->lock, flags);
447
448 qc = ata_qc_from_tag(ap, ap->active_tag);
449
450 switch (qc->tf.protocol) {
451 case ATA_PROT_DMA:
452 case ATA_PROT_NODATA:
453 ata_port_printk(ap, KERN_ERR, "command timeout\n");
454 drv_stat = ata_wait_idle(ap);
455 qc->err_mask |= __ac_err_mask(drv_stat);
456 break;
457
458 default:
459 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
460
461 ata_port_printk(ap, KERN_ERR,
462 "unknown timeout, cmd 0x%x stat 0x%x\n",
463 qc->tf.command, drv_stat);
464
465 qc->err_mask |= ac_err_mask(drv_stat);
466 break;
467 }
468
469 spin_unlock_irqrestore(&host_set->lock, flags);
470 ata_eh_qc_complete(qc);
471 DPRINTK("EXIT\n");
472}
473
474static inline unsigned int pdc_host_intr( struct ata_port *ap,
475 struct ata_queued_cmd *qc)
476{
477 unsigned int handled = 0;
478 u32 tmp;
479 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
480
481 tmp = readl(mmio);
482 if (tmp & PDC_ERR_MASK) {
483 qc->err_mask |= AC_ERR_DEV;
484 pdc_reset_port(ap);
485 }
486
487 switch (qc->tf.protocol) {
488 case ATA_PROT_DMA:
489 case ATA_PROT_NODATA:
490 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
491 ata_qc_complete(qc);
492 handled = 1;
493 break;
494
495 default:
496 ap->stats.idle_irq++;
497 break;
498 }
499
500 return handled;
501}
502
503static void pdc_irq_clear(struct ata_port *ap)
504{
505 struct ata_host_set *host_set = ap->host_set;
506 void __iomem *mmio = host_set->mmio_base;
507
508 readl(mmio + PDC_INT_SEQMASK);
509}
510
511static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
512{
513 struct ata_host_set *host_set = dev_instance;
514 struct ata_port *ap;
515 u32 mask = 0;
516 unsigned int i, tmp;
517 unsigned int handled = 0;
518 void __iomem *mmio_base;
519
520 VPRINTK("ENTER\n");
521
522 if (!host_set || !host_set->mmio_base) {
523 VPRINTK("QUICK EXIT\n");
524 return IRQ_NONE;
525 }
526
527 mmio_base = host_set->mmio_base;
528
529 /* reading should also clear interrupts */
530 mask = readl(mmio_base + PDC_INT_SEQMASK);
531
532 if (mask == 0xffffffff) {
533 VPRINTK("QUICK EXIT 2\n");
534 return IRQ_NONE;
535 }
536
537 spin_lock(&host_set->lock);
538
539 mask &= 0xffff; /* only 16 tags possible */
540 if (!mask) {
541 VPRINTK("QUICK EXIT 3\n");
542 goto done_irq;
543 }
544
545 writel(mask, mmio_base + PDC_INT_SEQMASK);
546
547 for (i = 0; i < host_set->n_ports; i++) {
548 VPRINTK("port %u\n", i);
549 ap = host_set->ports[i];
550 tmp = mask & (1 << (i + 1));
551 if (tmp && ap &&
552 !(ap->flags & ATA_FLAG_DISABLED)) {
553 struct ata_queued_cmd *qc;
554
555 qc = ata_qc_from_tag(ap, ap->active_tag);
556 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
557 handled += pdc_host_intr(ap, qc);
558 }
559 }
560
561 VPRINTK("EXIT\n");
562
563done_irq:
564 spin_unlock(&host_set->lock);
565 return IRQ_RETVAL(handled);
566}
567
568static inline void pdc_packet_start(struct ata_queued_cmd *qc)
569{
570 struct ata_port *ap = qc->ap;
571 struct pdc_port_priv *pp = ap->private_data;
572 unsigned int port_no = ap->port_no;
573 u8 seq = (u8) (port_no + 1);
574
575 VPRINTK("ENTER, ap %p\n", ap);
576
577 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
578 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
579
580 pp->pkt[2] = seq;
581 wmb(); /* flush PRD, pkt writes */
582 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
583 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
584}
585
586static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
587{
588 switch (qc->tf.protocol) {
589 case ATA_PROT_DMA:
590 case ATA_PROT_NODATA:
591 pdc_packet_start(qc);
592 return 0;
593
594 case ATA_PROT_ATAPI_DMA:
595 BUG();
596 break;
597
598 default:
599 break;
600 }
601
602 return ata_qc_issue_prot(qc);
603}
604
605static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
606{
607 WARN_ON (tf->protocol == ATA_PROT_DMA ||
608 tf->protocol == ATA_PROT_NODATA);
609 ata_tf_load(ap, tf);
610}
611
612
613static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
614{
615 WARN_ON (tf->protocol == ATA_PROT_DMA ||
616 tf->protocol == ATA_PROT_NODATA);
617 ata_exec_command(ap, tf);
618}
619
620
621static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
622{
623 port->cmd_addr = base;
624 port->data_addr = base;
625 port->feature_addr =
626 port->error_addr = base + 0x4;
627 port->nsect_addr = base + 0x8;
628 port->lbal_addr = base + 0xc;
629 port->lbam_addr = base + 0x10;
630 port->lbah_addr = base + 0x14;
631 port->device_addr = base + 0x18;
632 port->command_addr =
633 port->status_addr = base + 0x1c;
634 port->altstatus_addr =
635 port->ctl_addr = base + 0x38;
636}
637
638
639static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
640{
641 void __iomem *mmio = pe->mmio_base;
642 struct pdc_host_priv *hp = pe->private_data;
643 int hotplug_offset = hp->hotplug_offset;
644 u32 tmp;
645
646 /*
647 * Except for the hotplug stuff, this is voodoo from the
648 * Promise driver. Label this entire section
649 * "TODO: figure out why we do this"
650 */
651
652 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
653 tmp = readl(mmio + PDC_FLASH_CTL);
654 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
655 writel(tmp, mmio + PDC_FLASH_CTL);
656
657 /* clear plug/unplug flags for all ports */
658 tmp = readl(mmio + hotplug_offset);
659 writel(tmp | 0xff, mmio + hotplug_offset);
660
661 /* mask plug/unplug ints */
662 tmp = readl(mmio + hotplug_offset);
663 writel(tmp | 0xff0000, mmio + hotplug_offset);
664
665 /* reduce TBG clock to 133 Mhz. */
666 tmp = readl(mmio + PDC_TBG_MODE);
667 tmp &= ~0x30000; /* clear bit 17, 16*/
668 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
669 writel(tmp, mmio + PDC_TBG_MODE);
670
671 readl(mmio + PDC_TBG_MODE); /* flush */
672 msleep(10);
673
674 /* adjust slew rate control register. */
675 tmp = readl(mmio + PDC_SLEW_CTL);
676 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
677 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
678 writel(tmp, mmio + PDC_SLEW_CTL);
679}
680
681static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
682{
683 static int printed_version;
684 struct ata_probe_ent *probe_ent = NULL;
685 struct pdc_host_priv *hp;
686 unsigned long base;
687 void __iomem *mmio_base;
688 unsigned int board_idx = (unsigned int) ent->driver_data;
689 int pci_dev_busy = 0;
690 int rc;
691
692 if (!printed_version++)
693 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
694
695 rc = pci_enable_device(pdev);
696 if (rc)
697 return rc;
698
699 rc = pci_request_regions(pdev, DRV_NAME);
700 if (rc) {
701 pci_dev_busy = 1;
702 goto err_out;
703 }
704
705 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
706 if (rc)
707 goto err_out_regions;
708 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
709 if (rc)
710 goto err_out_regions;
711
712 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
713 if (probe_ent == NULL) {
714 rc = -ENOMEM;
715 goto err_out_regions;
716 }
717
718 probe_ent->dev = pci_dev_to_dev(pdev);
719 INIT_LIST_HEAD(&probe_ent->node);
720
721 mmio_base = pci_iomap(pdev, 3, 0);
722 if (mmio_base == NULL) {
723 rc = -ENOMEM;
724 goto err_out_free_ent;
725 }
726 base = (unsigned long) mmio_base;
727
728 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
729 if (hp == NULL) {
730 rc = -ENOMEM;
731 goto err_out_free_ent;
732 }
733
734 /* Set default hotplug offset */
735 hp->hotplug_offset = PDC_SATA_PLUG_CSR;
736 probe_ent->private_data = hp;
737
738 probe_ent->sht = pdc_port_info[board_idx].sht;
739 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
740 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
741 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
742 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
743 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
744
745 probe_ent->irq = pdev->irq;
746 probe_ent->irq_flags = SA_SHIRQ;
747 probe_ent->mmio_base = mmio_base;
748
749 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
750 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
751
752 probe_ent->port[0].scr_addr = base + 0x400;
753 probe_ent->port[1].scr_addr = base + 0x500;
754
755 /* notice 4-port boards */
756 switch (board_idx) {
757 case board_40518:
758 /* Override hotplug offset for SATAII150 */
759 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
760 /* Fall through */
761 case board_20319:
762 probe_ent->n_ports = 4;
763
764 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
765 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
766
767 probe_ent->port[2].scr_addr = base + 0x600;
768 probe_ent->port[3].scr_addr = base + 0x700;
769 break;
770 case board_2057x:
771 /* Override hotplug offset for SATAII150 */
772 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
773 /* Fall through */
774 case board_2037x:
775 probe_ent->n_ports = 2;
776 break;
777 case board_20771:
778 probe_ent->n_ports = 2;
779 break;
780 case board_20619:
781 probe_ent->n_ports = 4;
782
783 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
784 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
785
786 probe_ent->port[2].scr_addr = base + 0x600;
787 probe_ent->port[3].scr_addr = base + 0x700;
788 break;
789 default:
790 BUG();
791 break;
792 }
793
794 pci_set_master(pdev);
795
796 /* initialize adapter */
797 pdc_host_init(board_idx, probe_ent);
798
799 /* FIXME: Need any other frees than hp? */
800 if (!ata_device_add(probe_ent))
801 kfree(hp);
802
803 kfree(probe_ent);
804
805 return 0;
806
807err_out_free_ent:
808 kfree(probe_ent);
809err_out_regions:
810 pci_release_regions(pdev);
811err_out:
812 if (!pci_dev_busy)
813 pci_disable_device(pdev);
814 return rc;
815}
816
817
818static int __init pdc_ata_init(void)
819{
820 return pci_module_init(&pdc_ata_pci_driver);
821}
822
823
824static void __exit pdc_ata_exit(void)
825{
826 pci_unregister_driver(&pdc_ata_pci_driver);
827}
828
829
830MODULE_AUTHOR("Jeff Garzik");
831MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
832MODULE_LICENSE("GPL");
833MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
834MODULE_VERSION(DRV_VERSION);
835
836module_init(pdc_ata_init);
837module_exit(pdc_ata_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-21 00:56:38 -0400