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path: root/drivers/scsi/sata_mv.c
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-rw-r--r--drivers/scsi/sata_mv.c1001
1 files changed, 829 insertions, 172 deletions
diff --git a/drivers/scsi/sata_mv.c b/drivers/scsi/sata_mv.c
index 93d55233af7b..9321cdf45680 100644
--- a/drivers/scsi/sata_mv.c
+++ b/drivers/scsi/sata_mv.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * sata_mv.c - Marvell SATA support 2 * sata_mv.c - Marvell SATA support
3 * 3 *
4 * Copyright 2005: EMC Corporation, all rights reserved. 4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
5 * 6 *
6 * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
7 * 8 *
@@ -36,7 +37,7 @@
36#include <asm/io.h> 37#include <asm/io.h>
37 38
38#define DRV_NAME "sata_mv" 39#define DRV_NAME "sata_mv"
39#define DRV_VERSION "0.25" 40#define DRV_VERSION "0.5"
40 41
41enum { 42enum {
42 /* BAR's are enumerated in terms of pci_resource_start() terms */ 43 /* BAR's are enumerated in terms of pci_resource_start() terms */
@@ -50,6 +51,9 @@ enum {
50 MV_PCI_REG_BASE = 0, 51 MV_PCI_REG_BASE = 0,
51 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 52 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
52 MV_SATAHC0_REG_BASE = 0x20000, 53 MV_SATAHC0_REG_BASE = 0x20000,
54 MV_FLASH_CTL = 0x1046c,
55 MV_GPIO_PORT_CTL = 0x104f0,
56 MV_RESET_CFG = 0x180d8,
53 57
54 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 58 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
55 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 59 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
@@ -72,11 +76,6 @@ enum {
72 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 76 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
73 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ), 77 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
74 78
75 /* Our DMA boundary is determined by an ePRD being unable to handle
76 * anything larger than 64KB
77 */
78 MV_DMA_BOUNDARY = 0xffffU,
79
80 MV_PORTS_PER_HC = 4, 79 MV_PORTS_PER_HC = 4,
81 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ 80 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
82 MV_PORT_HC_SHIFT = 2, 81 MV_PORT_HC_SHIFT = 2,
@@ -86,16 +85,10 @@ enum {
86 /* Host Flags */ 85 /* Host Flags */
87 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 86 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
88 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 87 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
89 MV_FLAG_GLBL_SFT_RST = (1 << 28), /* Global Soft Reset support */
90 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 88 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
91 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO), 89 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
92 MV_6XXX_FLAGS = (MV_FLAG_IRQ_COALESCE | 90 ATA_FLAG_NO_ATAPI),
93 MV_FLAG_GLBL_SFT_RST), 91 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
94
95 chip_504x = 0,
96 chip_508x = 1,
97 chip_604x = 2,
98 chip_608x = 3,
99 92
100 CRQB_FLAG_READ = (1 << 0), 93 CRQB_FLAG_READ = (1 << 0),
101 CRQB_TAG_SHIFT = 1, 94 CRQB_TAG_SHIFT = 1,
@@ -116,8 +109,19 @@ enum {
116 PCI_MASTER_EMPTY = (1 << 3), 109 PCI_MASTER_EMPTY = (1 << 3),
117 GLOB_SFT_RST = (1 << 4), 110 GLOB_SFT_RST = (1 << 4),
118 111
119 PCI_IRQ_CAUSE_OFS = 0x1d58, 112 MV_PCI_MODE = 0xd00,
120 PCI_IRQ_MASK_OFS = 0x1d5c, 113 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
114 MV_PCI_DISC_TIMER = 0xd04,
115 MV_PCI_MSI_TRIGGER = 0xc38,
116 MV_PCI_SERR_MASK = 0xc28,
117 MV_PCI_XBAR_TMOUT = 0x1d04,
118 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
119 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
120 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
121 MV_PCI_ERR_COMMAND = 0x1d50,
122
123 PCI_IRQ_CAUSE_OFS = 0x1d58,
124 PCI_IRQ_MASK_OFS = 0x1d5c,
121 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 125 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
122 126
123 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 127 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
@@ -134,7 +138,7 @@ enum {
134 SELF_INT = (1 << 23), 138 SELF_INT = (1 << 23),
135 TWSI_INT = (1 << 24), 139 TWSI_INT = (1 << 24),
136 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 140 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
137 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | 141 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
138 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | 142 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
139 HC_MAIN_RSVD), 143 HC_MAIN_RSVD),
140 144
@@ -153,6 +157,15 @@ enum {
153 /* SATA registers */ 157 /* SATA registers */
154 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 158 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
155 SATA_ACTIVE_OFS = 0x350, 159 SATA_ACTIVE_OFS = 0x350,
160 PHY_MODE3 = 0x310,
161 PHY_MODE4 = 0x314,
162 PHY_MODE2 = 0x330,
163 MV5_PHY_MODE = 0x74,
164 MV5_LT_MODE = 0x30,
165 MV5_PHY_CTL = 0x0C,
166 SATA_INTERFACE_CTL = 0x050,
167
168 MV_M2_PREAMP_MASK = 0x7e0,
156 169
157 /* Port registers */ 170 /* Port registers */
158 EDMA_CFG_OFS = 0, 171 EDMA_CFG_OFS = 0,
@@ -182,17 +195,16 @@ enum {
182 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), 195 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
183 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), 196 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
184 EDMA_ERR_TRANS_PROTO = (1 << 31), 197 EDMA_ERR_TRANS_PROTO = (1 << 31),
185 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 198 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
186 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR | 199 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
187 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR | 200 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
188 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 | 201 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
189 EDMA_ERR_LNK_DATA_RX | 202 EDMA_ERR_LNK_DATA_RX |
190 EDMA_ERR_LNK_DATA_TX | 203 EDMA_ERR_LNK_DATA_TX |
191 EDMA_ERR_TRANS_PROTO), 204 EDMA_ERR_TRANS_PROTO),
192 205
193 EDMA_REQ_Q_BASE_HI_OFS = 0x10, 206 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
194 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 207 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
195 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
196 208
197 EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 209 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
198 EDMA_REQ_Q_PTR_SHIFT = 5, 210 EDMA_REQ_Q_PTR_SHIFT = 5,
@@ -200,7 +212,6 @@ enum {
200 EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 212 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
201 EDMA_RSP_Q_IN_PTR_OFS = 0x20, 213 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
202 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 214 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
203 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
204 EDMA_RSP_Q_PTR_SHIFT = 3, 215 EDMA_RSP_Q_PTR_SHIFT = 3,
205 216
206 EDMA_CMD_OFS = 0x28, 217 EDMA_CMD_OFS = 0x28,
@@ -208,14 +219,44 @@ enum {
208 EDMA_DS = (1 << 1), 219 EDMA_DS = (1 << 1),
209 ATA_RST = (1 << 2), 220 ATA_RST = (1 << 2),
210 221
222 EDMA_IORDY_TMOUT = 0x34,
223 EDMA_ARB_CFG = 0x38,
224
211 /* Host private flags (hp_flags) */ 225 /* Host private flags (hp_flags) */
212 MV_HP_FLAG_MSI = (1 << 0), 226 MV_HP_FLAG_MSI = (1 << 0),
227 MV_HP_ERRATA_50XXB0 = (1 << 1),
228 MV_HP_ERRATA_50XXB2 = (1 << 2),
229 MV_HP_ERRATA_60X1B2 = (1 << 3),
230 MV_HP_ERRATA_60X1C0 = (1 << 4),
231 MV_HP_50XX = (1 << 5),
213 232
214 /* Port private flags (pp_flags) */ 233 /* Port private flags (pp_flags) */
215 MV_PP_FLAG_EDMA_EN = (1 << 0), 234 MV_PP_FLAG_EDMA_EN = (1 << 0),
216 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1), 235 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
217}; 236};
218 237
238#define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
239#define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
240
241enum {
242 /* Our DMA boundary is determined by an ePRD being unable to handle
243 * anything larger than 64KB
244 */
245 MV_DMA_BOUNDARY = 0xffffU,
246
247 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
248
249 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
250};
251
252enum chip_type {
253 chip_504x,
254 chip_508x,
255 chip_5080,
256 chip_604x,
257 chip_608x,
258};
259
219/* Command ReQuest Block: 32B */ 260/* Command ReQuest Block: 32B */
220struct mv_crqb { 261struct mv_crqb {
221 u32 sg_addr; 262 u32 sg_addr;
@@ -252,14 +293,37 @@ struct mv_port_priv {
252 u32 pp_flags; 293 u32 pp_flags;
253}; 294};
254 295
296struct mv_port_signal {
297 u32 amps;
298 u32 pre;
299};
300
301struct mv_host_priv;
302struct mv_hw_ops {
303 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
304 unsigned int port);
305 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
306 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
307 void __iomem *mmio);
308 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
309 unsigned int n_hc);
310 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
311 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
312};
313
255struct mv_host_priv { 314struct mv_host_priv {
256 u32 hp_flags; 315 u32 hp_flags;
316 struct mv_port_signal signal[8];
317 const struct mv_hw_ops *ops;
257}; 318};
258 319
259static void mv_irq_clear(struct ata_port *ap); 320static void mv_irq_clear(struct ata_port *ap);
260static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in); 321static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
261static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 322static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
323static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
324static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
262static void mv_phy_reset(struct ata_port *ap); 325static void mv_phy_reset(struct ata_port *ap);
326static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
263static void mv_host_stop(struct ata_host_set *host_set); 327static void mv_host_stop(struct ata_host_set *host_set);
264static int mv_port_start(struct ata_port *ap); 328static int mv_port_start(struct ata_port *ap);
265static void mv_port_stop(struct ata_port *ap); 329static void mv_port_stop(struct ata_port *ap);
@@ -270,6 +334,29 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance,
270static void mv_eng_timeout(struct ata_port *ap); 334static void mv_eng_timeout(struct ata_port *ap);
271static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 335static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
272 336
337static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
338 unsigned int port);
339static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
340static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
341 void __iomem *mmio);
342static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
343 unsigned int n_hc);
344static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
345static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
346
347static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
348 unsigned int port);
349static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
350static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
351 void __iomem *mmio);
352static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
353 unsigned int n_hc);
354static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
355static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
356static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
357 unsigned int port_no);
358static void mv_stop_and_reset(struct ata_port *ap);
359
273static struct scsi_host_template mv_sht = { 360static struct scsi_host_template mv_sht = {
274 .module = THIS_MODULE, 361 .module = THIS_MODULE,
275 .name = DRV_NAME, 362 .name = DRV_NAME,
@@ -278,7 +365,7 @@ static struct scsi_host_template mv_sht = {
278 .eh_strategy_handler = ata_scsi_error, 365 .eh_strategy_handler = ata_scsi_error,
279 .can_queue = MV_USE_Q_DEPTH, 366 .can_queue = MV_USE_Q_DEPTH,
280 .this_id = ATA_SHT_THIS_ID, 367 .this_id = ATA_SHT_THIS_ID,
281 .sg_tablesize = MV_MAX_SG_CT, 368 .sg_tablesize = MV_MAX_SG_CT / 2,
282 .max_sectors = ATA_MAX_SECTORS, 369 .max_sectors = ATA_MAX_SECTORS,
283 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 370 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
284 .emulated = ATA_SHT_EMULATED, 371 .emulated = ATA_SHT_EMULATED,
@@ -290,7 +377,34 @@ static struct scsi_host_template mv_sht = {
290 .ordered_flush = 1, 377 .ordered_flush = 1,
291}; 378};
292 379
293static const struct ata_port_operations mv_ops = { 380static const struct ata_port_operations mv5_ops = {
381 .port_disable = ata_port_disable,
382
383 .tf_load = ata_tf_load,
384 .tf_read = ata_tf_read,
385 .check_status = ata_check_status,
386 .exec_command = ata_exec_command,
387 .dev_select = ata_std_dev_select,
388
389 .phy_reset = mv_phy_reset,
390
391 .qc_prep = mv_qc_prep,
392 .qc_issue = mv_qc_issue,
393
394 .eng_timeout = mv_eng_timeout,
395
396 .irq_handler = mv_interrupt,
397 .irq_clear = mv_irq_clear,
398
399 .scr_read = mv5_scr_read,
400 .scr_write = mv5_scr_write,
401
402 .port_start = mv_port_start,
403 .port_stop = mv_port_stop,
404 .host_stop = mv_host_stop,
405};
406
407static const struct ata_port_operations mv6_ops = {
294 .port_disable = ata_port_disable, 408 .port_disable = ata_port_disable,
295 409
296 .tf_load = ata_tf_load, 410 .tf_load = ata_tf_load,
@@ -322,43 +436,52 @@ static struct ata_port_info mv_port_info[] = {
322 .sht = &mv_sht, 436 .sht = &mv_sht,
323 .host_flags = MV_COMMON_FLAGS, 437 .host_flags = MV_COMMON_FLAGS,
324 .pio_mask = 0x1f, /* pio0-4 */ 438 .pio_mask = 0x1f, /* pio0-4 */
325 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */ 439 .udma_mask = 0x7f, /* udma0-6 */
326 .port_ops = &mv_ops, 440 .port_ops = &mv5_ops,
327 }, 441 },
328 { /* chip_508x */ 442 { /* chip_508x */
329 .sht = &mv_sht, 443 .sht = &mv_sht,
330 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), 444 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
331 .pio_mask = 0x1f, /* pio0-4 */ 445 .pio_mask = 0x1f, /* pio0-4 */
332 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */ 446 .udma_mask = 0x7f, /* udma0-6 */
333 .port_ops = &mv_ops, 447 .port_ops = &mv5_ops,
448 },
449 { /* chip_5080 */
450 .sht = &mv_sht,
451 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
452 .pio_mask = 0x1f, /* pio0-4 */
453 .udma_mask = 0x7f, /* udma0-6 */
454 .port_ops = &mv5_ops,
334 }, 455 },
335 { /* chip_604x */ 456 { /* chip_604x */
336 .sht = &mv_sht, 457 .sht = &mv_sht,
337 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), 458 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
338 .pio_mask = 0x1f, /* pio0-4 */ 459 .pio_mask = 0x1f, /* pio0-4 */
339 .udma_mask = 0x7f, /* udma0-6 */ 460 .udma_mask = 0x7f, /* udma0-6 */
340 .port_ops = &mv_ops, 461 .port_ops = &mv6_ops,
341 }, 462 },
342 { /* chip_608x */ 463 { /* chip_608x */
343 .sht = &mv_sht, 464 .sht = &mv_sht,
344 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS | 465 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
345 MV_FLAG_DUAL_HC), 466 MV_FLAG_DUAL_HC),
346 .pio_mask = 0x1f, /* pio0-4 */ 467 .pio_mask = 0x1f, /* pio0-4 */
347 .udma_mask = 0x7f, /* udma0-6 */ 468 .udma_mask = 0x7f, /* udma0-6 */
348 .port_ops = &mv_ops, 469 .port_ops = &mv6_ops,
349 }, 470 },
350}; 471};
351 472
352static struct pci_device_id mv_pci_tbl[] = { 473static const struct pci_device_id mv_pci_tbl[] = {
353 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x}, 474 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
354 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x}, 475 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
355 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_508x}, 476 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
356 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x}, 477 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
357 478
358 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x}, 479 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
359 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x}, 480 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
360 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x}, 481 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
361 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x}, 482 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
483
484 {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x},
362 {} /* terminate list */ 485 {} /* terminate list */
363}; 486};
364 487
@@ -369,6 +492,24 @@ static struct pci_driver mv_pci_driver = {
369 .remove = ata_pci_remove_one, 492 .remove = ata_pci_remove_one,
370}; 493};
371 494
495static const struct mv_hw_ops mv5xxx_ops = {
496 .phy_errata = mv5_phy_errata,
497 .enable_leds = mv5_enable_leds,
498 .read_preamp = mv5_read_preamp,
499 .reset_hc = mv5_reset_hc,
500 .reset_flash = mv5_reset_flash,
501 .reset_bus = mv5_reset_bus,
502};
503
504static const struct mv_hw_ops mv6xxx_ops = {
505 .phy_errata = mv6_phy_errata,
506 .enable_leds = mv6_enable_leds,
507 .read_preamp = mv6_read_preamp,
508 .reset_hc = mv6_reset_hc,
509 .reset_flash = mv6_reset_flash,
510 .reset_bus = mv_reset_pci_bus,
511};
512
372/* 513/*
373 * Functions 514 * Functions
374 */ 515 */
@@ -384,11 +525,27 @@ static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
384 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 525 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
385} 526}
386 527
528static inline unsigned int mv_hc_from_port(unsigned int port)
529{
530 return port >> MV_PORT_HC_SHIFT;
531}
532
533static inline unsigned int mv_hardport_from_port(unsigned int port)
534{
535 return port & MV_PORT_MASK;
536}
537
538static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
539 unsigned int port)
540{
541 return mv_hc_base(base, mv_hc_from_port(port));
542}
543
387static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 544static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
388{ 545{
389 return (mv_hc_base(base, port >> MV_PORT_HC_SHIFT) + 546 return mv_hc_base_from_port(base, port) +
390 MV_SATAHC_ARBTR_REG_SZ + 547 MV_SATAHC_ARBTR_REG_SZ +
391 ((port & MV_PORT_MASK) * MV_PORT_REG_SZ)); 548 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
392} 549}
393 550
394static inline void __iomem *mv_ap_base(struct ata_port *ap) 551static inline void __iomem *mv_ap_base(struct ata_port *ap)
@@ -396,9 +553,9 @@ static inline void __iomem *mv_ap_base(struct ata_port *ap)
396 return mv_port_base(ap->host_set->mmio_base, ap->port_no); 553 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
397} 554}
398 555
399static inline int mv_get_hc_count(unsigned long hp_flags) 556static inline int mv_get_hc_count(unsigned long host_flags)
400{ 557{
401 return ((hp_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 558 return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
402} 559}
403 560
404static void mv_irq_clear(struct ata_port *ap) 561static void mv_irq_clear(struct ata_port *ap)
@@ -450,7 +607,7 @@ static void mv_stop_dma(struct ata_port *ap)
450 } else { 607 } else {
451 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS))); 608 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
452 } 609 }
453 610
454 /* now properly wait for the eDMA to stop */ 611 /* now properly wait for the eDMA to stop */
455 for (i = 1000; i > 0; i--) { 612 for (i = 1000; i > 0; i--) {
456 reg = readl(port_mmio + EDMA_CMD_OFS); 613 reg = readl(port_mmio + EDMA_CMD_OFS);
@@ -501,7 +658,7 @@ static void mv_dump_all_regs(void __iomem *mmio_base, int port,
501 struct pci_dev *pdev) 658 struct pci_dev *pdev)
502{ 659{
503#ifdef ATA_DEBUG 660#ifdef ATA_DEBUG
504 void __iomem *hc_base = mv_hc_base(mmio_base, 661 void __iomem *hc_base = mv_hc_base(mmio_base,
505 port >> MV_PORT_HC_SHIFT); 662 port >> MV_PORT_HC_SHIFT);
506 void __iomem *port_base; 663 void __iomem *port_base;
507 int start_port, num_ports, p, start_hc, num_hcs, hc; 664 int start_port, num_ports, p, start_hc, num_hcs, hc;
@@ -515,7 +672,7 @@ static void mv_dump_all_regs(void __iomem *mmio_base, int port,
515 start_port = port; 672 start_port = port;
516 num_ports = num_hcs = 1; 673 num_ports = num_hcs = 1;
517 } 674 }
518 DPRINTK("All registers for port(s) %u-%u:\n", start_port, 675 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
519 num_ports > 1 ? num_ports - 1 : start_port); 676 num_ports > 1 ? num_ports - 1 : start_port);
520 677
521 if (NULL != pdev) { 678 if (NULL != pdev) {
@@ -583,70 +740,6 @@ static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
583} 740}
584 741
585/** 742/**
586 * mv_global_soft_reset - Perform the 6xxx global soft reset
587 * @mmio_base: base address of the HBA
588 *
589 * This routine only applies to 6xxx parts.
590 *
591 * LOCKING:
592 * Inherited from caller.
593 */
594static int mv_global_soft_reset(void __iomem *mmio_base)
595{
596 void __iomem *reg = mmio_base + PCI_MAIN_CMD_STS_OFS;
597 int i, rc = 0;
598 u32 t;
599
600 /* Following procedure defined in PCI "main command and status
601 * register" table.
602 */
603 t = readl(reg);
604 writel(t | STOP_PCI_MASTER, reg);
605
606 for (i = 0; i < 1000; i++) {
607 udelay(1);
608 t = readl(reg);
609 if (PCI_MASTER_EMPTY & t) {
610 break;
611 }
612 }
613 if (!(PCI_MASTER_EMPTY & t)) {
614 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
615 rc = 1;
616 goto done;
617 }
618
619 /* set reset */
620 i = 5;
621 do {
622 writel(t | GLOB_SFT_RST, reg);
623 t = readl(reg);
624 udelay(1);
625 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
626
627 if (!(GLOB_SFT_RST & t)) {
628 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
629 rc = 1;
630 goto done;
631 }
632
633 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
634 i = 5;
635 do {
636 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
637 t = readl(reg);
638 udelay(1);
639 } while ((GLOB_SFT_RST & t) && (i-- > 0));
640
641 if (GLOB_SFT_RST & t) {
642 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
643 rc = 1;
644 }
645done:
646 return rc;
647}
648
649/**
650 * mv_host_stop - Host specific cleanup/stop routine. 743 * mv_host_stop - Host specific cleanup/stop routine.
651 * @host_set: host data structure 744 * @host_set: host data structure
652 * 745 *
@@ -699,7 +792,7 @@ static int mv_port_start(struct ata_port *ap)
699 goto err_out; 792 goto err_out;
700 memset(pp, 0, sizeof(*pp)); 793 memset(pp, 0, sizeof(*pp));
701 794
702 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma, 795 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
703 GFP_KERNEL); 796 GFP_KERNEL);
704 if (!mem) 797 if (!mem)
705 goto err_out_pp; 798 goto err_out_pp;
@@ -709,7 +802,7 @@ static int mv_port_start(struct ata_port *ap)
709 if (rc) 802 if (rc)
710 goto err_out_priv; 803 goto err_out_priv;
711 804
712 /* First item in chunk of DMA memory: 805 /* First item in chunk of DMA memory:
713 * 32-slot command request table (CRQB), 32 bytes each in size 806 * 32-slot command request table (CRQB), 32 bytes each in size
714 */ 807 */
715 pp->crqb = mem; 808 pp->crqb = mem;
@@ -717,7 +810,7 @@ static int mv_port_start(struct ata_port *ap)
717 mem += MV_CRQB_Q_SZ; 810 mem += MV_CRQB_Q_SZ;
718 mem_dma += MV_CRQB_Q_SZ; 811 mem_dma += MV_CRQB_Q_SZ;
719 812
720 /* Second item: 813 /* Second item:
721 * 32-slot command response table (CRPB), 8 bytes each in size 814 * 32-slot command response table (CRPB), 8 bytes each in size
722 */ 815 */
723 pp->crpb = mem; 816 pp->crpb = mem;
@@ -731,18 +824,18 @@ static int mv_port_start(struct ata_port *ap)
731 pp->sg_tbl = mem; 824 pp->sg_tbl = mem;
732 pp->sg_tbl_dma = mem_dma; 825 pp->sg_tbl_dma = mem_dma;
733 826
734 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT | 827 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
735 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS); 828 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
736 829
737 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 830 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
738 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK, 831 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
739 port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 832 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
740 833
741 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 834 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
742 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 835 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
743 836
744 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 837 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
745 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK, 838 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
746 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 839 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
747 840
748 pp->req_producer = pp->rsp_consumer = 0; 841 pp->req_producer = pp->rsp_consumer = 0;
@@ -803,20 +896,30 @@ static void mv_fill_sg(struct ata_queued_cmd *qc)
803 struct scatterlist *sg; 896 struct scatterlist *sg;
804 897
805 ata_for_each_sg(sg, qc) { 898 ata_for_each_sg(sg, qc) {
806 u32 sg_len;
807 dma_addr_t addr; 899 dma_addr_t addr;
900 u32 sg_len, len, offset;
808 901
809 addr = sg_dma_address(sg); 902 addr = sg_dma_address(sg);
810 sg_len = sg_dma_len(sg); 903 sg_len = sg_dma_len(sg);
811 904
812 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff); 905 while (sg_len) {
813 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16); 906 offset = addr & MV_DMA_BOUNDARY;
814 assert(0 == (sg_len & ~MV_DMA_BOUNDARY)); 907 len = sg_len;
815 pp->sg_tbl[i].flags_size = cpu_to_le32(sg_len); 908 if ((offset + sg_len) > 0x10000)
816 if (ata_sg_is_last(sg, qc)) 909 len = 0x10000 - offset;
817 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 910
911 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
912 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
913 pp->sg_tbl[i].flags_size = cpu_to_le32(len);
914
915 sg_len -= len;
916 addr += len;
917
918 if (!sg_len && ata_sg_is_last(sg, qc))
919 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
818 920
819 i++; 921 i++;
922 }
820 } 923 }
821} 924}
822 925
@@ -857,7 +960,7 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
857 } 960 }
858 961
859 /* the req producer index should be the same as we remember it */ 962 /* the req producer index should be the same as we remember it */
860 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >> 963 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
861 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == 964 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
862 pp->req_producer); 965 pp->req_producer);
863 966
@@ -869,9 +972,9 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
869 assert(MV_MAX_Q_DEPTH > qc->tag); 972 assert(MV_MAX_Q_DEPTH > qc->tag);
870 flags |= qc->tag << CRQB_TAG_SHIFT; 973 flags |= qc->tag << CRQB_TAG_SHIFT;
871 974
872 pp->crqb[pp->req_producer].sg_addr = 975 pp->crqb[pp->req_producer].sg_addr =
873 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff); 976 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
874 pp->crqb[pp->req_producer].sg_addr_hi = 977 pp->crqb[pp->req_producer].sg_addr_hi =
875 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16); 978 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
876 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags); 979 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
877 980
@@ -894,7 +997,7 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
894#ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */ 997#ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
895 case ATA_CMD_FPDMA_READ: 998 case ATA_CMD_FPDMA_READ:
896 case ATA_CMD_FPDMA_WRITE: 999 case ATA_CMD_FPDMA_WRITE:
897 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 1000 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
898 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 1001 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
899 break; 1002 break;
900#endif /* FIXME: remove this line when NCQ added */ 1003#endif /* FIXME: remove this line when NCQ added */
@@ -960,7 +1063,7 @@ static int mv_qc_issue(struct ata_queued_cmd *qc)
960 pp->req_producer); 1063 pp->req_producer);
961 /* until we do queuing, the queue should be empty at this point */ 1064 /* until we do queuing, the queue should be empty at this point */
962 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == 1065 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
963 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >> 1066 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
964 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK)); 1067 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
965 1068
966 mv_inc_q_index(&pp->req_producer); /* now incr producer index */ 1069 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
@@ -997,15 +1100,15 @@ static u8 mv_get_crpb_status(struct ata_port *ap)
997 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 1100 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
998 1101
999 /* the response consumer index should be the same as we remember it */ 1102 /* the response consumer index should be the same as we remember it */
1000 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == 1103 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1001 pp->rsp_consumer); 1104 pp->rsp_consumer);
1002 1105
1003 /* increment our consumer index... */ 1106 /* increment our consumer index... */
1004 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer); 1107 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
1005 1108
1006 /* and, until we do NCQ, there should only be 1 CRPB waiting */ 1109 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1007 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >> 1110 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
1008 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == 1111 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1009 pp->rsp_consumer); 1112 pp->rsp_consumer);
1010 1113
1011 /* write out our inc'd consumer index so EDMA knows we're caught up */ 1114 /* write out our inc'd consumer index so EDMA knows we're caught up */
@@ -1053,7 +1156,7 @@ static void mv_err_intr(struct ata_port *ap)
1053 1156
1054 /* check for fatal here and recover if needed */ 1157 /* check for fatal here and recover if needed */
1055 if (EDMA_ERR_FATAL & edma_err_cause) { 1158 if (EDMA_ERR_FATAL & edma_err_cause) {
1056 mv_phy_reset(ap); 1159 mv_stop_and_reset(ap);
1057 } 1160 }
1058} 1161}
1059 1162
@@ -1118,6 +1221,10 @@ static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1118 handled++; 1221 handled++;
1119 } 1222 }
1120 1223
1224 if (ap &&
1225 (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR)))
1226 continue;
1227
1121 err_mask = ac_err_mask(ata_status); 1228 err_mask = ac_err_mask(ata_status);
1122 1229
1123 shift = port << 1; /* (port * 2) */ 1230 shift = port << 1; /* (port * 2) */
@@ -1129,14 +1236,15 @@ static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1129 err_mask |= AC_ERR_OTHER; 1236 err_mask |= AC_ERR_OTHER;
1130 handled++; 1237 handled++;
1131 } 1238 }
1132 1239
1133 if (handled && ap) { 1240 if (handled && ap) {
1134 qc = ata_qc_from_tag(ap, ap->active_tag); 1241 qc = ata_qc_from_tag(ap, ap->active_tag);
1135 if (NULL != qc) { 1242 if (NULL != qc) {
1136 VPRINTK("port %u IRQ found for qc, " 1243 VPRINTK("port %u IRQ found for qc, "
1137 "ata_status 0x%x\n", port,ata_status); 1244 "ata_status 0x%x\n", port,ata_status);
1138 /* mark qc status appropriately */ 1245 /* mark qc status appropriately */
1139 ata_qc_complete(qc, err_mask); 1246 if (!(qc->tf.ctl & ATA_NIEN))
1247 ata_qc_complete(qc, err_mask);
1140 } 1248 }
1141 } 1249 }
1142 } 1250 }
@@ -1144,7 +1252,7 @@ static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1144} 1252}
1145 1253
1146/** 1254/**
1147 * mv_interrupt - 1255 * mv_interrupt -
1148 * @irq: unused 1256 * @irq: unused
1149 * @dev_instance: private data; in this case the host structure 1257 * @dev_instance: private data; in this case the host structure
1150 * @regs: unused 1258 * @regs: unused
@@ -1154,7 +1262,7 @@ static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1154 * routine to handle. Also check for PCI errors which are only 1262 * routine to handle. Also check for PCI errors which are only
1155 * reported here. 1263 * reported here.
1156 * 1264 *
1157 * LOCKING: 1265 * LOCKING:
1158 * This routine holds the host_set lock while processing pending 1266 * This routine holds the host_set lock while processing pending
1159 * interrupts. 1267 * interrupts.
1160 */ 1268 */
@@ -1200,8 +1308,422 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1200 return IRQ_RETVAL(handled); 1308 return IRQ_RETVAL(handled);
1201} 1309}
1202 1310
1311static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1312{
1313 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1314 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1315
1316 return hc_mmio + ofs;
1317}
1318
1319static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1320{
1321 unsigned int ofs;
1322
1323 switch (sc_reg_in) {
1324 case SCR_STATUS:
1325 case SCR_ERROR:
1326 case SCR_CONTROL:
1327 ofs = sc_reg_in * sizeof(u32);
1328 break;
1329 default:
1330 ofs = 0xffffffffU;
1331 break;
1332 }
1333 return ofs;
1334}
1335
1336static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1337{
1338 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1339 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1340
1341 if (ofs != 0xffffffffU)
1342 return readl(mmio + ofs);
1343 else
1344 return (u32) ofs;
1345}
1346
1347static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1348{
1349 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1350 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1351
1352 if (ofs != 0xffffffffU)
1353 writelfl(val, mmio + ofs);
1354}
1355
1356static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1357{
1358 u8 rev_id;
1359 int early_5080;
1360
1361 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1362
1363 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1364
1365 if (!early_5080) {
1366 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1367 tmp |= (1 << 0);
1368 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1369 }
1370
1371 mv_reset_pci_bus(pdev, mmio);
1372}
1373
1374static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1375{
1376 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1377}
1378
1379static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1380 void __iomem *mmio)
1381{
1382 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1383 u32 tmp;
1384
1385 tmp = readl(phy_mmio + MV5_PHY_MODE);
1386
1387 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1388 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1389}
1390
1391static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1392{
1393 u32 tmp;
1394
1395 writel(0, mmio + MV_GPIO_PORT_CTL);
1396
1397 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1398
1399 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1400 tmp |= ~(1 << 0);
1401 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1402}
1403
1404static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1405 unsigned int port)
1406{
1407 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1408 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1409 u32 tmp;
1410 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1411
1412 if (fix_apm_sq) {
1413 tmp = readl(phy_mmio + MV5_LT_MODE);
1414 tmp |= (1 << 19);
1415 writel(tmp, phy_mmio + MV5_LT_MODE);
1416
1417 tmp = readl(phy_mmio + MV5_PHY_CTL);
1418 tmp &= ~0x3;
1419 tmp |= 0x1;
1420 writel(tmp, phy_mmio + MV5_PHY_CTL);
1421 }
1422
1423 tmp = readl(phy_mmio + MV5_PHY_MODE);
1424 tmp &= ~mask;
1425 tmp |= hpriv->signal[port].pre;
1426 tmp |= hpriv->signal[port].amps;
1427 writel(tmp, phy_mmio + MV5_PHY_MODE);
1428}
1429
1430
1431#undef ZERO
1432#define ZERO(reg) writel(0, port_mmio + (reg))
1433static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1434 unsigned int port)
1435{
1436 void __iomem *port_mmio = mv_port_base(mmio, port);
1437
1438 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1439
1440 mv_channel_reset(hpriv, mmio, port);
1441
1442 ZERO(0x028); /* command */
1443 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1444 ZERO(0x004); /* timer */
1445 ZERO(0x008); /* irq err cause */
1446 ZERO(0x00c); /* irq err mask */
1447 ZERO(0x010); /* rq bah */
1448 ZERO(0x014); /* rq inp */
1449 ZERO(0x018); /* rq outp */
1450 ZERO(0x01c); /* respq bah */
1451 ZERO(0x024); /* respq outp */
1452 ZERO(0x020); /* respq inp */
1453 ZERO(0x02c); /* test control */
1454 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1455}
1456#undef ZERO
1457
1458#define ZERO(reg) writel(0, hc_mmio + (reg))
1459static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1460 unsigned int hc)
1461{
1462 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1463 u32 tmp;
1464
1465 ZERO(0x00c);
1466 ZERO(0x010);
1467 ZERO(0x014);
1468 ZERO(0x018);
1469
1470 tmp = readl(hc_mmio + 0x20);
1471 tmp &= 0x1c1c1c1c;
1472 tmp |= 0x03030303;
1473 writel(tmp, hc_mmio + 0x20);
1474}
1475#undef ZERO
1476
1477static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1478 unsigned int n_hc)
1479{
1480 unsigned int hc, port;
1481
1482 for (hc = 0; hc < n_hc; hc++) {
1483 for (port = 0; port < MV_PORTS_PER_HC; port++)
1484 mv5_reset_hc_port(hpriv, mmio,
1485 (hc * MV_PORTS_PER_HC) + port);
1486
1487 mv5_reset_one_hc(hpriv, mmio, hc);
1488 }
1489
1490 return 0;
1491}
1492
1493#undef ZERO
1494#define ZERO(reg) writel(0, mmio + (reg))
1495static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1496{
1497 u32 tmp;
1498
1499 tmp = readl(mmio + MV_PCI_MODE);
1500 tmp &= 0xff00ffff;
1501 writel(tmp, mmio + MV_PCI_MODE);
1502
1503 ZERO(MV_PCI_DISC_TIMER);
1504 ZERO(MV_PCI_MSI_TRIGGER);
1505 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1506 ZERO(HC_MAIN_IRQ_MASK_OFS);
1507 ZERO(MV_PCI_SERR_MASK);
1508 ZERO(PCI_IRQ_CAUSE_OFS);
1509 ZERO(PCI_IRQ_MASK_OFS);
1510 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1511 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1512 ZERO(MV_PCI_ERR_ATTRIBUTE);
1513 ZERO(MV_PCI_ERR_COMMAND);
1514}
1515#undef ZERO
1516
1517static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1518{
1519 u32 tmp;
1520
1521 mv5_reset_flash(hpriv, mmio);
1522
1523 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1524 tmp &= 0x3;
1525 tmp |= (1 << 5) | (1 << 6);
1526 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1527}
1528
1529/**
1530 * mv6_reset_hc - Perform the 6xxx global soft reset
1531 * @mmio: base address of the HBA
1532 *
1533 * This routine only applies to 6xxx parts.
1534 *
1535 * LOCKING:
1536 * Inherited from caller.
1537 */
1538static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1539 unsigned int n_hc)
1540{
1541 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1542 int i, rc = 0;
1543 u32 t;
1544
1545 /* Following procedure defined in PCI "main command and status
1546 * register" table.
1547 */
1548 t = readl(reg);
1549 writel(t | STOP_PCI_MASTER, reg);
1550
1551 for (i = 0; i < 1000; i++) {
1552 udelay(1);
1553 t = readl(reg);
1554 if (PCI_MASTER_EMPTY & t) {
1555 break;
1556 }
1557 }
1558 if (!(PCI_MASTER_EMPTY & t)) {
1559 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1560 rc = 1;
1561 goto done;
1562 }
1563
1564 /* set reset */
1565 i = 5;
1566 do {
1567 writel(t | GLOB_SFT_RST, reg);
1568 t = readl(reg);
1569 udelay(1);
1570 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1571
1572 if (!(GLOB_SFT_RST & t)) {
1573 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1574 rc = 1;
1575 goto done;
1576 }
1577
1578 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1579 i = 5;
1580 do {
1581 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1582 t = readl(reg);
1583 udelay(1);
1584 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1585
1586 if (GLOB_SFT_RST & t) {
1587 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1588 rc = 1;
1589 }
1590done:
1591 return rc;
1592}
1593
1594static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1595 void __iomem *mmio)
1596{
1597 void __iomem *port_mmio;
1598 u32 tmp;
1599
1600 tmp = readl(mmio + MV_RESET_CFG);
1601 if ((tmp & (1 << 0)) == 0) {
1602 hpriv->signal[idx].amps = 0x7 << 8;
1603 hpriv->signal[idx].pre = 0x1 << 5;
1604 return;
1605 }
1606
1607 port_mmio = mv_port_base(mmio, idx);
1608 tmp = readl(port_mmio + PHY_MODE2);
1609
1610 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1611 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1612}
1613
1614static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1615{
1616 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1617}
1618
1619static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1620 unsigned int port)
1621{
1622 void __iomem *port_mmio = mv_port_base(mmio, port);
1623
1624 u32 hp_flags = hpriv->hp_flags;
1625 int fix_phy_mode2 =
1626 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1627 int fix_phy_mode4 =
1628 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1629 u32 m2, tmp;
1630
1631 if (fix_phy_mode2) {
1632 m2 = readl(port_mmio + PHY_MODE2);
1633 m2 &= ~(1 << 16);
1634 m2 |= (1 << 31);
1635 writel(m2, port_mmio + PHY_MODE2);
1636
1637 udelay(200);
1638
1639 m2 = readl(port_mmio + PHY_MODE2);
1640 m2 &= ~((1 << 16) | (1 << 31));
1641 writel(m2, port_mmio + PHY_MODE2);
1642
1643 udelay(200);
1644 }
1645
1646 /* who knows what this magic does */
1647 tmp = readl(port_mmio + PHY_MODE3);
1648 tmp &= ~0x7F800000;
1649 tmp |= 0x2A800000;
1650 writel(tmp, port_mmio + PHY_MODE3);
1651
1652 if (fix_phy_mode4) {
1653 u32 m4;
1654
1655 m4 = readl(port_mmio + PHY_MODE4);
1656
1657 if (hp_flags & MV_HP_ERRATA_60X1B2)
1658 tmp = readl(port_mmio + 0x310);
1659
1660 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1661
1662 writel(m4, port_mmio + PHY_MODE4);
1663
1664 if (hp_flags & MV_HP_ERRATA_60X1B2)
1665 writel(tmp, port_mmio + 0x310);
1666 }
1667
1668 /* Revert values of pre-emphasis and signal amps to the saved ones */
1669 m2 = readl(port_mmio + PHY_MODE2);
1670
1671 m2 &= ~MV_M2_PREAMP_MASK;
1672 m2 |= hpriv->signal[port].amps;
1673 m2 |= hpriv->signal[port].pre;
1674 m2 &= ~(1 << 16);
1675
1676 writel(m2, port_mmio + PHY_MODE2);
1677}
1678
1679static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1680 unsigned int port_no)
1681{
1682 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1683
1684 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1685
1686 if (IS_60XX(hpriv)) {
1687 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1688 ifctl |= (1 << 12) | (1 << 7);
1689 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1690 }
1691
1692 udelay(25); /* allow reset propagation */
1693
1694 /* Spec never mentions clearing the bit. Marvell's driver does
1695 * clear the bit, however.
1696 */
1697 writelfl(0, port_mmio + EDMA_CMD_OFS);
1698
1699 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1700
1701 if (IS_50XX(hpriv))
1702 mdelay(1);
1703}
1704
1705static void mv_stop_and_reset(struct ata_port *ap)
1706{
1707 struct mv_host_priv *hpriv = ap->host_set->private_data;
1708 void __iomem *mmio = ap->host_set->mmio_base;
1709
1710 mv_stop_dma(ap);
1711
1712 mv_channel_reset(hpriv, mmio, ap->port_no);
1713
1714 __mv_phy_reset(ap, 0);
1715}
1716
1717static inline void __msleep(unsigned int msec, int can_sleep)
1718{
1719 if (can_sleep)
1720 msleep(msec);
1721 else
1722 mdelay(msec);
1723}
1724
1203/** 1725/**
1204 * mv_phy_reset - Perform eDMA reset followed by COMRESET 1726 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1205 * @ap: ATA channel to manipulate 1727 * @ap: ATA channel to manipulate
1206 * 1728 *
1207 * Part of this is taken from __sata_phy_reset and modified to 1729 * Part of this is taken from __sata_phy_reset and modified to
@@ -1211,41 +1733,47 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1211 * Inherited from caller. This is coded to safe to call at 1733 * Inherited from caller. This is coded to safe to call at
1212 * interrupt level, i.e. it does not sleep. 1734 * interrupt level, i.e. it does not sleep.
1213 */ 1735 */
1214static void mv_phy_reset(struct ata_port *ap) 1736static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1215{ 1737{
1738 struct mv_port_priv *pp = ap->private_data;
1739 struct mv_host_priv *hpriv = ap->host_set->private_data;
1216 void __iomem *port_mmio = mv_ap_base(ap); 1740 void __iomem *port_mmio = mv_ap_base(ap);
1217 struct ata_taskfile tf; 1741 struct ata_taskfile tf;
1218 struct ata_device *dev = &ap->device[0]; 1742 struct ata_device *dev = &ap->device[0];
1219 unsigned long timeout; 1743 unsigned long timeout;
1744 int retry = 5;
1745 u32 sstatus;
1220 1746
1221 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio); 1747 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1222 1748
1223 mv_stop_dma(ap); 1749 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1224
1225 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1226 udelay(25); /* allow reset propagation */
1227
1228 /* Spec never mentions clearing the bit. Marvell's driver does
1229 * clear the bit, however.
1230 */
1231 writelfl(0, port_mmio + EDMA_CMD_OFS);
1232
1233 VPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1234 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), 1750 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1235 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); 1751 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1236 1752
1237 /* proceed to init communications via the scr_control reg */ 1753 /* Issue COMRESET via SControl */
1754comreset_retry:
1238 scr_write_flush(ap, SCR_CONTROL, 0x301); 1755 scr_write_flush(ap, SCR_CONTROL, 0x301);
1239 mdelay(1); 1756 __msleep(1, can_sleep);
1757
1240 scr_write_flush(ap, SCR_CONTROL, 0x300); 1758 scr_write_flush(ap, SCR_CONTROL, 0x300);
1241 timeout = jiffies + (HZ * 1); 1759 __msleep(20, can_sleep);
1760
1761 timeout = jiffies + msecs_to_jiffies(200);
1242 do { 1762 do {
1243 mdelay(10); 1763 sstatus = scr_read(ap, SCR_STATUS) & 0x3;
1244 if ((scr_read(ap, SCR_STATUS) & 0xf) != 1) 1764 if ((sstatus == 3) || (sstatus == 0))
1245 break; 1765 break;
1766
1767 __msleep(1, can_sleep);
1246 } while (time_before(jiffies, timeout)); 1768 } while (time_before(jiffies, timeout));
1247 1769
1248 VPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " 1770 /* work around errata */
1771 if (IS_60XX(hpriv) &&
1772 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1773 (retry-- > 0))
1774 goto comreset_retry;
1775
1776 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1249 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), 1777 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1250 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); 1778 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1251 1779
@@ -1259,6 +1787,21 @@ static void mv_phy_reset(struct ata_port *ap)
1259 } 1787 }
1260 ap->cbl = ATA_CBL_SATA; 1788 ap->cbl = ATA_CBL_SATA;
1261 1789
1790 /* even after SStatus reflects that device is ready,
1791 * it seems to take a while for link to be fully
1792 * established (and thus Status no longer 0x80/0x7F),
1793 * so we poll a bit for that, here.
1794 */
1795 retry = 20;
1796 while (1) {
1797 u8 drv_stat = ata_check_status(ap);
1798 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1799 break;
1800 __msleep(500, can_sleep);
1801 if (retry-- <= 0)
1802 break;
1803 }
1804
1262 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr); 1805 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1263 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr); 1806 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1264 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr); 1807 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
@@ -1269,9 +1812,19 @@ static void mv_phy_reset(struct ata_port *ap)
1269 VPRINTK("Port disabled post-sig: No device present.\n"); 1812 VPRINTK("Port disabled post-sig: No device present.\n");
1270 ata_port_disable(ap); 1813 ata_port_disable(ap);
1271 } 1814 }
1815
1816 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1817
1818 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1819
1272 VPRINTK("EXIT\n"); 1820 VPRINTK("EXIT\n");
1273} 1821}
1274 1822
1823static void mv_phy_reset(struct ata_port *ap)
1824{
1825 __mv_phy_reset(ap, 1);
1826}
1827
1275/** 1828/**
1276 * mv_eng_timeout - Routine called by libata when SCSI times out I/O 1829 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1277 * @ap: ATA channel to manipulate 1830 * @ap: ATA channel to manipulate
@@ -1289,16 +1842,16 @@ static void mv_eng_timeout(struct ata_port *ap)
1289 1842
1290 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id); 1843 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
1291 DPRINTK("All regs @ start of eng_timeout\n"); 1844 DPRINTK("All regs @ start of eng_timeout\n");
1292 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no, 1845 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
1293 to_pci_dev(ap->host_set->dev)); 1846 to_pci_dev(ap->host_set->dev));
1294 1847
1295 qc = ata_qc_from_tag(ap, ap->active_tag); 1848 qc = ata_qc_from_tag(ap, ap->active_tag);
1296 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n", 1849 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1297 ap->host_set->mmio_base, ap, qc, qc->scsicmd, 1850 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
1298 &qc->scsicmd->cmnd); 1851 &qc->scsicmd->cmnd);
1299 1852
1300 mv_err_intr(ap); 1853 mv_err_intr(ap);
1301 mv_phy_reset(ap); 1854 mv_stop_and_reset(ap);
1302 1855
1303 if (!qc) { 1856 if (!qc) {
1304 printk(KERN_ERR "ata%u: BUG: timeout without command\n", 1857 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
@@ -1334,17 +1887,17 @@ static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1334 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS; 1887 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
1335 unsigned serr_ofs; 1888 unsigned serr_ofs;
1336 1889
1337 /* PIO related setup 1890 /* PIO related setup
1338 */ 1891 */
1339 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 1892 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
1340 port->error_addr = 1893 port->error_addr =
1341 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 1894 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
1342 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 1895 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
1343 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 1896 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
1344 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 1897 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
1345 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 1898 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
1346 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 1899 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
1347 port->status_addr = 1900 port->status_addr =
1348 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 1901 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
1349 /* special case: control/altstatus doesn't have ATA_REG_ address */ 1902 /* special case: control/altstatus doesn't have ATA_REG_ address */
1350 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 1903 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
@@ -1360,14 +1913,92 @@ static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1360 /* unmask all EDMA error interrupts */ 1913 /* unmask all EDMA error interrupts */
1361 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 1914 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
1362 1915
1363 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 1916 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1364 readl(port_mmio + EDMA_CFG_OFS), 1917 readl(port_mmio + EDMA_CFG_OFS),
1365 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 1918 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
1366 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 1919 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
1367} 1920}
1368 1921
1922static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
1923 unsigned int board_idx)
1924{
1925 u8 rev_id;
1926 u32 hp_flags = hpriv->hp_flags;
1927
1928 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1929
1930 switch(board_idx) {
1931 case chip_5080:
1932 hpriv->ops = &mv5xxx_ops;
1933 hp_flags |= MV_HP_50XX;
1934
1935 switch (rev_id) {
1936 case 0x1:
1937 hp_flags |= MV_HP_ERRATA_50XXB0;
1938 break;
1939 case 0x3:
1940 hp_flags |= MV_HP_ERRATA_50XXB2;
1941 break;
1942 default:
1943 dev_printk(KERN_WARNING, &pdev->dev,
1944 "Applying 50XXB2 workarounds to unknown rev\n");
1945 hp_flags |= MV_HP_ERRATA_50XXB2;
1946 break;
1947 }
1948 break;
1949
1950 case chip_504x:
1951 case chip_508x:
1952 hpriv->ops = &mv5xxx_ops;
1953 hp_flags |= MV_HP_50XX;
1954
1955 switch (rev_id) {
1956 case 0x0:
1957 hp_flags |= MV_HP_ERRATA_50XXB0;
1958 break;
1959 case 0x3:
1960 hp_flags |= MV_HP_ERRATA_50XXB2;
1961 break;
1962 default:
1963 dev_printk(KERN_WARNING, &pdev->dev,
1964 "Applying B2 workarounds to unknown rev\n");
1965 hp_flags |= MV_HP_ERRATA_50XXB2;
1966 break;
1967 }
1968 break;
1969
1970 case chip_604x:
1971 case chip_608x:
1972 hpriv->ops = &mv6xxx_ops;
1973
1974 switch (rev_id) {
1975 case 0x7:
1976 hp_flags |= MV_HP_ERRATA_60X1B2;
1977 break;
1978 case 0x9:
1979 hp_flags |= MV_HP_ERRATA_60X1C0;
1980 break;
1981 default:
1982 dev_printk(KERN_WARNING, &pdev->dev,
1983 "Applying B2 workarounds to unknown rev\n");
1984 hp_flags |= MV_HP_ERRATA_60X1B2;
1985 break;
1986 }
1987 break;
1988
1989 default:
1990 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
1991 return 1;
1992 }
1993
1994 hpriv->hp_flags = hp_flags;
1995
1996 return 0;
1997}
1998
1369/** 1999/**
1370 * mv_host_init - Perform some early initialization of the host. 2000 * mv_init_host - Perform some early initialization of the host.
2001 * @pdev: host PCI device
1371 * @probe_ent: early data struct representing the host 2002 * @probe_ent: early data struct representing the host
1372 * 2003 *
1373 * If possible, do an early global reset of the host. Then do 2004 * If possible, do an early global reset of the host. Then do
@@ -1376,23 +2007,48 @@ static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1376 * LOCKING: 2007 * LOCKING:
1377 * Inherited from caller. 2008 * Inherited from caller.
1378 */ 2009 */
1379static int mv_host_init(struct ata_probe_ent *probe_ent) 2010static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2011 unsigned int board_idx)
1380{ 2012{
1381 int rc = 0, n_hc, port, hc; 2013 int rc = 0, n_hc, port, hc;
1382 void __iomem *mmio = probe_ent->mmio_base; 2014 void __iomem *mmio = probe_ent->mmio_base;
1383 void __iomem *port_mmio; 2015 struct mv_host_priv *hpriv = probe_ent->private_data;
1384 2016
1385 if ((MV_FLAG_GLBL_SFT_RST & probe_ent->host_flags) && 2017 /* global interrupt mask */
1386 mv_global_soft_reset(probe_ent->mmio_base)) { 2018 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
1387 rc = 1; 2019
2020 rc = mv_chip_id(pdev, hpriv, board_idx);
2021 if (rc)
1388 goto done; 2022 goto done;
1389 }
1390 2023
1391 n_hc = mv_get_hc_count(probe_ent->host_flags); 2024 n_hc = mv_get_hc_count(probe_ent->host_flags);
1392 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc; 2025 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
1393 2026
2027 for (port = 0; port < probe_ent->n_ports; port++)
2028 hpriv->ops->read_preamp(hpriv, port, mmio);
2029
2030 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2031 if (rc)
2032 goto done;
2033
2034 hpriv->ops->reset_flash(hpriv, mmio);
2035 hpriv->ops->reset_bus(pdev, mmio);
2036 hpriv->ops->enable_leds(hpriv, mmio);
2037
1394 for (port = 0; port < probe_ent->n_ports; port++) { 2038 for (port = 0; port < probe_ent->n_ports; port++) {
1395 port_mmio = mv_port_base(mmio, port); 2039 if (IS_60XX(hpriv)) {
2040 void __iomem *port_mmio = mv_port_base(mmio, port);
2041
2042 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2043 ifctl |= (1 << 12);
2044 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2045 }
2046
2047 hpriv->ops->phy_errata(hpriv, mmio, port);
2048 }
2049
2050 for (port = 0; port < probe_ent->n_ports; port++) {
2051 void __iomem *port_mmio = mv_port_base(mmio, port);
1396 mv_port_init(&probe_ent->port[port], port_mmio); 2052 mv_port_init(&probe_ent->port[port], port_mmio);
1397 } 2053 }
1398 2054
@@ -1416,11 +2072,12 @@ static int mv_host_init(struct ata_probe_ent *probe_ent)
1416 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS); 2072 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
1417 2073
1418 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " 2074 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
1419 "PCI int cause/mask=0x%08x/0x%08x\n", 2075 "PCI int cause/mask=0x%08x/0x%08x\n",
1420 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS), 2076 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
1421 readl(mmio + HC_MAIN_IRQ_MASK_OFS), 2077 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
1422 readl(mmio + PCI_IRQ_CAUSE_OFS), 2078 readl(mmio + PCI_IRQ_CAUSE_OFS),
1423 readl(mmio + PCI_IRQ_MASK_OFS)); 2079 readl(mmio + PCI_IRQ_MASK_OFS));
2080
1424done: 2081done:
1425 return rc; 2082 return rc;
1426} 2083}
@@ -1456,7 +2113,7 @@ static void mv_print_info(struct ata_probe_ent *probe_ent)
1456 2113
1457 dev_printk(KERN_INFO, &pdev->dev, 2114 dev_printk(KERN_INFO, &pdev->dev,
1458 "%u slots %u ports %s mode IRQ via %s\n", 2115 "%u slots %u ports %s mode IRQ via %s\n",
1459 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports, 2116 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
1460 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 2117 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
1461} 2118}
1462 2119
@@ -1526,7 +2183,7 @@ static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1526 probe_ent->private_data = hpriv; 2183 probe_ent->private_data = hpriv;
1527 2184
1528 /* initialize adapter */ 2185 /* initialize adapter */
1529 rc = mv_host_init(probe_ent); 2186 rc = mv_init_host(pdev, probe_ent, board_idx);
1530 if (rc) { 2187 if (rc) {
1531 goto err_out_hpriv; 2188 goto err_out_hpriv;
1532 } 2189 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 04:52:28 -0500