diff options
Diffstat (limited to 'drivers/scsi/qla4xxx/ql4_mbx.c')
-rw-r--r-- | drivers/scsi/qla4xxx/ql4_mbx.c | 191 |
1 files changed, 138 insertions, 53 deletions
diff --git a/drivers/scsi/qla4xxx/ql4_mbx.c b/drivers/scsi/qla4xxx/ql4_mbx.c index 75496fb0ae75..940ee561ee0a 100644 --- a/drivers/scsi/qla4xxx/ql4_mbx.c +++ b/drivers/scsi/qla4xxx/ql4_mbx.c | |||
@@ -19,13 +19,13 @@ | |||
19 | * @mbx_cmd: data pointer for mailbox in registers. | 19 | * @mbx_cmd: data pointer for mailbox in registers. |
20 | * @mbx_sts: data pointer for mailbox out registers. | 20 | * @mbx_sts: data pointer for mailbox out registers. |
21 | * | 21 | * |
22 | * This routine sssue mailbox commands and waits for completion. | 22 | * This routine isssue mailbox commands and waits for completion. |
23 | * If outCount is 0, this routine completes successfully WITHOUT waiting | 23 | * If outCount is 0, this routine completes successfully WITHOUT waiting |
24 | * for the mailbox command to complete. | 24 | * for the mailbox command to complete. |
25 | **/ | 25 | **/ |
26 | static int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount, | 26 | int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount, |
27 | uint8_t outCount, uint32_t *mbx_cmd, | 27 | uint8_t outCount, uint32_t *mbx_cmd, |
28 | uint32_t *mbx_sts) | 28 | uint32_t *mbx_sts) |
29 | { | 29 | { |
30 | int status = QLA_ERROR; | 30 | int status = QLA_ERROR; |
31 | uint8_t i; | 31 | uint8_t i; |
@@ -59,32 +59,66 @@ static int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount, | |||
59 | } | 59 | } |
60 | 60 | ||
61 | /* To prevent overwriting mailbox registers for a command that has | 61 | /* To prevent overwriting mailbox registers for a command that has |
62 | * not yet been serviced, check to see if a previously issued | 62 | * not yet been serviced, check to see if an active command |
63 | * mailbox command is interrupting. | 63 | * (AEN, IOCB, etc.) is interrupting, then service it. |
64 | * ----------------------------------------------------------------- | 64 | * ----------------------------------------------------------------- |
65 | */ | 65 | */ |
66 | spin_lock_irqsave(&ha->hardware_lock, flags); | 66 | spin_lock_irqsave(&ha->hardware_lock, flags); |
67 | intr_status = readl(&ha->reg->ctrl_status); | 67 | |
68 | if (intr_status & CSR_SCSI_PROCESSOR_INTR) { | 68 | if (is_qla8022(ha)) { |
69 | /* Service existing interrupt */ | 69 | intr_status = readl(&ha->qla4_8xxx_reg->host_int); |
70 | qla4xxx_interrupt_service_routine(ha, intr_status); | 70 | if (intr_status & ISRX_82XX_RISC_INT) { |
71 | clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags); | 71 | /* Service existing interrupt */ |
72 | DEBUG2(printk("scsi%ld: %s: " | ||
73 | "servicing existing interrupt\n", | ||
74 | ha->host_no, __func__)); | ||
75 | intr_status = readl(&ha->qla4_8xxx_reg->host_status); | ||
76 | ha->isp_ops->interrupt_service_routine(ha, intr_status); | ||
77 | clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags); | ||
78 | if (test_bit(AF_INTERRUPTS_ON, &ha->flags) && | ||
79 | test_bit(AF_INTx_ENABLED, &ha->flags)) | ||
80 | qla4_8xxx_wr_32(ha, | ||
81 | ha->nx_legacy_intr.tgt_mask_reg, | ||
82 | 0xfbff); | ||
83 | } | ||
84 | } else { | ||
85 | intr_status = readl(&ha->reg->ctrl_status); | ||
86 | if (intr_status & CSR_SCSI_PROCESSOR_INTR) { | ||
87 | /* Service existing interrupt */ | ||
88 | ha->isp_ops->interrupt_service_routine(ha, intr_status); | ||
89 | clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags); | ||
90 | } | ||
72 | } | 91 | } |
73 | 92 | ||
74 | /* Send the mailbox command to the firmware */ | ||
75 | ha->mbox_status_count = outCount; | 93 | ha->mbox_status_count = outCount; |
76 | for (i = 0; i < outCount; i++) | 94 | for (i = 0; i < outCount; i++) |
77 | ha->mbox_status[i] = 0; | 95 | ha->mbox_status[i] = 0; |
78 | 96 | ||
79 | /* Load all mailbox registers, except mailbox 0. */ | 97 | if (is_qla8022(ha)) { |
80 | for (i = 1; i < inCount; i++) | 98 | /* Load all mailbox registers, except mailbox 0. */ |
81 | writel(mbx_cmd[i], &ha->reg->mailbox[i]); | 99 | DEBUG5( |
100 | printk("scsi%ld: %s: Cmd ", ha->host_no, __func__); | ||
101 | for (i = 0; i < inCount; i++) | ||
102 | printk("mb%d=%04x ", i, mbx_cmd[i]); | ||
103 | printk("\n")); | ||
104 | |||
105 | for (i = 1; i < inCount; i++) | ||
106 | writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]); | ||
107 | writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]); | ||
108 | readl(&ha->qla4_8xxx_reg->mailbox_in[0]); | ||
109 | writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint); | ||
110 | } else { | ||
111 | /* Load all mailbox registers, except mailbox 0. */ | ||
112 | for (i = 1; i < inCount; i++) | ||
113 | writel(mbx_cmd[i], &ha->reg->mailbox[i]); | ||
114 | |||
115 | /* Wakeup firmware */ | ||
116 | writel(mbx_cmd[0], &ha->reg->mailbox[0]); | ||
117 | readl(&ha->reg->mailbox[0]); | ||
118 | writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status); | ||
119 | readl(&ha->reg->ctrl_status); | ||
120 | } | ||
82 | 121 | ||
83 | /* Wakeup firmware */ | ||
84 | writel(mbx_cmd[0], &ha->reg->mailbox[0]); | ||
85 | readl(&ha->reg->mailbox[0]); | ||
86 | writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status); | ||
87 | readl(&ha->reg->ctrl_status); | ||
88 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | 122 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
89 | 123 | ||
90 | /* Wait for completion */ | 124 | /* Wait for completion */ |
@@ -98,26 +132,66 @@ static int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount, | |||
98 | status = QLA_SUCCESS; | 132 | status = QLA_SUCCESS; |
99 | goto mbox_exit; | 133 | goto mbox_exit; |
100 | } | 134 | } |
101 | /* Wait for command to complete */ | ||
102 | wait_count = jiffies + MBOX_TOV * HZ; | ||
103 | while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) { | ||
104 | if (time_after_eq(jiffies, wait_count)) | ||
105 | break; | ||
106 | 135 | ||
107 | spin_lock_irqsave(&ha->hardware_lock, flags); | 136 | /* |
108 | intr_status = readl(&ha->reg->ctrl_status); | 137 | * Wait for completion: Poll or completion queue |
109 | if (intr_status & INTR_PENDING) { | 138 | */ |
139 | if (test_bit(AF_IRQ_ATTACHED, &ha->flags) && | ||
140 | test_bit(AF_INTERRUPTS_ON, &ha->flags) && | ||
141 | test_bit(AF_ONLINE, &ha->flags) && | ||
142 | !test_bit(AF_HBA_GOING_AWAY, &ha->flags)) { | ||
143 | /* Do not poll for completion. Use completion queue */ | ||
144 | set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags); | ||
145 | wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ); | ||
146 | clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags); | ||
147 | } else { | ||
148 | /* Poll for command to complete */ | ||
149 | wait_count = jiffies + MBOX_TOV * HZ; | ||
150 | while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) { | ||
151 | if (time_after_eq(jiffies, wait_count)) | ||
152 | break; | ||
110 | /* | 153 | /* |
111 | * Service the interrupt. | 154 | * Service the interrupt. |
112 | * The ISR will save the mailbox status registers | 155 | * The ISR will save the mailbox status registers |
113 | * to a temporary storage location in the adapter | 156 | * to a temporary storage location in the adapter |
114 | * structure. | 157 | * structure. |
115 | */ | 158 | */ |
116 | ha->mbox_status_count = outCount; | 159 | |
117 | qla4xxx_interrupt_service_routine(ha, intr_status); | 160 | spin_lock_irqsave(&ha->hardware_lock, flags); |
161 | if (is_qla8022(ha)) { | ||
162 | intr_status = | ||
163 | readl(&ha->qla4_8xxx_reg->host_int); | ||
164 | if (intr_status & ISRX_82XX_RISC_INT) { | ||
165 | ha->mbox_status_count = outCount; | ||
166 | intr_status = | ||
167 | readl(&ha->qla4_8xxx_reg->host_status); | ||
168 | ha->isp_ops->interrupt_service_routine( | ||
169 | ha, intr_status); | ||
170 | if (test_bit(AF_INTERRUPTS_ON, | ||
171 | &ha->flags) && | ||
172 | test_bit(AF_INTx_ENABLED, | ||
173 | &ha->flags)) | ||
174 | qla4_8xxx_wr_32(ha, | ||
175 | ha->nx_legacy_intr.tgt_mask_reg, | ||
176 | 0xfbff); | ||
177 | } | ||
178 | } else { | ||
179 | intr_status = readl(&ha->reg->ctrl_status); | ||
180 | if (intr_status & INTR_PENDING) { | ||
181 | /* | ||
182 | * Service the interrupt. | ||
183 | * The ISR will save the mailbox status | ||
184 | * registers to a temporary storage | ||
185 | * location in the adapter structure. | ||
186 | */ | ||
187 | ha->mbox_status_count = outCount; | ||
188 | ha->isp_ops->interrupt_service_routine( | ||
189 | ha, intr_status); | ||
190 | } | ||
191 | } | ||
192 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | ||
193 | msleep(10); | ||
118 | } | 194 | } |
119 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | ||
120 | msleep(10); | ||
121 | } | 195 | } |
122 | 196 | ||
123 | /* Check for mailbox timeout. */ | 197 | /* Check for mailbox timeout. */ |
@@ -172,7 +246,7 @@ mbox_exit: | |||
172 | return status; | 246 | return status; |
173 | } | 247 | } |
174 | 248 | ||
175 | uint8_t | 249 | static uint8_t |
176 | qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, | 250 | qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, |
177 | uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma) | 251 | uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma) |
178 | { | 252 | { |
@@ -196,7 +270,7 @@ qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, | |||
196 | return QLA_SUCCESS; | 270 | return QLA_SUCCESS; |
197 | } | 271 | } |
198 | 272 | ||
199 | uint8_t | 273 | static uint8_t |
200 | qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, | 274 | qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, |
201 | uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma) | 275 | uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma) |
202 | { | 276 | { |
@@ -218,7 +292,7 @@ qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, | |||
218 | return QLA_SUCCESS; | 292 | return QLA_SUCCESS; |
219 | } | 293 | } |
220 | 294 | ||
221 | void | 295 | static void |
222 | qla4xxx_update_local_ip(struct scsi_qla_host *ha, | 296 | qla4xxx_update_local_ip(struct scsi_qla_host *ha, |
223 | struct addr_ctrl_blk *init_fw_cb) | 297 | struct addr_ctrl_blk *init_fw_cb) |
224 | { | 298 | { |
@@ -256,7 +330,7 @@ qla4xxx_update_local_ip(struct scsi_qla_host *ha, | |||
256 | } | 330 | } |
257 | } | 331 | } |
258 | 332 | ||
259 | uint8_t | 333 | static uint8_t |
260 | qla4xxx_update_local_ifcb(struct scsi_qla_host *ha, | 334 | qla4xxx_update_local_ifcb(struct scsi_qla_host *ha, |
261 | uint32_t *mbox_cmd, | 335 | uint32_t *mbox_cmd, |
262 | uint32_t *mbox_sts, | 336 | uint32_t *mbox_sts, |
@@ -317,7 +391,7 @@ int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha) | |||
317 | if (init_fw_cb == NULL) { | 391 | if (init_fw_cb == NULL) { |
318 | DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n", | 392 | DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n", |
319 | ha->host_no, __func__)); | 393 | ha->host_no, __func__)); |
320 | return 10; | 394 | goto exit_init_fw_cb_no_free; |
321 | } | 395 | } |
322 | memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk)); | 396 | memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk)); |
323 | 397 | ||
@@ -373,7 +447,7 @@ int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha) | |||
373 | exit_init_fw_cb: | 447 | exit_init_fw_cb: |
374 | dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk), | 448 | dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk), |
375 | init_fw_cb, init_fw_cb_dma); | 449 | init_fw_cb, init_fw_cb_dma); |
376 | 450 | exit_init_fw_cb_no_free: | |
377 | return status; | 451 | return status; |
378 | } | 452 | } |
379 | 453 | ||
@@ -394,7 +468,7 @@ int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha) | |||
394 | if (init_fw_cb == NULL) { | 468 | if (init_fw_cb == NULL) { |
395 | printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no, | 469 | printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no, |
396 | __func__); | 470 | __func__); |
397 | return 10; | 471 | return QLA_ERROR; |
398 | } | 472 | } |
399 | 473 | ||
400 | /* Get Initialize Firmware Control Block. */ | 474 | /* Get Initialize Firmware Control Block. */ |
@@ -445,7 +519,7 @@ int qla4xxx_get_firmware_state(struct scsi_qla_host * ha) | |||
445 | DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n", | 519 | DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n", |
446 | ha->host_no, __func__, ha->firmware_state);) | 520 | ha->host_no, __func__, ha->firmware_state);) |
447 | 521 | ||
448 | return QLA_SUCCESS; | 522 | return QLA_SUCCESS; |
449 | } | 523 | } |
450 | 524 | ||
451 | /** | 525 | /** |
@@ -470,6 +544,10 @@ int qla4xxx_get_firmware_status(struct scsi_qla_host * ha) | |||
470 | mbox_sts[0])); | 544 | mbox_sts[0])); |
471 | return QLA_ERROR; | 545 | return QLA_ERROR; |
472 | } | 546 | } |
547 | |||
548 | ql4_printk(KERN_INFO, ha, "%ld firmare IOCBs available (%d).\n", | ||
549 | ha->host_no, mbox_cmd[2]); | ||
550 | |||
473 | return QLA_SUCCESS; | 551 | return QLA_SUCCESS; |
474 | } | 552 | } |
475 | 553 | ||
@@ -500,7 +578,7 @@ int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha, | |||
500 | 578 | ||
501 | /* Make sure the device index is valid */ | 579 | /* Make sure the device index is valid */ |
502 | if (fw_ddb_index >= MAX_DDB_ENTRIES) { | 580 | if (fw_ddb_index >= MAX_DDB_ENTRIES) { |
503 | DEBUG2(printk("scsi%ld: %s: index [%d] out of range.\n", | 581 | DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n", |
504 | ha->host_no, __func__, fw_ddb_index)); | 582 | ha->host_no, __func__, fw_ddb_index)); |
505 | goto exit_get_fwddb; | 583 | goto exit_get_fwddb; |
506 | } | 584 | } |
@@ -521,7 +599,7 @@ int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha, | |||
521 | goto exit_get_fwddb; | 599 | goto exit_get_fwddb; |
522 | } | 600 | } |
523 | if (fw_ddb_index != mbox_sts[1]) { | 601 | if (fw_ddb_index != mbox_sts[1]) { |
524 | DEBUG2(printk("scsi%ld: %s: index mismatch [%d] != [%d].\n", | 602 | DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n", |
525 | ha->host_no, __func__, fw_ddb_index, | 603 | ha->host_no, __func__, fw_ddb_index, |
526 | mbox_sts[1])); | 604 | mbox_sts[1])); |
527 | goto exit_get_fwddb; | 605 | goto exit_get_fwddb; |
@@ -529,7 +607,7 @@ int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha, | |||
529 | if (fw_ddb_entry) { | 607 | if (fw_ddb_entry) { |
530 | options = le16_to_cpu(fw_ddb_entry->options); | 608 | options = le16_to_cpu(fw_ddb_entry->options); |
531 | if (options & DDB_OPT_IPV6_DEVICE) { | 609 | if (options & DDB_OPT_IPV6_DEVICE) { |
532 | dev_info(&ha->pdev->dev, "%s: DDB[%d] MB0 %04x Tot %d " | 610 | ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d " |
533 | "Next %d State %04x ConnErr %08x %pI6 " | 611 | "Next %d State %04x ConnErr %08x %pI6 " |
534 | ":%04d \"%s\"\n", __func__, fw_ddb_index, | 612 | ":%04d \"%s\"\n", __func__, fw_ddb_index, |
535 | mbox_sts[0], mbox_sts[2], mbox_sts[3], | 613 | mbox_sts[0], mbox_sts[2], mbox_sts[3], |
@@ -538,7 +616,7 @@ int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha, | |||
538 | le16_to_cpu(fw_ddb_entry->port), | 616 | le16_to_cpu(fw_ddb_entry->port), |
539 | fw_ddb_entry->iscsi_name); | 617 | fw_ddb_entry->iscsi_name); |
540 | } else { | 618 | } else { |
541 | dev_info(&ha->pdev->dev, "%s: DDB[%d] MB0 %04x Tot %d " | 619 | ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d " |
542 | "Next %d State %04x ConnErr %08x %pI4 " | 620 | "Next %d State %04x ConnErr %08x %pI4 " |
543 | ":%04d \"%s\"\n", __func__, fw_ddb_index, | 621 | ":%04d \"%s\"\n", __func__, fw_ddb_index, |
544 | mbox_sts[0], mbox_sts[2], mbox_sts[3], | 622 | mbox_sts[0], mbox_sts[2], mbox_sts[3], |
@@ -590,6 +668,7 @@ int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index, | |||
590 | { | 668 | { |
591 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | 669 | uint32_t mbox_cmd[MBOX_REG_COUNT]; |
592 | uint32_t mbox_sts[MBOX_REG_COUNT]; | 670 | uint32_t mbox_sts[MBOX_REG_COUNT]; |
671 | int status; | ||
593 | 672 | ||
594 | /* Do not wait for completion. The firmware will send us an | 673 | /* Do not wait for completion. The firmware will send us an |
595 | * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status. | 674 | * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status. |
@@ -603,7 +682,12 @@ int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index, | |||
603 | mbox_cmd[3] = MSDW(fw_ddb_entry_dma); | 682 | mbox_cmd[3] = MSDW(fw_ddb_entry_dma); |
604 | mbox_cmd[4] = sizeof(struct dev_db_entry); | 683 | mbox_cmd[4] = sizeof(struct dev_db_entry); |
605 | 684 | ||
606 | return qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]); | 685 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], |
686 | &mbox_sts[0]); | ||
687 | DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n", | ||
688 | ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);) | ||
689 | |||
690 | return status; | ||
607 | } | 691 | } |
608 | 692 | ||
609 | /** | 693 | /** |
@@ -817,8 +901,8 @@ int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb) | |||
817 | /** | 901 | /** |
818 | * qla4xxx_reset_lun - issues LUN Reset | 902 | * qla4xxx_reset_lun - issues LUN Reset |
819 | * @ha: Pointer to host adapter structure. | 903 | * @ha: Pointer to host adapter structure. |
820 | * @db_entry: Pointer to device database entry | 904 | * @ddb_entry: Pointer to device database entry |
821 | * @un_entry: Pointer to lun entry structure | 905 | * @lun: lun number |
822 | * | 906 | * |
823 | * This routine performs a LUN RESET on the specified target/lun. | 907 | * This routine performs a LUN RESET on the specified target/lun. |
824 | * The caller must ensure that the ddb_entry and lun_entry pointers | 908 | * The caller must ensure that the ddb_entry and lun_entry pointers |
@@ -832,7 +916,7 @@ int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry, | |||
832 | int status = QLA_SUCCESS; | 916 | int status = QLA_SUCCESS; |
833 | 917 | ||
834 | DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no, | 918 | DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no, |
835 | ddb_entry->os_target_id, lun)); | 919 | ddb_entry->fw_ddb_index, lun)); |
836 | 920 | ||
837 | /* | 921 | /* |
838 | * Send lun reset command to ISP, so that the ISP will return all | 922 | * Send lun reset command to ISP, so that the ISP will return all |
@@ -872,7 +956,7 @@ int qla4xxx_reset_target(struct scsi_qla_host *ha, | |||
872 | int status = QLA_SUCCESS; | 956 | int status = QLA_SUCCESS; |
873 | 957 | ||
874 | DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no, | 958 | DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no, |
875 | ddb_entry->os_target_id)); | 959 | ddb_entry->fw_ddb_index)); |
876 | 960 | ||
877 | /* | 961 | /* |
878 | * Send target reset command to ISP, so that the ISP will return all | 962 | * Send target reset command to ISP, so that the ISP will return all |
@@ -1019,16 +1103,16 @@ int qla4xxx_send_tgts(struct scsi_qla_host *ha, char *ip, uint16_t port) | |||
1019 | DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n", | 1103 | DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n", |
1020 | ha->host_no, __func__)); | 1104 | ha->host_no, __func__)); |
1021 | ret_val = QLA_ERROR; | 1105 | ret_val = QLA_ERROR; |
1022 | goto qla4xxx_send_tgts_exit; | 1106 | goto exit_send_tgts_no_free; |
1023 | } | 1107 | } |
1024 | 1108 | ||
1025 | ret_val = qla4xxx_get_default_ddb(ha, fw_ddb_entry_dma); | 1109 | ret_val = qla4xxx_get_default_ddb(ha, fw_ddb_entry_dma); |
1026 | if (ret_val != QLA_SUCCESS) | 1110 | if (ret_val != QLA_SUCCESS) |
1027 | goto qla4xxx_send_tgts_exit; | 1111 | goto exit_send_tgts; |
1028 | 1112 | ||
1029 | ret_val = qla4xxx_req_ddb_entry(ha, &ddb_index); | 1113 | ret_val = qla4xxx_req_ddb_entry(ha, &ddb_index); |
1030 | if (ret_val != QLA_SUCCESS) | 1114 | if (ret_val != QLA_SUCCESS) |
1031 | goto qla4xxx_send_tgts_exit; | 1115 | goto exit_send_tgts; |
1032 | 1116 | ||
1033 | memset(fw_ddb_entry->iscsi_alias, 0, | 1117 | memset(fw_ddb_entry->iscsi_alias, 0, |
1034 | sizeof(fw_ddb_entry->iscsi_alias)); | 1118 | sizeof(fw_ddb_entry->iscsi_alias)); |
@@ -1050,9 +1134,10 @@ int qla4xxx_send_tgts(struct scsi_qla_host *ha, char *ip, uint16_t port) | |||
1050 | 1134 | ||
1051 | ret_val = qla4xxx_set_ddb_entry(ha, ddb_index, fw_ddb_entry_dma); | 1135 | ret_val = qla4xxx_set_ddb_entry(ha, ddb_index, fw_ddb_entry_dma); |
1052 | 1136 | ||
1053 | qla4xxx_send_tgts_exit: | 1137 | exit_send_tgts: |
1054 | dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry), | 1138 | dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry), |
1055 | fw_ddb_entry, fw_ddb_entry_dma); | 1139 | fw_ddb_entry, fw_ddb_entry_dma); |
1140 | exit_send_tgts_no_free: | ||
1056 | return ret_val; | 1141 | return ret_val; |
1057 | } | 1142 | } |
1058 | 1143 | ||