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Diffstat (limited to 'drivers/scsi/qla4xxx/ql4_fw.h')
-rw-r--r--drivers/scsi/qla4xxx/ql4_fw.h843
1 files changed, 843 insertions, 0 deletions
diff --git a/drivers/scsi/qla4xxx/ql4_fw.h b/drivers/scsi/qla4xxx/ql4_fw.h
new file mode 100644
index 000000000000..427489de64bc
--- /dev/null
+++ b/drivers/scsi/qla4xxx/ql4_fw.h
@@ -0,0 +1,843 @@
1/*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8#ifndef _QLA4X_FW_H
9#define _QLA4X_FW_H
10
11
12#define MAX_PRST_DEV_DB_ENTRIES 64
13#define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES
14#define MAX_DEV_DB_ENTRIES 512
15
16/*************************************************************************
17 *
18 * ISP 4010 I/O Register Set Structure and Definitions
19 *
20 *************************************************************************/
21
22struct port_ctrl_stat_regs {
23 __le32 ext_hw_conf; /* 80 x50 R/W */
24 __le32 intChipConfiguration; /* 84 x54 */
25 __le32 port_ctrl; /* 88 x58 */
26 __le32 port_status; /* 92 x5c */
27 __le32 HostPrimMACHi; /* 96 x60 */
28 __le32 HostPrimMACLow; /* 100 x64 */
29 __le32 HostSecMACHi; /* 104 x68 */
30 __le32 HostSecMACLow; /* 108 x6c */
31 __le32 EPPrimMACHi; /* 112 x70 */
32 __le32 EPPrimMACLow; /* 116 x74 */
33 __le32 EPSecMACHi; /* 120 x78 */
34 __le32 EPSecMACLow; /* 124 x7c */
35 __le32 HostPrimIPHi; /* 128 x80 */
36 __le32 HostPrimIPMidHi; /* 132 x84 */
37 __le32 HostPrimIPMidLow; /* 136 x88 */
38 __le32 HostPrimIPLow; /* 140 x8c */
39 __le32 HostSecIPHi; /* 144 x90 */
40 __le32 HostSecIPMidHi; /* 148 x94 */
41 __le32 HostSecIPMidLow; /* 152 x98 */
42 __le32 HostSecIPLow; /* 156 x9c */
43 __le32 EPPrimIPHi; /* 160 xa0 */
44 __le32 EPPrimIPMidHi; /* 164 xa4 */
45 __le32 EPPrimIPMidLow; /* 168 xa8 */
46 __le32 EPPrimIPLow; /* 172 xac */
47 __le32 EPSecIPHi; /* 176 xb0 */
48 __le32 EPSecIPMidHi; /* 180 xb4 */
49 __le32 EPSecIPMidLow; /* 184 xb8 */
50 __le32 EPSecIPLow; /* 188 xbc */
51 __le32 IPReassemblyTimeout; /* 192 xc0 */
52 __le32 EthMaxFramePayload; /* 196 xc4 */
53 __le32 TCPMaxWindowSize; /* 200 xc8 */
54 __le32 TCPCurrentTimestampHi; /* 204 xcc */
55 __le32 TCPCurrentTimestampLow; /* 208 xd0 */
56 __le32 LocalRAMAddress; /* 212 xd4 */
57 __le32 LocalRAMData; /* 216 xd8 */
58 __le32 PCSReserved1; /* 220 xdc */
59 __le32 gp_out; /* 224 xe0 */
60 __le32 gp_in; /* 228 xe4 */
61 __le32 ProbeMuxAddr; /* 232 xe8 */
62 __le32 ProbeMuxData; /* 236 xec */
63 __le32 ERMQueueBaseAddr0; /* 240 xf0 */
64 __le32 ERMQueueBaseAddr1; /* 244 xf4 */
65 __le32 MACConfiguration; /* 248 xf8 */
66 __le32 port_err_status; /* 252 xfc COR */
67};
68
69struct host_mem_cfg_regs {
70 __le32 NetRequestQueueOut; /* 80 x50 */
71 __le32 NetRequestQueueOutAddrHi; /* 84 x54 */
72 __le32 NetRequestQueueOutAddrLow; /* 88 x58 */
73 __le32 NetRequestQueueBaseAddrHi; /* 92 x5c */
74 __le32 NetRequestQueueBaseAddrLow; /* 96 x60 */
75 __le32 NetRequestQueueLength; /* 100 x64 */
76 __le32 NetResponseQueueIn; /* 104 x68 */
77 __le32 NetResponseQueueInAddrHi; /* 108 x6c */
78 __le32 NetResponseQueueInAddrLow; /* 112 x70 */
79 __le32 NetResponseQueueBaseAddrHi; /* 116 x74 */
80 __le32 NetResponseQueueBaseAddrLow; /* 120 x78 */
81 __le32 NetResponseQueueLength; /* 124 x7c */
82 __le32 req_q_out; /* 128 x80 */
83 __le32 RequestQueueOutAddrHi; /* 132 x84 */
84 __le32 RequestQueueOutAddrLow; /* 136 x88 */
85 __le32 RequestQueueBaseAddrHi; /* 140 x8c */
86 __le32 RequestQueueBaseAddrLow; /* 144 x90 */
87 __le32 RequestQueueLength; /* 148 x94 */
88 __le32 ResponseQueueIn; /* 152 x98 */
89 __le32 ResponseQueueInAddrHi; /* 156 x9c */
90 __le32 ResponseQueueInAddrLow; /* 160 xa0 */
91 __le32 ResponseQueueBaseAddrHi; /* 164 xa4 */
92 __le32 ResponseQueueBaseAddrLow; /* 168 xa8 */
93 __le32 ResponseQueueLength; /* 172 xac */
94 __le32 NetRxLargeBufferQueueOut; /* 176 xb0 */
95 __le32 NetRxLargeBufferQueueBaseAddrHi; /* 180 xb4 */
96 __le32 NetRxLargeBufferQueueBaseAddrLow; /* 184 xb8 */
97 __le32 NetRxLargeBufferQueueLength; /* 188 xbc */
98 __le32 NetRxLargeBufferLength; /* 192 xc0 */
99 __le32 NetRxSmallBufferQueueOut; /* 196 xc4 */
100 __le32 NetRxSmallBufferQueueBaseAddrHi; /* 200 xc8 */
101 __le32 NetRxSmallBufferQueueBaseAddrLow; /* 204 xcc */
102 __le32 NetRxSmallBufferQueueLength; /* 208 xd0 */
103 __le32 NetRxSmallBufferLength; /* 212 xd4 */
104 __le32 HMCReserved0[10]; /* 216 xd8 */
105};
106
107struct local_ram_cfg_regs {
108 __le32 BufletSize; /* 80 x50 */
109 __le32 BufletMaxCount; /* 84 x54 */
110 __le32 BufletCurrCount; /* 88 x58 */
111 __le32 BufletPauseThresholdCount; /* 92 x5c */
112 __le32 BufletTCPWinThresholdHi; /* 96 x60 */
113 __le32 BufletTCPWinThresholdLow; /* 100 x64 */
114 __le32 IPHashTableBaseAddr; /* 104 x68 */
115 __le32 IPHashTableSize; /* 108 x6c */
116 __le32 TCPHashTableBaseAddr; /* 112 x70 */
117 __le32 TCPHashTableSize; /* 116 x74 */
118 __le32 NCBAreaBaseAddr; /* 120 x78 */
119 __le32 NCBMaxCount; /* 124 x7c */
120 __le32 NCBCurrCount; /* 128 x80 */
121 __le32 DRBAreaBaseAddr; /* 132 x84 */
122 __le32 DRBMaxCount; /* 136 x88 */
123 __le32 DRBCurrCount; /* 140 x8c */
124 __le32 LRCReserved[28]; /* 144 x90 */
125};
126
127struct prot_stat_regs {
128 __le32 MACTxFrameCount; /* 80 x50 R */
129 __le32 MACTxByteCount; /* 84 x54 R */
130 __le32 MACRxFrameCount; /* 88 x58 R */
131 __le32 MACRxByteCount; /* 92 x5c R */
132 __le32 MACCRCErrCount; /* 96 x60 R */
133 __le32 MACEncErrCount; /* 100 x64 R */
134 __le32 MACRxLengthErrCount; /* 104 x68 R */
135 __le32 IPTxPacketCount; /* 108 x6c R */
136 __le32 IPTxByteCount; /* 112 x70 R */
137 __le32 IPTxFragmentCount; /* 116 x74 R */
138 __le32 IPRxPacketCount; /* 120 x78 R */
139 __le32 IPRxByteCount; /* 124 x7c R */
140 __le32 IPRxFragmentCount; /* 128 x80 R */
141 __le32 IPDatagramReassemblyCount; /* 132 x84 R */
142 __le32 IPV6RxPacketCount; /* 136 x88 R */
143 __le32 IPErrPacketCount; /* 140 x8c R */
144 __le32 IPReassemblyErrCount; /* 144 x90 R */
145 __le32 TCPTxSegmentCount; /* 148 x94 R */
146 __le32 TCPTxByteCount; /* 152 x98 R */
147 __le32 TCPRxSegmentCount; /* 156 x9c R */
148 __le32 TCPRxByteCount; /* 160 xa0 R */
149 __le32 TCPTimerExpCount; /* 164 xa4 R */
150 __le32 TCPRxAckCount; /* 168 xa8 R */
151 __le32 TCPTxAckCount; /* 172 xac R */
152 __le32 TCPRxErrOOOCount; /* 176 xb0 R */
153 __le32 PSReserved0; /* 180 xb4 */
154 __le32 TCPRxWindowProbeUpdateCount; /* 184 xb8 R */
155 __le32 ECCErrCorrectionCount; /* 188 xbc R */
156 __le32 PSReserved1[16]; /* 192 xc0 */
157};
158
159
160/* remote register set (access via PCI memory read/write) */
161struct isp_reg {
162#define MBOX_REG_COUNT 8
163 __le32 mailbox[MBOX_REG_COUNT];
164
165 __le32 flash_address; /* 0x20 */
166 __le32 flash_data;
167 __le32 ctrl_status;
168
169 union {
170 struct {
171 __le32 nvram;
172 __le32 reserved1[2]; /* 0x30 */
173 } __attribute__ ((packed)) isp4010;
174 struct {
175 __le32 intr_mask;
176 __le32 nvram; /* 0x30 */
177 __le32 semaphore;
178 } __attribute__ ((packed)) isp4022;
179 } u1;
180
181 __le32 req_q_in; /* SCSI Request Queue Producer Index */
182 __le32 rsp_q_out; /* SCSI Completion Queue Consumer Index */
183
184 __le32 reserved2[4]; /* 0x40 */
185
186 union {
187 struct {
188 __le32 ext_hw_conf; /* 0x50 */
189 __le32 flow_ctrl;
190 __le32 port_ctrl;
191 __le32 port_status;
192
193 __le32 reserved3[8]; /* 0x60 */
194
195 __le32 req_q_out; /* 0x80 */
196
197 __le32 reserved4[23]; /* 0x84 */
198
199 __le32 gp_out; /* 0xe0 */
200 __le32 gp_in;
201
202 __le32 reserved5[5];
203
204 __le32 port_err_status; /* 0xfc */
205 } __attribute__ ((packed)) isp4010;
206 struct {
207 union {
208 struct port_ctrl_stat_regs p0;
209 struct host_mem_cfg_regs p1;
210 struct local_ram_cfg_regs p2;
211 struct prot_stat_regs p3;
212 __le32 r_union[44];
213 };
214
215 } __attribute__ ((packed)) isp4022;
216 } u2;
217}; /* 256 x100 */
218
219
220/* Semaphore Defines for 4010 */
221#define QL4010_DRVR_SEM_BITS 0x00000030
222#define QL4010_GPIO_SEM_BITS 0x000000c0
223#define QL4010_SDRAM_SEM_BITS 0x00000300
224#define QL4010_PHY_SEM_BITS 0x00000c00
225#define QL4010_NVRAM_SEM_BITS 0x00003000
226#define QL4010_FLASH_SEM_BITS 0x0000c000
227
228#define QL4010_DRVR_SEM_MASK 0x00300000
229#define QL4010_GPIO_SEM_MASK 0x00c00000
230#define QL4010_SDRAM_SEM_MASK 0x03000000
231#define QL4010_PHY_SEM_MASK 0x0c000000
232#define QL4010_NVRAM_SEM_MASK 0x30000000
233#define QL4010_FLASH_SEM_MASK 0xc0000000
234
235/* Semaphore Defines for 4022 */
236#define QL4022_RESOURCE_MASK_BASE_CODE 0x7
237#define QL4022_RESOURCE_BITS_BASE_CODE 0x4
238
239
240#define QL4022_DRVR_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (1+16))
241#define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16))
242#define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16))
243#define QL4022_NVRAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (10+16))
244#define QL4022_FLASH_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (13+16))
245
246
247
248/* Page # defines for 4022 */
249#define PORT_CTRL_STAT_PAGE 0 /* 4022 */
250#define HOST_MEM_CFG_PAGE 1 /* 4022 */
251#define LOCAL_RAM_CFG_PAGE 2 /* 4022 */
252#define PROT_STAT_PAGE 3 /* 4022 */
253
254/* Register Mask - sets corresponding mask bits in the upper word */
255static inline uint32_t set_rmask(uint32_t val)
256{
257 return (val & 0xffff) | (val << 16);
258}
259
260
261static inline uint32_t clr_rmask(uint32_t val)
262{
263 return 0 | (val << 16);
264}
265
266/* ctrl_status definitions */
267#define CSR_SCSI_PAGE_SELECT 0x00000003
268#define CSR_SCSI_INTR_ENABLE 0x00000004 /* 4010 */
269#define CSR_SCSI_RESET_INTR 0x00000008
270#define CSR_SCSI_COMPLETION_INTR 0x00000010
271#define CSR_SCSI_PROCESSOR_INTR 0x00000020
272#define CSR_INTR_RISC 0x00000040
273#define CSR_BOOT_ENABLE 0x00000080
274#define CSR_NET_PAGE_SELECT 0x00000300 /* 4010 */
275#define CSR_FUNC_NUM 0x00000700 /* 4022 */
276#define CSR_NET_RESET_INTR 0x00000800 /* 4010 */
277#define CSR_FORCE_SOFT_RESET 0x00002000 /* 4022 */
278#define CSR_FATAL_ERROR 0x00004000
279#define CSR_SOFT_RESET 0x00008000
280#define ISP_CONTROL_FN_MASK CSR_FUNC_NUM
281#define ISP_CONTROL_FN0_SCSI 0x0500
282#define ISP_CONTROL_FN1_SCSI 0x0700
283
284#define INTR_PENDING (CSR_SCSI_COMPLETION_INTR |\
285 CSR_SCSI_PROCESSOR_INTR |\
286 CSR_SCSI_RESET_INTR)
287
288/* ISP InterruptMask definitions */
289#define IMR_SCSI_INTR_ENABLE 0x00000004 /* 4022 */
290
291/* ISP 4022 nvram definitions */
292#define NVR_WRITE_ENABLE 0x00000010 /* 4022 */
293
294/* ISP port_status definitions */
295
296/* ISP Semaphore definitions */
297
298/* ISP General Purpose Output definitions */
299#define GPOR_TOPCAT_RESET 0x00000004
300
301/* shadow registers (DMA'd from HA to system memory. read only) */
302struct shadow_regs {
303 /* SCSI Request Queue Consumer Index */
304 __le32 req_q_out; /* 0 x0 R */
305
306 /* SCSI Completion Queue Producer Index */
307 __le32 rsp_q_in; /* 4 x4 R */
308}; /* 8 x8 */
309
310
311/* External hardware configuration register */
312union external_hw_config_reg {
313 struct {
314 /* FIXME: Do we even need this? All values are
315 * referred to by 16 bit quantities. Platform and
316 * endianess issues. */
317 __le32 bReserved0:1;
318 __le32 bSDRAMProtectionMethod:2;
319 __le32 bSDRAMBanks:1;
320 __le32 bSDRAMChipWidth:1;
321 __le32 bSDRAMChipSize:2;
322 __le32 bParityDisable:1;
323 __le32 bExternalMemoryType:1;
324 __le32 bFlashBIOSWriteEnable:1;
325 __le32 bFlashUpperBankSelect:1;
326 __le32 bWriteBurst:2;
327 __le32 bReserved1:3;
328 __le32 bMask:16;
329 };
330 uint32_t Asuint32_t;
331};
332
333/*************************************************************************
334 *
335 * Mailbox Commands Structures and Definitions
336 *
337 *************************************************************************/
338
339/* Mailbox command definitions */
340#define MBOX_CMD_ABOUT_FW 0x0009
341#define MBOX_CMD_LUN_RESET 0x0016
342#define MBOX_CMD_GET_FW_STATUS 0x001F
343#define MBOX_CMD_SET_ISNS_SERVICE 0x0021
344#define ISNS_DISABLE 0
345#define ISNS_ENABLE 1
346#define MBOX_CMD_READ_FLASH 0x0026
347#define MBOX_CMD_CLEAR_DATABASE_ENTRY 0x0031
348#define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT 0x0056
349#define LOGOUT_OPTION_CLOSE_SESSION 0x01
350#define LOGOUT_OPTION_RELOGIN 0x02
351#define MBOX_CMD_EXECUTE_IOCB_A64 0x005A
352#define MBOX_CMD_INITIALIZE_FIRMWARE 0x0060
353#define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK 0x0061
354#define MBOX_CMD_REQUEST_DATABASE_ENTRY 0x0062
355#define MBOX_CMD_SET_DATABASE_ENTRY 0x0063
356#define MBOX_CMD_GET_DATABASE_ENTRY 0x0064
357#define DDB_DS_UNASSIGNED 0x00
358#define DDB_DS_NO_CONNECTION_ACTIVE 0x01
359#define DDB_DS_SESSION_ACTIVE 0x04
360#define DDB_DS_SESSION_FAILED 0x06
361#define DDB_DS_LOGIN_IN_PROCESS 0x07
362#define MBOX_CMD_GET_FW_STATE 0x0069
363
364/* Mailbox 1 */
365#define FW_STATE_READY 0x0000
366#define FW_STATE_CONFIG_WAIT 0x0001
367#define FW_STATE_ERROR 0x0004
368#define FW_STATE_DHCP_IN_PROGRESS 0x0008
369
370/* Mailbox 3 */
371#define FW_ADDSTATE_OPTICAL_MEDIA 0x0001
372#define FW_ADDSTATE_DHCP_ENABLED 0x0002
373#define FW_ADDSTATE_LINK_UP 0x0010
374#define FW_ADDSTATE_ISNS_SVC_ENABLED 0x0020
375#define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS 0x006B
376#define MBOX_CMD_CONN_OPEN_SESS_LOGIN 0x0074
377#define MBOX_CMD_GET_CRASH_RECORD 0x0076 /* 4010 only */
378#define MBOX_CMD_GET_CONN_EVENT_LOG 0x0077
379
380/* Mailbox status definitions */
381#define MBOX_COMPLETION_STATUS 4
382#define MBOX_STS_BUSY 0x0007
383#define MBOX_STS_INTERMEDIATE_COMPLETION 0x1000
384#define MBOX_STS_COMMAND_COMPLETE 0x4000
385#define MBOX_STS_COMMAND_ERROR 0x4005
386
387#define MBOX_ASYNC_EVENT_STATUS 8
388#define MBOX_ASTS_SYSTEM_ERROR 0x8002
389#define MBOX_ASTS_REQUEST_TRANSFER_ERROR 0x8003
390#define MBOX_ASTS_RESPONSE_TRANSFER_ERROR 0x8004
391#define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM 0x8005
392#define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED 0x8006
393#define MBOX_ASTS_LINK_UP 0x8010
394#define MBOX_ASTS_LINK_DOWN 0x8011
395#define MBOX_ASTS_DATABASE_CHANGED 0x8014
396#define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED 0x8015
397#define MBOX_ASTS_SELF_TEST_FAILED 0x8016
398#define MBOX_ASTS_LOGIN_FAILED 0x8017
399#define MBOX_ASTS_DNS 0x8018
400#define MBOX_ASTS_HEARTBEAT 0x8019
401#define MBOX_ASTS_NVRAM_INVALID 0x801A
402#define MBOX_ASTS_MAC_ADDRESS_CHANGED 0x801B
403#define MBOX_ASTS_IP_ADDRESS_CHANGED 0x801C
404#define MBOX_ASTS_DHCP_LEASE_EXPIRED 0x801D
405#define MBOX_ASTS_DHCP_LEASE_ACQUIRED 0x801F
406#define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021
407#define ISNS_EVENT_DATA_RECEIVED 0x0000
408#define ISNS_EVENT_CONNECTION_OPENED 0x0001
409#define ISNS_EVENT_CONNECTION_FAILED 0x0002
410#define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR 0x8022
411#define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027
412
413/*************************************************************************/
414
415/* Host Adapter Initialization Control Block (from host) */
416struct init_fw_ctrl_blk {
417 uint8_t Version; /* 00 */
418 uint8_t Control; /* 01 */
419
420 uint16_t FwOptions; /* 02-03 */
421#define FWOPT_HEARTBEAT_ENABLE 0x1000
422#define FWOPT_SESSION_MODE 0x0040
423#define FWOPT_INITIATOR_MODE 0x0020
424#define FWOPT_TARGET_MODE 0x0010
425
426 uint16_t ExecThrottle; /* 04-05 */
427 uint8_t RetryCount; /* 06 */
428 uint8_t RetryDelay; /* 07 */
429 uint16_t MaxEthFrPayloadSize; /* 08-09 */
430 uint16_t AddFwOptions; /* 0A-0B */
431
432 uint8_t HeartbeatInterval; /* 0C */
433 uint8_t InstanceNumber; /* 0D */
434 uint16_t RES2; /* 0E-0F */
435 uint16_t ReqQConsumerIndex; /* 10-11 */
436 uint16_t ComplQProducerIndex; /* 12-13 */
437 uint16_t ReqQLen; /* 14-15 */
438 uint16_t ComplQLen; /* 16-17 */
439 uint32_t ReqQAddrLo; /* 18-1B */
440 uint32_t ReqQAddrHi; /* 1C-1F */
441 uint32_t ComplQAddrLo; /* 20-23 */
442 uint32_t ComplQAddrHi; /* 24-27 */
443 uint32_t ShadowRegBufAddrLo; /* 28-2B */
444 uint32_t ShadowRegBufAddrHi; /* 2C-2F */
445
446 uint16_t iSCSIOptions; /* 30-31 */
447
448 uint16_t TCPOptions; /* 32-33 */
449
450 uint16_t IPOptions; /* 34-35 */
451
452 uint16_t MaxPDUSize; /* 36-37 */
453 uint16_t RcvMarkerInt; /* 38-39 */
454 uint16_t SndMarkerInt; /* 3A-3B */
455 uint16_t InitMarkerlessInt; /* 3C-3D */
456 uint16_t FirstBurstSize; /* 3E-3F */
457 uint16_t DefaultTime2Wait; /* 40-41 */
458 uint16_t DefaultTime2Retain; /* 42-43 */
459 uint16_t MaxOutStndngR2T; /* 44-45 */
460 uint16_t KeepAliveTimeout; /* 46-47 */
461 uint16_t PortNumber; /* 48-49 */
462 uint16_t MaxBurstSize; /* 4A-4B */
463 uint32_t RES4; /* 4C-4F */
464 uint8_t IPAddr[4]; /* 50-53 */
465 uint8_t RES5[12]; /* 54-5F */
466 uint8_t SubnetMask[4]; /* 60-63 */
467 uint8_t RES6[12]; /* 64-6F */
468 uint8_t GatewayIPAddr[4]; /* 70-73 */
469 uint8_t RES7[12]; /* 74-7F */
470 uint8_t PriDNSIPAddr[4]; /* 80-83 */
471 uint8_t SecDNSIPAddr[4]; /* 84-87 */
472 uint8_t RES8[8]; /* 88-8F */
473 uint8_t Alias[32]; /* 90-AF */
474 uint8_t TargAddr[8]; /* B0-B7 *//* /FIXME: Remove?? */
475 uint8_t CHAPNameSecretsTable[8]; /* B8-BF */
476 uint8_t EthernetMACAddr[6]; /* C0-C5 */
477 uint16_t TargetPortalGroup; /* C6-C7 */
478 uint8_t SendScale; /* C8 */
479 uint8_t RecvScale; /* C9 */
480 uint8_t TypeOfService; /* CA */
481 uint8_t Time2Live; /* CB */
482 uint16_t VLANPriority; /* CC-CD */
483 uint16_t Reserved8; /* CE-CF */
484 uint8_t SecIPAddr[4]; /* D0-D3 */
485 uint8_t Reserved9[12]; /* D4-DF */
486 uint8_t iSNSIPAddr[4]; /* E0-E3 */
487 uint16_t iSNSServerPortNumber; /* E4-E5 */
488 uint8_t Reserved10[10]; /* E6-EF */
489 uint8_t SLPDAIPAddr[4]; /* F0-F3 */
490 uint8_t Reserved11[12]; /* F4-FF */
491 uint8_t iSCSINameString[256]; /* 100-1FF */
492};
493
494/*************************************************************************/
495
496struct dev_db_entry {
497 uint8_t options; /* 00 */
498#define DDB_OPT_DISC_SESSION 0x10
499#define DDB_OPT_TARGET 0x02 /* device is a target */
500
501 uint8_t control; /* 01 */
502
503 uint16_t exeThrottle; /* 02-03 */
504 uint16_t exeCount; /* 04-05 */
505 uint8_t retryCount; /* 06 */
506 uint8_t retryDelay; /* 07 */
507 uint16_t iSCSIOptions; /* 08-09 */
508
509 uint16_t TCPOptions; /* 0A-0B */
510
511 uint16_t IPOptions; /* 0C-0D */
512
513 uint16_t maxPDUSize; /* 0E-0F */
514 uint16_t rcvMarkerInt; /* 10-11 */
515 uint16_t sndMarkerInt; /* 12-13 */
516 uint16_t iSCSIMaxSndDataSegLen; /* 14-15 */
517 uint16_t firstBurstSize; /* 16-17 */
518 uint16_t minTime2Wait; /* 18-19 : RA :default_time2wait */
519 uint16_t maxTime2Retain; /* 1A-1B */
520 uint16_t maxOutstndngR2T; /* 1C-1D */
521 uint16_t keepAliveTimeout; /* 1E-1F */
522 uint8_t ISID[6]; /* 20-25 big-endian, must be converted
523 * to little-endian */
524 uint16_t TSID; /* 26-27 */
525 uint16_t portNumber; /* 28-29 */
526 uint16_t maxBurstSize; /* 2A-2B */
527 uint16_t taskMngmntTimeout; /* 2C-2D */
528 uint16_t reserved1; /* 2E-2F */
529 uint8_t ipAddr[0x10]; /* 30-3F */
530 uint8_t iSCSIAlias[0x20]; /* 40-5F */
531 uint8_t targetAddr[0x20]; /* 60-7F */
532 uint8_t userID[0x20]; /* 80-9F */
533 uint8_t password[0x20]; /* A0-BF */
534 uint8_t iscsiName[0x100]; /* C0-1BF : xxzzy Make this a
535 * pointer to a string so we
536 * don't have to reserve soooo
537 * much RAM */
538 uint16_t ddbLink; /* 1C0-1C1 */
539 uint16_t CHAPTableIndex; /* 1C2-1C3 */
540 uint16_t TargetPortalGroup; /* 1C4-1C5 */
541 uint16_t reserved2[2]; /* 1C6-1C7 */
542 uint32_t statSN; /* 1C8-1CB */
543 uint32_t expStatSN; /* 1CC-1CF */
544 uint16_t reserved3[0x2C]; /* 1D0-1FB */
545 uint16_t ddbValidCookie; /* 1FC-1FD */
546 uint16_t ddbValidSize; /* 1FE-1FF */
547};
548
549/*************************************************************************/
550
551/* Flash definitions */
552
553#define FLASH_OFFSET_SYS_INFO 0x02000000
554#define FLASH_DEFAULTBLOCKSIZE 0x20000
555#define FLASH_EOF_OFFSET (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes
556 * for EOF
557 * signature */
558
559struct sys_info_phys_addr {
560 uint8_t address[6]; /* 00-05 */
561 uint8_t filler[2]; /* 06-07 */
562};
563
564struct flash_sys_info {
565 uint32_t cookie; /* 00-03 */
566 uint32_t physAddrCount; /* 04-07 */
567 struct sys_info_phys_addr physAddr[4]; /* 08-27 */
568 uint8_t vendorId[128]; /* 28-A7 */
569 uint8_t productId[128]; /* A8-127 */
570 uint32_t serialNumber; /* 128-12B */
571
572 /* PCI Configuration values */
573 uint32_t pciDeviceVendor; /* 12C-12F */
574 uint32_t pciDeviceId; /* 130-133 */
575 uint32_t pciSubsysVendor; /* 134-137 */
576 uint32_t pciSubsysId; /* 138-13B */
577
578 /* This validates version 1. */
579 uint32_t crumbs; /* 13C-13F */
580
581 uint32_t enterpriseNumber; /* 140-143 */
582
583 uint32_t mtu; /* 144-147 */
584 uint32_t reserved0; /* 148-14b */
585 uint32_t crumbs2; /* 14c-14f */
586 uint8_t acSerialNumber[16]; /* 150-15f */
587 uint32_t crumbs3; /* 160-16f */
588
589 /* Leave this last in the struct so it is declared invalid if
590 * any new items are added.
591 */
592 uint32_t reserved1[39]; /* 170-1ff */
593}; /* 200 */
594
595struct crash_record {
596 uint16_t fw_major_version; /* 00 - 01 */
597 uint16_t fw_minor_version; /* 02 - 03 */
598 uint16_t fw_patch_version; /* 04 - 05 */
599 uint16_t fw_build_version; /* 06 - 07 */
600
601 uint8_t build_date[16]; /* 08 - 17 */
602 uint8_t build_time[16]; /* 18 - 27 */
603 uint8_t build_user[16]; /* 28 - 37 */
604 uint8_t card_serial_num[16]; /* 38 - 47 */
605
606 uint32_t time_of_crash_in_secs; /* 48 - 4B */
607 uint32_t time_of_crash_in_ms; /* 4C - 4F */
608
609 uint16_t out_RISC_sd_num_frames; /* 50 - 51 */
610 uint16_t OAP_sd_num_words; /* 52 - 53 */
611 uint16_t IAP_sd_num_frames; /* 54 - 55 */
612 uint16_t in_RISC_sd_num_words; /* 56 - 57 */
613
614 uint8_t reserved1[28]; /* 58 - 7F */
615
616 uint8_t out_RISC_reg_dump[256]; /* 80 -17F */
617 uint8_t in_RISC_reg_dump[256]; /*180 -27F */
618 uint8_t in_out_RISC_stack_dump[0]; /*280 - ??? */
619};
620
621struct conn_event_log_entry {
622#define MAX_CONN_EVENT_LOG_ENTRIES 100
623 uint32_t timestamp_sec; /* 00 - 03 seconds since boot */
624 uint32_t timestamp_ms; /* 04 - 07 milliseconds since boot */
625 uint16_t device_index; /* 08 - 09 */
626 uint16_t fw_conn_state; /* 0A - 0B */
627 uint8_t event_type; /* 0C - 0C */
628 uint8_t error_code; /* 0D - 0D */
629 uint16_t error_code_detail; /* 0E - 0F */
630 uint8_t num_consecutive_events; /* 10 - 10 */
631 uint8_t rsvd[3]; /* 11 - 13 */
632};
633
634/*************************************************************************
635 *
636 * IOCB Commands Structures and Definitions
637 *
638 *************************************************************************/
639#define IOCB_MAX_CDB_LEN 16 /* Bytes in a CBD */
640#define IOCB_MAX_SENSEDATA_LEN 32 /* Bytes of sense data */
641
642/* IOCB header structure */
643struct qla4_header {
644 uint8_t entryType;
645#define ET_STATUS 0x03
646#define ET_MARKER 0x04
647#define ET_CONT_T1 0x0A
648#define ET_STATUS_CONTINUATION 0x10
649#define ET_CMND_T3 0x19
650#define ET_PASSTHRU0 0x3A
651#define ET_PASSTHRU_STATUS 0x3C
652
653 uint8_t entryStatus;
654 uint8_t systemDefined;
655 uint8_t entryCount;
656
657 /* SyetemDefined definition */
658};
659
660/* Generic queue entry structure*/
661struct queue_entry {
662 uint8_t data[60];
663 uint32_t signature;
664
665};
666
667/* 64 bit addressing segment counts*/
668
669#define COMMAND_SEG_A64 1
670#define CONTINUE_SEG_A64 5
671
672/* 64 bit addressing segment definition*/
673
674struct data_seg_a64 {
675 struct {
676 uint32_t addrLow;
677 uint32_t addrHigh;
678
679 } base;
680
681 uint32_t count;
682
683};
684
685/* Command Type 3 entry structure*/
686
687struct command_t3_entry {
688 struct qla4_header hdr; /* 00-03 */
689
690 uint32_t handle; /* 04-07 */
691 uint16_t target; /* 08-09 */
692 uint16_t connection_id; /* 0A-0B */
693
694 uint8_t control_flags; /* 0C */
695
696 /* data direction (bits 5-6) */
697#define CF_WRITE 0x20
698#define CF_READ 0x40
699#define CF_NO_DATA 0x00
700
701 /* task attributes (bits 2-0) */
702#define CF_HEAD_TAG 0x03
703#define CF_ORDERED_TAG 0x02
704#define CF_SIMPLE_TAG 0x01
705
706 /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS
707 * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS
708 * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET
709 * PROPERLY.
710 */
711 uint8_t state_flags; /* 0D */
712 uint8_t cmdRefNum; /* 0E */
713 uint8_t reserved1; /* 0F */
714 uint8_t cdb[IOCB_MAX_CDB_LEN]; /* 10-1F */
715 struct scsi_lun lun; /* FCP LUN (BE). */
716 uint32_t cmdSeqNum; /* 28-2B */
717 uint16_t timeout; /* 2C-2D */
718 uint16_t dataSegCnt; /* 2E-2F */
719 uint32_t ttlByteCnt; /* 30-33 */
720 struct data_seg_a64 dataseg[COMMAND_SEG_A64]; /* 34-3F */
721
722};
723
724
725/* Continuation Type 1 entry structure*/
726struct continuation_t1_entry {
727 struct qla4_header hdr;
728
729 struct data_seg_a64 dataseg[CONTINUE_SEG_A64];
730
731};
732
733/* Parameterize for 64 or 32 bits */
734#define COMMAND_SEG COMMAND_SEG_A64
735#define CONTINUE_SEG CONTINUE_SEG_A64
736
737#define ET_COMMAND ET_CMND_T3
738#define ET_CONTINUE ET_CONT_T1
739
740/* Marker entry structure*/
741struct marker_entry {
742 struct qla4_header hdr; /* 00-03 */
743
744 uint32_t system_defined; /* 04-07 */
745 uint16_t target; /* 08-09 */
746 uint16_t modifier; /* 0A-0B */
747#define MM_LUN_RESET 0
748
749 uint16_t flags; /* 0C-0D */
750 uint16_t reserved1; /* 0E-0F */
751 struct scsi_lun lun; /* FCP LUN (BE). */
752 uint64_t reserved2; /* 18-1F */
753 uint64_t reserved3; /* 20-27 */
754 uint64_t reserved4; /* 28-2F */
755 uint64_t reserved5; /* 30-37 */
756 uint64_t reserved6; /* 38-3F */
757};
758
759/* Status entry structure*/
760struct status_entry {
761 struct qla4_header hdr; /* 00-03 */
762
763 uint32_t handle; /* 04-07 */
764
765 uint8_t scsiStatus; /* 08 */
766#define SCSI_CHECK_CONDITION 0x02
767
768 uint8_t iscsiFlags; /* 09 */
769#define ISCSI_FLAG_RESIDUAL_UNDER 0x02
770#define ISCSI_FLAG_RESIDUAL_OVER 0x04
771
772 uint8_t iscsiResponse; /* 0A */
773
774 uint8_t completionStatus; /* 0B */
775#define SCS_COMPLETE 0x00
776#define SCS_INCOMPLETE 0x01
777#define SCS_RESET_OCCURRED 0x04
778#define SCS_ABORTED 0x05
779#define SCS_TIMEOUT 0x06
780#define SCS_DATA_OVERRUN 0x07
781#define SCS_DATA_UNDERRUN 0x15
782#define SCS_QUEUE_FULL 0x1C
783#define SCS_DEVICE_UNAVAILABLE 0x28
784#define SCS_DEVICE_LOGGED_OUT 0x29
785
786 uint8_t reserved1; /* 0C */
787
788 /* state_flags MUST be at the same location as state_flags in
789 * the Command_T3/4_Entry */
790 uint8_t state_flags; /* 0D */
791
792 uint16_t senseDataByteCnt; /* 0E-0F */
793 uint32_t residualByteCnt; /* 10-13 */
794 uint32_t bidiResidualByteCnt; /* 14-17 */
795 uint32_t expSeqNum; /* 18-1B */
796 uint32_t maxCmdSeqNum; /* 1C-1F */
797 uint8_t senseData[IOCB_MAX_SENSEDATA_LEN]; /* 20-3F */
798
799};
800
801struct passthru0 {
802 struct qla4_header hdr; /* 00-03 */
803 uint32_t handle; /* 04-07 */
804 uint16_t target; /* 08-09 */
805 uint16_t connectionID; /* 0A-0B */
806#define ISNS_DEFAULT_SERVER_CONN_ID ((uint16_t)0x8000)
807
808 uint16_t controlFlags; /* 0C-0D */
809#define PT_FLAG_ETHERNET_FRAME 0x8000
810#define PT_FLAG_ISNS_PDU 0x8000
811#define PT_FLAG_SEND_BUFFER 0x0200
812#define PT_FLAG_WAIT_4_RESPONSE 0x0100
813
814 uint16_t timeout; /* 0E-0F */
815#define PT_DEFAULT_TIMEOUT 30 /* seconds */
816
817 struct data_seg_a64 outDataSeg64; /* 10-1B */
818 uint32_t res1; /* 1C-1F */
819 struct data_seg_a64 inDataSeg64; /* 20-2B */
820 uint8_t res2[20]; /* 2C-3F */
821};
822
823struct passthru_status {
824 struct qla4_header hdr; /* 00-03 */
825 uint32_t handle; /* 04-07 */
826 uint16_t target; /* 08-09 */
827 uint16_t connectionID; /* 0A-0B */
828
829 uint8_t completionStatus; /* 0C */
830#define PASSTHRU_STATUS_COMPLETE 0x01
831
832 uint8_t residualFlags; /* 0D */
833
834 uint16_t timeout; /* 0E-0F */
835 uint16_t portNumber; /* 10-11 */
836 uint8_t res1[10]; /* 12-1B */
837 uint32_t outResidual; /* 1C-1F */
838 uint8_t res2[12]; /* 20-2B */
839 uint32_t inResidual; /* 2C-2F */
840 uint8_t res4[16]; /* 30-3F */
841};
842
843#endif /* _QLA4X_FW_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 17:15:32 -0500