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path: root/drivers/scsi/qla2xxx
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-rw-r--r--drivers/scsi/qla2xxx/qla_attr.c120
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.c925
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.h151
-rw-r--r--drivers/scsi/qla2xxx/qla_def.h19
-rw-r--r--drivers/scsi/qla2xxx/qla_devtbl.h17
-rw-r--r--drivers/scsi/qla2xxx/qla_fw.h4
-rw-r--r--drivers/scsi/qla2xxx/qla_gbl.h26
-rw-r--r--drivers/scsi/qla2xxx/qla_init.c143
-rw-r--r--drivers/scsi/qla2xxx/qla_iocb.c3
-rw-r--r--drivers/scsi/qla2xxx/qla_isr.c24
-rw-r--r--drivers/scsi/qla2xxx/qla_mbx.c280
-rw-r--r--drivers/scsi/qla2xxx/qla_os.c125
-rw-r--r--drivers/scsi/qla2xxx/qla_version.h2
13 files changed, 735 insertions, 1104 deletions
diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c
index e96d58ded57c..87f90c4f08e9 100644
--- a/drivers/scsi/qla2xxx/qla_attr.c
+++ b/drivers/scsi/qla2xxx/qla_attr.c
@@ -16,15 +16,16 @@ qla2x00_sysfs_read_fw_dump(struct kobject *kobj, char *buf, loff_t off,
16{ 16{
17 struct scsi_qla_host *ha = to_qla_host(dev_to_shost(container_of(kobj, 17 struct scsi_qla_host *ha = to_qla_host(dev_to_shost(container_of(kobj,
18 struct device, kobj))); 18 struct device, kobj)));
19 char *rbuf = (char *)ha->fw_dump;
19 20
20 if (ha->fw_dump_reading == 0) 21 if (ha->fw_dump_reading == 0)
21 return 0; 22 return 0;
22 if (off > ha->fw_dump_buffer_len) 23 if (off > ha->fw_dump_len)
23 return 0; 24 return 0;
24 if (off + count > ha->fw_dump_buffer_len) 25 if (off + count > ha->fw_dump_len)
25 count = ha->fw_dump_buffer_len - off; 26 count = ha->fw_dump_len - off;
26 27
27 memcpy(buf, &ha->fw_dump_buffer[off], count); 28 memcpy(buf, &rbuf[off], count);
28 29
29 return (count); 30 return (count);
30} 31}
@@ -36,7 +37,6 @@ qla2x00_sysfs_write_fw_dump(struct kobject *kobj, char *buf, loff_t off,
36 struct scsi_qla_host *ha = to_qla_host(dev_to_shost(container_of(kobj, 37 struct scsi_qla_host *ha = to_qla_host(dev_to_shost(container_of(kobj,
37 struct device, kobj))); 38 struct device, kobj)));
38 int reading; 39 int reading;
39 uint32_t dump_size;
40 40
41 if (off != 0) 41 if (off != 0)
42 return (0); 42 return (0);
@@ -44,46 +44,27 @@ qla2x00_sysfs_write_fw_dump(struct kobject *kobj, char *buf, loff_t off,
44 reading = simple_strtol(buf, NULL, 10); 44 reading = simple_strtol(buf, NULL, 10);
45 switch (reading) { 45 switch (reading) {
46 case 0: 46 case 0:
47 if (ha->fw_dump_reading == 1) { 47 if (!ha->fw_dump_reading)
48 qla_printk(KERN_INFO, ha, 48 break;
49 "Firmware dump cleared on (%ld).\n", ha->host_no);
50 49
51 vfree(ha->fw_dump_buffer); 50 qla_printk(KERN_INFO, ha,
52 ha->fw_dump_buffer = NULL; 51 "Firmware dump cleared on (%ld).\n", ha->host_no);
53 ha->fw_dump_reading = 0; 52
54 ha->fw_dumped = 0; 53 ha->fw_dump_reading = 0;
55 } 54 ha->fw_dumped = 0;
56 break; 55 break;
57 case 1: 56 case 1:
58 if (ha->fw_dumped && !ha->fw_dump_reading) { 57 if (ha->fw_dumped && !ha->fw_dump_reading) {
59 ha->fw_dump_reading = 1; 58 ha->fw_dump_reading = 1;
60 59
61 if (IS_QLA24XX(ha) || IS_QLA54XX(ha))
62 dump_size = FW_DUMP_SIZE_24XX;
63 else {
64 dump_size = FW_DUMP_SIZE_1M;
65 if (ha->fw_memory_size < 0x20000)
66 dump_size = FW_DUMP_SIZE_128K;
67 else if (ha->fw_memory_size < 0x80000)
68 dump_size = FW_DUMP_SIZE_512K;
69 }
70 ha->fw_dump_buffer = (char *)vmalloc(dump_size);
71 if (ha->fw_dump_buffer == NULL) {
72 qla_printk(KERN_WARNING, ha,
73 "Unable to allocate memory for firmware "
74 "dump buffer (%d).\n", dump_size);
75
76 ha->fw_dump_reading = 0;
77 return (count);
78 }
79 qla_printk(KERN_INFO, ha, 60 qla_printk(KERN_INFO, ha,
80 "Firmware dump ready for read on (%ld).\n", 61 "Raw firmware dump ready for read on (%ld).\n",
81 ha->host_no); 62 ha->host_no);
82 memset(ha->fw_dump_buffer, 0, dump_size);
83 ha->isp_ops.ascii_fw_dump(ha);
84 ha->fw_dump_buffer_len = strlen(ha->fw_dump_buffer);
85 } 63 }
86 break; 64 break;
65 case 2:
66 qla2x00_alloc_fw_dump(ha);
67 break;
87 } 68 }
88 return (count); 69 return (count);
89} 70}
@@ -313,9 +294,6 @@ qla2x00_sysfs_read_vpd(struct kobject *kobj, char *buf, loff_t off,
313 if (!capable(CAP_SYS_ADMIN) || off != 0) 294 if (!capable(CAP_SYS_ADMIN) || off != 0)
314 return 0; 295 return 0;
315 296
316 if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha))
317 return -ENOTSUPP;
318
319 /* Read NVRAM. */ 297 /* Read NVRAM. */
320 spin_lock_irqsave(&ha->hardware_lock, flags); 298 spin_lock_irqsave(&ha->hardware_lock, flags);
321 ha->isp_ops.read_nvram(ha, (uint8_t *)buf, ha->vpd_base, ha->vpd_size); 299 ha->isp_ops.read_nvram(ha, (uint8_t *)buf, ha->vpd_base, ha->vpd_size);
@@ -335,9 +313,6 @@ qla2x00_sysfs_write_vpd(struct kobject *kobj, char *buf, loff_t off,
335 if (!capable(CAP_SYS_ADMIN) || off != 0 || count != ha->vpd_size) 313 if (!capable(CAP_SYS_ADMIN) || off != 0 || count != ha->vpd_size)
336 return 0; 314 return 0;
337 315
338 if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha))
339 return -ENOTSUPP;
340
341 /* Write NVRAM. */ 316 /* Write NVRAM. */
342 spin_lock_irqsave(&ha->hardware_lock, flags); 317 spin_lock_irqsave(&ha->hardware_lock, flags);
343 ha->isp_ops.write_nvram(ha, (uint8_t *)buf, ha->vpd_base, count); 318 ha->isp_ops.write_nvram(ha, (uint8_t *)buf, ha->vpd_base, count);
@@ -357,6 +332,53 @@ static struct bin_attribute sysfs_vpd_attr = {
357 .write = qla2x00_sysfs_write_vpd, 332 .write = qla2x00_sysfs_write_vpd,
358}; 333};
359 334
335static ssize_t
336qla2x00_sysfs_read_sfp(struct kobject *kobj, char *buf, loff_t off,
337 size_t count)
338{
339 struct scsi_qla_host *ha = to_qla_host(dev_to_shost(container_of(kobj,
340 struct device, kobj)));
341 uint16_t iter, addr, offset;
342 int rval;
343
344 if (!capable(CAP_SYS_ADMIN) || off != 0 || count != SFP_DEV_SIZE * 2)
345 return 0;
346
347 addr = 0xa0;
348 for (iter = 0, offset = 0; iter < (SFP_DEV_SIZE * 2) / SFP_BLOCK_SIZE;
349 iter++, offset += SFP_BLOCK_SIZE) {
350 if (iter == 4) {
351 /* Skip to next device address. */
352 addr = 0xa2;
353 offset = 0;
354 }
355
356 rval = qla2x00_read_sfp(ha, ha->sfp_data_dma, addr, offset,
357 SFP_BLOCK_SIZE);
358 if (rval != QLA_SUCCESS) {
359 qla_printk(KERN_WARNING, ha,
360 "Unable to read SFP data (%x/%x/%x).\n", rval,
361 addr, offset);
362 count = 0;
363 break;
364 }
365 memcpy(buf, ha->sfp_data, SFP_BLOCK_SIZE);
366 buf += SFP_BLOCK_SIZE;
367 }
368
369 return count;
370}
371
372static struct bin_attribute sysfs_sfp_attr = {
373 .attr = {
374 .name = "sfp",
375 .mode = S_IRUSR | S_IWUSR,
376 .owner = THIS_MODULE,
377 },
378 .size = SFP_DEV_SIZE * 2,
379 .read = qla2x00_sysfs_read_sfp,
380};
381
360void 382void
361qla2x00_alloc_sysfs_attr(scsi_qla_host_t *ha) 383qla2x00_alloc_sysfs_attr(scsi_qla_host_t *ha)
362{ 384{
@@ -367,7 +389,12 @@ qla2x00_alloc_sysfs_attr(scsi_qla_host_t *ha)
367 sysfs_create_bin_file(&host->shost_gendev.kobj, &sysfs_optrom_attr); 389 sysfs_create_bin_file(&host->shost_gendev.kobj, &sysfs_optrom_attr);
368 sysfs_create_bin_file(&host->shost_gendev.kobj, 390 sysfs_create_bin_file(&host->shost_gendev.kobj,
369 &sysfs_optrom_ctl_attr); 391 &sysfs_optrom_ctl_attr);
370 sysfs_create_bin_file(&host->shost_gendev.kobj, &sysfs_vpd_attr); 392 if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) {
393 sysfs_create_bin_file(&host->shost_gendev.kobj,
394 &sysfs_vpd_attr);
395 sysfs_create_bin_file(&host->shost_gendev.kobj,
396 &sysfs_sfp_attr);
397 }
371} 398}
372 399
373void 400void
@@ -380,7 +407,12 @@ qla2x00_free_sysfs_attr(scsi_qla_host_t *ha)
380 sysfs_remove_bin_file(&host->shost_gendev.kobj, &sysfs_optrom_attr); 407 sysfs_remove_bin_file(&host->shost_gendev.kobj, &sysfs_optrom_attr);
381 sysfs_remove_bin_file(&host->shost_gendev.kobj, 408 sysfs_remove_bin_file(&host->shost_gendev.kobj,
382 &sysfs_optrom_ctl_attr); 409 &sysfs_optrom_ctl_attr);
383 sysfs_remove_bin_file(&host->shost_gendev.kobj, &sysfs_vpd_attr); 410 if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) {
411 sysfs_remove_bin_file(&host->shost_gendev.kobj,
412 &sysfs_vpd_attr);
413 sysfs_remove_bin_file(&host->shost_gendev.kobj,
414 &sysfs_sfp_attr);
415 }
384 416
385 if (ha->beacon_blink_led == 1) 417 if (ha->beacon_blink_led == 1)
386 ha->isp_ops.beacon_off(ha); 418 ha->isp_ops.beacon_off(ha);
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
index 74e54713aa7c..f6ed6962bc2b 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.c
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
@@ -8,7 +8,34 @@
8 8
9#include <linux/delay.h> 9#include <linux/delay.h>
10 10
11static int qla_uprintf(char **, char *, ...); 11static inline void
12qla2xxx_prep_dump(scsi_qla_host_t *ha, struct qla2xxx_fw_dump *fw_dump)
13{
14 fw_dump->fw_major_version = htonl(ha->fw_major_version);
15 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
16 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
17 fw_dump->fw_attributes = htonl(ha->fw_attributes);
18
19 fw_dump->vendor = htonl(ha->pdev->vendor);
20 fw_dump->device = htonl(ha->pdev->device);
21 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
22 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
23}
24
25static inline void *
26qla2xxx_copy_queues(scsi_qla_host_t *ha, void *ptr)
27{
28 /* Request queue. */
29 memcpy(ptr, ha->request_ring, ha->request_q_length *
30 sizeof(request_t));
31
32 /* Response queue. */
33 ptr += ha->request_q_length * sizeof(request_t);
34 memcpy(ptr, ha->response_ring, ha->response_q_length *
35 sizeof(response_t));
36
37 return ptr + (ha->response_q_length * sizeof(response_t));
38}
12 39
13/** 40/**
14 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. 41 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
@@ -49,10 +76,11 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
49 "request...\n", ha->fw_dump); 76 "request...\n", ha->fw_dump);
50 goto qla2300_fw_dump_failed; 77 goto qla2300_fw_dump_failed;
51 } 78 }
52 fw = ha->fw_dump; 79 fw = &ha->fw_dump->isp.isp23;
80 qla2xxx_prep_dump(ha, ha->fw_dump);
53 81
54 rval = QLA_SUCCESS; 82 rval = QLA_SUCCESS;
55 fw->hccr = RD_REG_WORD(&reg->hccr); 83 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
56 84
57 /* Pause RISC. */ 85 /* Pause RISC. */
58 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); 86 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
@@ -73,85 +101,86 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
73 if (rval == QLA_SUCCESS) { 101 if (rval == QLA_SUCCESS) {
74 dmp_reg = (uint16_t __iomem *)(reg + 0); 102 dmp_reg = (uint16_t __iomem *)(reg + 0);
75 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 103 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
76 fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++); 104 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
77 105
78 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10); 106 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
79 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) 107 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
80 fw->risc_host_reg[cnt] = RD_REG_WORD(dmp_reg++); 108 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
81 109
82 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40); 110 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40);
83 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 111 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
84 fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++); 112 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
85 113
86 WRT_REG_WORD(&reg->ctrl_status, 0x40); 114 WRT_REG_WORD(&reg->ctrl_status, 0x40);
87 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 115 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
88 for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++) 116 for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++)
89 fw->resp_dma_reg[cnt] = RD_REG_WORD(dmp_reg++); 117 fw->resp_dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
90 118
91 WRT_REG_WORD(&reg->ctrl_status, 0x50); 119 WRT_REG_WORD(&reg->ctrl_status, 0x50);
92 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 120 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
93 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 121 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
94 fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++); 122 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
95 123
96 WRT_REG_WORD(&reg->ctrl_status, 0x00); 124 WRT_REG_WORD(&reg->ctrl_status, 0x00);
97 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0); 125 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
98 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 126 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
99 fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); 127 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
100 128
101 WRT_REG_WORD(&reg->pcr, 0x2000); 129 WRT_REG_WORD(&reg->pcr, 0x2000);
102 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 130 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
103 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++) 131 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
104 fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++); 132 fw->risc_gp0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
105 133
106 WRT_REG_WORD(&reg->pcr, 0x2200); 134 WRT_REG_WORD(&reg->pcr, 0x2200);
107 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 135 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
108 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++) 136 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
109 fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++); 137 fw->risc_gp1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
110 138
111 WRT_REG_WORD(&reg->pcr, 0x2400); 139 WRT_REG_WORD(&reg->pcr, 0x2400);
112 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 140 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
113 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++) 141 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
114 fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++); 142 fw->risc_gp2_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
115 143
116 WRT_REG_WORD(&reg->pcr, 0x2600); 144 WRT_REG_WORD(&reg->pcr, 0x2600);
117 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 145 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
118 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++) 146 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
119 fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++); 147 fw->risc_gp3_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
120 148
121 WRT_REG_WORD(&reg->pcr, 0x2800); 149 WRT_REG_WORD(&reg->pcr, 0x2800);
122 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 150 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
123 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++) 151 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
124 fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++); 152 fw->risc_gp4_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
125 153
126 WRT_REG_WORD(&reg->pcr, 0x2A00); 154 WRT_REG_WORD(&reg->pcr, 0x2A00);
127 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 155 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
128 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++) 156 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
129 fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++); 157 fw->risc_gp5_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
130 158
131 WRT_REG_WORD(&reg->pcr, 0x2C00); 159 WRT_REG_WORD(&reg->pcr, 0x2C00);
132 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 160 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
133 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++) 161 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
134 fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++); 162 fw->risc_gp6_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
135 163
136 WRT_REG_WORD(&reg->pcr, 0x2E00); 164 WRT_REG_WORD(&reg->pcr, 0x2E00);
137 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 165 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
138 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++) 166 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
139 fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++); 167 fw->risc_gp7_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
140 168
141 WRT_REG_WORD(&reg->ctrl_status, 0x10); 169 WRT_REG_WORD(&reg->ctrl_status, 0x10);
142 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 170 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
143 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++) 171 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
144 fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); 172 fw->frame_buf_hdw_reg[cnt] =
173 htons(RD_REG_WORD(dmp_reg++));
145 174
146 WRT_REG_WORD(&reg->ctrl_status, 0x20); 175 WRT_REG_WORD(&reg->ctrl_status, 0x20);
147 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 176 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
148 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++) 177 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
149 fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++); 178 fw->fpm_b0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
150 179
151 WRT_REG_WORD(&reg->ctrl_status, 0x30); 180 WRT_REG_WORD(&reg->ctrl_status, 0x30);
152 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 181 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
153 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++) 182 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
154 fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++); 183 fw->fpm_b1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
155 184
156 /* Reset RISC. */ 185 /* Reset RISC. */
157 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET); 186 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
@@ -226,7 +255,7 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
226 255
227 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 256 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
228 rval = mb0 & MBS_MASK; 257 rval = mb0 & MBS_MASK;
229 fw->risc_ram[cnt] = mb2; 258 fw->risc_ram[cnt] = htons(mb2);
230 } else { 259 } else {
231 rval = QLA_FUNCTION_FAILED; 260 rval = QLA_FUNCTION_FAILED;
232 } 261 }
@@ -285,7 +314,7 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
285 314
286 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 315 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
287 rval = mb0 & MBS_MASK; 316 rval = mb0 & MBS_MASK;
288 fw->stack_ram[cnt] = mb2; 317 fw->stack_ram[cnt] = htons(mb2);
289 } else { 318 } else {
290 rval = QLA_FUNCTION_FAILED; 319 rval = QLA_FUNCTION_FAILED;
291 } 320 }
@@ -345,12 +374,15 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
345 374
346 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 375 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
347 rval = mb0 & MBS_MASK; 376 rval = mb0 & MBS_MASK;
348 fw->data_ram[cnt] = mb2; 377 fw->data_ram[cnt] = htons(mb2);
349 } else { 378 } else {
350 rval = QLA_FUNCTION_FAILED; 379 rval = QLA_FUNCTION_FAILED;
351 } 380 }
352 } 381 }
353 382
383 if (rval == QLA_SUCCESS)
384 qla2xxx_copy_queues(ha, &fw->data_ram[cnt]);
385
354 if (rval != QLA_SUCCESS) { 386 if (rval != QLA_SUCCESS) {
355 qla_printk(KERN_WARNING, ha, 387 qla_printk(KERN_WARNING, ha,
356 "Failed to dump firmware (%x)!!!\n", rval); 388 "Failed to dump firmware (%x)!!!\n", rval);
@@ -369,193 +401,6 @@ qla2300_fw_dump_failed:
369} 401}
370 402
371/** 403/**
372 * qla2300_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
373 * @ha: HA context
374 */
375void
376qla2300_ascii_fw_dump(scsi_qla_host_t *ha)
377{
378 uint32_t cnt;
379 char *uiter;
380 char fw_info[30];
381 struct qla2300_fw_dump *fw;
382 uint32_t data_ram_cnt;
383
384 uiter = ha->fw_dump_buffer;
385 fw = ha->fw_dump;
386
387 qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
388 ha->isp_ops.fw_version_str(ha, fw_info));
389
390 qla_uprintf(&uiter, "\n[==>BEG]\n");
391
392 qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
393
394 qla_uprintf(&uiter, "PBIU Registers:");
395 for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
396 if (cnt % 8 == 0) {
397 qla_uprintf(&uiter, "\n");
398 }
399 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
400 }
401
402 qla_uprintf(&uiter, "\n\nReqQ-RspQ-Risc2Host Status registers:");
403 for (cnt = 0; cnt < sizeof (fw->risc_host_reg) / 2; cnt++) {
404 if (cnt % 8 == 0) {
405 qla_uprintf(&uiter, "\n");
406 }
407 qla_uprintf(&uiter, "%04x ", fw->risc_host_reg[cnt]);
408 }
409
410 qla_uprintf(&uiter, "\n\nMailbox Registers:");
411 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
412 if (cnt % 8 == 0) {
413 qla_uprintf(&uiter, "\n");
414 }
415 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
416 }
417
418 qla_uprintf(&uiter, "\n\nAuto Request Response DMA Registers:");
419 for (cnt = 0; cnt < sizeof (fw->resp_dma_reg) / 2; cnt++) {
420 if (cnt % 8 == 0) {
421 qla_uprintf(&uiter, "\n");
422 }
423 qla_uprintf(&uiter, "%04x ", fw->resp_dma_reg[cnt]);
424 }
425
426 qla_uprintf(&uiter, "\n\nDMA Registers:");
427 for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
428 if (cnt % 8 == 0) {
429 qla_uprintf(&uiter, "\n");
430 }
431 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
432 }
433
434 qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
435 for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
436 if (cnt % 8 == 0) {
437 qla_uprintf(&uiter, "\n");
438 }
439 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
440 }
441
442 qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
443 for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
444 if (cnt % 8 == 0) {
445 qla_uprintf(&uiter, "\n");
446 }
447 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
448 }
449
450 qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
451 for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
452 if (cnt % 8 == 0) {
453 qla_uprintf(&uiter, "\n");
454 }
455 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
456 }
457
458 qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
459 for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
460 if (cnt % 8 == 0) {
461 qla_uprintf(&uiter, "\n");
462 }
463 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
464 }
465
466 qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
467 for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
468 if (cnt % 8 == 0) {
469 qla_uprintf(&uiter, "\n");
470 }
471 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
472 }
473
474 qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
475 for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
476 if (cnt % 8 == 0) {
477 qla_uprintf(&uiter, "\n");
478 }
479 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
480 }
481
482 qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
483 for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
484 if (cnt % 8 == 0) {
485 qla_uprintf(&uiter, "\n");
486 }
487 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
488 }
489
490 qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
491 for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
492 if (cnt % 8 == 0) {
493 qla_uprintf(&uiter, "\n");
494 }
495 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
496 }
497
498 qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
499 for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
500 if (cnt % 8 == 0) {
501 qla_uprintf(&uiter, "\n");
502 }
503 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
504 }
505
506 qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
507 for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
508 if (cnt % 8 == 0) {
509 qla_uprintf(&uiter, "\n");
510 }
511 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
512 }
513
514 qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
515 for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
516 if (cnt % 8 == 0) {
517 qla_uprintf(&uiter, "\n");
518 }
519 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
520 }
521
522 qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
523 for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
524 if (cnt % 8 == 0) {
525 qla_uprintf(&uiter, "\n");
526 }
527 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
528 }
529
530 qla_uprintf(&uiter, "\n\nCode RAM Dump:");
531 for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
532 if (cnt % 8 == 0) {
533 qla_uprintf(&uiter, "\n%04x: ", cnt + 0x0800);
534 }
535 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
536 }
537
538 qla_uprintf(&uiter, "\n\nStack RAM Dump:");
539 for (cnt = 0; cnt < sizeof (fw->stack_ram) / 2; cnt++) {
540 if (cnt % 8 == 0) {
541 qla_uprintf(&uiter, "\n%05x: ", cnt + 0x10000);
542 }
543 qla_uprintf(&uiter, "%04x ", fw->stack_ram[cnt]);
544 }
545
546 qla_uprintf(&uiter, "\n\nData RAM Dump:");
547 data_ram_cnt = ha->fw_memory_size - 0x11000 + 1;
548 for (cnt = 0; cnt < data_ram_cnt; cnt++) {
549 if (cnt % 8 == 0) {
550 qla_uprintf(&uiter, "\n%05x: ", cnt + 0x11000);
551 }
552 qla_uprintf(&uiter, "%04x ", fw->data_ram[cnt]);
553 }
554
555 qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
556}
557
558/**
559 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. 404 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
560 * @ha: HA context 405 * @ha: HA context
561 * @hardware_locked: Called with the hardware_lock 406 * @hardware_locked: Called with the hardware_lock
@@ -591,10 +436,11 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
591 "request...\n", ha->fw_dump); 436 "request...\n", ha->fw_dump);
592 goto qla2100_fw_dump_failed; 437 goto qla2100_fw_dump_failed;
593 } 438 }
594 fw = ha->fw_dump; 439 fw = &ha->fw_dump->isp.isp21;
440 qla2xxx_prep_dump(ha, ha->fw_dump);
595 441
596 rval = QLA_SUCCESS; 442 rval = QLA_SUCCESS;
597 fw->hccr = RD_REG_WORD(&reg->hccr); 443 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
598 444
599 /* Pause RISC. */ 445 /* Pause RISC. */
600 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); 446 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
@@ -608,79 +454,81 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
608 if (rval == QLA_SUCCESS) { 454 if (rval == QLA_SUCCESS) {
609 dmp_reg = (uint16_t __iomem *)(reg + 0); 455 dmp_reg = (uint16_t __iomem *)(reg + 0);
610 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 456 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
611 fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++); 457 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
612 458
613 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10); 459 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
614 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 460 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
615 if (cnt == 8) { 461 if (cnt == 8) {
616 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xe0); 462 dmp_reg = (uint16_t __iomem *)
463 ((uint8_t __iomem *)reg + 0xe0);
617 } 464 }
618 fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++); 465 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
619 } 466 }
620 467
621 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x20); 468 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x20);
622 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 469 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
623 fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++); 470 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
624 471
625 WRT_REG_WORD(&reg->ctrl_status, 0x00); 472 WRT_REG_WORD(&reg->ctrl_status, 0x00);
626 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0); 473 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
627 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 474 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
628 fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); 475 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
629 476
630 WRT_REG_WORD(&reg->pcr, 0x2000); 477 WRT_REG_WORD(&reg->pcr, 0x2000);
631 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 478 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
632 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++) 479 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
633 fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++); 480 fw->risc_gp0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
634 481
635 WRT_REG_WORD(&reg->pcr, 0x2100); 482 WRT_REG_WORD(&reg->pcr, 0x2100);
636 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 483 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
637 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++) 484 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
638 fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++); 485 fw->risc_gp1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
639 486
640 WRT_REG_WORD(&reg->pcr, 0x2200); 487 WRT_REG_WORD(&reg->pcr, 0x2200);
641 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 488 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
642 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++) 489 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
643 fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++); 490 fw->risc_gp2_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
644 491
645 WRT_REG_WORD(&reg->pcr, 0x2300); 492 WRT_REG_WORD(&reg->pcr, 0x2300);
646 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 493 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
647 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++) 494 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
648 fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++); 495 fw->risc_gp3_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
649 496
650 WRT_REG_WORD(&reg->pcr, 0x2400); 497 WRT_REG_WORD(&reg->pcr, 0x2400);
651 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 498 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
652 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++) 499 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
653 fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++); 500 fw->risc_gp4_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
654 501
655 WRT_REG_WORD(&reg->pcr, 0x2500); 502 WRT_REG_WORD(&reg->pcr, 0x2500);
656 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 503 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
657 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++) 504 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
658 fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++); 505 fw->risc_gp5_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
659 506
660 WRT_REG_WORD(&reg->pcr, 0x2600); 507 WRT_REG_WORD(&reg->pcr, 0x2600);
661 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 508 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
662 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++) 509 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
663 fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++); 510 fw->risc_gp6_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
664 511
665 WRT_REG_WORD(&reg->pcr, 0x2700); 512 WRT_REG_WORD(&reg->pcr, 0x2700);
666 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 513 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
667 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++) 514 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
668 fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++); 515 fw->risc_gp7_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
669 516
670 WRT_REG_WORD(&reg->ctrl_status, 0x10); 517 WRT_REG_WORD(&reg->ctrl_status, 0x10);
671 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 518 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
672 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++) 519 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
673 fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); 520 fw->frame_buf_hdw_reg[cnt] =
521 htons(RD_REG_WORD(dmp_reg++));
674 522
675 WRT_REG_WORD(&reg->ctrl_status, 0x20); 523 WRT_REG_WORD(&reg->ctrl_status, 0x20);
676 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 524 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
677 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++) 525 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
678 fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++); 526 fw->fpm_b0_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
679 527
680 WRT_REG_WORD(&reg->ctrl_status, 0x30); 528 WRT_REG_WORD(&reg->ctrl_status, 0x30);
681 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 529 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
682 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++) 530 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
683 fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++); 531 fw->fpm_b1_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
684 532
685 /* Reset the ISP. */ 533 /* Reset the ISP. */
686 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET); 534 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
@@ -755,12 +603,15 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
755 603
756 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 604 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
757 rval = mb0 & MBS_MASK; 605 rval = mb0 & MBS_MASK;
758 fw->risc_ram[cnt] = mb2; 606 fw->risc_ram[cnt] = htons(mb2);
759 } else { 607 } else {
760 rval = QLA_FUNCTION_FAILED; 608 rval = QLA_FUNCTION_FAILED;
761 } 609 }
762 } 610 }
763 611
612 if (rval == QLA_SUCCESS)
613 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
614
764 if (rval != QLA_SUCCESS) { 615 if (rval != QLA_SUCCESS) {
765 qla_printk(KERN_WARNING, ha, 616 qla_printk(KERN_WARNING, ha,
766 "Failed to dump firmware (%x)!!!\n", rval); 617 "Failed to dump firmware (%x)!!!\n", rval);
@@ -778,179 +629,6 @@ qla2100_fw_dump_failed:
778 spin_unlock_irqrestore(&ha->hardware_lock, flags); 629 spin_unlock_irqrestore(&ha->hardware_lock, flags);
779} 630}
780 631
781/**
782 * qla2100_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
783 * @ha: HA context
784 */
785void
786qla2100_ascii_fw_dump(scsi_qla_host_t *ha)
787{
788 uint32_t cnt;
789 char *uiter;
790 char fw_info[30];
791 struct qla2100_fw_dump *fw;
792
793 uiter = ha->fw_dump_buffer;
794 fw = ha->fw_dump;
795
796 qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
797 ha->isp_ops.fw_version_str(ha, fw_info));
798
799 qla_uprintf(&uiter, "\n[==>BEG]\n");
800
801 qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
802
803 qla_uprintf(&uiter, "PBIU Registers:");
804 for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
805 if (cnt % 8 == 0) {
806 qla_uprintf(&uiter, "\n");
807 }
808 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
809 }
810
811 qla_uprintf(&uiter, "\n\nMailbox Registers:");
812 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
813 if (cnt % 8 == 0) {
814 qla_uprintf(&uiter, "\n");
815 }
816 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
817 }
818
819 qla_uprintf(&uiter, "\n\nDMA Registers:");
820 for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
821 if (cnt % 8 == 0) {
822 qla_uprintf(&uiter, "\n");
823 }
824 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
825 }
826
827 qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
828 for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
829 if (cnt % 8 == 0) {
830 qla_uprintf(&uiter, "\n");
831 }
832 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
833 }
834
835 qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
836 for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
837 if (cnt % 8 == 0) {
838 qla_uprintf(&uiter, "\n");
839 }
840 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
841 }
842
843 qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
844 for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
845 if (cnt % 8 == 0) {
846 qla_uprintf(&uiter, "\n");
847 }
848 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
849 }
850
851 qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
852 for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
853 if (cnt % 8 == 0) {
854 qla_uprintf(&uiter, "\n");
855 }
856 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
857 }
858
859 qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
860 for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
861 if (cnt % 8 == 0) {
862 qla_uprintf(&uiter, "\n");
863 }
864 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
865 }
866
867 qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
868 for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
869 if (cnt % 8 == 0) {
870 qla_uprintf(&uiter, "\n");
871 }
872 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
873 }
874
875 qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
876 for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
877 if (cnt % 8 == 0) {
878 qla_uprintf(&uiter, "\n");
879 }
880 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
881 }
882
883 qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
884 for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
885 if (cnt % 8 == 0) {
886 qla_uprintf(&uiter, "\n");
887 }
888 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
889 }
890
891 qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
892 for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
893 if (cnt % 8 == 0) {
894 qla_uprintf(&uiter, "\n");
895 }
896 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
897 }
898
899 qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
900 for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
901 if (cnt % 8 == 0) {
902 qla_uprintf(&uiter, "\n");
903 }
904 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
905 }
906
907 qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
908 for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
909 if (cnt % 8 == 0) {
910 qla_uprintf(&uiter, "\n");
911 }
912 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
913 }
914
915 qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
916 for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
917 if (cnt % 8 == 0) {
918 qla_uprintf(&uiter, "\n");
919 }
920 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
921 }
922
923 qla_uprintf(&uiter, "\n\nRISC SRAM:");
924 for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
925 if (cnt % 8 == 0) {
926 qla_uprintf(&uiter, "\n%04x: ", cnt + 0x1000);
927 }
928 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
929 }
930
931 qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
932
933 return;
934}
935
936static int
937qla_uprintf(char **uiter, char *fmt, ...)
938{
939 int iter, len;
940 char buf[128];
941 va_list args;
942
943 va_start(args, fmt);
944 len = vsprintf(buf, fmt, args);
945 va_end(args);
946
947 for (iter = 0; iter < len; iter++, *uiter += 1)
948 *uiter[0] = buf[iter];
949
950 return (len);
951}
952
953
954void 632void
955qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) 633qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
956{ 634{
@@ -967,6 +645,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
967 unsigned long flags; 645 unsigned long flags;
968 struct qla24xx_fw_dump *fw; 646 struct qla24xx_fw_dump *fw;
969 uint32_t ext_mem_cnt; 647 uint32_t ext_mem_cnt;
648 void *eft;
970 649
971 risc_address = ext_mem_cnt = 0; 650 risc_address = ext_mem_cnt = 0;
972 memset(mb, 0, sizeof(mb)); 651 memset(mb, 0, sizeof(mb));
@@ -987,10 +666,11 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
987 "request...\n", ha->fw_dump); 666 "request...\n", ha->fw_dump);
988 goto qla24xx_fw_dump_failed; 667 goto qla24xx_fw_dump_failed;
989 } 668 }
990 fw = ha->fw_dump; 669 fw = &ha->fw_dump->isp.isp24;
670 qla2xxx_prep_dump(ha, ha->fw_dump);
991 671
992 rval = QLA_SUCCESS; 672 rval = QLA_SUCCESS;
993 fw->host_status = RD_REG_DWORD(&reg->host_status); 673 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
994 674
995 /* Pause RISC. */ 675 /* Pause RISC. */
996 if ((RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0) { 676 if ((RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0) {
@@ -1012,7 +692,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1012 /* Host interface registers. */ 692 /* Host interface registers. */
1013 dmp_reg = (uint32_t __iomem *)(reg + 0); 693 dmp_reg = (uint32_t __iomem *)(reg + 0);
1014 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 694 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1015 fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++); 695 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1016 696
1017 /* Disable interrupts. */ 697 /* Disable interrupts. */
1018 WRT_REG_DWORD(&reg->ictrl, 0); 698 WRT_REG_DWORD(&reg->ictrl, 0);
@@ -1024,470 +704,471 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1024 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 704 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1025 WRT_REG_DWORD(dmp_reg, 0xB0000000); 705 WRT_REG_DWORD(dmp_reg, 0xB0000000);
1026 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 706 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1027 fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg); 707 fw->shadow_reg[0] = htonl(RD_REG_DWORD(dmp_reg));
1028 708
1029 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 709 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1030 WRT_REG_DWORD(dmp_reg, 0xB0100000); 710 WRT_REG_DWORD(dmp_reg, 0xB0100000);
1031 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 711 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1032 fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg); 712 fw->shadow_reg[1] = htonl(RD_REG_DWORD(dmp_reg));
1033 713
1034 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 714 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1035 WRT_REG_DWORD(dmp_reg, 0xB0200000); 715 WRT_REG_DWORD(dmp_reg, 0xB0200000);
1036 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 716 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1037 fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg); 717 fw->shadow_reg[2] = htonl(RD_REG_DWORD(dmp_reg));
1038 718
1039 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 719 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1040 WRT_REG_DWORD(dmp_reg, 0xB0300000); 720 WRT_REG_DWORD(dmp_reg, 0xB0300000);
1041 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 721 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1042 fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg); 722 fw->shadow_reg[3] = htonl(RD_REG_DWORD(dmp_reg));
1043 723
1044 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 724 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1045 WRT_REG_DWORD(dmp_reg, 0xB0400000); 725 WRT_REG_DWORD(dmp_reg, 0xB0400000);
1046 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 726 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1047 fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg); 727 fw->shadow_reg[4] = htonl(RD_REG_DWORD(dmp_reg));
1048 728
1049 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 729 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1050 WRT_REG_DWORD(dmp_reg, 0xB0500000); 730 WRT_REG_DWORD(dmp_reg, 0xB0500000);
1051 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 731 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1052 fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg); 732 fw->shadow_reg[5] = htonl(RD_REG_DWORD(dmp_reg));
1053 733
1054 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 734 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1055 WRT_REG_DWORD(dmp_reg, 0xB0600000); 735 WRT_REG_DWORD(dmp_reg, 0xB0600000);
1056 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 736 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1057 fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg); 737 fw->shadow_reg[6] = htonl(RD_REG_DWORD(dmp_reg));
1058 738
1059 /* Mailbox registers. */ 739 /* Mailbox registers. */
1060 mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 740 mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
1061 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 741 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1062 fw->mailbox_reg[cnt] = RD_REG_WORD(mbx_reg++); 742 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1063 743
1064 /* Transfer sequence registers. */ 744 /* Transfer sequence registers. */
1065 iter_reg = fw->xseq_gp_reg; 745 iter_reg = fw->xseq_gp_reg;
1066 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00); 746 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00);
1067 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 747 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1068 for (cnt = 0; cnt < 16; cnt++) 748 for (cnt = 0; cnt < 16; cnt++)
1069 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 749 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1070 750
1071 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10); 751 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10);
1072 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 752 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1073 for (cnt = 0; cnt < 16; cnt++) 753 for (cnt = 0; cnt < 16; cnt++)
1074 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 754 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1075 755
1076 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20); 756 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20);
1077 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 757 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1078 for (cnt = 0; cnt < 16; cnt++) 758 for (cnt = 0; cnt < 16; cnt++)
1079 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 759 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1080 760
1081 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30); 761 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30);
1082 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 762 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1083 for (cnt = 0; cnt < 16; cnt++) 763 for (cnt = 0; cnt < 16; cnt++)
1084 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 764 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1085 765
1086 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40); 766 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40);
1087 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 767 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1088 for (cnt = 0; cnt < 16; cnt++) 768 for (cnt = 0; cnt < 16; cnt++)
1089 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 769 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1090 770
1091 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50); 771 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50);
1092 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 772 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1093 for (cnt = 0; cnt < 16; cnt++) 773 for (cnt = 0; cnt < 16; cnt++)
1094 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 774 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1095 775
1096 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60); 776 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60);
1097 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 777 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1098 for (cnt = 0; cnt < 16; cnt++) 778 for (cnt = 0; cnt < 16; cnt++)
1099 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 779 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1100 780
1101 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70); 781 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70);
1102 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 782 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1103 for (cnt = 0; cnt < 16; cnt++) 783 for (cnt = 0; cnt < 16; cnt++)
1104 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 784 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1105 785
1106 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0); 786 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0);
1107 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 787 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1108 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) 788 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++)
1109 fw->xseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++); 789 fw->xseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1110 790
1111 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0); 791 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0);
1112 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 792 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1113 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) 793 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++)
1114 fw->xseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++); 794 fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1115 795
1116 /* Receive sequence registers. */ 796 /* Receive sequence registers. */
1117 iter_reg = fw->rseq_gp_reg; 797 iter_reg = fw->rseq_gp_reg;
1118 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00); 798 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00);
1119 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 799 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1120 for (cnt = 0; cnt < 16; cnt++) 800 for (cnt = 0; cnt < 16; cnt++)
1121 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 801 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1122 802
1123 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10); 803 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10);
1124 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 804 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1125 for (cnt = 0; cnt < 16; cnt++) 805 for (cnt = 0; cnt < 16; cnt++)
1126 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 806 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1127 807
1128 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20); 808 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20);
1129 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 809 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1130 for (cnt = 0; cnt < 16; cnt++) 810 for (cnt = 0; cnt < 16; cnt++)
1131 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 811 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1132 812
1133 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30); 813 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30);
1134 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 814 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1135 for (cnt = 0; cnt < 16; cnt++) 815 for (cnt = 0; cnt < 16; cnt++)
1136 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 816 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1137 817
1138 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40); 818 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40);
1139 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 819 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1140 for (cnt = 0; cnt < 16; cnt++) 820 for (cnt = 0; cnt < 16; cnt++)
1141 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 821 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1142 822
1143 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50); 823 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50);
1144 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 824 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1145 for (cnt = 0; cnt < 16; cnt++) 825 for (cnt = 0; cnt < 16; cnt++)
1146 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 826 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1147 827
1148 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60); 828 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60);
1149 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 829 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1150 for (cnt = 0; cnt < 16; cnt++) 830 for (cnt = 0; cnt < 16; cnt++)
1151 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 831 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1152 832
1153 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70); 833 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70);
1154 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 834 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1155 for (cnt = 0; cnt < 16; cnt++) 835 for (cnt = 0; cnt < 16; cnt++)
1156 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 836 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1157 837
1158 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0); 838 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0);
1159 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 839 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1160 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) 840 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++)
1161 fw->rseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++); 841 fw->rseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1162 842
1163 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0); 843 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0);
1164 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 844 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1165 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) 845 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++)
1166 fw->rseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++); 846 fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1167 847
1168 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0); 848 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0);
1169 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 849 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1170 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) 850 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++)
1171 fw->rseq_2_reg[cnt] = RD_REG_DWORD(dmp_reg++); 851 fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1172 852
1173 /* Command DMA registers. */ 853 /* Command DMA registers. */
1174 WRT_REG_DWORD(&reg->iobase_addr, 0x7100); 854 WRT_REG_DWORD(&reg->iobase_addr, 0x7100);
1175 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 855 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1176 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) 856 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++)
1177 fw->cmd_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++); 857 fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1178 858
1179 /* Queues. */ 859 /* Queues. */
1180 iter_reg = fw->req0_dma_reg; 860 iter_reg = fw->req0_dma_reg;
1181 WRT_REG_DWORD(&reg->iobase_addr, 0x7200); 861 WRT_REG_DWORD(&reg->iobase_addr, 0x7200);
1182 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 862 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1183 for (cnt = 0; cnt < 8; cnt++) 863 for (cnt = 0; cnt < 8; cnt++)
1184 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 864 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1185 865
1186 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 866 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1187 for (cnt = 0; cnt < 7; cnt++) 867 for (cnt = 0; cnt < 7; cnt++)
1188 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 868 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1189 869
1190 iter_reg = fw->resp0_dma_reg; 870 iter_reg = fw->resp0_dma_reg;
1191 WRT_REG_DWORD(&reg->iobase_addr, 0x7300); 871 WRT_REG_DWORD(&reg->iobase_addr, 0x7300);
1192 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 872 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1193 for (cnt = 0; cnt < 8; cnt++) 873 for (cnt = 0; cnt < 8; cnt++)
1194 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 874 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1195 875
1196 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 876 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1197 for (cnt = 0; cnt < 7; cnt++) 877 for (cnt = 0; cnt < 7; cnt++)
1198 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 878 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1199 879
1200 iter_reg = fw->req1_dma_reg; 880 iter_reg = fw->req1_dma_reg;
1201 WRT_REG_DWORD(&reg->iobase_addr, 0x7400); 881 WRT_REG_DWORD(&reg->iobase_addr, 0x7400);
1202 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 882 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1203 for (cnt = 0; cnt < 8; cnt++) 883 for (cnt = 0; cnt < 8; cnt++)
1204 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 884 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1205 885
1206 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 886 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1207 for (cnt = 0; cnt < 7; cnt++) 887 for (cnt = 0; cnt < 7; cnt++)
1208 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 888 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1209 889
1210 /* Transmit DMA registers. */ 890 /* Transmit DMA registers. */
1211 iter_reg = fw->xmt0_dma_reg; 891 iter_reg = fw->xmt0_dma_reg;
1212 WRT_REG_DWORD(&reg->iobase_addr, 0x7600); 892 WRT_REG_DWORD(&reg->iobase_addr, 0x7600);
1213 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 893 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1214 for (cnt = 0; cnt < 16; cnt++) 894 for (cnt = 0; cnt < 16; cnt++)
1215 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 895 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1216 896
1217 WRT_REG_DWORD(&reg->iobase_addr, 0x7610); 897 WRT_REG_DWORD(&reg->iobase_addr, 0x7610);
1218 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 898 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1219 for (cnt = 0; cnt < 16; cnt++) 899 for (cnt = 0; cnt < 16; cnt++)
1220 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 900 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1221 901
1222 iter_reg = fw->xmt1_dma_reg; 902 iter_reg = fw->xmt1_dma_reg;
1223 WRT_REG_DWORD(&reg->iobase_addr, 0x7620); 903 WRT_REG_DWORD(&reg->iobase_addr, 0x7620);
1224 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 904 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1225 for (cnt = 0; cnt < 16; cnt++) 905 for (cnt = 0; cnt < 16; cnt++)
1226 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 906 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1227 907
1228 WRT_REG_DWORD(&reg->iobase_addr, 0x7630); 908 WRT_REG_DWORD(&reg->iobase_addr, 0x7630);
1229 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 909 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1230 for (cnt = 0; cnt < 16; cnt++) 910 for (cnt = 0; cnt < 16; cnt++)
1231 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 911 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1232 912
1233 iter_reg = fw->xmt2_dma_reg; 913 iter_reg = fw->xmt2_dma_reg;
1234 WRT_REG_DWORD(&reg->iobase_addr, 0x7640); 914 WRT_REG_DWORD(&reg->iobase_addr, 0x7640);
1235 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 915 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1236 for (cnt = 0; cnt < 16; cnt++) 916 for (cnt = 0; cnt < 16; cnt++)
1237 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 917 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1238 918
1239 WRT_REG_DWORD(&reg->iobase_addr, 0x7650); 919 WRT_REG_DWORD(&reg->iobase_addr, 0x7650);
1240 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 920 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1241 for (cnt = 0; cnt < 16; cnt++) 921 for (cnt = 0; cnt < 16; cnt++)
1242 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 922 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1243 923
1244 iter_reg = fw->xmt3_dma_reg; 924 iter_reg = fw->xmt3_dma_reg;
1245 WRT_REG_DWORD(&reg->iobase_addr, 0x7660); 925 WRT_REG_DWORD(&reg->iobase_addr, 0x7660);
1246 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 926 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1247 for (cnt = 0; cnt < 16; cnt++) 927 for (cnt = 0; cnt < 16; cnt++)
1248 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 928 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1249 929
1250 WRT_REG_DWORD(&reg->iobase_addr, 0x7670); 930 WRT_REG_DWORD(&reg->iobase_addr, 0x7670);
1251 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 931 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1252 for (cnt = 0; cnt < 16; cnt++) 932 for (cnt = 0; cnt < 16; cnt++)
1253 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 933 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1254 934
1255 iter_reg = fw->xmt4_dma_reg; 935 iter_reg = fw->xmt4_dma_reg;
1256 WRT_REG_DWORD(&reg->iobase_addr, 0x7680); 936 WRT_REG_DWORD(&reg->iobase_addr, 0x7680);
1257 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 937 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1258 for (cnt = 0; cnt < 16; cnt++) 938 for (cnt = 0; cnt < 16; cnt++)
1259 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 939 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1260 940
1261 WRT_REG_DWORD(&reg->iobase_addr, 0x7690); 941 WRT_REG_DWORD(&reg->iobase_addr, 0x7690);
1262 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 942 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1263 for (cnt = 0; cnt < 16; cnt++) 943 for (cnt = 0; cnt < 16; cnt++)
1264 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 944 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1265 945
1266 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0); 946 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0);
1267 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 947 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1268 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) 948 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
1269 fw->xmt_data_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++); 949 fw->xmt_data_dma_reg[cnt] =
950 htonl(RD_REG_DWORD(dmp_reg++));
1270 951
1271 /* Receive DMA registers. */ 952 /* Receive DMA registers. */
1272 iter_reg = fw->rcvt0_data_dma_reg; 953 iter_reg = fw->rcvt0_data_dma_reg;
1273 WRT_REG_DWORD(&reg->iobase_addr, 0x7700); 954 WRT_REG_DWORD(&reg->iobase_addr, 0x7700);
1274 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 955 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1275 for (cnt = 0; cnt < 16; cnt++) 956 for (cnt = 0; cnt < 16; cnt++)
1276 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 957 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1277 958
1278 WRT_REG_DWORD(&reg->iobase_addr, 0x7710); 959 WRT_REG_DWORD(&reg->iobase_addr, 0x7710);
1279 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 960 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1280 for (cnt = 0; cnt < 16; cnt++) 961 for (cnt = 0; cnt < 16; cnt++)
1281 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 962 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1282 963
1283 iter_reg = fw->rcvt1_data_dma_reg; 964 iter_reg = fw->rcvt1_data_dma_reg;
1284 WRT_REG_DWORD(&reg->iobase_addr, 0x7720); 965 WRT_REG_DWORD(&reg->iobase_addr, 0x7720);
1285 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 966 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1286 for (cnt = 0; cnt < 16; cnt++) 967 for (cnt = 0; cnt < 16; cnt++)
1287 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 968 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1288 969
1289 WRT_REG_DWORD(&reg->iobase_addr, 0x7730); 970 WRT_REG_DWORD(&reg->iobase_addr, 0x7730);
1290 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 971 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1291 for (cnt = 0; cnt < 16; cnt++) 972 for (cnt = 0; cnt < 16; cnt++)
1292 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 973 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1293 974
1294 /* RISC registers. */ 975 /* RISC registers. */
1295 iter_reg = fw->risc_gp_reg; 976 iter_reg = fw->risc_gp_reg;
1296 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00); 977 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00);
1297 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 978 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1298 for (cnt = 0; cnt < 16; cnt++) 979 for (cnt = 0; cnt < 16; cnt++)
1299 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 980 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1300 981
1301 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10); 982 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10);
1302 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 983 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1303 for (cnt = 0; cnt < 16; cnt++) 984 for (cnt = 0; cnt < 16; cnt++)
1304 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 985 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1305 986
1306 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20); 987 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20);
1307 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 988 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1308 for (cnt = 0; cnt < 16; cnt++) 989 for (cnt = 0; cnt < 16; cnt++)
1309 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 990 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1310 991
1311 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30); 992 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30);
1312 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 993 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1313 for (cnt = 0; cnt < 16; cnt++) 994 for (cnt = 0; cnt < 16; cnt++)
1314 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 995 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1315 996
1316 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40); 997 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40);
1317 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 998 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1318 for (cnt = 0; cnt < 16; cnt++) 999 for (cnt = 0; cnt < 16; cnt++)
1319 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1000 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1320 1001
1321 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50); 1002 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50);
1322 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1003 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1323 for (cnt = 0; cnt < 16; cnt++) 1004 for (cnt = 0; cnt < 16; cnt++)
1324 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1005 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1325 1006
1326 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60); 1007 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60);
1327 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1008 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1328 for (cnt = 0; cnt < 16; cnt++) 1009 for (cnt = 0; cnt < 16; cnt++)
1329 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1010 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1330 1011
1331 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 1012 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1332 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1013 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1333 for (cnt = 0; cnt < 16; cnt++) 1014 for (cnt = 0; cnt < 16; cnt++)
1334 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1015 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1335 1016
1336 /* Local memory controller registers. */ 1017 /* Local memory controller registers. */
1337 iter_reg = fw->lmc_reg; 1018 iter_reg = fw->lmc_reg;
1338 WRT_REG_DWORD(&reg->iobase_addr, 0x3000); 1019 WRT_REG_DWORD(&reg->iobase_addr, 0x3000);
1339 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1020 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1340 for (cnt = 0; cnt < 16; cnt++) 1021 for (cnt = 0; cnt < 16; cnt++)
1341 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1022 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1342 1023
1343 WRT_REG_DWORD(&reg->iobase_addr, 0x3010); 1024 WRT_REG_DWORD(&reg->iobase_addr, 0x3010);
1344 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1025 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1345 for (cnt = 0; cnt < 16; cnt++) 1026 for (cnt = 0; cnt < 16; cnt++)
1346 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1027 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1347 1028
1348 WRT_REG_DWORD(&reg->iobase_addr, 0x3020); 1029 WRT_REG_DWORD(&reg->iobase_addr, 0x3020);
1349 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1030 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1350 for (cnt = 0; cnt < 16; cnt++) 1031 for (cnt = 0; cnt < 16; cnt++)
1351 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1032 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1352 1033
1353 WRT_REG_DWORD(&reg->iobase_addr, 0x3030); 1034 WRT_REG_DWORD(&reg->iobase_addr, 0x3030);
1354 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1035 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1355 for (cnt = 0; cnt < 16; cnt++) 1036 for (cnt = 0; cnt < 16; cnt++)
1356 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1037 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1357 1038
1358 WRT_REG_DWORD(&reg->iobase_addr, 0x3040); 1039 WRT_REG_DWORD(&reg->iobase_addr, 0x3040);
1359 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1040 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1360 for (cnt = 0; cnt < 16; cnt++) 1041 for (cnt = 0; cnt < 16; cnt++)
1361 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1042 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1362 1043
1363 WRT_REG_DWORD(&reg->iobase_addr, 0x3050); 1044 WRT_REG_DWORD(&reg->iobase_addr, 0x3050);
1364 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1045 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1365 for (cnt = 0; cnt < 16; cnt++) 1046 for (cnt = 0; cnt < 16; cnt++)
1366 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1047 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1367 1048
1368 WRT_REG_DWORD(&reg->iobase_addr, 0x3060); 1049 WRT_REG_DWORD(&reg->iobase_addr, 0x3060);
1369 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1050 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1370 for (cnt = 0; cnt < 16; cnt++) 1051 for (cnt = 0; cnt < 16; cnt++)
1371 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1052 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1372 1053
1373 /* Fibre Protocol Module registers. */ 1054 /* Fibre Protocol Module registers. */
1374 iter_reg = fw->fpm_hdw_reg; 1055 iter_reg = fw->fpm_hdw_reg;
1375 WRT_REG_DWORD(&reg->iobase_addr, 0x4000); 1056 WRT_REG_DWORD(&reg->iobase_addr, 0x4000);
1376 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1057 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1377 for (cnt = 0; cnt < 16; cnt++) 1058 for (cnt = 0; cnt < 16; cnt++)
1378 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1059 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1379 1060
1380 WRT_REG_DWORD(&reg->iobase_addr, 0x4010); 1061 WRT_REG_DWORD(&reg->iobase_addr, 0x4010);
1381 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1062 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1382 for (cnt = 0; cnt < 16; cnt++) 1063 for (cnt = 0; cnt < 16; cnt++)
1383 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1064 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1384 1065
1385 WRT_REG_DWORD(&reg->iobase_addr, 0x4020); 1066 WRT_REG_DWORD(&reg->iobase_addr, 0x4020);
1386 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1067 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1387 for (cnt = 0; cnt < 16; cnt++) 1068 for (cnt = 0; cnt < 16; cnt++)
1388 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1069 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1389 1070
1390 WRT_REG_DWORD(&reg->iobase_addr, 0x4030); 1071 WRT_REG_DWORD(&reg->iobase_addr, 0x4030);
1391 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1072 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1392 for (cnt = 0; cnt < 16; cnt++) 1073 for (cnt = 0; cnt < 16; cnt++)
1393 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1074 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1394 1075
1395 WRT_REG_DWORD(&reg->iobase_addr, 0x4040); 1076 WRT_REG_DWORD(&reg->iobase_addr, 0x4040);
1396 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1077 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1397 for (cnt = 0; cnt < 16; cnt++) 1078 for (cnt = 0; cnt < 16; cnt++)
1398 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1079 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1399 1080
1400 WRT_REG_DWORD(&reg->iobase_addr, 0x4050); 1081 WRT_REG_DWORD(&reg->iobase_addr, 0x4050);
1401 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1082 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1402 for (cnt = 0; cnt < 16; cnt++) 1083 for (cnt = 0; cnt < 16; cnt++)
1403 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1084 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1404 1085
1405 WRT_REG_DWORD(&reg->iobase_addr, 0x4060); 1086 WRT_REG_DWORD(&reg->iobase_addr, 0x4060);
1406 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1087 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1407 for (cnt = 0; cnt < 16; cnt++) 1088 for (cnt = 0; cnt < 16; cnt++)
1408 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1089 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1409 1090
1410 WRT_REG_DWORD(&reg->iobase_addr, 0x4070); 1091 WRT_REG_DWORD(&reg->iobase_addr, 0x4070);
1411 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1092 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1412 for (cnt = 0; cnt < 16; cnt++) 1093 for (cnt = 0; cnt < 16; cnt++)
1413 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1094 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1414 1095
1415 WRT_REG_DWORD(&reg->iobase_addr, 0x4080); 1096 WRT_REG_DWORD(&reg->iobase_addr, 0x4080);
1416 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1097 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1417 for (cnt = 0; cnt < 16; cnt++) 1098 for (cnt = 0; cnt < 16; cnt++)
1418 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1099 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1419 1100
1420 WRT_REG_DWORD(&reg->iobase_addr, 0x4090); 1101 WRT_REG_DWORD(&reg->iobase_addr, 0x4090);
1421 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1102 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1422 for (cnt = 0; cnt < 16; cnt++) 1103 for (cnt = 0; cnt < 16; cnt++)
1423 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1104 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1424 1105
1425 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0); 1106 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0);
1426 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1107 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1427 for (cnt = 0; cnt < 16; cnt++) 1108 for (cnt = 0; cnt < 16; cnt++)
1428 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1109 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1429 1110
1430 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0); 1111 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0);
1431 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1112 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1432 for (cnt = 0; cnt < 16; cnt++) 1113 for (cnt = 0; cnt < 16; cnt++)
1433 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1114 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1434 1115
1435 /* Frame Buffer registers. */ 1116 /* Frame Buffer registers. */
1436 iter_reg = fw->fb_hdw_reg; 1117 iter_reg = fw->fb_hdw_reg;
1437 WRT_REG_DWORD(&reg->iobase_addr, 0x6000); 1118 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1438 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1119 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1439 for (cnt = 0; cnt < 16; cnt++) 1120 for (cnt = 0; cnt < 16; cnt++)
1440 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1121 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1441 1122
1442 WRT_REG_DWORD(&reg->iobase_addr, 0x6010); 1123 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1443 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1124 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1444 for (cnt = 0; cnt < 16; cnt++) 1125 for (cnt = 0; cnt < 16; cnt++)
1445 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1126 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1446 1127
1447 WRT_REG_DWORD(&reg->iobase_addr, 0x6020); 1128 WRT_REG_DWORD(&reg->iobase_addr, 0x6020);
1448 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1129 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1449 for (cnt = 0; cnt < 16; cnt++) 1130 for (cnt = 0; cnt < 16; cnt++)
1450 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1131 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1451 1132
1452 WRT_REG_DWORD(&reg->iobase_addr, 0x6030); 1133 WRT_REG_DWORD(&reg->iobase_addr, 0x6030);
1453 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1134 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1454 for (cnt = 0; cnt < 16; cnt++) 1135 for (cnt = 0; cnt < 16; cnt++)
1455 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1136 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1456 1137
1457 WRT_REG_DWORD(&reg->iobase_addr, 0x6040); 1138 WRT_REG_DWORD(&reg->iobase_addr, 0x6040);
1458 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1139 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1459 for (cnt = 0; cnt < 16; cnt++) 1140 for (cnt = 0; cnt < 16; cnt++)
1460 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1141 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1461 1142
1462 WRT_REG_DWORD(&reg->iobase_addr, 0x6100); 1143 WRT_REG_DWORD(&reg->iobase_addr, 0x6100);
1463 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1144 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1464 for (cnt = 0; cnt < 16; cnt++) 1145 for (cnt = 0; cnt < 16; cnt++)
1465 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1146 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1466 1147
1467 WRT_REG_DWORD(&reg->iobase_addr, 0x6130); 1148 WRT_REG_DWORD(&reg->iobase_addr, 0x6130);
1468 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1149 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1469 for (cnt = 0; cnt < 16; cnt++) 1150 for (cnt = 0; cnt < 16; cnt++)
1470 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1151 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1471 1152
1472 WRT_REG_DWORD(&reg->iobase_addr, 0x6150); 1153 WRT_REG_DWORD(&reg->iobase_addr, 0x6150);
1473 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1154 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1474 for (cnt = 0; cnt < 16; cnt++) 1155 for (cnt = 0; cnt < 16; cnt++)
1475 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1156 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1476 1157
1477 WRT_REG_DWORD(&reg->iobase_addr, 0x6170); 1158 WRT_REG_DWORD(&reg->iobase_addr, 0x6170);
1478 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1159 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1479 for (cnt = 0; cnt < 16; cnt++) 1160 for (cnt = 0; cnt < 16; cnt++)
1480 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1161 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1481 1162
1482 WRT_REG_DWORD(&reg->iobase_addr, 0x6190); 1163 WRT_REG_DWORD(&reg->iobase_addr, 0x6190);
1483 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1164 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1484 for (cnt = 0; cnt < 16; cnt++) 1165 for (cnt = 0; cnt < 16; cnt++)
1485 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1166 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1486 1167
1487 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0); 1168 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0);
1488 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1169 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1489 for (cnt = 0; cnt < 16; cnt++) 1170 for (cnt = 0; cnt < 16; cnt++)
1490 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1171 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1491 1172
1492 /* Reset RISC. */ 1173 /* Reset RISC. */
1493 WRT_REG_DWORD(&reg->ctrl_status, 1174 WRT_REG_DWORD(&reg->ctrl_status,
@@ -1577,7 +1258,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1577 1258
1578 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 1259 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1579 rval = mb[0] & MBS_MASK; 1260 rval = mb[0] & MBS_MASK;
1580 fw->code_ram[cnt] = (mb[3] << 16) | mb[2]; 1261 fw->code_ram[cnt] = htonl((mb[3] << 16) | mb[2]);
1581 } else { 1262 } else {
1582 rval = QLA_FUNCTION_FAILED; 1263 rval = QLA_FUNCTION_FAILED;
1583 } 1264 }
@@ -1627,12 +1308,18 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
1627 1308
1628 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 1309 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1629 rval = mb[0] & MBS_MASK; 1310 rval = mb[0] & MBS_MASK;
1630 fw->ext_mem[cnt] = (mb[3] << 16) | mb[2]; 1311 fw->ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]);
1631 } else { 1312 } else {
1632 rval = QLA_FUNCTION_FAILED; 1313 rval = QLA_FUNCTION_FAILED;
1633 } 1314 }
1634 } 1315 }
1635 1316
1317 if (rval == QLA_SUCCESS) {
1318 eft = qla2xxx_copy_queues(ha, &fw->ext_mem[cnt]);
1319 if (ha->eft)
1320 memcpy(eft, ha->eft, ntohl(ha->fw_dump->eft_size));
1321 }
1322
1636 if (rval != QLA_SUCCESS) { 1323 if (rval != QLA_SUCCESS) {
1637 qla_printk(KERN_WARNING, ha, 1324 qla_printk(KERN_WARNING, ha,
1638 "Failed to dump firmware (%x)!!!\n", rval); 1325 "Failed to dump firmware (%x)!!!\n", rval);
@@ -1650,252 +1337,6 @@ qla24xx_fw_dump_failed:
1650 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1337 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1651} 1338}
1652 1339
1653void
1654qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
1655{
1656 uint32_t cnt;
1657 char *uiter;
1658 struct qla24xx_fw_dump *fw;
1659 uint32_t ext_mem_cnt;
1660
1661 uiter = ha->fw_dump_buffer;
1662 fw = ha->fw_dump;
1663
1664 qla_uprintf(&uiter, "ISP FW Version %d.%02d.%02d Attributes %04x\n",
1665 ha->fw_major_version, ha->fw_minor_version,
1666 ha->fw_subminor_version, ha->fw_attributes);
1667
1668 qla_uprintf(&uiter, "\nR2H Status Register\n%04x\n", fw->host_status);
1669
1670 qla_uprintf(&uiter, "\nHost Interface Registers");
1671 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) {
1672 if (cnt % 8 == 0)
1673 qla_uprintf(&uiter, "\n");
1674
1675 qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]);
1676 }
1677
1678 qla_uprintf(&uiter, "\n\nShadow Registers");
1679 for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) {
1680 if (cnt % 8 == 0)
1681 qla_uprintf(&uiter, "\n");
1682
1683 qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]);
1684 }
1685
1686 qla_uprintf(&uiter, "\n\nMailbox Registers");
1687 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) {
1688 if (cnt % 8 == 0)
1689 qla_uprintf(&uiter, "\n");
1690
1691 qla_uprintf(&uiter, "%08x ", fw->mailbox_reg[cnt]);
1692 }
1693
1694 qla_uprintf(&uiter, "\n\nXSEQ GP Registers");
1695 for (cnt = 0; cnt < sizeof(fw->xseq_gp_reg) / 4; cnt++) {
1696 if (cnt % 8 == 0)
1697 qla_uprintf(&uiter, "\n");
1698
1699 qla_uprintf(&uiter, "%08x ", fw->xseq_gp_reg[cnt]);
1700 }
1701
1702 qla_uprintf(&uiter, "\n\nXSEQ-0 Registers");
1703 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) {
1704 if (cnt % 8 == 0)
1705 qla_uprintf(&uiter, "\n");
1706
1707 qla_uprintf(&uiter, "%08x ", fw->xseq_0_reg[cnt]);
1708 }
1709
1710 qla_uprintf(&uiter, "\n\nXSEQ-1 Registers");
1711 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) {
1712 if (cnt % 8 == 0)
1713 qla_uprintf(&uiter, "\n");
1714
1715 qla_uprintf(&uiter, "%08x ", fw->xseq_1_reg[cnt]);
1716 }
1717
1718 qla_uprintf(&uiter, "\n\nRSEQ GP Registers");
1719 for (cnt = 0; cnt < sizeof(fw->rseq_gp_reg) / 4; cnt++) {
1720 if (cnt % 8 == 0)
1721 qla_uprintf(&uiter, "\n");
1722
1723 qla_uprintf(&uiter, "%08x ", fw->rseq_gp_reg[cnt]);
1724 }
1725
1726 qla_uprintf(&uiter, "\n\nRSEQ-0 Registers");
1727 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) {
1728 if (cnt % 8 == 0)
1729 qla_uprintf(&uiter, "\n");
1730
1731 qla_uprintf(&uiter, "%08x ", fw->rseq_0_reg[cnt]);
1732 }
1733
1734 qla_uprintf(&uiter, "\n\nRSEQ-1 Registers");
1735 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) {
1736 if (cnt % 8 == 0)
1737 qla_uprintf(&uiter, "\n");
1738
1739 qla_uprintf(&uiter, "%08x ", fw->rseq_1_reg[cnt]);
1740 }
1741
1742 qla_uprintf(&uiter, "\n\nRSEQ-2 Registers");
1743 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) {
1744 if (cnt % 8 == 0)
1745 qla_uprintf(&uiter, "\n");
1746
1747 qla_uprintf(&uiter, "%08x ", fw->rseq_2_reg[cnt]);
1748 }
1749
1750 qla_uprintf(&uiter, "\n\nCommand DMA Registers");
1751 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) {
1752 if (cnt % 8 == 0)
1753 qla_uprintf(&uiter, "\n");
1754
1755 qla_uprintf(&uiter, "%08x ", fw->cmd_dma_reg[cnt]);
1756 }
1757
1758 qla_uprintf(&uiter, "\n\nRequest0 Queue DMA Channel Registers");
1759 for (cnt = 0; cnt < sizeof(fw->req0_dma_reg) / 4; cnt++) {
1760 if (cnt % 8 == 0)
1761 qla_uprintf(&uiter, "\n");
1762
1763 qla_uprintf(&uiter, "%08x ", fw->req0_dma_reg[cnt]);
1764 }
1765
1766 qla_uprintf(&uiter, "\n\nResponse0 Queue DMA Channel Registers");
1767 for (cnt = 0; cnt < sizeof(fw->resp0_dma_reg) / 4; cnt++) {
1768 if (cnt % 8 == 0)
1769 qla_uprintf(&uiter, "\n");
1770
1771 qla_uprintf(&uiter, "%08x ", fw->resp0_dma_reg[cnt]);
1772 }
1773
1774 qla_uprintf(&uiter, "\n\nRequest1 Queue DMA Channel Registers");
1775 for (cnt = 0; cnt < sizeof(fw->req1_dma_reg) / 4; cnt++) {
1776 if (cnt % 8 == 0)
1777 qla_uprintf(&uiter, "\n");
1778
1779 qla_uprintf(&uiter, "%08x ", fw->req1_dma_reg[cnt]);
1780 }
1781
1782 qla_uprintf(&uiter, "\n\nXMT0 Data DMA Registers");
1783 for (cnt = 0; cnt < sizeof(fw->xmt0_dma_reg) / 4; cnt++) {
1784 if (cnt % 8 == 0)
1785 qla_uprintf(&uiter, "\n");
1786
1787 qla_uprintf(&uiter, "%08x ", fw->xmt0_dma_reg[cnt]);
1788 }
1789
1790 qla_uprintf(&uiter, "\n\nXMT1 Data DMA Registers");
1791 for (cnt = 0; cnt < sizeof(fw->xmt1_dma_reg) / 4; cnt++) {
1792 if (cnt % 8 == 0)
1793 qla_uprintf(&uiter, "\n");
1794
1795 qla_uprintf(&uiter, "%08x ", fw->xmt1_dma_reg[cnt]);
1796 }
1797
1798 qla_uprintf(&uiter, "\n\nXMT2 Data DMA Registers");
1799 for (cnt = 0; cnt < sizeof(fw->xmt2_dma_reg) / 4; cnt++) {
1800 if (cnt % 8 == 0)
1801 qla_uprintf(&uiter, "\n");
1802
1803 qla_uprintf(&uiter, "%08x ", fw->xmt2_dma_reg[cnt]);
1804 }
1805
1806 qla_uprintf(&uiter, "\n\nXMT3 Data DMA Registers");
1807 for (cnt = 0; cnt < sizeof(fw->xmt3_dma_reg) / 4; cnt++) {
1808 if (cnt % 8 == 0)
1809 qla_uprintf(&uiter, "\n");
1810
1811 qla_uprintf(&uiter, "%08x ", fw->xmt3_dma_reg[cnt]);
1812 }
1813
1814 qla_uprintf(&uiter, "\n\nXMT4 Data DMA Registers");
1815 for (cnt = 0; cnt < sizeof(fw->xmt4_dma_reg) / 4; cnt++) {
1816 if (cnt % 8 == 0)
1817 qla_uprintf(&uiter, "\n");
1818
1819 qla_uprintf(&uiter, "%08x ", fw->xmt4_dma_reg[cnt]);
1820 }
1821
1822 qla_uprintf(&uiter, "\n\nXMT Data DMA Common Registers");
1823 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) {
1824 if (cnt % 8 == 0)
1825 qla_uprintf(&uiter, "\n");
1826
1827 qla_uprintf(&uiter, "%08x ", fw->xmt_data_dma_reg[cnt]);
1828 }
1829
1830 qla_uprintf(&uiter, "\n\nRCV Thread 0 Data DMA Registers");
1831 for (cnt = 0; cnt < sizeof(fw->rcvt0_data_dma_reg) / 4; cnt++) {
1832 if (cnt % 8 == 0)
1833 qla_uprintf(&uiter, "\n");
1834
1835 qla_uprintf(&uiter, "%08x ", fw->rcvt0_data_dma_reg[cnt]);
1836 }
1837
1838 qla_uprintf(&uiter, "\n\nRCV Thread 1 Data DMA Registers");
1839 for (cnt = 0; cnt < sizeof(fw->rcvt1_data_dma_reg) / 4; cnt++) {
1840 if (cnt % 8 == 0)
1841 qla_uprintf(&uiter, "\n");
1842
1843 qla_uprintf(&uiter, "%08x ", fw->rcvt1_data_dma_reg[cnt]);
1844 }
1845
1846 qla_uprintf(&uiter, "\n\nRISC GP Registers");
1847 for (cnt = 0; cnt < sizeof(fw->risc_gp_reg) / 4; cnt++) {
1848 if (cnt % 8 == 0)
1849 qla_uprintf(&uiter, "\n");
1850
1851 qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]);
1852 }
1853
1854 qla_uprintf(&uiter, "\n\nLMC Registers");
1855 for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) {
1856 if (cnt % 8 == 0)
1857 qla_uprintf(&uiter, "\n");
1858
1859 qla_uprintf(&uiter, "%08x ", fw->lmc_reg[cnt]);
1860 }
1861
1862 qla_uprintf(&uiter, "\n\nFPM Hardware Registers");
1863 for (cnt = 0; cnt < sizeof(fw->fpm_hdw_reg) / 4; cnt++) {
1864 if (cnt % 8 == 0)
1865 qla_uprintf(&uiter, "\n");
1866
1867 qla_uprintf(&uiter, "%08x ", fw->fpm_hdw_reg[cnt]);
1868 }
1869
1870 qla_uprintf(&uiter, "\n\nFB Hardware Registers");
1871 for (cnt = 0; cnt < sizeof(fw->fb_hdw_reg) / 4; cnt++) {
1872 if (cnt % 8 == 0)
1873 qla_uprintf(&uiter, "\n");
1874
1875 qla_uprintf(&uiter, "%08x ", fw->fb_hdw_reg[cnt]);
1876 }
1877
1878 qla_uprintf(&uiter, "\n\nCode RAM");
1879 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
1880 if (cnt % 8 == 0) {
1881 qla_uprintf(&uiter, "\n%08x: ", cnt + 0x20000);
1882 }
1883 qla_uprintf(&uiter, "%08x ", fw->code_ram[cnt]);
1884 }
1885
1886 qla_uprintf(&uiter, "\n\nExternal Memory");
1887 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
1888 for (cnt = 0; cnt < ext_mem_cnt; cnt++) {
1889 if (cnt % 8 == 0) {
1890 qla_uprintf(&uiter, "\n%08x: ", cnt + 0x100000);
1891 }
1892 qla_uprintf(&uiter, "%08x ", fw->ext_mem[cnt]);
1893 }
1894
1895 qla_uprintf(&uiter, "\n[<==END] ISP Debug Dump");
1896}
1897
1898
1899/****************************************************************************/ 1340/****************************************************************************/
1900/* Driver Debug Functions. */ 1341/* Driver Debug Functions. */
1901/****************************************************************************/ 1342/****************************************************************************/
diff --git a/drivers/scsi/qla2xxx/qla_dbg.h b/drivers/scsi/qla2xxx/qla_dbg.h
index ab6afeaa2f2c..533425338e05 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.h
+++ b/drivers/scsi/qla2xxx/qla_dbg.h
@@ -37,134 +37,86 @@
37/* 37/*
38* Macros use for debugging the driver. 38* Macros use for debugging the driver.
39*/ 39*/
40#undef ENTER_TRACE
41#if defined(ENTER_TRACE)
42#define ENTER(x) do { printk("qla2100 : Entering %s()\n", x); } while (0)
43#define LEAVE(x) do { printk("qla2100 : Leaving %s()\n", x); } while (0)
44#define ENTER_INTR(x) do { printk("qla2100 : Entering %s()\n", x); } while (0)
45#define LEAVE_INTR(x) do { printk("qla2100 : Leaving %s()\n", x); } while (0)
46#else
47#define ENTER(x) do {} while (0)
48#define LEAVE(x) do {} while (0)
49#define ENTER_INTR(x) do {} while (0)
50#define LEAVE_INTR(x) do {} while (0)
51#endif
52 40
53#if DEBUG_QLA2100 41#define DEBUG(x) do { if (extended_error_logging) { x; } } while (0)
54#define DEBUG(x) do {x;} while (0);
55#else
56#define DEBUG(x) do {} while (0);
57#endif
58 42
59#if defined(QL_DEBUG_LEVEL_1) 43#if defined(QL_DEBUG_LEVEL_1)
60#define DEBUG1(x) do {x;} while (0); 44#define DEBUG1(x) do {x;} while (0)
61#else 45#else
62#define DEBUG1(x) do {} while (0); 46#define DEBUG1(x) do {} while (0)
63#endif 47#endif
64 48
65#if defined(QL_DEBUG_LEVEL_2) 49#define DEBUG2(x) do { if (extended_error_logging) { x; } } while (0)
66#define DEBUG2(x) do {x;} while (0); 50#define DEBUG2_3(x) do { if (extended_error_logging) { x; } } while (0)
67#define DEBUG2_3(x) do {x;} while (0); 51#define DEBUG2_3_11(x) do { if (extended_error_logging) { x; } } while (0)
68#define DEBUG2_3_11(x) do {x;} while (0); 52#define DEBUG2_9_10(x) do { if (extended_error_logging) { x; } } while (0)
69#define DEBUG2_9_10(x) do {x;} while (0); 53#define DEBUG2_11(x) do { if (extended_error_logging) { x; } } while (0)
70#define DEBUG2_11(x) do {x;} while (0); 54#define DEBUG2_13(x) do { if (extended_error_logging) { x; } } while (0)
71#define DEBUG2_13(x) do {x;} while (0);
72#else
73#define DEBUG2(x) do {} while (0);
74#endif
75 55
76#if defined(QL_DEBUG_LEVEL_3) 56#if defined(QL_DEBUG_LEVEL_3)
77#define DEBUG3(x) do {x;} while (0); 57#define DEBUG3(x) do {x;} while (0)
78#define DEBUG2_3(x) do {x;} while (0); 58#define DEBUG3_11(x) do {x;} while (0)
79#define DEBUG2_3_11(x) do {x;} while (0);
80#define DEBUG3_11(x) do {x;} while (0);
81#else 59#else
82#define DEBUG3(x) do {} while (0); 60#define DEBUG3(x) do {} while (0)
83 #if !defined(QL_DEBUG_LEVEL_2)
84 #define DEBUG2_3(x) do {} while (0);
85 #endif
86#endif 61#endif
87 62
88#if defined(QL_DEBUG_LEVEL_4) 63#if defined(QL_DEBUG_LEVEL_4)
89#define DEBUG4(x) do {x;} while (0); 64#define DEBUG4(x) do {x;} while (0)
90#else 65#else
91#define DEBUG4(x) do {} while (0); 66#define DEBUG4(x) do {} while (0)
92#endif 67#endif
93 68
94#if defined(QL_DEBUG_LEVEL_5) 69#if defined(QL_DEBUG_LEVEL_5)
95#define DEBUG5(x) do {x;} while (0); 70#define DEBUG5(x) do {x;} while (0)
96#else 71#else
97#define DEBUG5(x) do {} while (0); 72#define DEBUG5(x) do {} while (0)
98#endif 73#endif
99 74
100#if defined(QL_DEBUG_LEVEL_7) 75#if defined(QL_DEBUG_LEVEL_7)
101#define DEBUG7(x) do {x;} while (0); 76#define DEBUG7(x) do {x;} while (0)
102#else 77#else
103#define DEBUG7(x) do {} while (0); 78#define DEBUG7(x) do {} while (0)
104#endif 79#endif
105 80
106#if defined(QL_DEBUG_LEVEL_9) 81#if defined(QL_DEBUG_LEVEL_9)
107#define DEBUG9(x) do {x;} while (0); 82#define DEBUG9(x) do {x;} while (0)
108#define DEBUG9_10(x) do {x;} while (0); 83#define DEBUG9_10(x) do {x;} while (0)
109#define DEBUG2_9_10(x) do {x;} while (0);
110#else 84#else
111#define DEBUG9(x) do {} while (0); 85#define DEBUG9(x) do {} while (0)
112#endif 86#endif
113 87
114#if defined(QL_DEBUG_LEVEL_10) 88#if defined(QL_DEBUG_LEVEL_10)
115#define DEBUG10(x) do {x;} while (0); 89#define DEBUG10(x) do {x;} while (0)
116#define DEBUG2_9_10(x) do {x;} while (0); 90#define DEBUG9_10(x) do {x;} while (0)
117#define DEBUG9_10(x) do {x;} while (0);
118#else 91#else
119#define DEBUG10(x) do {} while (0); 92#define DEBUG10(x) do {} while (0)
120 #if !defined(DEBUG2_9_10)
121 #define DEBUG2_9_10(x) do {} while (0);
122 #endif
123 #if !defined(DEBUG9_10) 93 #if !defined(DEBUG9_10)
124 #define DEBUG9_10(x) do {} while (0); 94 #define DEBUG9_10(x) do {} while (0)
125 #endif 95 #endif
126#endif 96#endif
127 97
128#if defined(QL_DEBUG_LEVEL_11) 98#if defined(QL_DEBUG_LEVEL_11)
129#define DEBUG11(x) do{x;} while(0); 99#define DEBUG11(x) do{x;} while(0)
130#if !defined(DEBUG2_11)
131#define DEBUG2_11(x) do{x;} while(0);
132#endif
133#if !defined(DEBUG2_3_11)
134#define DEBUG2_3_11(x) do{x;} while(0);
135#endif
136#if !defined(DEBUG3_11) 100#if !defined(DEBUG3_11)
137#define DEBUG3_11(x) do{x;} while(0); 101#define DEBUG3_11(x) do{x;} while(0)
138#endif 102#endif
139#else 103#else
140#define DEBUG11(x) do{} while(0); 104#define DEBUG11(x) do{} while(0)
141 #if !defined(QL_DEBUG_LEVEL_2)
142 #define DEBUG2_11(x) do{} while(0);
143 #if !defined(QL_DEBUG_LEVEL_3)
144 #define DEBUG2_3_11(x) do{} while(0);
145 #endif
146 #endif
147 #if !defined(QL_DEBUG_LEVEL_3) 105 #if !defined(QL_DEBUG_LEVEL_3)
148 #define DEBUG3_11(x) do{} while(0); 106 #define DEBUG3_11(x) do{} while(0)
149 #endif 107 #endif
150#endif 108#endif
151 109
152#if defined(QL_DEBUG_LEVEL_12) 110#if defined(QL_DEBUG_LEVEL_12)
153#define DEBUG12(x) do {x;} while (0); 111#define DEBUG12(x) do {x;} while (0)
154#else 112#else
155#define DEBUG12(x) do {} while (0); 113#define DEBUG12(x) do {} while (0)
156#endif 114#endif
157 115
158#if defined(QL_DEBUG_LEVEL_13) 116#if defined(QL_DEBUG_LEVEL_13)
159#define DEBUG13(x) do {x;} while (0) 117#define DEBUG13(x) do {x;} while (0)
160#if !defined(DEBUG2_13)
161#define DEBUG2_13(x) do {x;} while(0)
162#endif
163#else 118#else
164#define DEBUG13(x) do {} while (0) 119#define DEBUG13(x) do {} while (0)
165#if !defined(QL_DEBUG_LEVEL_2)
166#define DEBUG2_13(x) do {} while(0)
167#endif
168#endif 120#endif
169 121
170#if defined(QL_DEBUG_LEVEL_14) 122#if defined(QL_DEBUG_LEVEL_14)
@@ -176,9 +128,6 @@
176/* 128/*
177 * Firmware Dump structure definition 129 * Firmware Dump structure definition
178 */ 130 */
179#define FW_DUMP_SIZE_128K 0xBC000
180#define FW_DUMP_SIZE_512K 0x2FC000
181#define FW_DUMP_SIZE_1M 0x5FC000
182 131
183struct qla2300_fw_dump { 132struct qla2300_fw_dump {
184 uint16_t hccr; 133 uint16_t hccr;
@@ -224,8 +173,6 @@ struct qla2100_fw_dump {
224 uint16_t risc_ram[0xf000]; 173 uint16_t risc_ram[0xf000];
225}; 174};
226 175
227#define FW_DUMP_SIZE_24XX 0x2B0000
228
229struct qla24xx_fw_dump { 176struct qla24xx_fw_dump {
230 uint32_t host_status; 177 uint32_t host_status;
231 uint32_t host_reg[32]; 178 uint32_t host_reg[32];
@@ -257,3 +204,39 @@ struct qla24xx_fw_dump {
257 uint32_t code_ram[0x2000]; 204 uint32_t code_ram[0x2000];
258 uint32_t ext_mem[1]; 205 uint32_t ext_mem[1];
259}; 206};
207
208#define EFT_NUM_BUFFERS 4
209#define EFT_BYTES_PER_BUFFER 0x4000
210#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
211
212struct qla2xxx_fw_dump {
213 uint8_t signature[4];
214 uint32_t version;
215
216 uint32_t fw_major_version;
217 uint32_t fw_minor_version;
218 uint32_t fw_subminor_version;
219 uint32_t fw_attributes;
220
221 uint32_t vendor;
222 uint32_t device;
223 uint32_t subsystem_vendor;
224 uint32_t subsystem_device;
225
226 uint32_t fixed_size;
227 uint32_t mem_size;
228 uint32_t req_q_size;
229 uint32_t rsp_q_size;
230
231 uint32_t eft_size;
232 uint32_t eft_addr_l;
233 uint32_t eft_addr_h;
234
235 uint32_t header_size;
236
237 union {
238 struct qla2100_fw_dump isp21;
239 struct qla2300_fw_dump isp23;
240 struct qla24xx_fw_dump isp24;
241 } isp;
242};
diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h
index 6734453ea28a..139ea0e27fd7 100644
--- a/drivers/scsi/qla2xxx/qla_def.h
+++ b/drivers/scsi/qla2xxx/qla_def.h
@@ -608,7 +608,9 @@ typedef struct {
608#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 608#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
609#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 609#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
610#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 610#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
611#define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
611#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 612#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
613#define MBC_READ_SFP 0x31 /* Read SFP Data. */
612#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 614#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
613#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 615#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
614#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 616#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
@@ -618,6 +620,9 @@ typedef struct {
618#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 620#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
619#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 621#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
620 622
623#define TC_ENABLE 4
624#define TC_DISABLE 5
625
621/* Firmware return data sizes */ 626/* Firmware return data sizes */
622#define FCAL_MAP_SIZE 128 627#define FCAL_MAP_SIZE 128
623 628
@@ -1997,7 +2002,6 @@ struct isp_operations {
1997 uint32_t); 2002 uint32_t);
1998 2003
1999 void (*fw_dump) (struct scsi_qla_host *, int); 2004 void (*fw_dump) (struct scsi_qla_host *, int);
2000 void (*ascii_fw_dump) (struct scsi_qla_host *);
2001 2005
2002 int (*beacon_on) (struct scsi_qla_host *); 2006 int (*beacon_on) (struct scsi_qla_host *);
2003 int (*beacon_off) (struct scsi_qla_host *); 2007 int (*beacon_off) (struct scsi_qla_host *);
@@ -2041,6 +2045,7 @@ typedef struct scsi_qla_host {
2041 uint32_t enable_led_scheme :1; 2045 uint32_t enable_led_scheme :1;
2042 uint32_t msi_enabled :1; 2046 uint32_t msi_enabled :1;
2043 uint32_t msix_enabled :1; 2047 uint32_t msix_enabled :1;
2048 uint32_t disable_serdes :1;
2044 } flags; 2049 } flags;
2045 2050
2046 atomic_t loop_state; 2051 atomic_t loop_state;
@@ -2238,6 +2243,11 @@ typedef struct scsi_qla_host {
2238 struct sns_cmd_pkt *sns_cmd; 2243 struct sns_cmd_pkt *sns_cmd;
2239 dma_addr_t sns_cmd_dma; 2244 dma_addr_t sns_cmd_dma;
2240 2245
2246#define SFP_DEV_SIZE 256
2247#define SFP_BLOCK_SIZE 64
2248 void *sfp_data;
2249 dma_addr_t sfp_data_dma;
2250
2241 struct task_struct *dpc_thread; 2251 struct task_struct *dpc_thread;
2242 uint8_t dpc_active; /* DPC routine is active */ 2252 uint8_t dpc_active; /* DPC routine is active */
2243 2253
@@ -2303,11 +2313,12 @@ typedef struct scsi_qla_host {
2303 uint16_t fw_seriallink_options24[4]; 2313 uint16_t fw_seriallink_options24[4];
2304 2314
2305 /* Firmware dump information. */ 2315 /* Firmware dump information. */
2306 void *fw_dump; 2316 struct qla2xxx_fw_dump *fw_dump;
2317 uint32_t fw_dump_len;
2307 int fw_dumped; 2318 int fw_dumped;
2308 int fw_dump_reading; 2319 int fw_dump_reading;
2309 char *fw_dump_buffer; 2320 dma_addr_t eft_dma;
2310 int fw_dump_buffer_len; 2321 void *eft;
2311 2322
2312 uint8_t host_str[16]; 2323 uint8_t host_str[16];
2313 uint32_t pci_attr; 2324 uint32_t pci_attr;
diff --git a/drivers/scsi/qla2xxx/qla_devtbl.h b/drivers/scsi/qla2xxx/qla_devtbl.h
index a8fc0ffc7fc5..dd435410dfa2 100644
--- a/drivers/scsi/qla2xxx/qla_devtbl.h
+++ b/drivers/scsi/qla2xxx/qla_devtbl.h
@@ -1,4 +1,4 @@
1#define QLA_MODEL_NAMES 0x4A 1#define QLA_MODEL_NAMES 0x57
2 2
3/* 3/*
4 * Adapter model names and descriptions. 4 * Adapter model names and descriptions.
@@ -76,6 +76,19 @@ static char *qla2x00_model_name[QLA_MODEL_NAMES*2] = {
76 "QLE2440", "PCI-Express to 4Gb FC, Single Channel", /* 0x145 */ 76 "QLE2440", "PCI-Express to 4Gb FC, Single Channel", /* 0x145 */
77 "QLE2464", "PCI-Express to 4Gb FC, Quad Channel", /* 0x146 */ 77 "QLE2464", "PCI-Express to 4Gb FC, Quad Channel", /* 0x146 */
78 "QLA2440", "PCI-X 2.0 to 4Gb FC, Single Channel", /* 0x147 */ 78 "QLA2440", "PCI-X 2.0 to 4Gb FC, Single Channel", /* 0x147 */
79 " ", " ", /* 0x148 */ 79 "HP AE369A", "PCI-X 2.0 to 4Gb FC, Dual Channel", /* 0x148 */
80 "QLA2340", "Sun 133MHz PCI-X to 2Gb FC, Single Channel", /* 0x149 */ 80 "QLA2340", "Sun 133MHz PCI-X to 2Gb FC, Single Channel", /* 0x149 */
81 " ", " ", /* 0x14a */
82 " ", " ", /* 0x14b */
83 "QMC2432M", "IBM eServer BC 4Gb FC Expansion Card CFFE", /* 0x14c */
84 "QMC2422M", "IBM eServer BC 4Gb FC Expansion Card CFFX", /* 0x14d */
85 "QLE220", "Sun PCI-Express to 4Gb FC, Single Channel", /* 0x14e */
86 " ", " ", /* 0x14f */
87 " ", " ", /* 0x150 */
88 " ", " ", /* 0x151 */
89 "QME2462", "PCI-Express to 4Gb FC, Dual Channel Mezz HBA", /* 0x152 */
90 "QMH2462", "PCI-Express to 4Gb FC, Dual Channel Mezz HBA", /* 0x153 */
91 " ", " ", /* 0x154 */
92 "QLE220", "PCI-Express to 4Gb FC, Single Channel", /* 0x155 */
93 "QLE220", "PCI-Express to 4Gb FC, Single Channel", /* 0x156 */
81}; 94};
diff --git a/drivers/scsi/qla2xxx/qla_fw.h b/drivers/scsi/qla2xxx/qla_fw.h
index 3af478663be7..a0a722cf4237 100644
--- a/drivers/scsi/qla2xxx/qla_fw.h
+++ b/drivers/scsi/qla2xxx/qla_fw.h
@@ -141,7 +141,7 @@ struct nvram_24xx {
141 * BIT 2 = Enable Memory Map BIOS 141 * BIT 2 = Enable Memory Map BIOS
142 * BIT 3 = Enable Selectable Boot 142 * BIT 3 = Enable Selectable Boot
143 * BIT 4 = Disable RISC code load 143 * BIT 4 = Disable RISC code load
144 * BIT 5 = 144 * BIT 5 = Disable Serdes
145 * BIT 6 = 145 * BIT 6 =
146 * BIT 7 = 146 * BIT 7 =
147 * 147 *
@@ -278,7 +278,7 @@ struct init_cb_24xx {
278 uint16_t response_q_length; 278 uint16_t response_q_length;
279 uint16_t request_q_length; 279 uint16_t request_q_length;
280 280
281 uint16_t link_down_timeout; /* Milliseconds. */ 281 uint16_t link_down_on_nos; /* Milliseconds. */
282 282
283 uint16_t prio_request_q_length; 283 uint16_t prio_request_q_length;
284 284
diff --git a/drivers/scsi/qla2xxx/qla_gbl.h b/drivers/scsi/qla2xxx/qla_gbl.h
index 164d53ccbfd0..8311ac2b93a8 100644
--- a/drivers/scsi/qla2xxx/qla_gbl.h
+++ b/drivers/scsi/qla2xxx/qla_gbl.h
@@ -31,13 +31,9 @@ extern void qla2x00_update_fw_options(struct scsi_qla_host *);
31extern void qla24xx_update_fw_options(scsi_qla_host_t *); 31extern void qla24xx_update_fw_options(scsi_qla_host_t *);
32extern int qla2x00_load_risc(struct scsi_qla_host *, uint32_t *); 32extern int qla2x00_load_risc(struct scsi_qla_host *, uint32_t *);
33extern int qla24xx_load_risc(scsi_qla_host_t *, uint32_t *); 33extern int qla24xx_load_risc(scsi_qla_host_t *, uint32_t *);
34extern int qla24xx_load_risc_flash(scsi_qla_host_t *, uint32_t *);
35
36extern fc_port_t *qla2x00_alloc_fcport(scsi_qla_host_t *, gfp_t);
37 34
38extern int qla2x00_loop_resync(scsi_qla_host_t *); 35extern int qla2x00_loop_resync(scsi_qla_host_t *);
39 36
40extern int qla2x00_find_new_loop_id(scsi_qla_host_t *, fc_port_t *);
41extern int qla2x00_fabric_login(scsi_qla_host_t *, fc_port_t *, uint16_t *); 37extern int qla2x00_fabric_login(scsi_qla_host_t *, fc_port_t *, uint16_t *);
42extern int qla2x00_local_device_login(scsi_qla_host_t *, fc_port_t *); 38extern int qla2x00_local_device_login(scsi_qla_host_t *, fc_port_t *);
43 39
@@ -51,6 +47,8 @@ extern int qla2x00_abort_isp(scsi_qla_host_t *);
51extern void qla2x00_update_fcport(scsi_qla_host_t *, fc_port_t *); 47extern void qla2x00_update_fcport(scsi_qla_host_t *, fc_port_t *);
52extern void qla2x00_reg_remote_port(scsi_qla_host_t *, fc_port_t *); 48extern void qla2x00_reg_remote_port(scsi_qla_host_t *, fc_port_t *);
53 49
50extern void qla2x00_alloc_fw_dump(scsi_qla_host_t *);
51
54/* 52/*
55 * Global Data in qla_os.c source file. 53 * Global Data in qla_os.c source file.
56 */ 54 */
@@ -61,6 +59,8 @@ extern int qlport_down_retry;
61extern int ql2xplogiabsentdevice; 59extern int ql2xplogiabsentdevice;
62extern int ql2xloginretrycount; 60extern int ql2xloginretrycount;
63extern int ql2xfdmienable; 61extern int ql2xfdmienable;
62extern int ql2xallocfwdump;
63extern int extended_error_logging;
64 64
65extern void qla2x00_sp_compl(scsi_qla_host_t *, srb_t *); 65extern void qla2x00_sp_compl(scsi_qla_host_t *, srb_t *);
66 66
@@ -80,8 +80,6 @@ extern void qla2xxx_wake_dpc(scsi_qla_host_t *);
80/* 80/*
81 * Global Function Prototypes in qla_iocb.c source file. 81 * Global Function Prototypes in qla_iocb.c source file.
82 */ 82 */
83extern void qla2x00_isp_cmd(scsi_qla_host_t *);
84
85extern uint16_t qla2x00_calc_iocbs_32(uint16_t); 83extern uint16_t qla2x00_calc_iocbs_32(uint16_t);
86extern uint16_t qla2x00_calc_iocbs_64(uint16_t); 84extern uint16_t qla2x00_calc_iocbs_64(uint16_t);
87extern void qla2x00_build_scsi_iocbs_32(srb_t *, cmd_entry_t *, uint16_t); 85extern void qla2x00_build_scsi_iocbs_32(srb_t *, cmd_entry_t *, uint16_t);
@@ -204,6 +202,12 @@ qla2x00_set_serdes_params(scsi_qla_host_t *, uint16_t, uint16_t, uint16_t);
204extern int 202extern int
205qla2x00_stop_firmware(scsi_qla_host_t *); 203qla2x00_stop_firmware(scsi_qla_host_t *);
206 204
205extern int
206qla2x00_trace_control(scsi_qla_host_t *, uint16_t, dma_addr_t, uint16_t);
207
208extern int
209qla2x00_read_sfp(scsi_qla_host_t *, dma_addr_t, uint16_t, uint16_t, uint16_t);
210
207/* 211/*
208 * Global Function Prototypes in qla_isr.c source file. 212 * Global Function Prototypes in qla_isr.c source file.
209 */ 213 */
@@ -254,9 +258,6 @@ extern int qla24xx_write_optrom_data(struct scsi_qla_host *, uint8_t *,
254extern void qla2100_fw_dump(scsi_qla_host_t *, int); 258extern void qla2100_fw_dump(scsi_qla_host_t *, int);
255extern void qla2300_fw_dump(scsi_qla_host_t *, int); 259extern void qla2300_fw_dump(scsi_qla_host_t *, int);
256extern void qla24xx_fw_dump(scsi_qla_host_t *, int); 260extern void qla24xx_fw_dump(scsi_qla_host_t *, int);
257extern void qla2100_ascii_fw_dump(scsi_qla_host_t *);
258extern void qla2300_ascii_fw_dump(scsi_qla_host_t *);
259extern void qla24xx_ascii_fw_dump(scsi_qla_host_t *);
260extern void qla2x00_dump_regs(scsi_qla_host_t *); 261extern void qla2x00_dump_regs(scsi_qla_host_t *);
261extern void qla2x00_dump_buffer(uint8_t *, uint32_t); 262extern void qla2x00_dump_buffer(uint8_t *, uint32_t);
262extern void qla2x00_print_scsi_cmd(struct scsi_cmnd *); 263extern void qla2x00_print_scsi_cmd(struct scsi_cmnd *);
@@ -280,13 +281,6 @@ extern void *qla24xx_prep_ms_fdmi_iocb(scsi_qla_host_t *, uint32_t, uint32_t);
280extern int qla2x00_fdmi_register(scsi_qla_host_t *); 281extern int qla2x00_fdmi_register(scsi_qla_host_t *);
281 282
282/* 283/*
283 * Global Function Prototypes in qla_xioctl.c source file.
284 */
285#define qla2x00_enqueue_aen(ha, cmd, mode) do { } while (0)
286#define qla2x00_alloc_ioctl_mem(ha) (0)
287#define qla2x00_free_ioctl_mem(ha) do { } while (0)
288
289/*
290 * Global Function Prototypes in qla_attr.c source file. 284 * Global Function Prototypes in qla_attr.c source file.
291 */ 285 */
292struct class_device_attribute; 286struct class_device_attribute;
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
index 3d4487eac9b7..9758dba95542 100644
--- a/drivers/scsi/qla2xxx/qla_init.c
+++ b/drivers/scsi/qla2xxx/qla_init.c
@@ -39,6 +39,8 @@ static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
39 39
40static int qla2x00_restart_isp(scsi_qla_host_t *); 40static int qla2x00_restart_isp(scsi_qla_host_t *);
41 41
42static int qla2x00_find_new_loop_id(scsi_qla_host_t *ha, fc_port_t *dev);
43
42/****************************************************************************/ 44/****************************************************************************/
43/* QLogic ISP2x00 Hardware Support Functions. */ 45/* QLogic ISP2x00 Hardware Support Functions. */
44/****************************************************************************/ 46/****************************************************************************/
@@ -89,6 +91,17 @@ qla2x00_initialize_adapter(scsi_qla_host_t *ha)
89 91
90 ha->isp_ops.nvram_config(ha); 92 ha->isp_ops.nvram_config(ha);
91 93
94 if (ha->flags.disable_serdes) {
95 /* Mask HBA via NVRAM settings? */
96 qla_printk(KERN_INFO, ha, "Masking HBA WWPN "
97 "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
98 ha->port_name[0], ha->port_name[1],
99 ha->port_name[2], ha->port_name[3],
100 ha->port_name[4], ha->port_name[5],
101 ha->port_name[6], ha->port_name[7]);
102 return QLA_FUNCTION_FAILED;
103 }
104
92 qla_printk(KERN_INFO, ha, "Verifying loaded RISC code...\n"); 105 qla_printk(KERN_INFO, ha, "Verifying loaded RISC code...\n");
93 106
94 retry = 10; 107 retry = 10;
@@ -770,29 +783,104 @@ qla24xx_chip_diag(scsi_qla_host_t *ha)
770 return rval; 783 return rval;
771} 784}
772 785
773static void 786void
774qla2x00_alloc_fw_dump(scsi_qla_host_t *ha) 787qla2x00_alloc_fw_dump(scsi_qla_host_t *ha)
775{ 788{
776 uint32_t dump_size = 0; 789 int rval;
790 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
791 eft_size;
792 dma_addr_t eft_dma;
793 void *eft;
794
795 if (ha->fw_dump) {
796 qla_printk(KERN_WARNING, ha,
797 "Firmware dump previously allocated.\n");
798 return;
799 }
777 800
778 ha->fw_dumped = 0; 801 ha->fw_dumped = 0;
802 fixed_size = mem_size = eft_size = 0;
779 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 803 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
780 dump_size = sizeof(struct qla2100_fw_dump); 804 fixed_size = sizeof(struct qla2100_fw_dump);
781 } else if (IS_QLA23XX(ha)) { 805 } else if (IS_QLA23XX(ha)) {
782 dump_size = sizeof(struct qla2300_fw_dump); 806 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
783 dump_size += (ha->fw_memory_size - 0x11000) * sizeof(uint16_t); 807 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
784 } else if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 808 sizeof(uint16_t);
785 dump_size = sizeof(struct qla24xx_fw_dump); 809 } else if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) {
786 dump_size += (ha->fw_memory_size - 0x100000) * sizeof(uint32_t); 810 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
811 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
812 sizeof(uint32_t);
813
814 /* Allocate memory for Extended Trace Buffer. */
815 eft = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &eft_dma,
816 GFP_KERNEL);
817 if (!eft) {
818 qla_printk(KERN_WARNING, ha, "Unable to allocate "
819 "(%d KB) for EFT.\n", EFT_SIZE / 1024);
820 goto cont_alloc;
821 }
822
823 rval = qla2x00_trace_control(ha, TC_ENABLE, eft_dma,
824 EFT_NUM_BUFFERS);
825 if (rval) {
826 qla_printk(KERN_WARNING, ha, "Unable to initialize "
827 "EFT (%d).\n", rval);
828 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, eft,
829 eft_dma);
830 goto cont_alloc;
831 }
832
833 qla_printk(KERN_INFO, ha, "Allocated (%d KB) for EFT...\n",
834 EFT_SIZE / 1024);
835
836 eft_size = EFT_SIZE;
837 memset(eft, 0, eft_size);
838 ha->eft_dma = eft_dma;
839 ha->eft = eft;
787 } 840 }
841cont_alloc:
842 req_q_size = ha->request_q_length * sizeof(request_t);
843 rsp_q_size = ha->response_q_length * sizeof(response_t);
844
845 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
846 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size +
847 eft_size;
788 848
789 ha->fw_dump = vmalloc(dump_size); 849 ha->fw_dump = vmalloc(dump_size);
790 if (ha->fw_dump) 850 if (!ha->fw_dump) {
791 qla_printk(KERN_INFO, ha, "Allocated (%d KB) for firmware "
792 "dump...\n", dump_size / 1024);
793 else
794 qla_printk(KERN_WARNING, ha, "Unable to allocate (%d KB) for " 851 qla_printk(KERN_WARNING, ha, "Unable to allocate (%d KB) for "
795 "firmware dump!!!\n", dump_size / 1024); 852 "firmware dump!!!\n", dump_size / 1024);
853
854 if (ha->eft) {
855 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
856 ha->eft_dma);
857 ha->eft = NULL;
858 ha->eft_dma = 0;
859 }
860 return;
861 }
862
863 qla_printk(KERN_INFO, ha, "Allocated (%d KB) for firmware dump...\n",
864 dump_size / 1024);
865
866 ha->fw_dump_len = dump_size;
867 ha->fw_dump->signature[0] = 'Q';
868 ha->fw_dump->signature[1] = 'L';
869 ha->fw_dump->signature[2] = 'G';
870 ha->fw_dump->signature[3] = 'C';
871 ha->fw_dump->version = __constant_htonl(1);
872
873 ha->fw_dump->fixed_size = htonl(fixed_size);
874 ha->fw_dump->mem_size = htonl(mem_size);
875 ha->fw_dump->req_q_size = htonl(req_q_size);
876 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
877
878 ha->fw_dump->eft_size = htonl(eft_size);
879 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
880 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
881
882 ha->fw_dump->header_size =
883 htonl(offsetof(struct qla2xxx_fw_dump, isp));
796} 884}
797 885
798/** 886/**
@@ -810,8 +898,6 @@ qla2x00_resize_request_q(scsi_qla_host_t *ha)
810 dma_addr_t request_dma; 898 dma_addr_t request_dma;
811 request_t *request_ring; 899 request_t *request_ring;
812 900
813 qla2x00_alloc_fw_dump(ha);
814
815 /* Valid only on recent ISPs. */ 901 /* Valid only on recent ISPs. */
816 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 902 if (IS_QLA2100(ha) || IS_QLA2200(ha))
817 return; 903 return;
@@ -883,6 +969,9 @@ qla2x00_setup_chip(scsi_qla_host_t *ha)
883 &ha->fw_subminor_version, 969 &ha->fw_subminor_version,
884 &ha->fw_attributes, &ha->fw_memory_size); 970 &ha->fw_attributes, &ha->fw_memory_size);
885 qla2x00_resize_request_q(ha); 971 qla2x00_resize_request_q(ha);
972
973 if (ql2xallocfwdump)
974 qla2x00_alloc_fw_dump(ha);
886 } 975 }
887 } else { 976 } else {
888 DEBUG2(printk(KERN_INFO 977 DEBUG2(printk(KERN_INFO
@@ -1186,8 +1275,7 @@ qla2x00_fw_ready(scsi_qla_host_t *ha)
1186 rval = QLA_FUNCTION_FAILED; 1275 rval = QLA_FUNCTION_FAILED;
1187 1276
1188 if (atomic_read(&ha->loop_down_timer) && 1277 if (atomic_read(&ha->loop_down_timer) &&
1189 (fw_state >= FSTATE_LOSS_OF_SYNC || 1278 fw_state != FSTATE_READY) {
1190 fw_state == FSTATE_WAIT_AL_PA)) {
1191 /* Loop down. Timeout on min_wait for states 1279 /* Loop down. Timeout on min_wait for states
1192 * other than Wait for Login. 1280 * other than Wait for Login.
1193 */ 1281 */
@@ -1555,6 +1643,8 @@ qla2x00_nvram_config(scsi_qla_host_t *ha)
1555 /* 1643 /*
1556 * Set host adapter parameters. 1644 * Set host adapter parameters.
1557 */ 1645 */
1646 if (nv->host_p[0] & BIT_7)
1647 extended_error_logging = 1;
1558 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0); 1648 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
1559 /* Always load RISC code on non ISP2[12]00 chips. */ 1649 /* Always load RISC code on non ISP2[12]00 chips. */
1560 if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) 1650 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
@@ -1563,6 +1653,7 @@ qla2x00_nvram_config(scsi_qla_host_t *ha)
1563 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0); 1653 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
1564 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); 1654 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
1565 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0; 1655 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
1656 ha->flags.disable_serdes = 0;
1566 1657
1567 ha->operating_mode = 1658 ha->operating_mode =
1568 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4; 1659 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
@@ -1701,7 +1792,7 @@ qla2x00_rport_del(void *data)
1701 * 1792 *
1702 * Returns a pointer to the allocated fcport, or NULL, if none available. 1793 * Returns a pointer to the allocated fcport, or NULL, if none available.
1703 */ 1794 */
1704fc_port_t * 1795static fc_port_t *
1705qla2x00_alloc_fcport(scsi_qla_host_t *ha, gfp_t flags) 1796qla2x00_alloc_fcport(scsi_qla_host_t *ha, gfp_t flags)
1706{ 1797{
1707 fc_port_t *fcport; 1798 fc_port_t *fcport;
@@ -2497,7 +2588,7 @@ qla2x00_find_all_fabric_devs(scsi_qla_host_t *ha, struct list_head *new_fcports)
2497 * Context: 2588 * Context:
2498 * Kernel context. 2589 * Kernel context.
2499 */ 2590 */
2500int 2591static int
2501qla2x00_find_new_loop_id(scsi_qla_host_t *ha, fc_port_t *dev) 2592qla2x00_find_new_loop_id(scsi_qla_host_t *ha, fc_port_t *dev)
2502{ 2593{
2503 int rval; 2594 int rval;
@@ -3048,14 +3139,14 @@ qla2x00_abort_isp(scsi_qla_host_t *ha)
3048 ha->isp_abort_cnt--; 3139 ha->isp_abort_cnt--;
3049 DEBUG(printk("qla%ld: ISP abort - " 3140 DEBUG(printk("qla%ld: ISP abort - "
3050 "retry remaining %d\n", 3141 "retry remaining %d\n",
3051 ha->host_no, ha->isp_abort_cnt);) 3142 ha->host_no, ha->isp_abort_cnt));
3052 status = 1; 3143 status = 1;
3053 } 3144 }
3054 } else { 3145 } else {
3055 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 3146 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3056 DEBUG(printk("qla2x00(%ld): ISP error recovery " 3147 DEBUG(printk("qla2x00(%ld): ISP error recovery "
3057 "- retrying (%d) more times\n", 3148 "- retrying (%d) more times\n",
3058 ha->host_no, ha->isp_abort_cnt);) 3149 ha->host_no, ha->isp_abort_cnt));
3059 set_bit(ISP_ABORT_RETRY, &ha->dpc_flags); 3150 set_bit(ISP_ABORT_RETRY, &ha->dpc_flags);
3060 status = 1; 3151 status = 1;
3061 } 3152 }
@@ -3069,7 +3160,7 @@ qla2x00_abort_isp(scsi_qla_host_t *ha)
3069 } else { 3160 } else {
3070 DEBUG(printk(KERN_INFO 3161 DEBUG(printk(KERN_INFO
3071 "qla2x00_abort_isp(%ld): exiting.\n", 3162 "qla2x00_abort_isp(%ld): exiting.\n",
3072 ha->host_no);) 3163 ha->host_no));
3073 } 3164 }
3074 3165
3075 return(status); 3166 return(status);
@@ -3145,7 +3236,7 @@ qla2x00_restart_isp(scsi_qla_host_t *ha)
3145 clear_bit(RESET_MARKER_NEEDED, &ha->dpc_flags); 3236 clear_bit(RESET_MARKER_NEEDED, &ha->dpc_flags);
3146 if (!(status = qla2x00_fw_ready(ha))) { 3237 if (!(status = qla2x00_fw_ready(ha))) {
3147 DEBUG(printk("%s(): Start configure loop, " 3238 DEBUG(printk("%s(): Start configure loop, "
3148 "status = %d\n", __func__, status);) 3239 "status = %d\n", __func__, status));
3149 3240
3150 /* Issue a marker after FW becomes ready. */ 3241 /* Issue a marker after FW becomes ready. */
3151 qla2x00_marker(ha, 0, 0, MK_SYNC_ALL); 3242 qla2x00_marker(ha, 0, 0, MK_SYNC_ALL);
@@ -3169,7 +3260,7 @@ qla2x00_restart_isp(scsi_qla_host_t *ha)
3169 3260
3170 DEBUG(printk("%s(): Configure loop done, status = 0x%x\n", 3261 DEBUG(printk("%s(): Configure loop done, status = 0x%x\n",
3171 __func__, 3262 __func__,
3172 status);) 3263 status));
3173 } 3264 }
3174 return (status); 3265 return (status);
3175} 3266}
@@ -3289,7 +3380,6 @@ qla24xx_nvram_config(scsi_qla_host_t *ha)
3289 nv->node_name[6] = 0x55; 3380 nv->node_name[6] = 0x55;
3290 nv->node_name[7] = 0x86; 3381 nv->node_name[7] = 0x86;
3291 nv->login_retry_count = __constant_cpu_to_le16(8); 3382 nv->login_retry_count = __constant_cpu_to_le16(8);
3292 nv->link_down_timeout = __constant_cpu_to_le16(200);
3293 nv->interrupt_delay_timer = __constant_cpu_to_le16(0); 3383 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
3294 nv->login_timeout = __constant_cpu_to_le16(0); 3384 nv->login_timeout = __constant_cpu_to_le16(0);
3295 nv->firmware_options_1 = 3385 nv->firmware_options_1 =
@@ -3318,7 +3408,7 @@ qla24xx_nvram_config(scsi_qla_host_t *ha)
3318 *dptr1++ = *dptr2++; 3408 *dptr1++ = *dptr2++;
3319 3409
3320 icb->login_retry_count = nv->login_retry_count; 3410 icb->login_retry_count = nv->login_retry_count;
3321 icb->link_down_timeout = nv->link_down_timeout; 3411 icb->link_down_on_nos = nv->link_down_on_nos;
3322 3412
3323 /* Copy 2nd segment. */ 3413 /* Copy 2nd segment. */
3324 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 3414 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
@@ -3373,6 +3463,7 @@ qla24xx_nvram_config(scsi_qla_host_t *ha)
3373 ha->flags.enable_lip_full_login = 1; 3463 ha->flags.enable_lip_full_login = 1;
3374 ha->flags.enable_target_reset = 1; 3464 ha->flags.enable_target_reset = 1;
3375 ha->flags.enable_led_scheme = 0; 3465 ha->flags.enable_led_scheme = 0;
3466 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
3376 3467
3377 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 3468 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
3378 (BIT_6 | BIT_5 | BIT_4)) >> 4; 3469 (BIT_6 | BIT_5 | BIT_4)) >> 4;
@@ -3472,7 +3563,7 @@ qla24xx_nvram_config(scsi_qla_host_t *ha)
3472 return (rval); 3563 return (rval);
3473} 3564}
3474 3565
3475int 3566static int
3476qla24xx_load_risc_flash(scsi_qla_host_t *ha, uint32_t *srisc_addr) 3567qla24xx_load_risc_flash(scsi_qla_host_t *ha, uint32_t *srisc_addr)
3477{ 3568{
3478 int rval; 3569 int rval;
diff --git a/drivers/scsi/qla2xxx/qla_iocb.c b/drivers/scsi/qla2xxx/qla_iocb.c
index 8c769cfaa14c..2b60a27eff0b 100644
--- a/drivers/scsi/qla2xxx/qla_iocb.c
+++ b/drivers/scsi/qla2xxx/qla_iocb.c
@@ -15,6 +15,7 @@ static inline uint16_t qla2x00_get_cmd_direction(struct scsi_cmnd *cmd);
15static inline cont_entry_t *qla2x00_prep_cont_type0_iocb(scsi_qla_host_t *); 15static inline cont_entry_t *qla2x00_prep_cont_type0_iocb(scsi_qla_host_t *);
16static inline cont_a64_entry_t *qla2x00_prep_cont_type1_iocb(scsi_qla_host_t *); 16static inline cont_a64_entry_t *qla2x00_prep_cont_type1_iocb(scsi_qla_host_t *);
17static request_t *qla2x00_req_pkt(scsi_qla_host_t *ha); 17static request_t *qla2x00_req_pkt(scsi_qla_host_t *ha);
18static void qla2x00_isp_cmd(scsi_qla_host_t *ha);
18 19
19/** 20/**
20 * qla2x00_get_cmd_direction() - Determine control_flag data direction. 21 * qla2x00_get_cmd_direction() - Determine control_flag data direction.
@@ -574,7 +575,7 @@ qla2x00_req_pkt(scsi_qla_host_t *ha)
574 * 575 *
575 * Note: The caller must hold the hardware lock before calling this routine. 576 * Note: The caller must hold the hardware lock before calling this routine.
576 */ 577 */
577void 578static void
578qla2x00_isp_cmd(scsi_qla_host_t *ha) 579qla2x00_isp_cmd(scsi_qla_host_t *ha)
579{ 580{
580 device_reg_t __iomem *reg = ha->iobase; 581 device_reg_t __iomem *reg = ha->iobase;
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c
index b28ac0a27e25..795bf15b1b8f 100644
--- a/drivers/scsi/qla2xxx/qla_isr.c
+++ b/drivers/scsi/qla2xxx/qla_isr.c
@@ -395,10 +395,6 @@ qla2x00_async_event(scsi_qla_host_t *ha, uint16_t *mb)
395 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags); 395 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
396 396
397 ha->flags.management_server_logged_in = 0; 397 ha->flags.management_server_logged_in = 0;
398
399 /* Update AEN queue. */
400 qla2x00_enqueue_aen(ha, MBA_LIP_OCCURRED, NULL);
401
402 break; 398 break;
403 399
404 case MBA_LOOP_UP: /* Loop Up Event */ 400 case MBA_LOOP_UP: /* Loop Up Event */
@@ -418,9 +414,6 @@ qla2x00_async_event(scsi_qla_host_t *ha, uint16_t *mb)
418 link_speed); 414 link_speed);
419 415
420 ha->flags.management_server_logged_in = 0; 416 ha->flags.management_server_logged_in = 0;
421
422 /* Update AEN queue. */
423 qla2x00_enqueue_aen(ha, MBA_LOOP_UP, NULL);
424 break; 417 break;
425 418
426 case MBA_LOOP_DOWN: /* Loop Down Event */ 419 case MBA_LOOP_DOWN: /* Loop Down Event */
@@ -439,9 +432,6 @@ qla2x00_async_event(scsi_qla_host_t *ha, uint16_t *mb)
439 ha->link_data_rate = LDR_UNKNOWN; 432 ha->link_data_rate = LDR_UNKNOWN;
440 if (ql2xfdmienable) 433 if (ql2xfdmienable)
441 set_bit(REGISTER_FDMI_NEEDED, &ha->dpc_flags); 434 set_bit(REGISTER_FDMI_NEEDED, &ha->dpc_flags);
442
443 /* Update AEN queue. */
444 qla2x00_enqueue_aen(ha, MBA_LOOP_DOWN, NULL);
445 break; 435 break;
446 436
447 case MBA_LIP_RESET: /* LIP reset occurred */ 437 case MBA_LIP_RESET: /* LIP reset occurred */
@@ -460,10 +450,6 @@ qla2x00_async_event(scsi_qla_host_t *ha, uint16_t *mb)
460 450
461 ha->operating_mode = LOOP; 451 ha->operating_mode = LOOP;
462 ha->flags.management_server_logged_in = 0; 452 ha->flags.management_server_logged_in = 0;
463
464 /* Update AEN queue. */
465 qla2x00_enqueue_aen(ha, MBA_LIP_RESET, NULL);
466
467 break; 453 break;
468 454
469 case MBA_POINT_TO_POINT: /* Point-to-Point */ 455 case MBA_POINT_TO_POINT: /* Point-to-Point */
@@ -545,9 +531,6 @@ qla2x00_async_event(scsi_qla_host_t *ha, uint16_t *mb)
545 531
546 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags); 532 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
547 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags); 533 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
548
549 /* Update AEN queue. */
550 qla2x00_enqueue_aen(ha, MBA_PORT_UPDATE, NULL);
551 break; 534 break;
552 535
553 case MBA_RSCN_UPDATE: /* State Change Registration */ 536 case MBA_RSCN_UPDATE: /* State Change Registration */
@@ -584,9 +567,6 @@ qla2x00_async_event(scsi_qla_host_t *ha, uint16_t *mb)
584 567
585 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags); 568 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
586 set_bit(RSCN_UPDATE, &ha->dpc_flags); 569 set_bit(RSCN_UPDATE, &ha->dpc_flags);
587
588 /* Update AEN queue. */
589 qla2x00_enqueue_aen(ha, MBA_RSCN_UPDATE, &mb[0]);
590 break; 570 break;
591 571
592 /* case MBA_RIO_RESPONSE: */ 572 /* case MBA_RIO_RESPONSE: */
@@ -1452,8 +1432,8 @@ qla24xx_ms_entry(scsi_qla_host_t *ha, struct ct_entry_24xx *pkt)
1452 DEBUG3(printk("%s(%ld): pkt=%p pkthandle=%d.\n", 1432 DEBUG3(printk("%s(%ld): pkt=%p pkthandle=%d.\n",
1453 __func__, ha->host_no, pkt, pkt->handle)); 1433 __func__, ha->host_no, pkt, pkt->handle));
1454 1434
1455 DEBUG9(printk("%s: ct pkt dump:\n", __func__);) 1435 DEBUG9(printk("%s: ct pkt dump:\n", __func__));
1456 DEBUG9(qla2x00_dump_buffer((void *)pkt, sizeof(struct ct_entry_24xx));) 1436 DEBUG9(qla2x00_dump_buffer((void *)pkt, sizeof(struct ct_entry_24xx)));
1457 1437
1458 /* Validate handle. */ 1438 /* Validate handle. */
1459 if (pkt->handle < MAX_OUTSTANDING_COMMANDS) 1439 if (pkt->handle < MAX_OUTSTANDING_COMMANDS)
diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c
index d6cb3bd1a29a..879f281e2ea2 100644
--- a/drivers/scsi/qla2xxx/qla_mbx.c
+++ b/drivers/scsi/qla2xxx/qla_mbx.c
@@ -13,13 +13,13 @@ qla2x00_mbx_sem_timeout(unsigned long data)
13{ 13{
14 struct semaphore *sem_ptr = (struct semaphore *)data; 14 struct semaphore *sem_ptr = (struct semaphore *)data;
15 15
16 DEBUG11(printk("qla2x00_sem_timeout: entered.\n");) 16 DEBUG11(printk("qla2x00_sem_timeout: entered.\n"));
17 17
18 if (sem_ptr != NULL) { 18 if (sem_ptr != NULL) {
19 up(sem_ptr); 19 up(sem_ptr);
20 } 20 }
21 21
22 DEBUG11(printk("qla2x00_mbx_sem_timeout: exiting.\n");) 22 DEBUG11(printk("qla2x00_mbx_sem_timeout: exiting.\n"));
23} 23}
24 24
25/* 25/*
@@ -61,7 +61,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp)
61 rval = QLA_SUCCESS; 61 rval = QLA_SUCCESS;
62 abort_active = test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags); 62 abort_active = test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags);
63 63
64 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no);) 64 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no));
65 65
66 /* 66 /*
67 * Wait for active mailbox commands to finish by waiting at most tov 67 * Wait for active mailbox commands to finish by waiting at most tov
@@ -72,7 +72,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp)
72 if (qla2x00_down_timeout(&ha->mbx_cmd_sem, mcp->tov * HZ)) { 72 if (qla2x00_down_timeout(&ha->mbx_cmd_sem, mcp->tov * HZ)) {
73 /* Timeout occurred. Return error. */ 73 /* Timeout occurred. Return error. */
74 DEBUG2_3_11(printk("%s(%ld): cmd access timeout. " 74 DEBUG2_3_11(printk("%s(%ld): cmd access timeout. "
75 "Exiting.\n", __func__, ha->host_no);) 75 "Exiting.\n", __func__, ha->host_no));
76 return QLA_FUNCTION_TIMEOUT; 76 return QLA_FUNCTION_TIMEOUT;
77 } 77 }
78 } 78 }
@@ -86,7 +86,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp)
86 spin_lock_irqsave(&ha->mbx_reg_lock, mbx_flags); 86 spin_lock_irqsave(&ha->mbx_reg_lock, mbx_flags);
87 87
88 DEBUG11(printk("scsi(%ld): prepare to issue mbox cmd=0x%x.\n", 88 DEBUG11(printk("scsi(%ld): prepare to issue mbox cmd=0x%x.\n",
89 ha->host_no, mcp->mb[0]);) 89 ha->host_no, mcp->mb[0]));
90 90
91 spin_lock_irqsave(&ha->hardware_lock, flags); 91 spin_lock_irqsave(&ha->hardware_lock, flags);
92 92
@@ -131,14 +131,14 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp)
131 131
132 /* Unlock mbx registers and wait for interrupt */ 132 /* Unlock mbx registers and wait for interrupt */
133 DEBUG11(printk("%s(%ld): going to unlock irq & waiting for interrupt. " 133 DEBUG11(printk("%s(%ld): going to unlock irq & waiting for interrupt. "
134 "jiffies=%lx.\n", __func__, ha->host_no, jiffies);) 134 "jiffies=%lx.\n", __func__, ha->host_no, jiffies));
135 135
136 /* Wait for mbx cmd completion until timeout */ 136 /* Wait for mbx cmd completion until timeout */
137 137
138 if (!abort_active && io_lock_on) { 138 if (!abort_active && io_lock_on) {
139 /* sleep on completion semaphore */ 139 /* sleep on completion semaphore */
140 DEBUG11(printk("%s(%ld): INTERRUPT MODE. Initializing timer.\n", 140 DEBUG11(printk("%s(%ld): INTERRUPT MODE. Initializing timer.\n",
141 __func__, ha->host_no);) 141 __func__, ha->host_no));
142 142
143 init_timer(&tmp_intr_timer); 143 init_timer(&tmp_intr_timer);
144 tmp_intr_timer.data = (unsigned long)&ha->mbx_intr_sem; 144 tmp_intr_timer.data = (unsigned long)&ha->mbx_intr_sem;
@@ -147,11 +147,11 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp)
147 (void (*)(unsigned long))qla2x00_mbx_sem_timeout; 147 (void (*)(unsigned long))qla2x00_mbx_sem_timeout;
148 148
149 DEBUG11(printk("%s(%ld): Adding timer.\n", __func__, 149 DEBUG11(printk("%s(%ld): Adding timer.\n", __func__,
150 ha->host_no);) 150 ha->host_no));
151 add_timer(&tmp_intr_timer); 151 add_timer(&tmp_intr_timer);
152 152
153 DEBUG11(printk("%s(%ld): going to unlock & sleep. " 153 DEBUG11(printk("%s(%ld): going to unlock & sleep. "
154 "time=0x%lx.\n", __func__, ha->host_no, jiffies);) 154 "time=0x%lx.\n", __func__, ha->host_no, jiffies));
155 155
156 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 156 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
157 157
@@ -170,14 +170,14 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp)
170 down(&ha->mbx_intr_sem); 170 down(&ha->mbx_intr_sem);
171 171
172 DEBUG11(printk("%s(%ld): waking up. time=0x%lx\n", __func__, 172 DEBUG11(printk("%s(%ld): waking up. time=0x%lx\n", __func__,
173 ha->host_no, jiffies);) 173 ha->host_no, jiffies));
174 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 174 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
175 175
176 /* delete the timer */ 176 /* delete the timer */
177 del_timer(&tmp_intr_timer); 177 del_timer(&tmp_intr_timer);
178 } else { 178 } else {
179 DEBUG3_11(printk("%s(%ld): cmd=%x POLLING MODE.\n", __func__, 179 DEBUG3_11(printk("%s(%ld): cmd=%x POLLING MODE.\n", __func__,
180 ha->host_no, command);) 180 ha->host_no, command));
181 181
182 if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 182 if (IS_QLA24XX(ha) || IS_QLA54XX(ha))
183 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT); 183 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
@@ -209,7 +209,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp)
209 uint16_t *iptr2; 209 uint16_t *iptr2;
210 210
211 DEBUG3_11(printk("%s(%ld): cmd %x completed.\n", __func__, 211 DEBUG3_11(printk("%s(%ld): cmd %x completed.\n", __func__,
212 ha->host_no, command);) 212 ha->host_no, command));
213 213
214 /* Got interrupt. Clear the flag. */ 214 /* Got interrupt. Clear the flag. */
215 ha->flags.mbox_int = 0; 215 ha->flags.mbox_int = 0;
@@ -266,7 +266,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp)
266 266
267 if (!abort_active) { 267 if (!abort_active) {
268 DEBUG11(printk("%s(%ld): checking for additional resp " 268 DEBUG11(printk("%s(%ld): checking for additional resp "
269 "interrupt.\n", __func__, ha->host_no);) 269 "interrupt.\n", __func__, ha->host_no));
270 270
271 /* polling mode for non isp_abort commands. */ 271 /* polling mode for non isp_abort commands. */
272 qla2x00_poll(ha); 272 qla2x00_poll(ha);
@@ -277,9 +277,9 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp)
277 if (!io_lock_on || (mcp->flags & IOCTL_CMD)) { 277 if (!io_lock_on || (mcp->flags & IOCTL_CMD)) {
278 /* not in dpc. schedule it for dpc to take over. */ 278 /* not in dpc. schedule it for dpc to take over. */
279 DEBUG(printk("%s(%ld): timeout schedule " 279 DEBUG(printk("%s(%ld): timeout schedule "
280 "isp_abort_needed.\n", __func__, ha->host_no);) 280 "isp_abort_needed.\n", __func__, ha->host_no));
281 DEBUG2_3_11(printk("%s(%ld): timeout schedule " 281 DEBUG2_3_11(printk("%s(%ld): timeout schedule "
282 "isp_abort_needed.\n", __func__, ha->host_no);) 282 "isp_abort_needed.\n", __func__, ha->host_no));
283 qla_printk(KERN_WARNING, ha, 283 qla_printk(KERN_WARNING, ha,
284 "Mailbox command timeout occured. Scheduling ISP " 284 "Mailbox command timeout occured. Scheduling ISP "
285 "abort.\n"); 285 "abort.\n");
@@ -288,9 +288,9 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp)
288 } else if (!abort_active) { 288 } else if (!abort_active) {
289 /* call abort directly since we are in the DPC thread */ 289 /* call abort directly since we are in the DPC thread */
290 DEBUG(printk("%s(%ld): timeout calling abort_isp\n", 290 DEBUG(printk("%s(%ld): timeout calling abort_isp\n",
291 __func__, ha->host_no);) 291 __func__, ha->host_no));
292 DEBUG2_3_11(printk("%s(%ld): timeout calling " 292 DEBUG2_3_11(printk("%s(%ld): timeout calling "
293 "abort_isp\n", __func__, ha->host_no);) 293 "abort_isp\n", __func__, ha->host_no));
294 qla_printk(KERN_WARNING, ha, 294 qla_printk(KERN_WARNING, ha,
295 "Mailbox command timeout occured. Issuing ISP " 295 "Mailbox command timeout occured. Issuing ISP "
296 "abort.\n"); 296 "abort.\n");
@@ -303,9 +303,9 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp)
303 } 303 }
304 clear_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags); 304 clear_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags);
305 DEBUG(printk("%s(%ld): finished abort_isp\n", __func__, 305 DEBUG(printk("%s(%ld): finished abort_isp\n", __func__,
306 ha->host_no);) 306 ha->host_no));
307 DEBUG2_3_11(printk("%s(%ld): finished abort_isp\n", 307 DEBUG2_3_11(printk("%s(%ld): finished abort_isp\n",
308 __func__, ha->host_no);) 308 __func__, ha->host_no));
309 } 309 }
310 } 310 }
311 311
@@ -316,9 +316,9 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp)
316 if (rval) { 316 if (rval) {
317 DEBUG2_3_11(printk("%s(%ld): **** FAILED. mbx0=%x, mbx1=%x, " 317 DEBUG2_3_11(printk("%s(%ld): **** FAILED. mbx0=%x, mbx1=%x, "
318 "mbx2=%x, cmd=%x ****\n", __func__, ha->host_no, 318 "mbx2=%x, cmd=%x ****\n", __func__, ha->host_no,
319 mcp->mb[0], mcp->mb[1], mcp->mb[2], command);) 319 mcp->mb[0], mcp->mb[1], mcp->mb[2], command));
320 } else { 320 } else {
321 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no);) 321 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no));
322 } 322 }
323 323
324 return rval; 324 return rval;
@@ -394,7 +394,7 @@ qla2x00_execute_fw(scsi_qla_host_t *ha, uint32_t risc_addr)
394 mbx_cmd_t mc; 394 mbx_cmd_t mc;
395 mbx_cmd_t *mcp = &mc; 395 mbx_cmd_t *mcp = &mc;
396 396
397 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no);) 397 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no));
398 398
399 mcp->mb[0] = MBC_EXECUTE_FIRMWARE; 399 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
400 mcp->out_mb = MBX_0; 400 mcp->out_mb = MBX_0;
@@ -424,10 +424,10 @@ qla2x00_execute_fw(scsi_qla_host_t *ha, uint32_t risc_addr)
424 } else { 424 } else {
425 if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 425 if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) {
426 DEBUG11(printk("%s(%ld): done exchanges=%x.\n", 426 DEBUG11(printk("%s(%ld): done exchanges=%x.\n",
427 __func__, ha->host_no, mcp->mb[1]);) 427 __func__, ha->host_no, mcp->mb[1]));
428 } else { 428 } else {
429 DEBUG11(printk("%s(%ld): done.\n", __func__, 429 DEBUG11(printk("%s(%ld): done.\n", __func__,
430 ha->host_no);) 430 ha->host_no));
431 } 431 }
432 } 432 }
433 433
@@ -611,7 +611,7 @@ qla2x00_mbx_reg_test(scsi_qla_host_t *ha)
611 mbx_cmd_t mc; 611 mbx_cmd_t mc;
612 mbx_cmd_t *mcp = &mc; 612 mbx_cmd_t *mcp = &mc;
613 613
614 DEBUG11(printk("qla2x00_mbx_reg_test(%ld): entered.\n", ha->host_no);) 614 DEBUG11(printk("qla2x00_mbx_reg_test(%ld): entered.\n", ha->host_no));
615 615
616 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST; 616 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
617 mcp->mb[1] = 0xAAAA; 617 mcp->mb[1] = 0xAAAA;
@@ -639,11 +639,11 @@ qla2x00_mbx_reg_test(scsi_qla_host_t *ha)
639 if (rval != QLA_SUCCESS) { 639 if (rval != QLA_SUCCESS) {
640 /*EMPTY*/ 640 /*EMPTY*/
641 DEBUG2_3_11(printk("qla2x00_mbx_reg_test(%ld): failed=%x.\n", 641 DEBUG2_3_11(printk("qla2x00_mbx_reg_test(%ld): failed=%x.\n",
642 ha->host_no, rval);) 642 ha->host_no, rval));
643 } else { 643 } else {
644 /*EMPTY*/ 644 /*EMPTY*/
645 DEBUG11(printk("qla2x00_mbx_reg_test(%ld): done.\n", 645 DEBUG11(printk("qla2x00_mbx_reg_test(%ld): done.\n",
646 ha->host_no);) 646 ha->host_no));
647 } 647 }
648 648
649 return rval; 649 return rval;
@@ -671,7 +671,7 @@ qla2x00_verify_checksum(scsi_qla_host_t *ha, uint32_t risc_addr)
671 mbx_cmd_t mc; 671 mbx_cmd_t mc;
672 mbx_cmd_t *mcp = &mc; 672 mbx_cmd_t *mcp = &mc;
673 673
674 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no);) 674 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no));
675 675
676 mcp->mb[0] = MBC_VERIFY_CHECKSUM; 676 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
677 mcp->out_mb = MBX_0; 677 mcp->out_mb = MBX_0;
@@ -694,9 +694,9 @@ qla2x00_verify_checksum(scsi_qla_host_t *ha, uint32_t risc_addr)
694 if (rval != QLA_SUCCESS) { 694 if (rval != QLA_SUCCESS) {
695 DEBUG2_3_11(printk("%s(%ld): failed=%x chk sum=%x.\n", __func__, 695 DEBUG2_3_11(printk("%s(%ld): failed=%x chk sum=%x.\n", __func__,
696 ha->host_no, rval, (IS_QLA24XX(ha) || IS_QLA54XX(ha) ? 696 ha->host_no, rval, (IS_QLA24XX(ha) || IS_QLA54XX(ha) ?
697 (mcp->mb[2] << 16) | mcp->mb[1]: mcp->mb[1]));) 697 (mcp->mb[2] << 16) | mcp->mb[1]: mcp->mb[1])));
698 } else { 698 } else {
699 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no);) 699 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no));
700 } 700 }
701 701
702 return rval; 702 return rval;
@@ -743,9 +743,9 @@ qla2x00_issue_iocb(scsi_qla_host_t *ha, void* buffer, dma_addr_t phys_addr,
743 if (rval != QLA_SUCCESS) { 743 if (rval != QLA_SUCCESS) {
744 /*EMPTY*/ 744 /*EMPTY*/
745 DEBUG(printk("qla2x00_issue_iocb(%ld): failed rval 0x%x\n", 745 DEBUG(printk("qla2x00_issue_iocb(%ld): failed rval 0x%x\n",
746 ha->host_no, rval);) 746 ha->host_no, rval));
747 DEBUG2(printk("qla2x00_issue_iocb(%ld): failed rval 0x%x\n", 747 DEBUG2(printk("qla2x00_issue_iocb(%ld): failed rval 0x%x\n",
748 ha->host_no, rval);) 748 ha->host_no, rval));
749 } else { 749 } else {
750 sts_entry_t *sts_entry = (sts_entry_t *) buffer; 750 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
751 751
@@ -781,7 +781,7 @@ qla2x00_abort_command(scsi_qla_host_t *ha, srb_t *sp)
781 mbx_cmd_t mc; 781 mbx_cmd_t mc;
782 mbx_cmd_t *mcp = &mc; 782 mbx_cmd_t *mcp = &mc;
783 783
784 DEBUG11(printk("qla2x00_abort_command(%ld): entered.\n", ha->host_no);) 784 DEBUG11(printk("qla2x00_abort_command(%ld): entered.\n", ha->host_no));
785 785
786 fcport = sp->fcport; 786 fcport = sp->fcport;
787 787
@@ -813,11 +813,11 @@ qla2x00_abort_command(scsi_qla_host_t *ha, srb_t *sp)
813 813
814 if (rval != QLA_SUCCESS) { 814 if (rval != QLA_SUCCESS) {
815 DEBUG2_3_11(printk("qla2x00_abort_command(%ld): failed=%x.\n", 815 DEBUG2_3_11(printk("qla2x00_abort_command(%ld): failed=%x.\n",
816 ha->host_no, rval);) 816 ha->host_no, rval));
817 } else { 817 } else {
818 sp->flags |= SRB_ABORT_PENDING; 818 sp->flags |= SRB_ABORT_PENDING;
819 DEBUG11(printk("qla2x00_abort_command(%ld): done.\n", 819 DEBUG11(printk("qla2x00_abort_command(%ld): done.\n",
820 ha->host_no);) 820 ha->host_no));
821 } 821 }
822 822
823 return rval; 823 return rval;
@@ -848,7 +848,7 @@ qla2x00_abort_target(fc_port_t *fcport)
848 if (fcport == NULL) 848 if (fcport == NULL)
849 return 0; 849 return 0;
850 850
851 DEBUG11(printk("%s(%ld): entered.\n", __func__, fcport->ha->host_no);) 851 DEBUG11(printk("%s(%ld): entered.\n", __func__, fcport->ha->host_no));
852 852
853 ha = fcport->ha; 853 ha = fcport->ha;
854 mcp->mb[0] = MBC_ABORT_TARGET; 854 mcp->mb[0] = MBC_ABORT_TARGET;
@@ -872,11 +872,11 @@ qla2x00_abort_target(fc_port_t *fcport)
872 872
873 if (rval != QLA_SUCCESS) { 873 if (rval != QLA_SUCCESS) {
874 DEBUG2_3_11(printk("qla2x00_abort_target(%ld): failed=%x.\n", 874 DEBUG2_3_11(printk("qla2x00_abort_target(%ld): failed=%x.\n",
875 ha->host_no, rval);) 875 ha->host_no, rval));
876 } else { 876 } else {
877 /*EMPTY*/ 877 /*EMPTY*/
878 DEBUG11(printk("qla2x00_abort_target(%ld): done.\n", 878 DEBUG11(printk("qla2x00_abort_target(%ld): done.\n",
879 ha->host_no);) 879 ha->host_no));
880 } 880 }
881 881
882 return rval; 882 return rval;
@@ -912,7 +912,7 @@ qla2x00_get_adapter_id(scsi_qla_host_t *ha, uint16_t *id, uint8_t *al_pa,
912 mbx_cmd_t *mcp = &mc; 912 mbx_cmd_t *mcp = &mc;
913 913
914 DEBUG11(printk("qla2x00_get_adapter_id(%ld): entered.\n", 914 DEBUG11(printk("qla2x00_get_adapter_id(%ld): entered.\n",
915 ha->host_no);) 915 ha->host_no));
916 916
917 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID; 917 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
918 mcp->out_mb = MBX_0; 918 mcp->out_mb = MBX_0;
@@ -933,11 +933,11 @@ qla2x00_get_adapter_id(scsi_qla_host_t *ha, uint16_t *id, uint8_t *al_pa,
933 if (rval != QLA_SUCCESS) { 933 if (rval != QLA_SUCCESS) {
934 /*EMPTY*/ 934 /*EMPTY*/
935 DEBUG2_3_11(printk("qla2x00_get_adapter_id(%ld): failed=%x.\n", 935 DEBUG2_3_11(printk("qla2x00_get_adapter_id(%ld): failed=%x.\n",
936 ha->host_no, rval);) 936 ha->host_no, rval));
937 } else { 937 } else {
938 /*EMPTY*/ 938 /*EMPTY*/
939 DEBUG11(printk("qla2x00_get_adapter_id(%ld): done.\n", 939 DEBUG11(printk("qla2x00_get_adapter_id(%ld): done.\n",
940 ha->host_no);) 940 ha->host_no));
941 } 941 }
942 942
943 return rval; 943 return rval;
@@ -968,7 +968,7 @@ qla2x00_get_retry_cnt(scsi_qla_host_t *ha, uint8_t *retry_cnt, uint8_t *tov,
968 mbx_cmd_t *mcp = &mc; 968 mbx_cmd_t *mcp = &mc;
969 969
970 DEBUG11(printk("qla2x00_get_retry_cnt(%ld): entered.\n", 970 DEBUG11(printk("qla2x00_get_retry_cnt(%ld): entered.\n",
971 ha->host_no);) 971 ha->host_no));
972 972
973 mcp->mb[0] = MBC_GET_RETRY_COUNT; 973 mcp->mb[0] = MBC_GET_RETRY_COUNT;
974 mcp->out_mb = MBX_0; 974 mcp->out_mb = MBX_0;
@@ -980,7 +980,7 @@ qla2x00_get_retry_cnt(scsi_qla_host_t *ha, uint8_t *retry_cnt, uint8_t *tov,
980 if (rval != QLA_SUCCESS) { 980 if (rval != QLA_SUCCESS) {
981 /*EMPTY*/ 981 /*EMPTY*/
982 DEBUG2_3_11(printk("qla2x00_get_retry_cnt(%ld): failed = %x.\n", 982 DEBUG2_3_11(printk("qla2x00_get_retry_cnt(%ld): failed = %x.\n",
983 ha->host_no, mcp->mb[0]);) 983 ha->host_no, mcp->mb[0]));
984 } else { 984 } else {
985 /* Convert returned data and check our values. */ 985 /* Convert returned data and check our values. */
986 *r_a_tov = mcp->mb[3] / 2; 986 *r_a_tov = mcp->mb[3] / 2;
@@ -992,7 +992,7 @@ qla2x00_get_retry_cnt(scsi_qla_host_t *ha, uint8_t *retry_cnt, uint8_t *tov,
992 } 992 }
993 993
994 DEBUG11(printk("qla2x00_get_retry_cnt(%ld): done. mb3=%d " 994 DEBUG11(printk("qla2x00_get_retry_cnt(%ld): done. mb3=%d "
995 "ratov=%d.\n", ha->host_no, mcp->mb[3], ratov);) 995 "ratov=%d.\n", ha->host_no, mcp->mb[3], ratov));
996 } 996 }
997 997
998 return rval; 998 return rval;
@@ -1023,7 +1023,7 @@ qla2x00_init_firmware(scsi_qla_host_t *ha, uint16_t size)
1023 mbx_cmd_t *mcp = &mc; 1023 mbx_cmd_t *mcp = &mc;
1024 1024
1025 DEBUG11(printk("qla2x00_init_firmware(%ld): entered.\n", 1025 DEBUG11(printk("qla2x00_init_firmware(%ld): entered.\n",
1026 ha->host_no);) 1026 ha->host_no));
1027 1027
1028 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE; 1028 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1029 mcp->mb[2] = MSW(ha->init_cb_dma); 1029 mcp->mb[2] = MSW(ha->init_cb_dma);
@@ -1043,11 +1043,11 @@ qla2x00_init_firmware(scsi_qla_host_t *ha, uint16_t size)
1043 /*EMPTY*/ 1043 /*EMPTY*/
1044 DEBUG2_3_11(printk("qla2x00_init_firmware(%ld): failed=%x " 1044 DEBUG2_3_11(printk("qla2x00_init_firmware(%ld): failed=%x "
1045 "mb0=%x.\n", 1045 "mb0=%x.\n",
1046 ha->host_no, rval, mcp->mb[0]);) 1046 ha->host_no, rval, mcp->mb[0]));
1047 } else { 1047 } else {
1048 /*EMPTY*/ 1048 /*EMPTY*/
1049 DEBUG11(printk("qla2x00_init_firmware(%ld): done.\n", 1049 DEBUG11(printk("qla2x00_init_firmware(%ld): done.\n",
1050 ha->host_no);) 1050 ha->host_no));
1051 } 1051 }
1052 1052
1053 return rval; 1053 return rval;
@@ -1079,7 +1079,7 @@ qla2x00_get_port_database(scsi_qla_host_t *ha, fc_port_t *fcport, uint8_t opt)
1079 struct port_database_24xx *pd24; 1079 struct port_database_24xx *pd24;
1080 dma_addr_t pd_dma; 1080 dma_addr_t pd_dma;
1081 1081
1082 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no);) 1082 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no));
1083 1083
1084 pd24 = NULL; 1084 pd24 = NULL;
1085 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1085 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
@@ -1220,7 +1220,7 @@ qla2x00_get_firmware_state(scsi_qla_host_t *ha, uint16_t *dptr)
1220 mbx_cmd_t *mcp = &mc; 1220 mbx_cmd_t *mcp = &mc;
1221 1221
1222 DEBUG11(printk("qla2x00_get_firmware_state(%ld): entered.\n", 1222 DEBUG11(printk("qla2x00_get_firmware_state(%ld): entered.\n",
1223 ha->host_no);) 1223 ha->host_no));
1224 1224
1225 mcp->mb[0] = MBC_GET_FIRMWARE_STATE; 1225 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
1226 mcp->out_mb = MBX_0; 1226 mcp->out_mb = MBX_0;
@@ -1235,11 +1235,11 @@ qla2x00_get_firmware_state(scsi_qla_host_t *ha, uint16_t *dptr)
1235 if (rval != QLA_SUCCESS) { 1235 if (rval != QLA_SUCCESS) {
1236 /*EMPTY*/ 1236 /*EMPTY*/
1237 DEBUG2_3_11(printk("qla2x00_get_firmware_state(%ld): " 1237 DEBUG2_3_11(printk("qla2x00_get_firmware_state(%ld): "
1238 "failed=%x.\n", ha->host_no, rval);) 1238 "failed=%x.\n", ha->host_no, rval));
1239 } else { 1239 } else {
1240 /*EMPTY*/ 1240 /*EMPTY*/
1241 DEBUG11(printk("qla2x00_get_firmware_state(%ld): done.\n", 1241 DEBUG11(printk("qla2x00_get_firmware_state(%ld): done.\n",
1242 ha->host_no);) 1242 ha->host_no));
1243 } 1243 }
1244 1244
1245 return rval; 1245 return rval;
@@ -1272,7 +1272,7 @@ qla2x00_get_port_name(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t *name,
1272 mbx_cmd_t *mcp = &mc; 1272 mbx_cmd_t *mcp = &mc;
1273 1273
1274 DEBUG11(printk("qla2x00_get_port_name(%ld): entered.\n", 1274 DEBUG11(printk("qla2x00_get_port_name(%ld): entered.\n",
1275 ha->host_no);) 1275 ha->host_no));
1276 1276
1277 mcp->mb[0] = MBC_GET_PORT_NAME; 1277 mcp->mb[0] = MBC_GET_PORT_NAME;
1278 mcp->out_mb = MBX_1|MBX_0; 1278 mcp->out_mb = MBX_1|MBX_0;
@@ -1292,7 +1292,7 @@ qla2x00_get_port_name(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t *name,
1292 if (rval != QLA_SUCCESS) { 1292 if (rval != QLA_SUCCESS) {
1293 /*EMPTY*/ 1293 /*EMPTY*/
1294 DEBUG2_3_11(printk("qla2x00_get_port_name(%ld): failed=%x.\n", 1294 DEBUG2_3_11(printk("qla2x00_get_port_name(%ld): failed=%x.\n",
1295 ha->host_no, rval);) 1295 ha->host_no, rval));
1296 } else { 1296 } else {
1297 if (name != NULL) { 1297 if (name != NULL) {
1298 /* This function returns name in big endian. */ 1298 /* This function returns name in big endian. */
@@ -1307,7 +1307,7 @@ qla2x00_get_port_name(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t *name,
1307 } 1307 }
1308 1308
1309 DEBUG11(printk("qla2x00_get_port_name(%ld): done.\n", 1309 DEBUG11(printk("qla2x00_get_port_name(%ld): done.\n",
1310 ha->host_no);) 1310 ha->host_no));
1311 } 1311 }
1312 1312
1313 return rval; 1313 return rval;
@@ -1335,7 +1335,7 @@ qla2x00_lip_reset(scsi_qla_host_t *ha)
1335 mbx_cmd_t mc; 1335 mbx_cmd_t mc;
1336 mbx_cmd_t *mcp = &mc; 1336 mbx_cmd_t *mcp = &mc;
1337 1337
1338 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no);) 1338 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no));
1339 1339
1340 if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 1340 if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) {
1341 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 1341 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
@@ -1364,10 +1364,10 @@ qla2x00_lip_reset(scsi_qla_host_t *ha)
1364 if (rval != QLA_SUCCESS) { 1364 if (rval != QLA_SUCCESS) {
1365 /*EMPTY*/ 1365 /*EMPTY*/
1366 DEBUG2_3_11(printk("%s(%ld): failed=%x.\n", 1366 DEBUG2_3_11(printk("%s(%ld): failed=%x.\n",
1367 __func__, ha->host_no, rval);) 1367 __func__, ha->host_no, rval));
1368 } else { 1368 } else {
1369 /*EMPTY*/ 1369 /*EMPTY*/
1370 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no);) 1370 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no));
1371 } 1371 }
1372 1372
1373 return rval; 1373 return rval;
@@ -1400,10 +1400,10 @@ qla2x00_send_sns(scsi_qla_host_t *ha, dma_addr_t sns_phys_address,
1400 mbx_cmd_t *mcp = &mc; 1400 mbx_cmd_t *mcp = &mc;
1401 1401
1402 DEBUG11(printk("qla2x00_send_sns(%ld): entered.\n", 1402 DEBUG11(printk("qla2x00_send_sns(%ld): entered.\n",
1403 ha->host_no);) 1403 ha->host_no));
1404 1404
1405 DEBUG11(printk("qla2x00_send_sns: retry cnt=%d ratov=%d total " 1405 DEBUG11(printk("qla2x00_send_sns: retry cnt=%d ratov=%d total "
1406 "tov=%d.\n", ha->retry_count, ha->login_timeout, mcp->tov);) 1406 "tov=%d.\n", ha->retry_count, ha->login_timeout, mcp->tov));
1407 1407
1408 mcp->mb[0] = MBC_SEND_SNS_COMMAND; 1408 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
1409 mcp->mb[1] = cmd_size; 1409 mcp->mb[1] = cmd_size;
@@ -1421,12 +1421,12 @@ qla2x00_send_sns(scsi_qla_host_t *ha, dma_addr_t sns_phys_address,
1421 if (rval != QLA_SUCCESS) { 1421 if (rval != QLA_SUCCESS) {
1422 /*EMPTY*/ 1422 /*EMPTY*/
1423 DEBUG(printk("qla2x00_send_sns(%ld): failed=%x mb[0]=%x " 1423 DEBUG(printk("qla2x00_send_sns(%ld): failed=%x mb[0]=%x "
1424 "mb[1]=%x.\n", ha->host_no, rval, mcp->mb[0], mcp->mb[1]);) 1424 "mb[1]=%x.\n", ha->host_no, rval, mcp->mb[0], mcp->mb[1]));
1425 DEBUG2_3_11(printk("qla2x00_send_sns(%ld): failed=%x mb[0]=%x " 1425 DEBUG2_3_11(printk("qla2x00_send_sns(%ld): failed=%x mb[0]=%x "
1426 "mb[1]=%x.\n", ha->host_no, rval, mcp->mb[0], mcp->mb[1]);) 1426 "mb[1]=%x.\n", ha->host_no, rval, mcp->mb[0], mcp->mb[1]));
1427 } else { 1427 } else {
1428 /*EMPTY*/ 1428 /*EMPTY*/
1429 DEBUG11(printk("qla2x00_send_sns(%ld): done.\n", ha->host_no);) 1429 DEBUG11(printk("qla2x00_send_sns(%ld): done.\n", ha->host_no));
1430 } 1430 }
1431 1431
1432 return rval; 1432 return rval;
@@ -1442,7 +1442,7 @@ qla24xx_login_fabric(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t domain,
1442 dma_addr_t lg_dma; 1442 dma_addr_t lg_dma;
1443 uint32_t iop[2]; 1443 uint32_t iop[2];
1444 1444
1445 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no);) 1445 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no));
1446 1446
1447 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 1447 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1448 if (lg == NULL) { 1448 if (lg == NULL) {
@@ -1458,13 +1458,15 @@ qla24xx_login_fabric(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t domain,
1458 lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI); 1458 lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
1459 if (opt & BIT_0) 1459 if (opt & BIT_0)
1460 lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI); 1460 lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
1461 if (opt & BIT_1)
1462 lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
1461 lg->port_id[0] = al_pa; 1463 lg->port_id[0] = al_pa;
1462 lg->port_id[1] = area; 1464 lg->port_id[1] = area;
1463 lg->port_id[2] = domain; 1465 lg->port_id[2] = domain;
1464 rval = qla2x00_issue_iocb(ha, lg, lg_dma, 0); 1466 rval = qla2x00_issue_iocb(ha, lg, lg_dma, 0);
1465 if (rval != QLA_SUCCESS) { 1467 if (rval != QLA_SUCCESS) {
1466 DEBUG2_3_11(printk("%s(%ld): failed to issue Login IOCB " 1468 DEBUG2_3_11(printk("%s(%ld): failed to issue Login IOCB "
1467 "(%x).\n", __func__, ha->host_no, rval);) 1469 "(%x).\n", __func__, ha->host_no, rval));
1468 } else if (lg->entry_status != 0) { 1470 } else if (lg->entry_status != 0) {
1469 DEBUG2_3_11(printk("%s(%ld): failed to complete IOCB " 1471 DEBUG2_3_11(printk("%s(%ld): failed to complete IOCB "
1470 "-- error status (%x).\n", __func__, ha->host_no, 1472 "-- error status (%x).\n", __func__, ha->host_no,
@@ -1505,7 +1507,7 @@ qla24xx_login_fabric(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t domain,
1505 break; 1507 break;
1506 } 1508 }
1507 } else { 1509 } else {
1508 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no);) 1510 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no));
1509 1511
1510 iop[0] = le32_to_cpu(lg->io_parameter[0]); 1512 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1511 1513
@@ -1559,7 +1561,7 @@ qla2x00_login_fabric(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t domain,
1559 mbx_cmd_t mc; 1561 mbx_cmd_t mc;
1560 mbx_cmd_t *mcp = &mc; 1562 mbx_cmd_t *mcp = &mc;
1561 1563
1562 DEBUG11(printk("qla2x00_login_fabric(%ld): entered.\n", ha->host_no);) 1564 DEBUG11(printk("qla2x00_login_fabric(%ld): entered.\n", ha->host_no));
1563 1565
1564 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT; 1566 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
1565 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1567 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
@@ -1604,11 +1606,11 @@ qla2x00_login_fabric(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t domain,
1604 /*EMPTY*/ 1606 /*EMPTY*/
1605 DEBUG2_3_11(printk("qla2x00_login_fabric(%ld): failed=%x " 1607 DEBUG2_3_11(printk("qla2x00_login_fabric(%ld): failed=%x "
1606 "mb[0]=%x mb[1]=%x mb[2]=%x.\n", ha->host_no, rval, 1608 "mb[0]=%x mb[1]=%x mb[2]=%x.\n", ha->host_no, rval,
1607 mcp->mb[0], mcp->mb[1], mcp->mb[2]);) 1609 mcp->mb[0], mcp->mb[1], mcp->mb[2]));
1608 } else { 1610 } else {
1609 /*EMPTY*/ 1611 /*EMPTY*/
1610 DEBUG11(printk("qla2x00_login_fabric(%ld): done.\n", 1612 DEBUG11(printk("qla2x00_login_fabric(%ld): done.\n",
1611 ha->host_no);) 1613 ha->host_no));
1612 } 1614 }
1613 1615
1614 return rval; 1616 return rval;
@@ -1643,7 +1645,7 @@ qla2x00_login_local_device(scsi_qla_host_t *ha, fc_port_t *fcport,
1643 fcport->d_id.b.domain, fcport->d_id.b.area, 1645 fcport->d_id.b.domain, fcport->d_id.b.area,
1644 fcport->d_id.b.al_pa, mb_ret, opt); 1646 fcport->d_id.b.al_pa, mb_ret, opt);
1645 1647
1646 DEBUG3(printk("%s(%ld): entered.\n", __func__, ha->host_no);) 1648 DEBUG3(printk("%s(%ld): entered.\n", __func__, ha->host_no));
1647 1649
1648 mcp->mb[0] = MBC_LOGIN_LOOP_PORT; 1650 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
1649 if (HAS_EXTENDED_IDS(ha)) 1651 if (HAS_EXTENDED_IDS(ha))
@@ -1677,13 +1679,13 @@ qla2x00_login_local_device(scsi_qla_host_t *ha, fc_port_t *fcport,
1677 1679
1678 DEBUG(printk("%s(%ld): failed=%x mb[0]=%x mb[1]=%x " 1680 DEBUG(printk("%s(%ld): failed=%x mb[0]=%x mb[1]=%x "
1679 "mb[6]=%x mb[7]=%x.\n", __func__, ha->host_no, rval, 1681 "mb[6]=%x mb[7]=%x.\n", __func__, ha->host_no, rval,
1680 mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);) 1682 mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]));
1681 DEBUG2_3(printk("%s(%ld): failed=%x mb[0]=%x mb[1]=%x " 1683 DEBUG2_3(printk("%s(%ld): failed=%x mb[0]=%x mb[1]=%x "
1682 "mb[6]=%x mb[7]=%x.\n", __func__, ha->host_no, rval, 1684 "mb[6]=%x mb[7]=%x.\n", __func__, ha->host_no, rval,
1683 mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);) 1685 mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]));
1684 } else { 1686 } else {
1685 /*EMPTY*/ 1687 /*EMPTY*/
1686 DEBUG3(printk("%s(%ld): done.\n", __func__, ha->host_no);) 1688 DEBUG3(printk("%s(%ld): done.\n", __func__, ha->host_no));
1687 } 1689 }
1688 1690
1689 return (rval); 1691 return (rval);
@@ -1697,7 +1699,7 @@ qla24xx_fabric_logout(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t domain,
1697 struct logio_entry_24xx *lg; 1699 struct logio_entry_24xx *lg;
1698 dma_addr_t lg_dma; 1700 dma_addr_t lg_dma;
1699 1701
1700 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no);) 1702 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no));
1701 1703
1702 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 1704 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1703 if (lg == NULL) { 1705 if (lg == NULL) {
@@ -1718,7 +1720,7 @@ qla24xx_fabric_logout(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t domain,
1718 rval = qla2x00_issue_iocb(ha, lg, lg_dma, 0); 1720 rval = qla2x00_issue_iocb(ha, lg, lg_dma, 0);
1719 if (rval != QLA_SUCCESS) { 1721 if (rval != QLA_SUCCESS) {
1720 DEBUG2_3_11(printk("%s(%ld): failed to issue Logout IOCB " 1722 DEBUG2_3_11(printk("%s(%ld): failed to issue Logout IOCB "
1721 "(%x).\n", __func__, ha->host_no, rval);) 1723 "(%x).\n", __func__, ha->host_no, rval));
1722 } else if (lg->entry_status != 0) { 1724 } else if (lg->entry_status != 0) {
1723 DEBUG2_3_11(printk("%s(%ld): failed to complete IOCB " 1725 DEBUG2_3_11(printk("%s(%ld): failed to complete IOCB "
1724 "-- error status (%x).\n", __func__, ha->host_no, 1726 "-- error status (%x).\n", __func__, ha->host_no,
@@ -1729,10 +1731,10 @@ qla24xx_fabric_logout(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t domain,
1729 "-- completion status (%x) ioparam=%x/%x.\n", __func__, 1731 "-- completion status (%x) ioparam=%x/%x.\n", __func__,
1730 ha->host_no, le16_to_cpu(lg->comp_status), 1732 ha->host_no, le16_to_cpu(lg->comp_status),
1731 le32_to_cpu(lg->io_parameter[0]), 1733 le32_to_cpu(lg->io_parameter[0]),
1732 le32_to_cpu(lg->io_parameter[1]));) 1734 le32_to_cpu(lg->io_parameter[1])));
1733 } else { 1735 } else {
1734 /*EMPTY*/ 1736 /*EMPTY*/
1735 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no);) 1737 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no));
1736 } 1738 }
1737 1739
1738 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 1740 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
@@ -1765,7 +1767,7 @@ qla2x00_fabric_logout(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t domain,
1765 mbx_cmd_t *mcp = &mc; 1767 mbx_cmd_t *mcp = &mc;
1766 1768
1767 DEBUG11(printk("qla2x00_fabric_logout(%ld): entered.\n", 1769 DEBUG11(printk("qla2x00_fabric_logout(%ld): entered.\n",
1768 ha->host_no);) 1770 ha->host_no));
1769 1771
1770 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT; 1772 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
1771 mcp->out_mb = MBX_1|MBX_0; 1773 mcp->out_mb = MBX_1|MBX_0;
@@ -1785,11 +1787,11 @@ qla2x00_fabric_logout(scsi_qla_host_t *ha, uint16_t loop_id, uint8_t domain,
1785 if (rval != QLA_SUCCESS) { 1787 if (rval != QLA_SUCCESS) {
1786 /*EMPTY*/ 1788 /*EMPTY*/
1787 DEBUG2_3_11(printk("qla2x00_fabric_logout(%ld): failed=%x " 1789 DEBUG2_3_11(printk("qla2x00_fabric_logout(%ld): failed=%x "
1788 "mbx1=%x.\n", ha->host_no, rval, mcp->mb[1]);) 1790 "mbx1=%x.\n", ha->host_no, rval, mcp->mb[1]));
1789 } else { 1791 } else {
1790 /*EMPTY*/ 1792 /*EMPTY*/
1791 DEBUG11(printk("qla2x00_fabric_logout(%ld): done.\n", 1793 DEBUG11(printk("qla2x00_fabric_logout(%ld): done.\n",
1792 ha->host_no);) 1794 ha->host_no));
1793 } 1795 }
1794 1796
1795 return rval; 1797 return rval;
@@ -1818,7 +1820,7 @@ qla2x00_full_login_lip(scsi_qla_host_t *ha)
1818 mbx_cmd_t *mcp = &mc; 1820 mbx_cmd_t *mcp = &mc;
1819 1821
1820 DEBUG11(printk("qla2x00_full_login_lip(%ld): entered.\n", 1822 DEBUG11(printk("qla2x00_full_login_lip(%ld): entered.\n",
1821 ha->host_no);) 1823 ha->host_no));
1822 1824
1823 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 1825 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1824 mcp->mb[1] = 0; 1826 mcp->mb[1] = 0;
@@ -1833,11 +1835,11 @@ qla2x00_full_login_lip(scsi_qla_host_t *ha)
1833 if (rval != QLA_SUCCESS) { 1835 if (rval != QLA_SUCCESS) {
1834 /*EMPTY*/ 1836 /*EMPTY*/
1835 DEBUG2_3_11(printk("qla2x00_full_login_lip(%ld): failed=%x.\n", 1837 DEBUG2_3_11(printk("qla2x00_full_login_lip(%ld): failed=%x.\n",
1836 ha->host_no, rval);) 1838 ha->host_no, rval));
1837 } else { 1839 } else {
1838 /*EMPTY*/ 1840 /*EMPTY*/
1839 DEBUG11(printk("qla2x00_full_login_lip(%ld): done.\n", 1841 DEBUG11(printk("qla2x00_full_login_lip(%ld): done.\n",
1840 ha->host_no);) 1842 ha->host_no));
1841 } 1843 }
1842 1844
1843 return rval; 1845 return rval;
@@ -1864,7 +1866,7 @@ qla2x00_get_id_list(scsi_qla_host_t *ha, void *id_list, dma_addr_t id_list_dma,
1864 mbx_cmd_t *mcp = &mc; 1866 mbx_cmd_t *mcp = &mc;
1865 1867
1866 DEBUG11(printk("qla2x00_get_id_list(%ld): entered.\n", 1868 DEBUG11(printk("qla2x00_get_id_list(%ld): entered.\n",
1867 ha->host_no);) 1869 ha->host_no));
1868 1870
1869 if (id_list == NULL) 1871 if (id_list == NULL)
1870 return QLA_FUNCTION_FAILED; 1872 return QLA_FUNCTION_FAILED;
@@ -1893,11 +1895,11 @@ qla2x00_get_id_list(scsi_qla_host_t *ha, void *id_list, dma_addr_t id_list_dma,
1893 if (rval != QLA_SUCCESS) { 1895 if (rval != QLA_SUCCESS) {
1894 /*EMPTY*/ 1896 /*EMPTY*/
1895 DEBUG2_3_11(printk("qla2x00_get_id_list(%ld): failed=%x.\n", 1897 DEBUG2_3_11(printk("qla2x00_get_id_list(%ld): failed=%x.\n",
1896 ha->host_no, rval);) 1898 ha->host_no, rval));
1897 } else { 1899 } else {
1898 *entries = mcp->mb[1]; 1900 *entries = mcp->mb[1];
1899 DEBUG11(printk("qla2x00_get_id_list(%ld): done.\n", 1901 DEBUG11(printk("qla2x00_get_id_list(%ld): done.\n",
1900 ha->host_no);) 1902 ha->host_no));
1901 } 1903 }
1902 1904
1903 return rval; 1905 return rval;
@@ -1936,7 +1938,7 @@ qla2x00_get_resource_cnts(scsi_qla_host_t *ha, uint16_t *cur_xchg_cnt,
1936 if (rval != QLA_SUCCESS) { 1938 if (rval != QLA_SUCCESS) {
1937 /*EMPTY*/ 1939 /*EMPTY*/
1938 DEBUG2_3_11(printk("%s(%ld): failed = %x.\n", __func__, 1940 DEBUG2_3_11(printk("%s(%ld): failed = %x.\n", __func__,
1939 ha->host_no, mcp->mb[0]);) 1941 ha->host_no, mcp->mb[0]));
1940 } else { 1942 } else {
1941 DEBUG11(printk("%s(%ld): done. mb1=%x mb2=%x mb3=%x mb6=%x " 1943 DEBUG11(printk("%s(%ld): done. mb1=%x mb2=%x mb3=%x mb6=%x "
1942 "mb7=%x mb10=%x.\n", __func__, ha->host_no, 1944 "mb7=%x mb10=%x.\n", __func__, ha->host_no,
@@ -2045,7 +2047,7 @@ qla2x00_get_link_status(scsi_qla_host_t *ha, uint16_t loop_id,
2045 link_stat_t *stat_buf; 2047 link_stat_t *stat_buf;
2046 dma_addr_t stat_buf_dma; 2048 dma_addr_t stat_buf_dma;
2047 2049
2048 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no);) 2050 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no));
2049 2051
2050 stat_buf = dma_pool_alloc(ha->s_dma_pool, GFP_ATOMIC, &stat_buf_dma); 2052 stat_buf = dma_pool_alloc(ha->s_dma_pool, GFP_ATOMIC, &stat_buf_dma);
2051 if (stat_buf == NULL) { 2053 if (stat_buf == NULL) {
@@ -2083,7 +2085,7 @@ qla2x00_get_link_status(scsi_qla_host_t *ha, uint16_t loop_id,
2083 if (rval == QLA_SUCCESS) { 2085 if (rval == QLA_SUCCESS) {
2084 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2086 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
2085 DEBUG2_3_11(printk("%s(%ld): cmd failed. mbx0=%x.\n", 2087 DEBUG2_3_11(printk("%s(%ld): cmd failed. mbx0=%x.\n",
2086 __func__, ha->host_no, mcp->mb[0]);) 2088 __func__, ha->host_no, mcp->mb[0]));
2087 status[0] = mcp->mb[0]; 2089 status[0] = mcp->mb[0];
2088 rval = BIT_1; 2090 rval = BIT_1;
2089 } else { 2091 } else {
@@ -2108,12 +2110,12 @@ qla2x00_get_link_status(scsi_qla_host_t *ha, uint16_t loop_id,
2108 stat_buf->loss_sync_cnt, stat_buf->loss_sig_cnt, 2110 stat_buf->loss_sync_cnt, stat_buf->loss_sig_cnt,
2109 stat_buf->prim_seq_err_cnt, 2111 stat_buf->prim_seq_err_cnt,
2110 stat_buf->inval_xmit_word_cnt, 2112 stat_buf->inval_xmit_word_cnt,
2111 stat_buf->inval_crc_cnt);) 2113 stat_buf->inval_crc_cnt));
2112 } 2114 }
2113 } else { 2115 } else {
2114 /* Failed. */ 2116 /* Failed. */
2115 DEBUG2_3_11(printk("%s(%ld): failed=%x.\n", __func__, 2117 DEBUG2_3_11(printk("%s(%ld): failed=%x.\n", __func__,
2116 ha->host_no, rval);) 2118 ha->host_no, rval));
2117 rval = BIT_1; 2119 rval = BIT_1;
2118 } 2120 }
2119 2121
@@ -2132,7 +2134,7 @@ qla24xx_get_isp_stats(scsi_qla_host_t *ha, uint32_t *dwbuf, uint32_t dwords,
2132 uint32_t *sbuf, *siter; 2134 uint32_t *sbuf, *siter;
2133 dma_addr_t sbuf_dma; 2135 dma_addr_t sbuf_dma;
2134 2136
2135 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no);) 2137 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no));
2136 2138
2137 if (dwords > (DMA_POOL_SIZE / 4)) { 2139 if (dwords > (DMA_POOL_SIZE / 4)) {
2138 DEBUG2_3_11(printk("%s(%ld): Unabled to retrieve %d DWORDs " 2140 DEBUG2_3_11(printk("%s(%ld): Unabled to retrieve %d DWORDs "
@@ -2196,7 +2198,7 @@ qla24xx_abort_command(scsi_qla_host_t *ha, srb_t *sp)
2196 dma_addr_t abt_dma; 2198 dma_addr_t abt_dma;
2197 uint32_t handle; 2199 uint32_t handle;
2198 2200
2199 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no);) 2201 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no));
2200 2202
2201 fcport = sp->fcport; 2203 fcport = sp->fcport;
2202 2204
@@ -2229,7 +2231,7 @@ qla24xx_abort_command(scsi_qla_host_t *ha, srb_t *sp)
2229 rval = qla2x00_issue_iocb(ha, abt, abt_dma, 0); 2231 rval = qla2x00_issue_iocb(ha, abt, abt_dma, 0);
2230 if (rval != QLA_SUCCESS) { 2232 if (rval != QLA_SUCCESS) {
2231 DEBUG2_3_11(printk("%s(%ld): failed to issue IOCB (%x).\n", 2233 DEBUG2_3_11(printk("%s(%ld): failed to issue IOCB (%x).\n",
2232 __func__, ha->host_no, rval);) 2234 __func__, ha->host_no, rval));
2233 } else if (abt->entry_status != 0) { 2235 } else if (abt->entry_status != 0) {
2234 DEBUG2_3_11(printk("%s(%ld): failed to complete IOCB " 2236 DEBUG2_3_11(printk("%s(%ld): failed to complete IOCB "
2235 "-- error status (%x).\n", __func__, ha->host_no, 2237 "-- error status (%x).\n", __func__, ha->host_no,
@@ -2238,10 +2240,10 @@ qla24xx_abort_command(scsi_qla_host_t *ha, srb_t *sp)
2238 } else if (abt->nport_handle != __constant_cpu_to_le16(0)) { 2240 } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
2239 DEBUG2_3_11(printk("%s(%ld): failed to complete IOCB " 2241 DEBUG2_3_11(printk("%s(%ld): failed to complete IOCB "
2240 "-- completion status (%x).\n", __func__, ha->host_no, 2242 "-- completion status (%x).\n", __func__, ha->host_no,
2241 le16_to_cpu(abt->nport_handle));) 2243 le16_to_cpu(abt->nport_handle)));
2242 rval = QLA_FUNCTION_FAILED; 2244 rval = QLA_FUNCTION_FAILED;
2243 } else { 2245 } else {
2244 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no);) 2246 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no));
2245 sp->flags |= SRB_ABORT_PENDING; 2247 sp->flags |= SRB_ABORT_PENDING;
2246 } 2248 }
2247 2249
@@ -2268,7 +2270,7 @@ qla24xx_abort_target(fc_port_t *fcport)
2268 if (fcport == NULL) 2270 if (fcport == NULL)
2269 return 0; 2271 return 0;
2270 2272
2271 DEBUG11(printk("%s(%ld): entered.\n", __func__, fcport->ha->host_no);) 2273 DEBUG11(printk("%s(%ld): entered.\n", __func__, fcport->ha->host_no));
2272 2274
2273 ha = fcport->ha; 2275 ha = fcport->ha;
2274 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma); 2276 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
@@ -2290,7 +2292,7 @@ qla24xx_abort_target(fc_port_t *fcport)
2290 rval = qla2x00_issue_iocb(ha, tsk, tsk_dma, 0); 2292 rval = qla2x00_issue_iocb(ha, tsk, tsk_dma, 0);
2291 if (rval != QLA_SUCCESS) { 2293 if (rval != QLA_SUCCESS) {
2292 DEBUG2_3_11(printk("%s(%ld): failed to issue Target Reset IOCB " 2294 DEBUG2_3_11(printk("%s(%ld): failed to issue Target Reset IOCB "
2293 "(%x).\n", __func__, ha->host_no, rval);) 2295 "(%x).\n", __func__, ha->host_no, rval));
2294 goto atarget_done; 2296 goto atarget_done;
2295 } else if (tsk->p.sts.entry_status != 0) { 2297 } else if (tsk->p.sts.entry_status != 0) {
2296 DEBUG2_3_11(printk("%s(%ld): failed to complete IOCB " 2298 DEBUG2_3_11(printk("%s(%ld): failed to complete IOCB "
@@ -2302,7 +2304,7 @@ qla24xx_abort_target(fc_port_t *fcport)
2302 __constant_cpu_to_le16(CS_COMPLETE)) { 2304 __constant_cpu_to_le16(CS_COMPLETE)) {
2303 DEBUG2_3_11(printk("%s(%ld): failed to complete IOCB " 2305 DEBUG2_3_11(printk("%s(%ld): failed to complete IOCB "
2304 "-- completion status (%x).\n", __func__, 2306 "-- completion status (%x).\n", __func__,
2305 ha->host_no, le16_to_cpu(tsk->p.sts.comp_status));) 2307 ha->host_no, le16_to_cpu(tsk->p.sts.comp_status)));
2306 rval = QLA_FUNCTION_FAILED; 2308 rval = QLA_FUNCTION_FAILED;
2307 goto atarget_done; 2309 goto atarget_done;
2308 } 2310 }
@@ -2311,9 +2313,9 @@ qla24xx_abort_target(fc_port_t *fcport)
2311 rval = qla2x00_marker(ha, fcport->loop_id, 0, MK_SYNC_ID); 2313 rval = qla2x00_marker(ha, fcport->loop_id, 0, MK_SYNC_ID);
2312 if (rval != QLA_SUCCESS) { 2314 if (rval != QLA_SUCCESS) {
2313 DEBUG2_3_11(printk("%s(%ld): failed to issue Marker IOCB " 2315 DEBUG2_3_11(printk("%s(%ld): failed to issue Marker IOCB "
2314 "(%x).\n", __func__, ha->host_no, rval);) 2316 "(%x).\n", __func__, ha->host_no, rval));
2315 } else { 2317 } else {
2316 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no);) 2318 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no));
2317 } 2319 }
2318 2320
2319atarget_done: 2321atarget_done:
@@ -2460,3 +2462,81 @@ qla2x00_stop_firmware(scsi_qla_host_t *ha)
2460 2462
2461 return rval; 2463 return rval;
2462} 2464}
2465
2466int
2467qla2x00_trace_control(scsi_qla_host_t *ha, uint16_t ctrl, dma_addr_t eft_dma,
2468 uint16_t buffers)
2469{
2470 int rval;
2471 mbx_cmd_t mc;
2472 mbx_cmd_t *mcp = &mc;
2473
2474 if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha))
2475 return QLA_FUNCTION_FAILED;
2476
2477 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no));
2478
2479 mcp->mb[0] = MBC_TRACE_CONTROL;
2480 mcp->mb[1] = ctrl;
2481 mcp->out_mb = MBX_1|MBX_0;
2482 mcp->in_mb = MBX_1|MBX_0;
2483 if (ctrl == TC_ENABLE) {
2484 mcp->mb[2] = LSW(eft_dma);
2485 mcp->mb[3] = MSW(eft_dma);
2486 mcp->mb[4] = LSW(MSD(eft_dma));
2487 mcp->mb[5] = MSW(MSD(eft_dma));
2488 mcp->mb[6] = buffers;
2489 mcp->mb[7] = buffers;
2490 mcp->out_mb |= MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2;
2491 }
2492 mcp->tov = 30;
2493 mcp->flags = 0;
2494 rval = qla2x00_mailbox_command(ha, mcp);
2495
2496 if (rval != QLA_SUCCESS) {
2497 DEBUG2_3_11(printk("%s(%ld): failed=%x mb[0]=%x mb[1]=%x.\n",
2498 __func__, ha->host_no, rval, mcp->mb[0], mcp->mb[1]));
2499 } else {
2500 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no));
2501 }
2502
2503 return rval;
2504}
2505
2506int
2507qla2x00_read_sfp(scsi_qla_host_t *ha, dma_addr_t sfp_dma, uint16_t addr,
2508 uint16_t off, uint16_t count)
2509{
2510 int rval;
2511 mbx_cmd_t mc;
2512 mbx_cmd_t *mcp = &mc;
2513
2514 if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha))
2515 return QLA_FUNCTION_FAILED;
2516
2517 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no));
2518
2519 mcp->mb[0] = MBC_READ_SFP;
2520 mcp->mb[1] = addr;
2521 mcp->mb[2] = MSW(sfp_dma);
2522 mcp->mb[3] = LSW(sfp_dma);
2523 mcp->mb[6] = MSW(MSD(sfp_dma));
2524 mcp->mb[7] = LSW(MSD(sfp_dma));
2525 mcp->mb[8] = count;
2526 mcp->mb[9] = off;
2527 mcp->mb[10] = 0;
2528 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2529 mcp->in_mb = MBX_0;
2530 mcp->tov = 30;
2531 mcp->flags = 0;
2532 rval = qla2x00_mailbox_command(ha, mcp);
2533
2534 if (rval != QLA_SUCCESS) {
2535 DEBUG2_3_11(printk("%s(%ld): failed=%x (%x).\n", __func__,
2536 ha->host_no, rval, mcp->mb[0]));
2537 } else {
2538 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no));
2539 }
2540
2541 return rval;
2542}
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
index 93062593ebe7..ec7ebb6037e6 100644
--- a/drivers/scsi/qla2xxx/qla_os.c
+++ b/drivers/scsi/qla2xxx/qla_os.c
@@ -39,14 +39,14 @@ MODULE_PARM_DESC(ql2xlogintimeout,
39int qlport_down_retry = 30; 39int qlport_down_retry = 30;
40module_param(qlport_down_retry, int, S_IRUGO|S_IRUSR); 40module_param(qlport_down_retry, int, S_IRUGO|S_IRUSR);
41MODULE_PARM_DESC(qlport_down_retry, 41MODULE_PARM_DESC(qlport_down_retry,
42 "Maximum number of command retries to a port that returns" 42 "Maximum number of command retries to a port that returns "
43 "a PORT-DOWN status."); 43 "a PORT-DOWN status.");
44 44
45int ql2xplogiabsentdevice; 45int ql2xplogiabsentdevice;
46module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 46module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
47MODULE_PARM_DESC(ql2xplogiabsentdevice, 47MODULE_PARM_DESC(ql2xplogiabsentdevice,
48 "Option to enable PLOGI to devices that are not present after " 48 "Option to enable PLOGI to devices that are not present after "
49 "a Fabric scan. This is needed for several broken switches." 49 "a Fabric scan. This is needed for several broken switches. "
50 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 50 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
51 51
52int ql2xloginretrycount = 0; 52int ql2xloginretrycount = 0;
@@ -54,6 +54,19 @@ module_param(ql2xloginretrycount, int, S_IRUGO|S_IRUSR);
54MODULE_PARM_DESC(ql2xloginretrycount, 54MODULE_PARM_DESC(ql2xloginretrycount,
55 "Specify an alternate value for the NVRAM login retry count."); 55 "Specify an alternate value for the NVRAM login retry count.");
56 56
57int ql2xallocfwdump = 1;
58module_param(ql2xallocfwdump, int, S_IRUGO|S_IRUSR);
59MODULE_PARM_DESC(ql2xallocfwdump,
60 "Option to enable allocation of memory for a firmware dump "
61 "during HBA initialization. Memory allocation requirements "
62 "vary by ISP type. Default is 1 - allocate memory.");
63
64int extended_error_logging;
65module_param(extended_error_logging, int, S_IRUGO|S_IRUSR);
66MODULE_PARM_DESC(extended_error_logging,
67 "Option to enable extended error logging, "
68 "Default is 0 - no logging. 1 - log errors.");
69
57static void qla2x00_free_device(scsi_qla_host_t *); 70static void qla2x00_free_device(scsi_qla_host_t *);
58 71
59static void qla2x00_config_dma_addressing(scsi_qla_host_t *ha); 72static void qla2x00_config_dma_addressing(scsi_qla_host_t *ha);
@@ -624,7 +637,7 @@ qla2xxx_eh_abort(struct scsi_cmnd *cmd)
624 637
625 DEBUG2(printk("%s(%ld): aborting sp %p from RISC. pid=%ld.\n", 638 DEBUG2(printk("%s(%ld): aborting sp %p from RISC. pid=%ld.\n",
626 __func__, ha->host_no, sp, serial)); 639 __func__, ha->host_no, sp, serial));
627 DEBUG3(qla2x00_print_scsi_cmd(cmd);) 640 DEBUG3(qla2x00_print_scsi_cmd(cmd));
628 641
629 spin_unlock_irqrestore(&ha->hardware_lock, flags); 642 spin_unlock_irqrestore(&ha->hardware_lock, flags);
630 if (ha->isp_ops.abort_command(ha, sp)) { 643 if (ha->isp_ops.abort_command(ha, sp)) {
@@ -766,7 +779,7 @@ qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
766#endif 779#endif
767 } else { 780 } else {
768 DEBUG2(printk(KERN_INFO 781 DEBUG2(printk(KERN_INFO
769 "%s failed: loop not ready\n",__func__);) 782 "%s failed: loop not ready\n",__func__));
770 } 783 }
771 784
772 if (ret == FAILED) { 785 if (ret == FAILED) {
@@ -1021,12 +1034,12 @@ qla2x00_loop_reset(scsi_qla_host_t *ha)
1021 /* Empty */ 1034 /* Empty */
1022 DEBUG2_3(printk("%s(%ld): **** FAILED ****\n", 1035 DEBUG2_3(printk("%s(%ld): **** FAILED ****\n",
1023 __func__, 1036 __func__,
1024 ha->host_no);) 1037 ha->host_no));
1025 } else { 1038 } else {
1026 /* Empty */ 1039 /* Empty */
1027 DEBUG3(printk("%s(%ld): exiting normally.\n", 1040 DEBUG3(printk("%s(%ld): exiting normally.\n",
1028 __func__, 1041 __func__,
1029 ha->host_no);) 1042 ha->host_no));
1030 } 1043 }
1031 1044
1032 return(status); 1045 return(status);
@@ -1324,7 +1337,8 @@ qla24xx_disable_intrs(scsi_qla_host_t *ha)
1324/* 1337/*
1325 * PCI driver interface 1338 * PCI driver interface
1326 */ 1339 */
1327static int qla2x00_probe_one(struct pci_dev *pdev) 1340static int __devinit
1341qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1328{ 1342{
1329 int ret = -ENODEV; 1343 int ret = -ENODEV;
1330 device_reg_t __iomem *reg; 1344 device_reg_t __iomem *reg;
@@ -1405,7 +1419,6 @@ static int qla2x00_probe_one(struct pci_dev *pdev)
1405 ha->isp_ops.read_nvram = qla2x00_read_nvram_data; 1419 ha->isp_ops.read_nvram = qla2x00_read_nvram_data;
1406 ha->isp_ops.write_nvram = qla2x00_write_nvram_data; 1420 ha->isp_ops.write_nvram = qla2x00_write_nvram_data;
1407 ha->isp_ops.fw_dump = qla2100_fw_dump; 1421 ha->isp_ops.fw_dump = qla2100_fw_dump;
1408 ha->isp_ops.ascii_fw_dump = qla2100_ascii_fw_dump;
1409 ha->isp_ops.read_optrom = qla2x00_read_optrom_data; 1422 ha->isp_ops.read_optrom = qla2x00_read_optrom_data;
1410 ha->isp_ops.write_optrom = qla2x00_write_optrom_data; 1423 ha->isp_ops.write_optrom = qla2x00_write_optrom_data;
1411 if (IS_QLA2100(ha)) { 1424 if (IS_QLA2100(ha)) {
@@ -1432,7 +1445,6 @@ static int qla2x00_probe_one(struct pci_dev *pdev)
1432 ha->isp_ops.pci_config = qla2300_pci_config; 1445 ha->isp_ops.pci_config = qla2300_pci_config;
1433 ha->isp_ops.intr_handler = qla2300_intr_handler; 1446 ha->isp_ops.intr_handler = qla2300_intr_handler;
1434 ha->isp_ops.fw_dump = qla2300_fw_dump; 1447 ha->isp_ops.fw_dump = qla2300_fw_dump;
1435 ha->isp_ops.ascii_fw_dump = qla2300_ascii_fw_dump;
1436 ha->isp_ops.beacon_on = qla2x00_beacon_on; 1448 ha->isp_ops.beacon_on = qla2x00_beacon_on;
1437 ha->isp_ops.beacon_off = qla2x00_beacon_off; 1449 ha->isp_ops.beacon_off = qla2x00_beacon_off;
1438 ha->isp_ops.beacon_blink = qla2x00_beacon_blink; 1450 ha->isp_ops.beacon_blink = qla2x00_beacon_blink;
@@ -1469,7 +1481,6 @@ static int qla2x00_probe_one(struct pci_dev *pdev)
1469 ha->isp_ops.read_nvram = qla24xx_read_nvram_data; 1481 ha->isp_ops.read_nvram = qla24xx_read_nvram_data;
1470 ha->isp_ops.write_nvram = qla24xx_write_nvram_data; 1482 ha->isp_ops.write_nvram = qla24xx_write_nvram_data;
1471 ha->isp_ops.fw_dump = qla24xx_fw_dump; 1483 ha->isp_ops.fw_dump = qla24xx_fw_dump;
1472 ha->isp_ops.ascii_fw_dump = qla24xx_ascii_fw_dump;
1473 ha->isp_ops.read_optrom = qla24xx_read_optrom_data; 1484 ha->isp_ops.read_optrom = qla24xx_read_optrom_data;
1474 ha->isp_ops.write_optrom = qla24xx_write_optrom_data; 1485 ha->isp_ops.write_optrom = qla24xx_write_optrom_data;
1475 ha->isp_ops.beacon_on = qla24xx_beacon_on; 1486 ha->isp_ops.beacon_on = qla24xx_beacon_on;
@@ -1640,7 +1651,8 @@ probe_out:
1640 return ret; 1651 return ret;
1641} 1652}
1642 1653
1643static void qla2x00_remove_one(struct pci_dev *pdev) 1654static void __devexit
1655qla2x00_remove_one(struct pci_dev *pdev)
1644{ 1656{
1645 scsi_qla_host_t *ha; 1657 scsi_qla_host_t *ha;
1646 1658
@@ -1678,6 +1690,9 @@ qla2x00_free_device(scsi_qla_host_t *ha)
1678 kthread_stop(t); 1690 kthread_stop(t);
1679 } 1691 }
1680 1692
1693 if (ha->eft)
1694 qla2x00_trace_control(ha, TC_DISABLE, 0, 0);
1695
1681 /* Stop currently executing firmware. */ 1696 /* Stop currently executing firmware. */
1682 qla2x00_stop_firmware(ha); 1697 qla2x00_stop_firmware(ha);
1683 1698
@@ -1899,17 +1914,6 @@ qla2x00_mem_alloc(scsi_qla_host_t *ha)
1899 } 1914 }
1900 memset(ha->init_cb, 0, ha->init_cb_size); 1915 memset(ha->init_cb, 0, ha->init_cb_size);
1901 1916
1902 /* Allocate ioctl related memory. */
1903 if (qla2x00_alloc_ioctl_mem(ha)) {
1904 qla_printk(KERN_WARNING, ha,
1905 "Memory Allocation failed - ioctl_mem\n");
1906
1907 qla2x00_mem_free(ha);
1908 msleep(100);
1909
1910 continue;
1911 }
1912
1913 if (qla2x00_allocate_sp_pool(ha)) { 1917 if (qla2x00_allocate_sp_pool(ha)) {
1914 qla_printk(KERN_WARNING, ha, 1918 qla_printk(KERN_WARNING, ha,
1915 "Memory Allocation failed - " 1919 "Memory Allocation failed - "
@@ -1972,6 +1976,26 @@ qla2x00_mem_alloc(scsi_qla_host_t *ha)
1972 continue; 1976 continue;
1973 } 1977 }
1974 memset(ha->ct_sns, 0, sizeof(struct ct_sns_pkt)); 1978 memset(ha->ct_sns, 0, sizeof(struct ct_sns_pkt));
1979
1980 if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) {
1981 /*
1982 * Get consistent memory allocated for SFP
1983 * block.
1984 */
1985 ha->sfp_data = dma_pool_alloc(ha->s_dma_pool,
1986 GFP_KERNEL, &ha->sfp_data_dma);
1987 if (ha->sfp_data == NULL) {
1988 qla_printk(KERN_WARNING, ha,
1989 "Memory Allocation failed - "
1990 "sfp_data\n");
1991
1992 qla2x00_mem_free(ha);
1993 msleep(100);
1994
1995 continue;
1996 }
1997 memset(ha->sfp_data, 0, SFP_BLOCK_SIZE);
1998 }
1975 } 1999 }
1976 2000
1977 /* Done all allocations without any error. */ 2001 /* Done all allocations without any error. */
@@ -2006,12 +2030,16 @@ qla2x00_mem_free(scsi_qla_host_t *ha)
2006 return; 2030 return;
2007 } 2031 }
2008 2032
2009 /* free ioctl memory */
2010 qla2x00_free_ioctl_mem(ha);
2011
2012 /* free sp pool */ 2033 /* free sp pool */
2013 qla2x00_free_sp_pool(ha); 2034 qla2x00_free_sp_pool(ha);
2014 2035
2036 if (ha->fw_dump) {
2037 if (ha->eft)
2038 dma_free_coherent(&ha->pdev->dev,
2039 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
2040 vfree(ha->fw_dump);
2041 }
2042
2015 if (ha->sns_cmd) 2043 if (ha->sns_cmd)
2016 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 2044 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
2017 ha->sns_cmd, ha->sns_cmd_dma); 2045 ha->sns_cmd, ha->sns_cmd_dma);
@@ -2020,6 +2048,9 @@ qla2x00_mem_free(scsi_qla_host_t *ha)
2020 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 2048 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
2021 ha->ct_sns, ha->ct_sns_dma); 2049 ha->ct_sns, ha->ct_sns_dma);
2022 2050
2051 if (ha->sfp_data)
2052 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
2053
2023 if (ha->ms_iocb) 2054 if (ha->ms_iocb)
2024 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 2055 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
2025 2056
@@ -2043,6 +2074,8 @@ qla2x00_mem_free(scsi_qla_host_t *ha)
2043 (ha->request_q_length + 1) * sizeof(request_t), 2074 (ha->request_q_length + 1) * sizeof(request_t),
2044 ha->request_ring, ha->request_dma); 2075 ha->request_ring, ha->request_dma);
2045 2076
2077 ha->eft = NULL;
2078 ha->eft_dma = 0;
2046 ha->sns_cmd = NULL; 2079 ha->sns_cmd = NULL;
2047 ha->sns_cmd_dma = 0; 2080 ha->sns_cmd_dma = 0;
2048 ha->ct_sns = NULL; 2081 ha->ct_sns = NULL;
@@ -2071,13 +2104,9 @@ qla2x00_mem_free(scsi_qla_host_t *ha)
2071 } 2104 }
2072 INIT_LIST_HEAD(&ha->fcports); 2105 INIT_LIST_HEAD(&ha->fcports);
2073 2106
2074 vfree(ha->fw_dump);
2075 vfree(ha->fw_dump_buffer);
2076
2077 ha->fw_dump = NULL; 2107 ha->fw_dump = NULL;
2078 ha->fw_dumped = 0; 2108 ha->fw_dumped = 0;
2079 ha->fw_dump_reading = 0; 2109 ha->fw_dump_reading = 0;
2080 ha->fw_dump_buffer = NULL;
2081 2110
2082 vfree(ha->optrom_buffer); 2111 vfree(ha->optrom_buffer);
2083} 2112}
@@ -2617,40 +2646,16 @@ static struct pci_device_id qla2xxx_pci_tbl[] = {
2617}; 2646};
2618MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 2647MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
2619 2648
2620static int __devinit
2621qla2xxx_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2622{
2623 return qla2x00_probe_one(pdev);
2624}
2625
2626static void __devexit
2627qla2xxx_remove_one(struct pci_dev *pdev)
2628{
2629 qla2x00_remove_one(pdev);
2630}
2631
2632static struct pci_driver qla2xxx_pci_driver = { 2649static struct pci_driver qla2xxx_pci_driver = {
2633 .name = QLA2XXX_DRIVER_NAME, 2650 .name = QLA2XXX_DRIVER_NAME,
2634 .driver = { 2651 .driver = {
2635 .owner = THIS_MODULE, 2652 .owner = THIS_MODULE,
2636 }, 2653 },
2637 .id_table = qla2xxx_pci_tbl, 2654 .id_table = qla2xxx_pci_tbl,
2638 .probe = qla2xxx_probe_one, 2655 .probe = qla2x00_probe_one,
2639 .remove = __devexit_p(qla2xxx_remove_one), 2656 .remove = __devexit_p(qla2x00_remove_one),
2640}; 2657};
2641 2658
2642static inline int
2643qla2x00_pci_module_init(void)
2644{
2645 return pci_module_init(&qla2xxx_pci_driver);
2646}
2647
2648static inline void
2649qla2x00_pci_module_exit(void)
2650{
2651 pci_unregister_driver(&qla2xxx_pci_driver);
2652}
2653
2654/** 2659/**
2655 * qla2x00_module_init - Module initialization. 2660 * qla2x00_module_init - Module initialization.
2656 **/ 2661 **/
@@ -2670,16 +2675,16 @@ qla2x00_module_init(void)
2670 2675
2671 /* Derive version string. */ 2676 /* Derive version string. */
2672 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 2677 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
2673#if DEBUG_QLA2100 2678 if (extended_error_logging)
2674 strcat(qla2x00_version_str, "-debug"); 2679 strcat(qla2x00_version_str, "-debug");
2675#endif 2680
2676 qla2xxx_transport_template = 2681 qla2xxx_transport_template =
2677 fc_attach_transport(&qla2xxx_transport_functions); 2682 fc_attach_transport(&qla2xxx_transport_functions);
2678 if (!qla2xxx_transport_template) 2683 if (!qla2xxx_transport_template)
2679 return -ENODEV; 2684 return -ENODEV;
2680 2685
2681 printk(KERN_INFO "QLogic Fibre Channel HBA Driver\n"); 2686 printk(KERN_INFO "QLogic Fibre Channel HBA Driver\n");
2682 ret = qla2x00_pci_module_init(); 2687 ret = pci_register_driver(&qla2xxx_pci_driver);
2683 if (ret) { 2688 if (ret) {
2684 kmem_cache_destroy(srb_cachep); 2689 kmem_cache_destroy(srb_cachep);
2685 fc_release_transport(qla2xxx_transport_template); 2690 fc_release_transport(qla2xxx_transport_template);
@@ -2693,7 +2698,7 @@ qla2x00_module_init(void)
2693static void __exit 2698static void __exit
2694qla2x00_module_exit(void) 2699qla2x00_module_exit(void)
2695{ 2700{
2696 qla2x00_pci_module_exit(); 2701 pci_unregister_driver(&qla2xxx_pci_driver);
2697 qla2x00_release_firmware(); 2702 qla2x00_release_firmware();
2698 kmem_cache_destroy(srb_cachep); 2703 kmem_cache_destroy(srb_cachep);
2699 fc_release_transport(qla2xxx_transport_template); 2704 fc_release_transport(qla2xxx_transport_template);
diff --git a/drivers/scsi/qla2xxx/qla_version.h b/drivers/scsi/qla2xxx/qla_version.h
index 6b315521bd89..d2d683440659 100644
--- a/drivers/scsi/qla2xxx/qla_version.h
+++ b/drivers/scsi/qla2xxx/qla_version.h
@@ -7,7 +7,7 @@
7/* 7/*
8 * Driver version 8 * Driver version
9 */ 9 */
10#define QLA2XXX_VERSION "8.01.05-k2" 10#define QLA2XXX_VERSION "8.01.05-k3"
11 11
12#define QLA_DRIVER_MAJOR_VER 8 12#define QLA_DRIVER_MAJOR_VER 8
13#define QLA_DRIVER_MINOR_VER 1 13#define QLA_DRIVER_MINOR_VER 1
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 05:49:07 -0500