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path: root/drivers/scsi/qla2xxx/qla_nx.c
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Diffstat (limited to 'drivers/scsi/qla2xxx/qla_nx.c')
-rw-r--r--drivers/scsi/qla2xxx/qla_nx.c77
1 files changed, 29 insertions, 48 deletions
diff --git a/drivers/scsi/qla2xxx/qla_nx.c b/drivers/scsi/qla2xxx/qla_nx.c
index 14cd361742fa..f0fdc222770d 100644
--- a/drivers/scsi/qla2xxx/qla_nx.c
+++ b/drivers/scsi/qla2xxx/qla_nx.c
@@ -36,7 +36,7 @@
36 36
37#define MAX_CRB_XFORM 60 37#define MAX_CRB_XFORM 60
38static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 38static unsigned long crb_addr_xform[MAX_CRB_XFORM];
39int qla82xx_crb_table_initialized; 39static int qla82xx_crb_table_initialized;
40 40
41#define qla82xx_crb_addr_transform(name) \ 41#define qla82xx_crb_addr_transform(name) \
42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
@@ -102,7 +102,7 @@ static void qla82xx_crb_addr_transform_setup(void)
102 qla82xx_crb_table_initialized = 1; 102 qla82xx_crb_table_initialized = 1;
103} 103}
104 104
105struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 105static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
106 {{{0, 0, 0, 0} } }, 106 {{{0, 0, 0, 0} } },
107 {{{1, 0x0100000, 0x0102000, 0x120000}, 107 {{{1, 0x0100000, 0x0102000, 0x120000},
108 {1, 0x0110000, 0x0120000, 0x130000}, 108 {1, 0x0110000, 0x0120000, 0x130000},
@@ -262,7 +262,7 @@ struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
262/* 262/*
263 * top 12 bits of crb internal address (hub, agent) 263 * top 12 bits of crb internal address (hub, agent)
264 */ 264 */
265unsigned qla82xx_crb_hub_agt[64] = { 265static unsigned qla82xx_crb_hub_agt[64] = {
266 0, 266 0,
267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
@@ -330,7 +330,7 @@ unsigned qla82xx_crb_hub_agt[64] = {
330}; 330};
331 331
332/* Device states */ 332/* Device states */
333char *q_dev_state[] = { 333static char *q_dev_state[] = {
334 "Unknown", 334 "Unknown",
335 "Cold", 335 "Cold",
336 "Initializing", 336 "Initializing",
@@ -359,12 +359,13 @@ qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off)
359 359
360 ha->crb_win = CRB_HI(*off); 360 ha->crb_win = CRB_HI(*off);
361 writel(ha->crb_win, 361 writel(ha->crb_win,
362 (void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 362 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
363 363
364 /* Read back value to make sure write has gone through before trying 364 /* Read back value to make sure write has gone through before trying
365 * to use it. 365 * to use it.
366 */ 366 */
367 win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 367 win_read = RD_REG_DWORD((void __iomem *)
368 (CRB_WINDOW_2M + ha->nx_pcibase));
368 if (win_read != ha->crb_win) { 369 if (win_read != ha->crb_win) {
369 ql_dbg(ql_dbg_p3p, vha, 0xb000, 370 ql_dbg(ql_dbg_p3p, vha, 0xb000,
370 "%s: Written crbwin (0x%x) " 371 "%s: Written crbwin (0x%x) "
@@ -567,7 +568,7 @@ qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
567 return 1; 568 return 1;
568} 569}
569 570
570int qla82xx_pci_set_window_warning_count; 571static int qla82xx_pci_set_window_warning_count;
571 572
572static unsigned long 573static unsigned long
573qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) 574qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
@@ -677,10 +678,10 @@ static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
677 u64 off, void *data, int size) 678 u64 off, void *data, int size)
678{ 679{
679 unsigned long flags; 680 unsigned long flags;
680 void *addr = NULL; 681 void __iomem *addr = NULL;
681 int ret = 0; 682 int ret = 0;
682 u64 start; 683 u64 start;
683 uint8_t *mem_ptr = NULL; 684 uint8_t __iomem *mem_ptr = NULL;
684 unsigned long mem_base; 685 unsigned long mem_base;
685 unsigned long mem_page; 686 unsigned long mem_page;
686 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 687 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
@@ -712,7 +713,7 @@ static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
712 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 713 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
713 else 714 else
714 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 715 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
715 if (mem_ptr == 0UL) { 716 if (mem_ptr == NULL) {
716 *(u8 *)data = 0; 717 *(u8 *)data = 0;
717 return -1; 718 return -1;
718 } 719 }
@@ -749,10 +750,10 @@ qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
749 u64 off, void *data, int size) 750 u64 off, void *data, int size)
750{ 751{
751 unsigned long flags; 752 unsigned long flags;
752 void *addr = NULL; 753 void __iomem *addr = NULL;
753 int ret = 0; 754 int ret = 0;
754 u64 start; 755 u64 start;
755 uint8_t *mem_ptr = NULL; 756 uint8_t __iomem *mem_ptr = NULL;
756 unsigned long mem_base; 757 unsigned long mem_base;
757 unsigned long mem_page; 758 unsigned long mem_page;
758 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 759 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
@@ -784,7 +785,7 @@ qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
784 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 785 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
785 else 786 else
786 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 787 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
787 if (mem_ptr == 0UL) 788 if (mem_ptr == NULL)
788 return -1; 789 return -1;
789 790
790 addr = mem_ptr; 791 addr = mem_ptr;
@@ -908,24 +909,24 @@ qla82xx_wait_rom_done(struct qla_hw_data *ha)
908 return 0; 909 return 0;
909} 910}
910 911
911int 912static int
912qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) 913qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
913{ 914{
914 uint32_t off_value, rval = 0; 915 uint32_t off_value, rval = 0;
915 916
916 WRT_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase), 917 WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase),
917 (off & 0xFFFF0000)); 918 (off & 0xFFFF0000));
918 919
919 /* Read back value to make sure write has gone through */ 920 /* Read back value to make sure write has gone through */
920 RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); 921 RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
921 off_value = (off & 0x0000FFFF); 922 off_value = (off & 0x0000FFFF);
922 923
923 if (flag) 924 if (flag)
924 WRT_REG_DWORD((void *) 925 WRT_REG_DWORD((void __iomem *)
925 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), 926 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase),
926 data); 927 data);
927 else 928 else
928 rval = RD_REG_DWORD((void *) 929 rval = RD_REG_DWORD((void __iomem *)
929 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); 930 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase));
930 931
931 return rval; 932 return rval;
@@ -1764,14 +1765,6 @@ void qla82xx_config_rings(struct scsi_qla_host *vha)
1764 WRT_REG_DWORD((unsigned long __iomem *)&reg->rsp_q_out[0], 0); 1765 WRT_REG_DWORD((unsigned long __iomem *)&reg->rsp_q_out[0], 0);
1765} 1766}
1766 1767
1767void qla82xx_reset_adapter(struct scsi_qla_host *vha)
1768{
1769 struct qla_hw_data *ha = vha->hw;
1770 vha->flags.online = 0;
1771 qla2x00_try_to_stop_firmware(vha);
1772 ha->isp_ops->disable_intrs(ha);
1773}
1774
1775static int 1768static int
1776qla82xx_fw_load_from_blob(struct qla_hw_data *ha) 1769qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1777{ 1770{
@@ -1856,7 +1849,7 @@ qla82xx_set_product_offset(struct qla_hw_data *ha)
1856 return -1; 1849 return -1;
1857} 1850}
1858 1851
1859int 1852static int
1860qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) 1853qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1861{ 1854{
1862 __le32 val; 1855 __le32 val;
@@ -1961,20 +1954,6 @@ qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
1961} 1954}
1962 1955
1963/* ISR related functions */ 1956/* ISR related functions */
1964uint32_t qla82xx_isr_int_target_mask_enable[8] = {
1965 ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1,
1966 ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3,
1967 ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5,
1968 ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7
1969};
1970
1971uint32_t qla82xx_isr_int_target_status[8] = {
1972 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
1973 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
1974 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
1975 ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7
1976};
1977
1978static struct qla82xx_legacy_intr_set legacy_intr[] = \ 1957static struct qla82xx_legacy_intr_set legacy_intr[] = \
1979 QLA82XX_LEGACY_INTR_CONFIG; 1958 QLA82XX_LEGACY_INTR_CONFIG;
1980 1959
@@ -2813,7 +2792,7 @@ qla82xx_start_iocbs(scsi_qla_host_t *vha)
2813 else { 2792 else {
2814 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 2793 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval);
2815 wmb(); 2794 wmb();
2816 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { 2795 while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) {
2817 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 2796 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr,
2818 dbval); 2797 dbval);
2819 wmb(); 2798 wmb();
@@ -2821,7 +2800,8 @@ qla82xx_start_iocbs(scsi_qla_host_t *vha)
2821 } 2800 }
2822} 2801}
2823 2802
2824void qla82xx_rom_lock_recovery(struct qla_hw_data *ha) 2803static void
2804qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
2825{ 2805{
2826 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2806 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2827 2807
@@ -3177,7 +3157,7 @@ qla82xx_check_md_needed(scsi_qla_host_t *vha)
3177} 3157}
3178 3158
3179 3159
3180int 3160static int
3181qla82xx_check_fw_alive(scsi_qla_host_t *vha) 3161qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3182{ 3162{
3183 uint32_t fw_heartbeat_counter; 3163 uint32_t fw_heartbeat_counter;
@@ -3817,7 +3797,8 @@ qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3817 loop_cnt = ocm_hdr->op_count; 3797 loop_cnt = ocm_hdr->op_count;
3818 3798
3819 for (i = 0; i < loop_cnt; i++) { 3799 for (i = 0; i < loop_cnt; i++) {
3820 r_value = RD_REG_DWORD((void *)(r_addr + ha->nx_pcibase)); 3800 r_value = RD_REG_DWORD((void __iomem *)
3801 (r_addr + ha->nx_pcibase));
3821 *data_ptr++ = cpu_to_le32(r_value); 3802 *data_ptr++ = cpu_to_le32(r_value);
3822 r_addr += r_stride; 3803 r_addr += r_stride;
3823 } 3804 }
@@ -4376,7 +4357,7 @@ qla82xx_md_free(scsi_qla_host_t *vha)
4376 ha->md_tmplt_hdr, ha->md_template_size / 1024); 4357 ha->md_tmplt_hdr, ha->md_template_size / 1024);
4377 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, 4358 dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
4378 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4359 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4379 ha->md_tmplt_hdr = 0; 4360 ha->md_tmplt_hdr = NULL;
4380 } 4361 }
4381 4362
4382 /* Release the template data buffer allocated */ 4363 /* Release the template data buffer allocated */
@@ -4386,7 +4367,7 @@ qla82xx_md_free(scsi_qla_host_t *vha)
4386 ha->md_dump, ha->md_dump_size / 1024); 4367 ha->md_dump, ha->md_dump_size / 1024);
4387 vfree(ha->md_dump); 4368 vfree(ha->md_dump);
4388 ha->md_dump_size = 0; 4369 ha->md_dump_size = 0;
4389 ha->md_dump = 0; 4370 ha->md_dump = NULL;
4390 } 4371 }
4391} 4372}
4392 4373
@@ -4423,7 +4404,7 @@ qla82xx_md_prep(scsi_qla_host_t *vha)
4423 dma_free_coherent(&ha->pdev->dev, 4404 dma_free_coherent(&ha->pdev->dev,
4424 ha->md_template_size, 4405 ha->md_template_size,
4425 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); 4406 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4426 ha->md_tmplt_hdr = 0; 4407 ha->md_tmplt_hdr = NULL;
4427 } 4408 }
4428 4409
4429 } 4410 }