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diff --git a/drivers/scsi/qla2xxx/qla_fw.h b/drivers/scsi/qla2xxx/qla_fw.h
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1
2/********************************************************************************
3* QLOGIC LINUX SOFTWARE
4*
5* QLogic ISP2x00 device driver for Linux 2.6.x
6* Copyright (C) 2003-2004 QLogic Corporation
7* (www.qlogic.com)
8*
9* This program is free software; you can redistribute it and/or modify it
10* under the terms of the GNU General Public License as published by the
11* Free Software Foundation; either version 2, or (at your option) any
12* later version.
13*
14* This program is distributed in the hope that it will be useful, but
15* WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17* General Public License for more details.
18**
19******************************************************************************/
20
21#ifndef __QLA_FW_H
22#define __QLA_FW_H
23
24// ISP24xx
25
26#define RISC_SADDRESS 0x100000
27#define MBS_CHECKSUM_ERROR 0x4010
28
29/*
30 * Firmware Options.
31 */
32#define FO1_ENABLE_PUREX BIT_10
33#define FO1_DISABLE_LED_CTRL BIT_6
34#define FO2_ENABLE_SEL_CLASS2 BIT_5
35#define FO3_NO_ABTS_ON_LINKDOWN BIT_14
36
37/*
38 * Port Database structure definition for ISP 24xx.
39 */
40#define PDO_FORCE_ADISC BIT_1
41#define PDO_FORCE_PLOGI BIT_0
42
43
44#define PORT_DATABASE_24XX_SIZE 64
45struct port_database_24xx {
46 uint16_t flags;
47#define PDF_TASK_RETRY_ID BIT_14
48#define PDF_FC_TAPE BIT_7
49#define PDF_ACK0_CAPABLE BIT_6
50#define PDF_FCP2_CONF BIT_5
51#define PDF_CLASS_2 BIT_4
52#define PDF_HARD_ADDR BIT_1
53
54 uint8_t current_login_state;
55 uint8_t last_login_state;
56#define PDS_PLOGI_PENDING 0x03
57#define PDS_PLOGI_COMPLETE 0x04
58#define PDS_PRLI_PENDING 0x05
59#define PDS_PRLI_COMPLETE 0x06
60#define PDS_PORT_UNAVAILABLE 0x07
61#define PDS_PRLO_PENDING 0x09
62#define PDS_LOGO_PENDING 0x11
63//FIXME
64#define PDS_PRLI2_PENDING 0x12
65
66 uint8_t hard_address[3];
67 uint8_t reserved_1;
68
69 uint8_t port_id[3];
70 uint8_t sequence_id;
71
72 uint16_t port_timer;
73
74 uint16_t nport_handle; /* N_PORT handle. */
75
76 uint16_t receive_data_size;
77 uint16_t reserved_2;
78
79 uint8_t prli_svc_param_word_0[2]; /* Big endian */
80 /* Bits 15-0 of word 0 */
81 uint8_t prli_svc_param_word_3[2]; /* Big endian */
82 /* Bits 15-0 of word 3 */
83
84 uint8_t port_name[WWN_SIZE];
85 uint8_t node_name[WWN_SIZE];
86
87 uint8_t reserved_3[24];
88};
89
90struct nvram_24xx {
91 /* NVRAM header. */
92 uint8_t id[4];
93 uint16_t nvram_version;
94 uint16_t reserved_0;
95
96 /* Firmware Initialization Control Block. */
97 uint16_t version;
98 uint16_t reserved_1;
99 uint16_t frame_payload_size;
100 uint16_t execution_throttle;
101 uint16_t exchange_count;
102 uint16_t hard_address;
103
104 uint8_t port_name[WWN_SIZE];
105 uint8_t node_name[WWN_SIZE];
106
107 uint16_t login_retry_count;
108 uint16_t link_down_on_nos;
109 uint16_t interrupt_delay_timer;
110 uint16_t login_timeout;
111
112 uint32_t firmware_options_1;
113 uint32_t firmware_options_2;
114 uint32_t firmware_options_3;
115
116 /* Offset 56. */
117
118 /*
119 * BIT 0 = Control Enable
120 * BIT 1-15 =
121 *
122 * BIT 0-7 = Reserved
123 * BIT 8-10 = Output Swing 1G
124 * BIT 11-13 = Output Emphasis 1G
125 * BIT 14-15 = Reserved
126 *
127 * BIT 0-7 = Reserved
128 * BIT 8-10 = Output Swing 2G
129 * BIT 11-13 = Output Emphasis 2G
130 * BIT 14-15 = Reserved
131 *
132 * BIT 0-7 = Reserved
133 * BIT 8-10 = Output Swing 4G
134 * BIT 11-13 = Output Emphasis 4G
135 * BIT 14-15 = Reserved
136 */
137 uint16_t seriallink_options[4];
138
139 uint16_t reserved_2[16];
140
141 /* Offset 96. */
142 uint16_t reserved_3[16];
143
144 /* PCIe table entries. */
145 uint16_t reserved_4[16];
146
147 /* Offset 160. */
148 uint16_t reserved_5[16];
149
150 /* Offset 192. */
151 uint16_t reserved_6[16];
152
153 /* Offset 224. */
154 uint16_t reserved_7[16];
155
156 /*
157 * BIT 0 = Enable spinup delay
158 * BIT 1 = Disable BIOS
159 * BIT 2 = Enable Memory Map BIOS
160 * BIT 3 = Enable Selectable Boot
161 * BIT 4 = Disable RISC code load
162 * BIT 5 =
163 * BIT 6 =
164 * BIT 7 =
165 *
166 * BIT 8 =
167 * BIT 9 =
168 * BIT 10 = Enable lip full login
169 * BIT 11 = Enable target reset
170 * BIT 12 =
171 * BIT 13 =
172 * BIT 14 =
173 * BIT 15 = Enable alternate WWN
174 *
175 * BIT 16-31 =
176 */
177 uint32_t host_p;
178
179 uint8_t alternate_port_name[WWN_SIZE];
180 uint8_t alternate_node_name[WWN_SIZE];
181
182 uint8_t boot_port_name[WWN_SIZE];
183 uint16_t boot_lun_number;
184 uint16_t reserved_8;
185
186 uint8_t alt1_boot_port_name[WWN_SIZE];
187 uint16_t alt1_boot_lun_number;
188 uint16_t reserved_9;
189
190 uint8_t alt2_boot_port_name[WWN_SIZE];
191 uint16_t alt2_boot_lun_number;
192 uint16_t reserved_10;
193
194 uint8_t alt3_boot_port_name[WWN_SIZE];
195 uint16_t alt3_boot_lun_number;
196 uint16_t reserved_11;
197
198 /*
199 * BIT 0 = Selective Login
200 * BIT 1 = Alt-Boot Enable
201 * BIT 2 = Reserved
202 * BIT 3 = Boot Order List
203 * BIT 4 = Reserved
204 * BIT 5 = Selective LUN
205 * BIT 6 = Reserved
206 * BIT 7-31 =
207 */
208 uint32_t efi_parameters;
209
210 uint8_t reset_delay;
211 uint8_t reserved_12;
212 uint16_t reserved_13;
213
214 uint16_t boot_id_number;
215 uint16_t reserved_14;
216
217 uint16_t max_luns_per_target;
218 uint16_t reserved_15;
219
220 uint16_t port_down_retry_count;
221 uint16_t link_down_timeout;
222
223 /* FCode parameters. */
224 uint16_t fcode_parameter;
225
226 uint16_t reserved_16[3];
227
228 /* Offset 352. */
229 uint8_t prev_drv_ver_major;
230 uint8_t prev_drv_ver_submajob;
231 uint8_t prev_drv_ver_minor;
232 uint8_t prev_drv_ver_subminor;
233
234 uint16_t prev_bios_ver_major;
235 uint16_t prev_bios_ver_minor;
236
237 uint16_t prev_efi_ver_major;
238 uint16_t prev_efi_ver_minor;
239
240 uint16_t prev_fw_ver_major;
241 uint8_t prev_fw_ver_minor;
242 uint8_t prev_fw_ver_subminor;
243
244 uint16_t reserved_17[8];
245
246 /* Offset 384. */
247 uint16_t reserved_18[16];
248
249 /* Offset 416. */
250 uint16_t reserved_19[16];
251
252 /* Offset 448. */
253 uint16_t reserved_20[16];
254
255 /* Offset 480. */
256 uint8_t model_name[16];
257
258 uint16_t reserved_21[2];
259
260 /* Offset 500. */
261 /* HW Parameter Block. */
262 uint16_t pcie_table_sig;
263 uint16_t pcie_table_offset;
264
265 uint16_t subsystem_vendor_id;
266 uint16_t subsystem_device_id;
267
268 uint32_t checksum;
269};
270
271/*
272 * ISP Initialization Control Block.
273 * Little endian except where noted.
274 */
275#define ICB_VERSION 1
276struct init_cb_24xx {
277 uint16_t version;
278 uint16_t reserved_1;
279
280 uint16_t frame_payload_size;
281 uint16_t execution_throttle;
282 uint16_t exchange_count;
283
284 uint16_t hard_address;
285
286 uint8_t port_name[WWN_SIZE]; /* Big endian. */
287 uint8_t node_name[WWN_SIZE]; /* Big endian. */
288
289 uint16_t response_q_inpointer;
290 uint16_t request_q_outpointer;
291
292 uint16_t login_retry_count;
293
294 uint16_t prio_request_q_outpointer;
295
296 uint16_t response_q_length;
297 uint16_t request_q_length;
298
299 uint16_t link_down_timeout; /* Milliseconds. */
300
301 uint16_t prio_request_q_length;
302
303 uint32_t request_q_address[2];
304 uint32_t response_q_address[2];
305 uint32_t prio_request_q_address[2];
306
307 uint8_t reserved_2[8];
308
309 uint16_t atio_q_inpointer;
310 uint16_t atio_q_length;
311 uint32_t atio_q_address[2];
312
313 uint16_t interrupt_delay_timer; /* 100us increments. */
314 uint16_t login_timeout;
315
316 /*
317 * BIT 0 = Enable Hard Loop Id
318 * BIT 1 = Enable Fairness
319 * BIT 2 = Enable Full-Duplex
320 * BIT 3 = Reserved
321 * BIT 4 = Enable Target Mode
322 * BIT 5 = Disable Initiator Mode
323 * BIT 6 = Reserved
324 * BIT 7 = Reserved
325 *
326 * BIT 8 = Reserved
327 * BIT 9 = Non Participating LIP
328 * BIT 10 = Descending Loop ID Search
329 * BIT 11 = Acquire Loop ID in LIPA
330 * BIT 12 = Reserved
331 * BIT 13 = Full Login after LIP
332 * BIT 14 = Node Name Option
333 * BIT 15-31 = Reserved
334 */
335 uint32_t firmware_options_1;
336
337 /*
338 * BIT 0 = Operation Mode bit 0
339 * BIT 1 = Operation Mode bit 1
340 * BIT 2 = Operation Mode bit 2
341 * BIT 3 = Operation Mode bit 3
342 * BIT 4 = Connection Options bit 0
343 * BIT 5 = Connection Options bit 1
344 * BIT 6 = Connection Options bit 2
345 * BIT 7 = Enable Non part on LIHA failure
346 *
347 * BIT 8 = Enable Class 2
348 * BIT 9 = Enable ACK0
349 * BIT 10 = Reserved
350 * BIT 11 = Enable FC-SP Security
351 * BIT 12 = FC Tape Enable
352 * BIT 13-31 = Reserved
353 */
354 uint32_t firmware_options_2;
355
356 /*
357 * BIT 0 = Reserved
358 * BIT 1 = Soft ID only
359 * BIT 2 = Reserved
360 * BIT 3 = Reserved
361 * BIT 4 = FCP RSP Payload bit 0
362 * BIT 5 = FCP RSP Payload bit 1
363 * BIT 6 = Enable Receive Out-of-Order data frame handling
364 * BIT 7 = Disable Automatic PLOGI on Local Loop
365 *
366 * BIT 8 = Reserved
367 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
368 * BIT 10 = Reserved
369 * BIT 11 = Reserved
370 * BIT 12 = Reserved
371 * BIT 13 = Data Rate bit 0
372 * BIT 14 = Data Rate bit 1
373 * BIT 15 = Data Rate bit 2
374 * BIT 16-31 = Reserved
375 */
376 uint32_t firmware_options_3;
377
378 uint8_t reserved_3[24];
379};
380
381/*
382 * ISP queue - command entry structure definition.
383 */
384#define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */
385struct cmd_type_6 {
386 uint8_t entry_type; /* Entry type. */
387 uint8_t entry_count; /* Entry count. */
388 uint8_t sys_define; /* System defined. */
389 uint8_t entry_status; /* Entry Status. */
390
391 uint32_t handle; /* System handle. */
392
393 uint16_t nport_handle; /* N_PORT handle. */
394 uint16_t timeout; /* Command timeout. */
395
396 uint16_t dseg_count; /* Data segment count. */
397
398 uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */
399
400 uint8_t lun[8]; /* FCP LUN (BE). */
401
402 uint16_t control_flags; /* Control flags. */
403#define CF_DATA_SEG_DESCR_ENABLE BIT_2
404#define CF_READ_DATA BIT_1
405#define CF_WRITE_DATA BIT_0
406
407 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
408 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
409
410 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
411
412 uint32_t byte_count; /* Total byte count. */
413
414 uint8_t port_id[3]; /* PortID of destination port. */
415 uint8_t vp_index;
416
417 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */
418 uint16_t fcp_data_dseg_len; /* Data segment length. */
419 uint16_t reserved_1; /* MUST be set to 0. */
420};
421
422#define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */
423struct cmd_type_7 {
424 uint8_t entry_type; /* Entry type. */
425 uint8_t entry_count; /* Entry count. */
426 uint8_t sys_define; /* System defined. */
427 uint8_t entry_status; /* Entry Status. */
428
429 uint32_t handle; /* System handle. */
430
431 uint16_t nport_handle; /* N_PORT handle. */
432 uint16_t timeout; /* Command timeout. */
433#define FW_MAX_TIMEOUT 0x1999
434
435 uint16_t dseg_count; /* Data segment count. */
436 uint16_t reserved_1;
437
438 uint8_t lun[8]; /* FCP LUN (BE). */
439
440 uint16_t task_mgmt_flags; /* Task management flags. */
441#define TMF_CLEAR_ACA BIT_14
442#define TMF_TARGET_RESET BIT_13
443#define TMF_LUN_RESET BIT_12
444#define TMF_CLEAR_TASK_SET BIT_10
445#define TMF_ABORT_TASK_SET BIT_9
446#define TMF_READ_DATA BIT_1
447#define TMF_WRITE_DATA BIT_0
448
449 uint8_t task;
450#define TSK_SIMPLE 0
451#define TSK_HEAD_OF_QUEUE 1
452#define TSK_ORDERED 2
453#define TSK_ACA 4
454#define TSK_UNTAGGED 5
455
456 uint8_t crn;
457
458 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
459 uint32_t byte_count; /* Total byte count. */
460
461 uint8_t port_id[3]; /* PortID of destination port. */
462 uint8_t vp_index;
463
464 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
465 uint32_t dseg_0_len; /* Data segment 0 length. */
466};
467
468/*
469 * ISP queue - status entry structure definition.
470 */
471#define STATUS_TYPE 0x03 /* Status entry. */
472struct sts_entry_24xx {
473 uint8_t entry_type; /* Entry type. */
474 uint8_t entry_count; /* Entry count. */
475 uint8_t sys_define; /* System defined. */
476 uint8_t entry_status; /* Entry Status. */
477
478 uint32_t handle; /* System handle. */
479
480 uint16_t comp_status; /* Completion status. */
481 uint16_t ox_id; /* OX_ID used by the firmware. */
482
483 uint32_t residual_len; /* Residual transfer length. */
484
485 uint16_t reserved_1;
486 uint16_t state_flags; /* State flags. */
487#define SF_TRANSFERRED_DATA BIT_11
488#define SF_FCP_RSP_DMA BIT_0
489
490 uint16_t reserved_2;
491 uint16_t scsi_status; /* SCSI status. */
492#define SS_CONFIRMATION_REQ BIT_12
493
494 uint32_t rsp_residual_count; /* FCP RSP residual count. */
495
496 uint32_t sense_len; /* FCP SENSE length. */
497 uint32_t rsp_data_len; /* FCP response data length. */
498
499 uint8_t data[28]; /* FCP response/sense information. */
500};
501
502/*
503 * Status entry completion status
504 */
505#define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */
506#define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */
507#define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */
508#define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */
509#define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */
510
511/*
512 * ISP queue - marker entry structure definition.
513 */
514#define MARKER_TYPE 0x04 /* Marker entry. */
515struct mrk_entry_24xx {
516 uint8_t entry_type; /* Entry type. */
517 uint8_t entry_count; /* Entry count. */
518 uint8_t handle_count; /* Handle count. */
519 uint8_t entry_status; /* Entry Status. */
520
521 uint32_t handle; /* System handle. */
522
523 uint16_t nport_handle; /* N_PORT handle. */
524
525 uint8_t modifier; /* Modifier (7-0). */
526#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
527#define MK_SYNC_ID 1 /* Synchronize ID */
528#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
529 uint8_t reserved_1;
530
531 uint8_t reserved_2;
532 uint8_t vp_index;
533
534 uint16_t reserved_3;
535
536 uint8_t lun[8]; /* FCP LUN (BE). */
537 uint8_t reserved_4[40];
538};
539
540/*
541 * ISP queue - CT Pass-Through entry structure definition.
542 */
543#define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */
544struct ct_entry_24xx {
545 uint8_t entry_type; /* Entry type. */
546 uint8_t entry_count; /* Entry count. */
547 uint8_t sys_define; /* System Defined. */
548 uint8_t entry_status; /* Entry Status. */
549
550 uint32_t handle; /* System handle. */
551
552 uint16_t comp_status; /* Completion status. */
553
554 uint16_t nport_handle; /* N_PORT handle. */
555
556 uint16_t cmd_dsd_count;
557
558 uint8_t vp_index;
559 uint8_t reserved_1;
560
561 uint16_t timeout; /* Command timeout. */
562 uint16_t reserved_2;
563
564 uint16_t rsp_dsd_count;
565
566 uint8_t reserved_3[10];
567
568 uint32_t rsp_byte_count;
569 uint32_t cmd_byte_count;
570
571 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
572 uint32_t dseg_0_len; /* Data segment 0 length. */
573 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
574 uint32_t dseg_1_len; /* Data segment 1 length. */
575};
576
577/*
578 * ISP queue - ELS Pass-Through entry structure definition.
579 */
580#define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */
581struct els_entry_24xx {
582 uint8_t entry_type; /* Entry type. */
583 uint8_t entry_count; /* Entry count. */
584 uint8_t sys_define; /* System Defined. */
585 uint8_t entry_status; /* Entry Status. */
586
587 uint32_t handle; /* System handle. */
588
589 uint16_t reserved_1;
590
591 uint16_t nport_handle; /* N_PORT handle. */
592
593 uint16_t tx_dsd_count;
594
595 uint8_t vp_index;
596 uint8_t sof_type;
597#define EST_SOFI3 (1 << 4)
598#define EST_SOFI2 (3 << 4)
599
600 uint32_t rx_xchg_address[2]; /* Receive exchange address. */
601 uint16_t rx_dsd_count;
602
603 uint8_t opcode;
604 uint8_t reserved_2;
605
606 uint8_t port_id[3];
607 uint8_t reserved_3;
608
609 uint16_t reserved_4;
610
611 uint16_t control_flags; /* Control flags. */
612#define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13)
613#define EPD_ELS_COMMAND (0 << 13)
614#define EPD_ELS_ACC (1 << 13)
615#define EPD_ELS_RJT (2 << 13)
616#define EPD_RX_XCHG (3 << 13)
617#define ECF_CLR_PASSTHRU_PEND BIT_12
618#define ECF_INCL_FRAME_HDR BIT_11
619
620 uint32_t rx_byte_count;
621 uint32_t tx_byte_count;
622
623 uint32_t tx_address[2]; /* Data segment 0 address. */
624 uint32_t tx_len; /* Data segment 0 length. */
625 uint32_t rx_address[2]; /* Data segment 1 address. */
626 uint32_t rx_len; /* Data segment 1 length. */
627};
628
629/*
630 * ISP queue - Mailbox Command entry structure definition.
631 */
632#define MBX_IOCB_TYPE 0x39
633struct mbx_entry_24xx {
634 uint8_t entry_type; /* Entry type. */
635 uint8_t entry_count; /* Entry count. */
636 uint8_t handle_count; /* Handle count. */
637 uint8_t entry_status; /* Entry Status. */
638
639 uint32_t handle; /* System handle. */
640
641 uint16_t mbx[28];
642};
643
644
645#define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */
646struct logio_entry_24xx {
647 uint8_t entry_type; /* Entry type. */
648 uint8_t entry_count; /* Entry count. */
649 uint8_t sys_define; /* System defined. */
650 uint8_t entry_status; /* Entry Status. */
651
652 uint32_t handle; /* System handle. */
653
654 uint16_t comp_status; /* Completion status. */
655#define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */
656
657 uint16_t nport_handle; /* N_PORT handle. */
658
659 uint16_t control_flags; /* Control flags. */
660 /* Modifiers. */
661#define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */
662#define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */
663#define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */
664#define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */
665#define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */
666#define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */
667#define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */
668#define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */
669#define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */
670 /* Commands. */
671#define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */
672#define LCF_COMMAND_PRLI 0x01 /* PRLI. */
673#define LCF_COMMAND_PDISC 0x02 /* PDISC. */
674#define LCF_COMMAND_ADISC 0x03 /* ADISC. */
675#define LCF_COMMAND_LOGO 0x08 /* LOGO. */
676#define LCF_COMMAND_PRLO 0x09 /* PRLO. */
677#define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */
678
679 uint8_t vp_index;
680 uint8_t reserved_1;
681
682 uint8_t port_id[3]; /* PortID of destination port. */
683
684 uint8_t rsp_size; /* Response size in 32bit words. */
685
686 uint32_t io_parameter[11]; /* General I/O parameters. */
687#define LSC_SCODE_NOLINK 0x01
688#define LSC_SCODE_NOIOCB 0x02
689#define LSC_SCODE_NOXCB 0x03
690#define LSC_SCODE_CMD_FAILED 0x04
691#define LSC_SCODE_NOFABRIC 0x05
692#define LSC_SCODE_FW_NOT_READY 0x07
693#define LSC_SCODE_NOT_LOGGED_IN 0x09
694#define LSC_SCODE_NOPCB 0x0A
695
696#define LSC_SCODE_ELS_REJECT 0x18
697#define LSC_SCODE_CMD_PARAM_ERR 0x19
698#define LSC_SCODE_PORTID_USED 0x1A
699#define LSC_SCODE_NPORT_USED 0x1B
700#define LSC_SCODE_NONPORT 0x1C
701#define LSC_SCODE_LOGGED_IN 0x1D
702#define LSC_SCODE_NOFLOGI_ACC 0x1F
703};
704
705#define TSK_MGMT_IOCB_TYPE 0x14
706struct tsk_mgmt_entry {
707 uint8_t entry_type; /* Entry type. */
708 uint8_t entry_count; /* Entry count. */
709 uint8_t handle_count; /* Handle count. */
710 uint8_t entry_status; /* Entry Status. */
711
712 uint32_t handle; /* System handle. */
713
714 uint16_t nport_handle; /* N_PORT handle. */
715
716 uint16_t reserved_1;
717
718 uint16_t delay; /* Activity delay in seconds. */
719
720 uint16_t timeout; /* Command timeout. */
721
722 uint8_t lun[8]; /* FCP LUN (BE). */
723
724 uint32_t control_flags; /* Control Flags. */
725#define TCF_NOTMCMD_TO_TARGET BIT_31
726#define TCF_LUN_RESET BIT_4
727#define TCF_ABORT_TASK_SET BIT_3
728#define TCF_CLEAR_TASK_SET BIT_2
729#define TCF_TARGET_RESET BIT_1
730#define TCF_CLEAR_ACA BIT_0
731
732 uint8_t reserved_2[20];
733
734 uint8_t port_id[3]; /* PortID of destination port. */
735 uint8_t vp_index;
736
737 uint8_t reserved_3[12];
738};
739
740#define ABORT_IOCB_TYPE 0x33
741struct abort_entry_24xx {
742 uint8_t entry_type; /* Entry type. */
743 uint8_t entry_count; /* Entry count. */
744 uint8_t handle_count; /* Handle count. */
745 uint8_t entry_status; /* Entry Status. */
746
747 uint32_t handle; /* System handle. */
748
749 uint16_t nport_handle; /* N_PORT handle. */
750 /* or Completion status. */
751
752 uint16_t options; /* Options. */
753#define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */
754
755 uint32_t handle_to_abort; /* System handle to abort. */
756
757 uint8_t reserved_1[32];
758
759 uint8_t port_id[3]; /* PortID of destination port. */
760 uint8_t vp_index;
761
762 uint8_t reserved_2[12];
763};
764
765/*
766 * ISP I/O Register Set structure definitions.
767 */
768struct device_reg_24xx {
769 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */
770#define FARX_DATA_FLAG BIT_31
771#define FARX_ACCESS_FLASH_CONF 0x7FFD0000
772#define FARX_ACCESS_FLASH_DATA 0x7FF00000
773#define FARX_ACCESS_NVRAM_CONF 0x7FFF0000
774#define FARX_ACCESS_NVRAM_DATA 0x7FFE0000
775
776#define FA_NVRAM_FUNC0_ADDR 0x80
777#define FA_NVRAM_FUNC1_ADDR 0x180
778
779#define FA_NVRAM_VPD_SIZE 0x80
780#define FA_NVRAM_VPD0_ADDR 0x00
781#define FA_NVRAM_VPD1_ADDR 0x100
782 /*
783 * RISC code begins at offset 512KB
784 * within flash. Consisting of two
785 * contiguous RISC code segments.
786 */
787#define FA_RISC_CODE_ADDR 0x20000
788#define FA_RISC_CODE_SEGMENTS 2
789
790 uint32_t flash_data; /* Flash/NVRAM BIOS data. */
791
792 uint32_t ctrl_status; /* Control/Status. */
793#define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */
794#define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */
795#define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */
796#define CSRX_FUNCTION BIT_15 /* Function number. */
797 /* PCI-X Bus Mode. */
798#define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
799#define PBM_PCI_33MHZ (0 << 8)
800#define PBM_PCIX_M1_66MHZ (1 << 8)
801#define PBM_PCIX_M1_100MHZ (2 << 8)
802#define PBM_PCIX_M1_133MHZ (3 << 8)
803#define PBM_PCIX_M2_66MHZ (5 << 8)
804#define PBM_PCIX_M2_100MHZ (6 << 8)
805#define PBM_PCIX_M2_133MHZ (7 << 8)
806#define PBM_PCI_66MHZ (8 << 8)
807 /* Max Write Burst byte count. */
808#define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
809#define MWB_512_BYTES (0 << 4)
810#define MWB_1024_BYTES (1 << 4)
811#define MWB_2048_BYTES (2 << 4)
812#define MWB_4096_BYTES (3 << 4)
813
814#define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
815#define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
816#define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */
817
818 uint32_t ictrl; /* Interrupt control. */
819#define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */
820
821 uint32_t istatus; /* Interrupt status. */
822#define ISRX_RISC_INT BIT_3 /* RISC interrupt. */
823
824 uint32_t unused_1[2]; /* Gap. */
825
826 /* Request Queue. */
827 uint32_t req_q_in; /* In-Pointer. */
828 uint32_t req_q_out; /* Out-Pointer. */
829 /* Response Queue. */
830 uint32_t rsp_q_in; /* In-Pointer. */
831 uint32_t rsp_q_out; /* Out-Pointer. */
832 /* Priority Request Queue. */
833 uint32_t preq_q_in; /* In-Pointer. */
834 uint32_t preq_q_out; /* Out-Pointer. */
835
836 uint32_t unused_2[2]; /* Gap. */
837
838 /* ATIO Queue. */
839 uint32_t atio_q_in; /* In-Pointer. */
840 uint32_t atio_q_out; /* Out-Pointer. */
841
842 uint32_t host_status;
843#define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
844#define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
845
846 uint32_t hccr; /* Host command & control register. */
847 /* HCCR statuses. */
848#define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
849#define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
850#define HCCRX_RISC_PAUSE BIT_4 /* RISC Pause mode bit. */
851 /* HCCR commands. */
852 /* NOOP. */
853#define HCCRX_NOOP 0x00000000
854 /* Set RISC Reset. */
855#define HCCRX_SET_RISC_RESET 0x10000000
856 /* Clear RISC Reset. */
857#define HCCRX_CLR_RISC_RESET 0x20000000
858 /* Set RISC Pause. */
859#define HCCRX_SET_RISC_PAUSE 0x30000000
860 /* Releases RISC Pause. */
861#define HCCRX_REL_RISC_PAUSE 0x40000000
862 /* Set HOST to RISC interrupt. */
863#define HCCRX_SET_HOST_INT 0x50000000
864 /* Clear HOST to RISC interrupt. */
865#define HCCRX_CLR_HOST_INT 0x60000000
866 /* Clear RISC to PCI interrupt. */
867#define HCCRX_CLR_RISC_INT 0xA0000000
868
869 uint32_t gpiod; /* GPIO Data register. */
870 /* LED update mask. */
871#define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18)
872 /* Data update mask. */
873#define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16)
874 /* LED control mask. */
875#define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
876 /* LED bit values. Color names as
877 * referenced in fw spec.
878 */
879#define GPDX_LED_YELLOW_ON BIT_2
880#define GPDX_LED_GREEN_ON BIT_3
881#define GPDX_LED_AMBER_ON BIT_4
882 /* Data in/out. */
883#define GPDX_DATA_INOUT (BIT_1|BIT_0)
884
885 uint32_t gpioe; /* GPIO Enable register. */
886 /* Enable update mask. */
887#define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
888 /* Enable. */
889#define GPEX_ENABLE (BIT_1|BIT_0)
890
891 uint32_t iobase_addr; /* I/O Bus Base Address register. */
892
893 uint32_t unused_3[10]; /* Gap. */
894
895 uint16_t mailbox0;
896 uint16_t mailbox1;
897 uint16_t mailbox2;
898 uint16_t mailbox3;
899 uint16_t mailbox4;
900 uint16_t mailbox5;
901 uint16_t mailbox6;
902 uint16_t mailbox7;
903 uint16_t mailbox8;
904 uint16_t mailbox9;
905 uint16_t mailbox10;
906 uint16_t mailbox11;
907 uint16_t mailbox12;
908 uint16_t mailbox13;
909 uint16_t mailbox14;
910 uint16_t mailbox15;
911 uint16_t mailbox16;
912 uint16_t mailbox17;
913 uint16_t mailbox18;
914 uint16_t mailbox19;
915 uint16_t mailbox20;
916 uint16_t mailbox21;
917 uint16_t mailbox22;
918 uint16_t mailbox23;
919 uint16_t mailbox24;
920 uint16_t mailbox25;
921 uint16_t mailbox26;
922 uint16_t mailbox27;
923 uint16_t mailbox28;
924 uint16_t mailbox29;
925 uint16_t mailbox30;
926 uint16_t mailbox31;
927};
928
929/* MID Support ***************************************************************/
930
931#define MAX_MID_VPS 125
932
933struct mid_conf_entry_24xx {
934 uint16_t reserved_1;
935
936 /*
937 * BIT 0 = Enable Hard Loop Id
938 * BIT 1 = Acquire Loop ID in LIPA
939 * BIT 2 = ID not Acquired
940 * BIT 3 = Enable VP
941 * BIT 4 = Enable Initiator Mode
942 * BIT 5 = Disable Target Mode
943 * BIT 6-7 = Reserved
944 */
945 uint8_t options;
946
947 uint8_t hard_address;
948
949 uint8_t port_name[WWN_SIZE];
950 uint8_t node_name[WWN_SIZE];
951};
952
953struct mid_init_cb_24xx {
954 struct init_cb_24xx init_cb;
955
956 uint16_t count;
957 uint16_t options;
958
959 struct mid_conf_entry_24xx entries[MAX_MID_VPS];
960};
961
962
963struct mid_db_entry_24xx {
964 uint16_t status;
965#define MDBS_NON_PARTIC BIT_3
966#define MDBS_ID_ACQUIRED BIT_1
967#define MDBS_ENABLED BIT_0
968
969 uint8_t options;
970 uint8_t hard_address;
971
972 uint8_t port_name[WWN_SIZE];
973 uint8_t node_name[WWN_SIZE];
974
975 uint8_t port_id[3];
976 uint8_t reserved_1;
977};
978
979struct mid_db_24xx {
980 struct mid_db_entry_24xx entries[MAX_MID_VPS];
981};
982
983#define VP_CTRL_IOCB_TYPE 0x30 /* Vitual Port Control entry. */
984struct vp_ctrl_entry_24xx {
985 uint8_t entry_type; /* Entry type. */
986 uint8_t entry_count; /* Entry count. */
987 uint8_t sys_define; /* System defined. */
988 uint8_t entry_status; /* Entry Status. */
989
990 uint32_t handle; /* System handle. */
991
992 uint16_t vp_idx_failed;
993
994 uint16_t comp_status; /* Completion status. */
995#define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */
996#define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */
997
998 uint16_t command;
999#define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */
1000#define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */
1001#define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */
1002#define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */
1003
1004 uint16_t vp_count;
1005
1006 uint8_t vp_idx_map[16];
1007
1008 uint8_t reserved_4[32];
1009};
1010
1011#define VP_CONFIG_IOCB_TYPE 0x31 /* Vitual Port Config entry. */
1012struct vp_config_entry_24xx {
1013 uint8_t entry_type; /* Entry type. */
1014 uint8_t entry_count; /* Entry count. */
1015 uint8_t sys_define; /* System defined. */
1016 uint8_t entry_status; /* Entry Status. */
1017
1018 uint32_t handle; /* System handle. */
1019
1020 uint16_t reserved_1;
1021
1022 uint16_t comp_status; /* Completion status. */
1023#define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */
1024#define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */
1025#define CS_VCT_ERROR 0x03 /* Unknown error. */
1026#define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */
1027#define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */
1028
1029 uint8_t command;
1030#define VCT_COMMAND_MOD_VPS 0x00 /* Enable VPs. */
1031#define VCT_COMMAND_MOD_ENABLE_VPS 0x08 /* Disable VPs. */
1032
1033 uint8_t vp_count;
1034
1035 uint8_t vp_idx1;
1036 uint8_t vp_idx2;
1037
1038 uint8_t options_idx1;
1039 uint8_t hard_address_idx1;
1040 uint16_t reserved_2;
1041 uint8_t port_name_idx1[WWN_SIZE];
1042 uint8_t node_name_idx1[WWN_SIZE];
1043
1044 uint8_t options_idx2;
1045 uint8_t hard_address_idx2;
1046 uint16_t reserved_3;
1047 uint8_t port_name_idx2[WWN_SIZE];
1048 uint8_t node_name_idx2[WWN_SIZE];
1049
1050 uint8_t reserved_4[8];
1051};
1052
1053#define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */
1054struct vp_rpt_id_entry_24xx {
1055 uint8_t entry_type; /* Entry type. */
1056 uint8_t entry_count; /* Entry count. */
1057 uint8_t sys_define; /* System defined. */
1058 uint8_t entry_status; /* Entry Status. */
1059
1060 uint32_t handle; /* System handle. */
1061
1062 uint16_t vp_count; /* Format 0 -- | VP setup | VP acq |. */
1063 /* Format 1 -- | VP count |. */
1064 uint16_t vp_idx; /* Format 0 -- Reserved. */
1065 /* Format 1 -- VP status and index. */
1066
1067 uint8_t port_id[3];
1068 uint8_t format;
1069
1070 uint8_t vp_idx_map[16];
1071
1072 uint8_t reserved_4[32];
1073};
1074
1075/* END MID Support ***********************************************************/
1076#endif
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