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path: root/drivers/scsi/qla2xxx/qla_def.h
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Diffstat (limited to 'drivers/scsi/qla2xxx/qla_def.h')
-rw-r--r--drivers/scsi/qla2xxx/qla_def.h278
1 files changed, 181 insertions, 97 deletions
diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h
index 13901c24b9a0..03074e52160f 100644
--- a/drivers/scsi/qla2xxx/qla_def.h
+++ b/drivers/scsi/qla2xxx/qla_def.h
@@ -75,9 +75,28 @@
75#define IS_QLA6322(ha) 0 75#define IS_QLA6322(ha) 0
76#endif 76#endif
77 77
78#if defined(CONFIG_SCSI_QLA24XX) || defined(CONFIG_SCSI_QLA24XX_MODULE)
79#define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
80#define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
81#else
82#define IS_QLA2422(ha) 0
83#define IS_QLA2432(ha) 0
84#endif
85
86#if defined(CONFIG_SCSI_QLA25XX) || defined(CONFIG_SCSI_QLA25XX_MODULE)
87#define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
88#define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
89#else
90#define IS_QLA2512(ha) 0
91#define IS_QLA2522(ha) 0
92#endif
93
78#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 94#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
79 IS_QLA6312(ha) || IS_QLA6322(ha)) 95 IS_QLA6312(ha) || IS_QLA6322(ha))
80 96
97#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
98#define IS_QLA25XX(ha) (IS_QLA2512(ha) || IS_QLA2522(ha))
99
81/* 100/*
82 * Only non-ISP2[12]00 have extended addressing support in the firmware. 101 * Only non-ISP2[12]00 have extended addressing support in the firmware.
83 */ 102 */
@@ -191,10 +210,18 @@
191#define MANAGEMENT_SERVER 0xfe 210#define MANAGEMENT_SERVER 0xfe
192#define BROADCAST 0xff 211#define BROADCAST 0xff
193 212
194#define RESERVED_LOOP_ID(x) ((x > LAST_LOCAL_LOOP_ID && \ 213/*
195 x < SNS_FIRST_LOOP_ID) || \ 214 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
196 x == MANAGEMENT_SERVER || \ 215 * valid range of an N-PORT id is 0 through 0x7ef.
197 x == BROADCAST) 216 */
217#define NPH_LAST_HANDLE 0x7ef
218#define NPH_SNS 0x7fc /* FFFFFC */
219#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
220#define NPH_F_PORT 0x7fe /* FFFFFE */
221#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
222
223#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
224#include "qla_fw.h"
198 225
199/* 226/*
200 * Timeout timer counts in seconds 227 * Timeout timer counts in seconds
@@ -211,6 +238,7 @@
211#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 238#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
212#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 239#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
213#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */ 240#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
241#define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
214#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 242#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
215#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 243#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
216 244
@@ -279,24 +307,24 @@ typedef struct srb {
279/* 307/*
280 * ISP I/O Register Set structure definitions. 308 * ISP I/O Register Set structure definitions.
281 */ 309 */
282typedef volatile struct { 310struct device_reg_2xxx {
283 volatile uint16_t flash_address; /* Flash BIOS address */ 311 uint16_t flash_address; /* Flash BIOS address */
284 volatile uint16_t flash_data; /* Flash BIOS data */ 312 uint16_t flash_data; /* Flash BIOS data */
285 uint16_t unused_1[1]; /* Gap */ 313 uint16_t unused_1[1]; /* Gap */
286 volatile uint16_t ctrl_status; /* Control/Status */ 314 uint16_t ctrl_status; /* Control/Status */
287#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 315#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
288#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 316#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
289#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 317#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
290 318
291 volatile uint16_t ictrl; /* Interrupt control */ 319 uint16_t ictrl; /* Interrupt control */
292#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 320#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
293#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 321#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
294 322
295 volatile uint16_t istatus; /* Interrupt status */ 323 uint16_t istatus; /* Interrupt status */
296#define ISR_RISC_INT BIT_3 /* RISC interrupt */ 324#define ISR_RISC_INT BIT_3 /* RISC interrupt */
297 325
298 volatile uint16_t semaphore; /* Semaphore */ 326 uint16_t semaphore; /* Semaphore */
299 volatile uint16_t nvram; /* NVRAM register. */ 327 uint16_t nvram; /* NVRAM register. */
300#define NVR_DESELECT 0 328#define NVR_DESELECT 0
301#define NVR_BUSY BIT_15 329#define NVR_BUSY BIT_15
302#define NVR_WRT_ENABLE BIT_14 /* Write enable */ 330#define NVR_WRT_ENABLE BIT_14 /* Write enable */
@@ -308,78 +336,78 @@ typedef volatile struct {
308 336
309 union { 337 union {
310 struct { 338 struct {
311 volatile uint16_t mailbox0; 339 uint16_t mailbox0;
312 volatile uint16_t mailbox1; 340 uint16_t mailbox1;
313 volatile uint16_t mailbox2; 341 uint16_t mailbox2;
314 volatile uint16_t mailbox3; 342 uint16_t mailbox3;
315 volatile uint16_t mailbox4; 343 uint16_t mailbox4;
316 volatile uint16_t mailbox5; 344 uint16_t mailbox5;
317 volatile uint16_t mailbox6; 345 uint16_t mailbox6;
318 volatile uint16_t mailbox7; 346 uint16_t mailbox7;
319 uint16_t unused_2[59]; /* Gap */ 347 uint16_t unused_2[59]; /* Gap */
320 } __attribute__((packed)) isp2100; 348 } __attribute__((packed)) isp2100;
321 struct { 349 struct {
322 /* Request Queue */ 350 /* Request Queue */
323 volatile uint16_t req_q_in; /* In-Pointer */ 351 uint16_t req_q_in; /* In-Pointer */
324 volatile uint16_t req_q_out; /* Out-Pointer */ 352 uint16_t req_q_out; /* Out-Pointer */
325 /* Response Queue */ 353 /* Response Queue */
326 volatile uint16_t rsp_q_in; /* In-Pointer */ 354 uint16_t rsp_q_in; /* In-Pointer */
327 volatile uint16_t rsp_q_out; /* Out-Pointer */ 355 uint16_t rsp_q_out; /* Out-Pointer */
328 356
329 /* RISC to Host Status */ 357 /* RISC to Host Status */
330 volatile uint32_t host_status; 358 uint32_t host_status;
331#define HSR_RISC_INT BIT_15 /* RISC interrupt */ 359#define HSR_RISC_INT BIT_15 /* RISC interrupt */
332#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 360#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
333 361
334 /* Host to Host Semaphore */ 362 /* Host to Host Semaphore */
335 volatile uint16_t host_semaphore; 363 uint16_t host_semaphore;
336 uint16_t unused_3[17]; /* Gap */ 364 uint16_t unused_3[17]; /* Gap */
337 volatile uint16_t mailbox0; 365 uint16_t mailbox0;
338 volatile uint16_t mailbox1; 366 uint16_t mailbox1;
339 volatile uint16_t mailbox2; 367 uint16_t mailbox2;
340 volatile uint16_t mailbox3; 368 uint16_t mailbox3;
341 volatile uint16_t mailbox4; 369 uint16_t mailbox4;
342 volatile uint16_t mailbox5; 370 uint16_t mailbox5;
343 volatile uint16_t mailbox6; 371 uint16_t mailbox6;
344 volatile uint16_t mailbox7; 372 uint16_t mailbox7;
345 volatile uint16_t mailbox8; 373 uint16_t mailbox8;
346 volatile uint16_t mailbox9; 374 uint16_t mailbox9;
347 volatile uint16_t mailbox10; 375 uint16_t mailbox10;
348 volatile uint16_t mailbox11; 376 uint16_t mailbox11;
349 volatile uint16_t mailbox12; 377 uint16_t mailbox12;
350 volatile uint16_t mailbox13; 378 uint16_t mailbox13;
351 volatile uint16_t mailbox14; 379 uint16_t mailbox14;
352 volatile uint16_t mailbox15; 380 uint16_t mailbox15;
353 volatile uint16_t mailbox16; 381 uint16_t mailbox16;
354 volatile uint16_t mailbox17; 382 uint16_t mailbox17;
355 volatile uint16_t mailbox18; 383 uint16_t mailbox18;
356 volatile uint16_t mailbox19; 384 uint16_t mailbox19;
357 volatile uint16_t mailbox20; 385 uint16_t mailbox20;
358 volatile uint16_t mailbox21; 386 uint16_t mailbox21;
359 volatile uint16_t mailbox22; 387 uint16_t mailbox22;
360 volatile uint16_t mailbox23; 388 uint16_t mailbox23;
361 volatile uint16_t mailbox24; 389 uint16_t mailbox24;
362 volatile uint16_t mailbox25; 390 uint16_t mailbox25;
363 volatile uint16_t mailbox26; 391 uint16_t mailbox26;
364 volatile uint16_t mailbox27; 392 uint16_t mailbox27;
365 volatile uint16_t mailbox28; 393 uint16_t mailbox28;
366 volatile uint16_t mailbox29; 394 uint16_t mailbox29;
367 volatile uint16_t mailbox30; 395 uint16_t mailbox30;
368 volatile uint16_t mailbox31; 396 uint16_t mailbox31;
369 volatile uint16_t fb_cmd; 397 uint16_t fb_cmd;
370 uint16_t unused_4[10]; /* Gap */ 398 uint16_t unused_4[10]; /* Gap */
371 } __attribute__((packed)) isp2300; 399 } __attribute__((packed)) isp2300;
372 } u; 400 } u;
373 401
374 volatile uint16_t fpm_diag_config; 402 uint16_t fpm_diag_config;
375 uint16_t unused_5[0x6]; /* Gap */ 403 uint16_t unused_5[0x6]; /* Gap */
376 volatile uint16_t pcr; /* Processor Control Register. */ 404 uint16_t pcr; /* Processor Control Register. */
377 uint16_t unused_6[0x5]; /* Gap */ 405 uint16_t unused_6[0x5]; /* Gap */
378 volatile uint16_t mctr; /* Memory Configuration and Timing. */ 406 uint16_t mctr; /* Memory Configuration and Timing. */
379 uint16_t unused_7[0x3]; /* Gap */ 407 uint16_t unused_7[0x3]; /* Gap */
380 volatile uint16_t fb_cmd_2100; /* Unused on 23XX */ 408 uint16_t fb_cmd_2100; /* Unused on 23XX */
381 uint16_t unused_8[0x3]; /* Gap */ 409 uint16_t unused_8[0x3]; /* Gap */
382 volatile uint16_t hccr; /* Host command & control register. */ 410 uint16_t hccr; /* Host command & control register. */
383#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 411#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
384#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 412#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
385 /* HCCR commands */ 413 /* HCCR commands */
@@ -393,8 +421,8 @@ typedef volatile struct {
393#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 421#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
394 422
395 uint16_t unused_9[5]; /* Gap */ 423 uint16_t unused_9[5]; /* Gap */
396 volatile uint16_t gpiod; /* GPIO Data register. */ 424 uint16_t gpiod; /* GPIO Data register. */
397 volatile uint16_t gpioe; /* GPIO Enable register. */ 425 uint16_t gpioe; /* GPIO Enable register. */
398#define GPIO_LED_MASK 0x00C0 426#define GPIO_LED_MASK 0x00C0
399#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 427#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
400#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 428#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
@@ -403,25 +431,32 @@ typedef volatile struct {
403 431
404 union { 432 union {
405 struct { 433 struct {
406 uint16_t unused_10[8]; /* Gap */ 434 uint16_t unused_10[8]; /* Gap */
407 volatile uint16_t mailbox8; 435 uint16_t mailbox8;
408 volatile uint16_t mailbox9; 436 uint16_t mailbox9;
409 volatile uint16_t mailbox10; 437 uint16_t mailbox10;
410 volatile uint16_t mailbox11; 438 uint16_t mailbox11;
411 volatile uint16_t mailbox12; 439 uint16_t mailbox12;
412 volatile uint16_t mailbox13; 440 uint16_t mailbox13;
413 volatile uint16_t mailbox14; 441 uint16_t mailbox14;
414 volatile uint16_t mailbox15; 442 uint16_t mailbox15;
415 volatile uint16_t mailbox16; 443 uint16_t mailbox16;
416 volatile uint16_t mailbox17; 444 uint16_t mailbox17;
417 volatile uint16_t mailbox18; 445 uint16_t mailbox18;
418 volatile uint16_t mailbox19; 446 uint16_t mailbox19;
419 volatile uint16_t mailbox20; 447 uint16_t mailbox20;
420 volatile uint16_t mailbox21; 448 uint16_t mailbox21;
421 volatile uint16_t mailbox22; 449 uint16_t mailbox22;
422 volatile uint16_t mailbox23; /* Also probe reg. */ 450 uint16_t mailbox23; /* Also probe reg. */
423 } __attribute__((packed)) isp2200; 451 } __attribute__((packed)) isp2200;
424 } u_end; 452 } u_end;
453};
454
455typedef struct {
456 union {
457 struct device_reg_2xxx isp;
458 struct device_reg_24xx isp24;
459 };
425} device_reg_t; 460} device_reg_t;
426 461
427#define ISP_REQ_Q_IN(ha, reg) \ 462#define ISP_REQ_Q_IN(ha, reg) \
@@ -504,6 +539,8 @@ typedef struct {
504#define MBS_LOOP_ID_USED 0x4008 539#define MBS_LOOP_ID_USED 0x4008
505#define MBS_ALL_IDS_IN_USE 0x4009 540#define MBS_ALL_IDS_IN_USE 0x4009
506#define MBS_NOT_LOGGED_IN 0x400A 541#define MBS_NOT_LOGGED_IN 0x400A
542#define MBS_LINK_DOWN_ERROR 0x400B
543#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
507 544
508/* 545/*
509 * ISP mailbox asynchronous event status codes 546 * ISP mailbox asynchronous event status codes
@@ -555,7 +592,7 @@ typedef struct {
555#define FO1_CTIO_RETRY BIT_3 592#define FO1_CTIO_RETRY BIT_3
556#define FO1_DISABLE_LIP_F7_SW BIT_4 593#define FO1_DISABLE_LIP_F7_SW BIT_4
557#define FO1_DISABLE_100MS_LOS_WAIT BIT_5 594#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
558#define FO1_DISABLE_GPIO6_7 BIT_6 595#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
559#define FO1_AE_ON_LOOP_INIT_ERR BIT_7 596#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
560#define FO1_SET_EMPHASIS_SWING BIT_8 597#define FO1_SET_EMPHASIS_SWING BIT_8
561#define FO1_AE_AUTO_BYPASS BIT_9 598#define FO1_AE_AUTO_BYPASS BIT_9
@@ -570,6 +607,15 @@ typedef struct {
570#define FO3_ENABLE_EMERG_IOCB BIT_0 607#define FO3_ENABLE_EMERG_IOCB BIT_0
571#define FO3_AE_RND_ERROR BIT_1 608#define FO3_AE_RND_ERROR BIT_1
572 609
610/* 24XX additional firmware options */
611#define ADD_FO_COUNT 3
612#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
613#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
614
615#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
616
617#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
618
573/* 619/*
574 * ISP mailbox commands 620 * ISP mailbox commands
575 */ 621 */
@@ -638,6 +684,22 @@ typedef struct {
638#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 684#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
639#define MBC_LUN_RESET 0x7E /* Send LUN reset */ 685#define MBC_LUN_RESET 0x7E /* Send LUN reset */
640 686
687/*
688 * ISP24xx mailbox commands
689 */
690#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
691#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
692#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
693#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
694#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
695#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
696#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
697#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
698#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
699#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
700#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
701#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
702
641/* Firmware return data sizes */ 703/* Firmware return data sizes */
642#define FCAL_MAP_SIZE 128 704#define FCAL_MAP_SIZE 128
643 705
@@ -867,6 +929,9 @@ typedef struct {
867/* 929/*
868 * Get Link Status mailbox command return buffer. 930 * Get Link Status mailbox command return buffer.
869 */ 931 */
932#define GLSO_SEND_RPS BIT_0
933#define GLSO_USE_DID BIT_3
934
870typedef struct { 935typedef struct {
871 uint32_t link_fail_cnt; 936 uint32_t link_fail_cnt;
872 uint32_t loss_sync_cnt; 937 uint32_t loss_sync_cnt;
@@ -1161,7 +1226,6 @@ do { \
1161 * ISP queue - command entry structure definition. 1226 * ISP queue - command entry structure definition.
1162 */ 1227 */
1163#define COMMAND_TYPE 0x11 /* Command entry */ 1228#define COMMAND_TYPE 0x11 /* Command entry */
1164#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
1165typedef struct { 1229typedef struct {
1166 uint8_t entry_type; /* Entry type. */ 1230 uint8_t entry_type; /* Entry type. */
1167 uint8_t entry_count; /* Entry count. */ 1231 uint8_t entry_count; /* Entry count. */
@@ -1284,11 +1348,16 @@ typedef struct {
1284/* 1348/*
1285 * Status entry entry status 1349 * Status entry entry status
1286 */ 1350 */
1351#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1287#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1352#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1288#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1353#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1289#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1354#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1290#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1355#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1291#define RF_BUSY BIT_1 /* Busy */ 1356#define RF_BUSY BIT_1 /* Busy */
1357#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1358 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1359#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1360 RF_INV_E_TYPE)
1292 1361
1293/* 1362/*
1294 * Status entry SCSI status bit definitions. 1363 * Status entry SCSI status bit definitions.
@@ -1503,9 +1572,6 @@ typedef struct {
1503 port_id_t d_id; 1572 port_id_t d_id;
1504 uint8_t node_name[WWN_SIZE]; 1573 uint8_t node_name[WWN_SIZE];
1505 uint8_t port_name[WWN_SIZE]; 1574 uint8_t port_name[WWN_SIZE];
1506 uint32_t type;
1507#define SW_TYPE_IP BIT_1
1508#define SW_TYPE_SCSI BIT_0
1509} sw_info_t; 1575} sw_info_t;
1510 1576
1511/* 1577/*
@@ -1520,6 +1586,8 @@ typedef struct {
1520 union { 1586 union {
1521 cmd_a64_entry_t cmd; 1587 cmd_a64_entry_t cmd;
1522 sts_entry_t rsp; 1588 sts_entry_t rsp;
1589 struct cmd_type_7 cmd24;
1590 struct sts_entry_24xx rsp24;
1523 } p; 1591 } p;
1524 uint8_t inq[INQ_DATA_SIZE]; 1592 uint8_t inq[INQ_DATA_SIZE];
1525} inq_cmd_rsp_t; 1593} inq_cmd_rsp_t;
@@ -1555,10 +1623,13 @@ typedef struct {
1555 union { 1623 union {
1556 cmd_a64_entry_t cmd; 1624 cmd_a64_entry_t cmd;
1557 sts_entry_t rsp; 1625 sts_entry_t rsp;
1626 struct cmd_type_7 cmd24;
1627 struct sts_entry_24xx rsp24;
1558 } p; 1628 } p;
1559 rpt_lun_lst_t list; 1629 rpt_lun_lst_t list;
1560} rpt_lun_cmd_rsp_t; 1630} rpt_lun_cmd_rsp_t;
1561 1631
1632
1562/* 1633/*
1563 * Fibre channel port type. 1634 * Fibre channel port type.
1564 */ 1635 */
@@ -1646,6 +1717,7 @@ typedef struct fc_port {
1646#define FCF_FAILOVER_DISABLE BIT_22 1717#define FCF_FAILOVER_DISABLE BIT_22
1647#define FCF_DSXXX_DEVICE BIT_23 1718#define FCF_DSXXX_DEVICE BIT_23
1648#define FCF_AA_EVA_DEVICE BIT_24 1719#define FCF_AA_EVA_DEVICE BIT_24
1720#define FCF_AA_MSA_DEVICE BIT_25
1649 1721
1650/* No loop ID flag. */ 1722/* No loop ID flag. */
1651#define FC_NO_LOOP_ID 0x1000 1723#define FC_NO_LOOP_ID 0x1000
@@ -1917,6 +1989,7 @@ struct qla_board_info {
1917 1989
1918 char isp_name[8]; 1990 char isp_name[8];
1919 struct qla_fw_info *fw_info; 1991 struct qla_fw_info *fw_info;
1992 char *fw_fname;;
1920}; 1993};
1921 1994
1922/* Return data from MBC_GET_ID_LIST call. */ 1995/* Return data from MBC_GET_ID_LIST call. */
@@ -1926,6 +1999,7 @@ struct gid_list_info {
1926 uint8_t domain; 1999 uint8_t domain;
1927 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 2000 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
1928 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 2001 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2002 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
1929}; 2003};
1930#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES) 2004#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
1931 2005
@@ -2000,6 +2074,8 @@ typedef struct scsi_qla_host {
2000 uint32_t enable_lip_full_login :1; 2074 uint32_t enable_lip_full_login :1;
2001 uint32_t enable_target_reset :1; 2075 uint32_t enable_target_reset :1;
2002 uint32_t enable_led_scheme :1; 2076 uint32_t enable_led_scheme :1;
2077 uint32_t msi_enabled :1;
2078 uint32_t msix_enabled :1;
2003 } flags; 2079 } flags;
2004 2080
2005 atomic_t loop_state; 2081 atomic_t loop_state;
@@ -2036,6 +2112,7 @@ typedef struct scsi_qla_host {
2036#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */ 2112#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2037#define IOCTL_ERROR_RECOVERY 23 2113#define IOCTL_ERROR_RECOVERY 23
2038#define LOOP_RESET_NEEDED 24 2114#define LOOP_RESET_NEEDED 24
2115#define BEACON_BLINK_NEEDED 25
2039 2116
2040 uint32_t device_flags; 2117 uint32_t device_flags;
2041#define DFLG_LOCAL_DEVICES BIT_0 2118#define DFLG_LOCAL_DEVICES BIT_0
@@ -2119,6 +2196,7 @@ typedef struct scsi_qla_host {
2119 uint8_t serial2; 2196 uint8_t serial2;
2120 2197
2121 /* NVRAM configuration data */ 2198 /* NVRAM configuration data */
2199 uint16_t nvram_size;
2122 uint16_t nvram_base; 2200 uint16_t nvram_base;
2123 2201
2124 uint16_t loop_reset_delay; 2202 uint16_t loop_reset_delay;
@@ -2179,7 +2257,8 @@ typedef struct scsi_qla_host {
2179 struct dma_pool *s_dma_pool; 2257 struct dma_pool *s_dma_pool;
2180 2258
2181 dma_addr_t init_cb_dma; 2259 dma_addr_t init_cb_dma;
2182 init_cb_t *init_cb; 2260 init_cb_t *init_cb;
2261 int init_cb_size;
2183 2262
2184 dma_addr_t iodesc_pd_dma; 2263 dma_addr_t iodesc_pd_dma;
2185 port_database_t *iodesc_pd; 2264 port_database_t *iodesc_pd;
@@ -2220,6 +2299,7 @@ typedef struct scsi_qla_host {
2220 2299
2221 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 2300 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2222 uint8_t fw_seriallink_options[4]; 2301 uint8_t fw_seriallink_options[4];
2302 uint16_t fw_seriallink_options24[4];
2223 2303
2224 /* Firmware dump information. */ 2304 /* Firmware dump information. */
2225 void *fw_dump; 2305 void *fw_dump;
@@ -2228,8 +2308,12 @@ typedef struct scsi_qla_host {
2228 char *fw_dump_buffer; 2308 char *fw_dump_buffer;
2229 int fw_dump_buffer_len; 2309 int fw_dump_buffer_len;
2230 2310
2311 int fw_dumped;
2312 void *fw_dump24;
2313 int fw_dump24_len;
2314
2231 uint8_t host_str[16]; 2315 uint8_t host_str[16];
2232 uint16_t pci_attr; 2316 uint32_t pci_attr;
2233 2317
2234 uint16_t product_id[4]; 2318 uint16_t product_id[4];
2235 2319
@@ -2237,8 +2321,8 @@ typedef struct scsi_qla_host {
2237#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 2321#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2238 char *model_desc; 2322 char *model_desc;
2239 2323
2240 uint8_t node_name[WWN_SIZE]; 2324 uint8_t *node_name;
2241 uint8_t nvram_version; 2325 uint8_t *port_name;
2242 uint32_t isp_abort_cnt; 2326 uint32_t isp_abort_cnt;
2243 2327
2244 /* Needed for BEACON */ 2328 /* Needed for BEACON */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-09 16:24:43 -0400