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path: root/drivers/scsi/qla2xxx/qla_dbg.c
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Diffstat (limited to 'drivers/scsi/qla2xxx/qla_dbg.c')
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.c1102
1 files changed, 1030 insertions, 72 deletions
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
index 329d1a1fa547..72bbaa91dc77 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.c
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
@@ -2,7 +2,7 @@
2 * QLOGIC LINUX SOFTWARE 2 * QLOGIC LINUX SOFTWARE
3 * 3 *
4 * QLogic ISP2x00 device driver for Linux 2.6.x 4 * QLogic ISP2x00 device driver for Linux 2.6.x
5 * Copyright (C) 2003-2004 QLogic Corporation 5 * Copyright (C) 2003-2005 QLogic Corporation
6 * (www.qlogic.com) 6 * (www.qlogic.com)
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
@@ -36,7 +36,7 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
36 uint16_t mb0, mb2; 36 uint16_t mb0, mb2;
37 37
38 uint32_t stat; 38 uint32_t stat;
39 device_reg_t __iomem *reg = ha->iobase; 39 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
40 uint16_t __iomem *dmp_reg; 40 uint16_t __iomem *dmp_reg;
41 unsigned long flags; 41 unsigned long flags;
42 struct qla2300_fw_dump *fw; 42 struct qla2300_fw_dump *fw;
@@ -74,7 +74,7 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
74 fw->hccr = RD_REG_WORD(&reg->hccr); 74 fw->hccr = RD_REG_WORD(&reg->hccr);
75 75
76 /* Pause RISC. */ 76 /* Pause RISC. */
77 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); 77 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
78 if (IS_QLA2300(ha)) { 78 if (IS_QLA2300(ha)) {
79 for (cnt = 30000; 79 for (cnt = 30000;
80 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 && 80 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
@@ -91,85 +91,85 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
91 91
92 if (rval == QLA_SUCCESS) { 92 if (rval == QLA_SUCCESS) {
93 dmp_reg = (uint16_t __iomem *)(reg + 0); 93 dmp_reg = (uint16_t __iomem *)(reg + 0);
94 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 94 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
95 fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++); 95 fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
96 96
97 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10); 97 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
98 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) 98 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
99 fw->risc_host_reg[cnt] = RD_REG_WORD(dmp_reg++); 99 fw->risc_host_reg[cnt] = RD_REG_WORD(dmp_reg++);
100 100
101 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40); 101 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40);
102 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 102 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
103 fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++); 103 fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
104 104
105 WRT_REG_WORD(&reg->ctrl_status, 0x40); 105 WRT_REG_WORD(&reg->ctrl_status, 0x40);
106 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 106 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
107 for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++) 107 for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++)
108 fw->resp_dma_reg[cnt] = RD_REG_WORD(dmp_reg++); 108 fw->resp_dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
109 109
110 WRT_REG_WORD(&reg->ctrl_status, 0x50); 110 WRT_REG_WORD(&reg->ctrl_status, 0x50);
111 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 111 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
112 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 112 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
113 fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++); 113 fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
114 114
115 WRT_REG_WORD(&reg->ctrl_status, 0x00); 115 WRT_REG_WORD(&reg->ctrl_status, 0x00);
116 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0); 116 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
117 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 117 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
118 fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); 118 fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
119 119
120 WRT_REG_WORD(&reg->pcr, 0x2000); 120 WRT_REG_WORD(&reg->pcr, 0x2000);
121 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 121 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
122 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++) 122 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
123 fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++); 123 fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
124 124
125 WRT_REG_WORD(&reg->pcr, 0x2200); 125 WRT_REG_WORD(&reg->pcr, 0x2200);
126 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 126 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
127 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++) 127 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
128 fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++); 128 fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
129 129
130 WRT_REG_WORD(&reg->pcr, 0x2400); 130 WRT_REG_WORD(&reg->pcr, 0x2400);
131 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 131 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
132 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++) 132 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
133 fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++); 133 fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
134 134
135 WRT_REG_WORD(&reg->pcr, 0x2600); 135 WRT_REG_WORD(&reg->pcr, 0x2600);
136 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 136 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
137 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++) 137 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
138 fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++); 138 fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
139 139
140 WRT_REG_WORD(&reg->pcr, 0x2800); 140 WRT_REG_WORD(&reg->pcr, 0x2800);
141 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 141 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
142 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++) 142 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
143 fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++); 143 fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
144 144
145 WRT_REG_WORD(&reg->pcr, 0x2A00); 145 WRT_REG_WORD(&reg->pcr, 0x2A00);
146 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 146 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
147 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++) 147 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
148 fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++); 148 fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
149 149
150 WRT_REG_WORD(&reg->pcr, 0x2C00); 150 WRT_REG_WORD(&reg->pcr, 0x2C00);
151 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 151 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
152 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++) 152 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
153 fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++); 153 fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
154 154
155 WRT_REG_WORD(&reg->pcr, 0x2E00); 155 WRT_REG_WORD(&reg->pcr, 0x2E00);
156 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 156 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
157 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++) 157 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
158 fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++); 158 fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
159 159
160 WRT_REG_WORD(&reg->ctrl_status, 0x10); 160 WRT_REG_WORD(&reg->ctrl_status, 0x10);
161 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 161 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
162 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++) 162 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
163 fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); 163 fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
164 164
165 WRT_REG_WORD(&reg->ctrl_status, 0x20); 165 WRT_REG_WORD(&reg->ctrl_status, 0x20);
166 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 166 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
167 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++) 167 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
168 fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++); 168 fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
169 169
170 WRT_REG_WORD(&reg->ctrl_status, 0x30); 170 WRT_REG_WORD(&reg->ctrl_status, 0x30);
171 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 171 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
172 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++) 172 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
173 fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++); 173 fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
174 174
175 /* Reset RISC. */ 175 /* Reset RISC. */
@@ -405,7 +405,7 @@ qla2300_ascii_fw_dump(scsi_qla_host_t *ha)
405 fw = ha->fw_dump; 405 fw = ha->fw_dump;
406 406
407 qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number, 407 qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
408 qla2x00_get_fw_version_str(ha, fw_info)); 408 ha->isp_ops.fw_version_str(ha, fw_info));
409 409
410 qla_uprintf(&uiter, "\n[==>BEG]\n"); 410 qla_uprintf(&uiter, "\n[==>BEG]\n");
411 411
@@ -587,7 +587,7 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
587 uint32_t cnt, timer; 587 uint32_t cnt, timer;
588 uint16_t risc_address; 588 uint16_t risc_address;
589 uint16_t mb0, mb2; 589 uint16_t mb0, mb2;
590 device_reg_t __iomem *reg = ha->iobase; 590 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
591 uint16_t __iomem *dmp_reg; 591 uint16_t __iomem *dmp_reg;
592 unsigned long flags; 592 unsigned long flags;
593 struct qla2100_fw_dump *fw; 593 struct qla2100_fw_dump *fw;
@@ -622,7 +622,7 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
622 fw->hccr = RD_REG_WORD(&reg->hccr); 622 fw->hccr = RD_REG_WORD(&reg->hccr);
623 623
624 /* Pause RISC. */ 624 /* Pause RISC. */
625 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); 625 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
626 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 && 626 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
627 rval == QLA_SUCCESS; cnt--) { 627 rval == QLA_SUCCESS; cnt--) {
628 if (cnt) 628 if (cnt)
@@ -632,7 +632,7 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
632 } 632 }
633 if (rval == QLA_SUCCESS) { 633 if (rval == QLA_SUCCESS) {
634 dmp_reg = (uint16_t __iomem *)(reg + 0); 634 dmp_reg = (uint16_t __iomem *)(reg + 0);
635 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 635 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
636 fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++); 636 fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
637 637
638 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10); 638 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
@@ -644,67 +644,67 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
644 } 644 }
645 645
646 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x20); 646 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x20);
647 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 647 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
648 fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++); 648 fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
649 649
650 WRT_REG_WORD(&reg->ctrl_status, 0x00); 650 WRT_REG_WORD(&reg->ctrl_status, 0x00);
651 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0); 651 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
652 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 652 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
653 fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); 653 fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
654 654
655 WRT_REG_WORD(&reg->pcr, 0x2000); 655 WRT_REG_WORD(&reg->pcr, 0x2000);
656 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 656 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
657 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++) 657 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
658 fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++); 658 fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
659 659
660 WRT_REG_WORD(&reg->pcr, 0x2100); 660 WRT_REG_WORD(&reg->pcr, 0x2100);
661 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 661 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
662 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++) 662 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
663 fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++); 663 fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
664 664
665 WRT_REG_WORD(&reg->pcr, 0x2200); 665 WRT_REG_WORD(&reg->pcr, 0x2200);
666 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 666 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
667 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++) 667 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
668 fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++); 668 fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
669 669
670 WRT_REG_WORD(&reg->pcr, 0x2300); 670 WRT_REG_WORD(&reg->pcr, 0x2300);
671 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 671 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
672 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++) 672 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
673 fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++); 673 fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
674 674
675 WRT_REG_WORD(&reg->pcr, 0x2400); 675 WRT_REG_WORD(&reg->pcr, 0x2400);
676 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 676 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
677 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++) 677 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
678 fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++); 678 fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
679 679
680 WRT_REG_WORD(&reg->pcr, 0x2500); 680 WRT_REG_WORD(&reg->pcr, 0x2500);
681 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 681 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
682 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++) 682 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
683 fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++); 683 fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
684 684
685 WRT_REG_WORD(&reg->pcr, 0x2600); 685 WRT_REG_WORD(&reg->pcr, 0x2600);
686 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 686 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
687 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++) 687 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
688 fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++); 688 fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
689 689
690 WRT_REG_WORD(&reg->pcr, 0x2700); 690 WRT_REG_WORD(&reg->pcr, 0x2700);
691 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 691 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
692 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++) 692 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
693 fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++); 693 fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
694 694
695 WRT_REG_WORD(&reg->ctrl_status, 0x10); 695 WRT_REG_WORD(&reg->ctrl_status, 0x10);
696 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 696 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
697 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++) 697 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
698 fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++); 698 fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
699 699
700 WRT_REG_WORD(&reg->ctrl_status, 0x20); 700 WRT_REG_WORD(&reg->ctrl_status, 0x20);
701 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 701 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
702 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++) 702 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
703 fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++); 703 fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
704 704
705 WRT_REG_WORD(&reg->ctrl_status, 0x30); 705 WRT_REG_WORD(&reg->ctrl_status, 0x30);
706 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 706 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
707 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++) 707 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
708 fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++); 708 fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
709 709
710 /* Reset the ISP. */ 710 /* Reset the ISP. */
@@ -723,7 +723,7 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
723 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && 723 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
724 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) { 724 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
725 725
726 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); 726 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
727 for (cnt = 30000; 727 for (cnt = 30000;
728 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 && 728 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
729 rval == QLA_SUCCESS; cnt--) { 729 rval == QLA_SUCCESS; cnt--) {
@@ -819,7 +819,7 @@ qla2100_ascii_fw_dump(scsi_qla_host_t *ha)
819 fw = ha->fw_dump; 819 fw = ha->fw_dump;
820 820
821 qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number, 821 qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
822 qla2x00_get_fw_version_str(ha, fw_info)); 822 ha->isp_ops.fw_version_str(ha, fw_info));
823 823
824 qla_uprintf(&uiter, "\n[==>BEG]\n"); 824 qla_uprintf(&uiter, "\n[==>BEG]\n");
825 825
@@ -964,7 +964,7 @@ qla_uprintf(char **uiter, char *fmt, ...)
964 int iter, len; 964 int iter, len;
965 char buf[128]; 965 char buf[128];
966 va_list args; 966 va_list args;
967 967
968 va_start(args, fmt); 968 va_start(args, fmt);
969 len = vsprintf(buf, fmt, args); 969 len = vsprintf(buf, fmt, args);
970 va_end(args); 970 va_end(args);
@@ -975,16 +975,959 @@ qla_uprintf(char **uiter, char *fmt, ...)
975 return (len); 975 return (len);
976} 976}
977 977
978//FIXME 978
979void
980qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
981{
982 int rval;
983 uint32_t cnt, timer;
984 uint32_t risc_address;
985 uint16_t mb[4];
986
987 uint32_t stat;
988 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
989 uint32_t __iomem *dmp_reg;
990 uint32_t *iter_reg;
991 uint16_t __iomem *mbx_reg;
992 unsigned long flags;
993 struct qla24xx_fw_dump *fw;
994 uint32_t ext_mem_cnt;
995
996 risc_address = ext_mem_cnt = 0;
997 memset(mb, 0, sizeof(mb));
998 flags = 0;
999
1000 if (!hardware_locked)
1001 spin_lock_irqsave(&ha->hardware_lock, flags);
1002
1003 if (!ha->fw_dump24) {
1004 qla_printk(KERN_WARNING, ha,
1005 "No buffer available for dump!!!\n");
1006 goto qla24xx_fw_dump_failed;
1007 }
1008
1009 if (ha->fw_dumped) {
1010 qla_printk(KERN_WARNING, ha,
1011 "Firmware has been previously dumped (%p) -- ignoring "
1012 "request...\n", ha->fw_dump24);
1013 goto qla24xx_fw_dump_failed;
1014 }
1015 fw = (struct qla24xx_fw_dump *) ha->fw_dump24;
1016
1017 rval = QLA_SUCCESS;
1018 fw->hccr = RD_REG_DWORD(&reg->hccr);
1019
1020 /* Pause RISC. */
1021 if ((fw->hccr & HCCRX_RISC_PAUSE) == 0) {
1022 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET |
1023 HCCRX_CLR_HOST_INT);
1024 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
1025 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
1026 for (cnt = 30000;
1027 (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 &&
1028 rval == QLA_SUCCESS; cnt--) {
1029 if (cnt)
1030 udelay(100);
1031 else
1032 rval = QLA_FUNCTION_TIMEOUT;
1033 }
1034 }
1035
1036 /* Disable interrupts. */
1037 WRT_REG_DWORD(&reg->ictrl, 0);
1038 RD_REG_DWORD(&reg->ictrl);
1039
1040 if (rval == QLA_SUCCESS) {
1041 /* Host interface registers. */
1042 dmp_reg = (uint32_t __iomem *)(reg + 0);
1043 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1044 fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1045
1046 /* Mailbox registers. */
1047 mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
1048 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1049 fw->mailbox_reg[cnt] = RD_REG_WORD(mbx_reg++);
1050
1051 /* Transfer sequence registers. */
1052 iter_reg = fw->xseq_gp_reg;
1053 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00);
1054 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1055 for (cnt = 0; cnt < 16; cnt++)
1056 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1057
1058 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10);
1059 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1060 for (cnt = 0; cnt < 16; cnt++)
1061 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1062
1063 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20);
1064 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1065 for (cnt = 0; cnt < 16; cnt++)
1066 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1067
1068 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30);
1069 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1070 for (cnt = 0; cnt < 16; cnt++)
1071 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1072
1073 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40);
1074 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1075 for (cnt = 0; cnt < 16; cnt++)
1076 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1077
1078 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50);
1079 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1080 for (cnt = 0; cnt < 16; cnt++)
1081 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1082
1083 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60);
1084 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1085 for (cnt = 0; cnt < 16; cnt++)
1086 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1087
1088 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70);
1089 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1090 for (cnt = 0; cnt < 16; cnt++)
1091 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1092
1093 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0);
1094 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1095 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++)
1096 fw->xseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1097
1098 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0);
1099 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1100 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++)
1101 fw->xseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1102
1103 /* Receive sequence registers. */
1104 iter_reg = fw->rseq_gp_reg;
1105 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00);
1106 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1107 for (cnt = 0; cnt < 16; cnt++)
1108 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1109
1110 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10);
1111 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1112 for (cnt = 0; cnt < 16; cnt++)
1113 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1114
1115 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20);
1116 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1117 for (cnt = 0; cnt < 16; cnt++)
1118 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1119
1120 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30);
1121 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1122 for (cnt = 0; cnt < 16; cnt++)
1123 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1124
1125 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40);
1126 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1127 for (cnt = 0; cnt < 16; cnt++)
1128 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1129
1130 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50);
1131 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1132 for (cnt = 0; cnt < 16; cnt++)
1133 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1134
1135 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60);
1136 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1137 for (cnt = 0; cnt < 16; cnt++)
1138 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1139
1140 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70);
1141 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1142 for (cnt = 0; cnt < 16; cnt++)
1143 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1144
1145 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0);
1146 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1147 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++)
1148 fw->rseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1149
1150 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0);
1151 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1152 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++)
1153 fw->rseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1154
1155 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0);
1156 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1157 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++)
1158 fw->rseq_2_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1159
1160 /* Command DMA registers. */
1161 WRT_REG_DWORD(&reg->iobase_addr, 0x7100);
1162 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1163 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++)
1164 fw->cmd_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1165
1166 /* Queues. */
1167 iter_reg = fw->req0_dma_reg;
1168 WRT_REG_DWORD(&reg->iobase_addr, 0x7200);
1169 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1170 for (cnt = 0; cnt < 8; cnt++)
1171 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1172
1173 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1174 for (cnt = 0; cnt < 7; cnt++)
1175 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1176
1177 iter_reg = fw->resp0_dma_reg;
1178 WRT_REG_DWORD(&reg->iobase_addr, 0x7300);
1179 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1180 for (cnt = 0; cnt < 8; cnt++)
1181 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1182
1183 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1184 for (cnt = 0; cnt < 7; cnt++)
1185 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1186
1187 iter_reg = fw->req1_dma_reg;
1188 WRT_REG_DWORD(&reg->iobase_addr, 0x7400);
1189 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1190 for (cnt = 0; cnt < 8; cnt++)
1191 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1192
1193 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1194 for (cnt = 0; cnt < 7; cnt++)
1195 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1196
1197 /* Transmit DMA registers. */
1198 iter_reg = fw->xmt0_dma_reg;
1199 WRT_REG_DWORD(&reg->iobase_addr, 0x7600);
1200 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1201 for (cnt = 0; cnt < 16; cnt++)
1202 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1203
1204 WRT_REG_DWORD(&reg->iobase_addr, 0x7610);
1205 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1206 for (cnt = 0; cnt < 16; cnt++)
1207 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1208
1209 iter_reg = fw->xmt1_dma_reg;
1210 WRT_REG_DWORD(&reg->iobase_addr, 0x7620);
1211 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1212 for (cnt = 0; cnt < 16; cnt++)
1213 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1214
1215 WRT_REG_DWORD(&reg->iobase_addr, 0x7630);
1216 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1217 for (cnt = 0; cnt < 16; cnt++)
1218 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1219
1220 iter_reg = fw->xmt2_dma_reg;
1221 WRT_REG_DWORD(&reg->iobase_addr, 0x7640);
1222 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1223 for (cnt = 0; cnt < 16; cnt++)
1224 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1225
1226 WRT_REG_DWORD(&reg->iobase_addr, 0x7650);
1227 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1228 for (cnt = 0; cnt < 16; cnt++)
1229 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1230
1231 iter_reg = fw->xmt3_dma_reg;
1232 WRT_REG_DWORD(&reg->iobase_addr, 0x7660);
1233 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1234 for (cnt = 0; cnt < 16; cnt++)
1235 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1236
1237 WRT_REG_DWORD(&reg->iobase_addr, 0x7670);
1238 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1239 for (cnt = 0; cnt < 16; cnt++)
1240 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1241
1242 iter_reg = fw->xmt4_dma_reg;
1243 WRT_REG_DWORD(&reg->iobase_addr, 0x7680);
1244 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1245 for (cnt = 0; cnt < 16; cnt++)
1246 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1247
1248 WRT_REG_DWORD(&reg->iobase_addr, 0x7690);
1249 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1250 for (cnt = 0; cnt < 16; cnt++)
1251 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1252
1253 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0);
1254 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1255 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
1256 fw->xmt_data_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1257
1258 /* Receive DMA registers. */
1259 iter_reg = fw->rcvt0_data_dma_reg;
1260 WRT_REG_DWORD(&reg->iobase_addr, 0x7700);
1261 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1262 for (cnt = 0; cnt < 16; cnt++)
1263 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1264
1265 WRT_REG_DWORD(&reg->iobase_addr, 0x7710);
1266 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1267 for (cnt = 0; cnt < 16; cnt++)
1268 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1269
1270 iter_reg = fw->rcvt1_data_dma_reg;
1271 WRT_REG_DWORD(&reg->iobase_addr, 0x7720);
1272 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1273 for (cnt = 0; cnt < 16; cnt++)
1274 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1275
1276 WRT_REG_DWORD(&reg->iobase_addr, 0x7730);
1277 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1278 for (cnt = 0; cnt < 16; cnt++)
1279 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1280
1281 /* RISC registers. */
1282 iter_reg = fw->risc_gp_reg;
1283 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00);
1284 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1285 for (cnt = 0; cnt < 16; cnt++)
1286 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1287
1288 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10);
1289 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1290 for (cnt = 0; cnt < 16; cnt++)
1291 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1292
1293 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20);
1294 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1295 for (cnt = 0; cnt < 16; cnt++)
1296 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1297
1298 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30);
1299 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1300 for (cnt = 0; cnt < 16; cnt++)
1301 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1302
1303 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40);
1304 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1305 for (cnt = 0; cnt < 16; cnt++)
1306 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1307
1308 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50);
1309 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1310 for (cnt = 0; cnt < 16; cnt++)
1311 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1312
1313 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60);
1314 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1315 for (cnt = 0; cnt < 16; cnt++)
1316 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1317
1318 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1319 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1320 for (cnt = 0; cnt < 16; cnt++)
1321 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1322
1323 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1324 RD_REG_DWORD(&reg->iobase_addr);
1325 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1326 WRT_REG_DWORD(dmp_reg, 0xB0000000);
1327 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1328 fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg);
1329
1330 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1331 WRT_REG_DWORD(dmp_reg, 0xB0100000);
1332 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1333 fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg);
1334
1335 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1336 WRT_REG_DWORD(dmp_reg, 0xB0200000);
1337 dmp_reg = (uint32_t *)((uint8_t *)reg + 0xFC);
1338 fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg);
1339
1340 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1341 WRT_REG_DWORD(dmp_reg, 0xB0300000);
1342 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1343 fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg);
1344
1345 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1346 WRT_REG_DWORD(dmp_reg, 0xB0400000);
1347 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1348 fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg);
1349
1350 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1351 WRT_REG_DWORD(dmp_reg, 0xB0500000);
1352 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1353 fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg);
1354
1355 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1356 WRT_REG_DWORD(dmp_reg, 0xB0600000);
1357 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1358 fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg);
1359
1360 /* Local memory controller registers. */
1361 iter_reg = fw->lmc_reg;
1362 WRT_REG_DWORD(&reg->iobase_addr, 0x3000);
1363 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1364 for (cnt = 0; cnt < 16; cnt++)
1365 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1366
1367 WRT_REG_DWORD(&reg->iobase_addr, 0x3010);
1368 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1369 for (cnt = 0; cnt < 16; cnt++)
1370 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1371
1372 WRT_REG_DWORD(&reg->iobase_addr, 0x3020);
1373 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1374 for (cnt = 0; cnt < 16; cnt++)
1375 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1376
1377 WRT_REG_DWORD(&reg->iobase_addr, 0x3030);
1378 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1379 for (cnt = 0; cnt < 16; cnt++)
1380 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1381
1382 WRT_REG_DWORD(&reg->iobase_addr, 0x3040);
1383 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1384 for (cnt = 0; cnt < 16; cnt++)
1385 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1386
1387 WRT_REG_DWORD(&reg->iobase_addr, 0x3050);
1388 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1389 for (cnt = 0; cnt < 16; cnt++)
1390 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1391
1392 WRT_REG_DWORD(&reg->iobase_addr, 0x3060);
1393 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1394 for (cnt = 0; cnt < 16; cnt++)
1395 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1396
1397 /* Fibre Protocol Module registers. */
1398 iter_reg = fw->fpm_hdw_reg;
1399 WRT_REG_DWORD(&reg->iobase_addr, 0x4000);
1400 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1401 for (cnt = 0; cnt < 16; cnt++)
1402 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1403
1404 WRT_REG_DWORD(&reg->iobase_addr, 0x4010);
1405 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1406 for (cnt = 0; cnt < 16; cnt++)
1407 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1408
1409 WRT_REG_DWORD(&reg->iobase_addr, 0x4020);
1410 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1411 for (cnt = 0; cnt < 16; cnt++)
1412 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1413
1414 WRT_REG_DWORD(&reg->iobase_addr, 0x4030);
1415 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1416 for (cnt = 0; cnt < 16; cnt++)
1417 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1418
1419 WRT_REG_DWORD(&reg->iobase_addr, 0x4040);
1420 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1421 for (cnt = 0; cnt < 16; cnt++)
1422 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1423
1424 WRT_REG_DWORD(&reg->iobase_addr, 0x4050);
1425 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1426 for (cnt = 0; cnt < 16; cnt++)
1427 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1428
1429 WRT_REG_DWORD(&reg->iobase_addr, 0x4060);
1430 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1431 for (cnt = 0; cnt < 16; cnt++)
1432 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1433
1434 WRT_REG_DWORD(&reg->iobase_addr, 0x4070);
1435 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1436 for (cnt = 0; cnt < 16; cnt++)
1437 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1438
1439 WRT_REG_DWORD(&reg->iobase_addr, 0x4080);
1440 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1441 for (cnt = 0; cnt < 16; cnt++)
1442 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1443
1444 WRT_REG_DWORD(&reg->iobase_addr, 0x4090);
1445 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1446 for (cnt = 0; cnt < 16; cnt++)
1447 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1448
1449 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0);
1450 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1451 for (cnt = 0; cnt < 16; cnt++)
1452 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1453
1454 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0);
1455 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1456 for (cnt = 0; cnt < 16; cnt++)
1457 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1458
1459 /* Frame Buffer registers. */
1460 iter_reg = fw->fb_hdw_reg;
1461 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1462 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1463 for (cnt = 0; cnt < 16; cnt++)
1464 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1465
1466 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1467 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1468 for (cnt = 0; cnt < 16; cnt++)
1469 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1470
1471 WRT_REG_DWORD(&reg->iobase_addr, 0x6020);
1472 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1473 for (cnt = 0; cnt < 16; cnt++)
1474 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1475
1476 WRT_REG_DWORD(&reg->iobase_addr, 0x6030);
1477 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1478 for (cnt = 0; cnt < 16; cnt++)
1479 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1480
1481 WRT_REG_DWORD(&reg->iobase_addr, 0x6040);
1482 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1483 for (cnt = 0; cnt < 16; cnt++)
1484 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1485
1486 WRT_REG_DWORD(&reg->iobase_addr, 0x6100);
1487 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1488 for (cnt = 0; cnt < 16; cnt++)
1489 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1490
1491 WRT_REG_DWORD(&reg->iobase_addr, 0x6130);
1492 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1493 for (cnt = 0; cnt < 16; cnt++)
1494 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1495
1496 WRT_REG_DWORD(&reg->iobase_addr, 0x6150);
1497 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1498 for (cnt = 0; cnt < 16; cnt++)
1499 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1500
1501 WRT_REG_DWORD(&reg->iobase_addr, 0x6170);
1502 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1503 for (cnt = 0; cnt < 16; cnt++)
1504 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1505
1506 WRT_REG_DWORD(&reg->iobase_addr, 0x6190);
1507 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1508 for (cnt = 0; cnt < 16; cnt++)
1509 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1510
1511 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0);
1512 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1513 for (cnt = 0; cnt < 16; cnt++)
1514 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1515
1516 /* Reset RISC. */
1517 WRT_REG_DWORD(&reg->ctrl_status,
1518 CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1519 for (cnt = 0; cnt < 30000; cnt++) {
1520 if ((RD_REG_DWORD(&reg->ctrl_status) &
1521 CSRX_DMA_ACTIVE) == 0)
1522 break;
1523
1524 udelay(10);
1525 }
1526
1527 WRT_REG_DWORD(&reg->ctrl_status,
1528 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1529 RD_REG_DWORD(&reg->ctrl_status);
1530
1531 /* Wait for firmware to complete NVRAM accesses. */
1532 udelay(5);
1533 mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1534 for (cnt = 10000 ; cnt && mb[0]; cnt--) {
1535 udelay(5);
1536 mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1537 barrier();
1538 }
1539
1540 udelay(20);
1541 for (cnt = 0; cnt < 30000; cnt++) {
1542 if ((RD_REG_DWORD(&reg->ctrl_status) &
1543 CSRX_ISP_SOFT_RESET) == 0)
1544 break;
1545
1546 udelay(10);
1547 }
1548 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1549 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
1550 }
1551
1552 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
1553 rval == QLA_SUCCESS; cnt--) {
1554 if (cnt)
1555 udelay(100);
1556 else
1557 rval = QLA_FUNCTION_TIMEOUT;
1558 }
1559
1560 /* Memory. */
1561 if (rval == QLA_SUCCESS) {
1562 /* Code RAM. */
1563 risc_address = 0x20000;
1564 WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED);
1565 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
1566 }
1567 for (cnt = 0; cnt < sizeof(fw->code_ram) / 4 && rval == QLA_SUCCESS;
1568 cnt++, risc_address++) {
1569 WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
1570 WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
1571 RD_REG_WORD(&reg->mailbox8);
1572 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
1573
1574 for (timer = 6000000; timer; timer--) {
1575 /* Check for pending interrupts. */
1576 stat = RD_REG_DWORD(&reg->host_status);
1577 if (stat & HSRX_RISC_INT) {
1578 stat &= 0xff;
1579
1580 if (stat == 0x1 || stat == 0x2 ||
1581 stat == 0x10 || stat == 0x11) {
1582 set_bit(MBX_INTERRUPT,
1583 &ha->mbx_cmd_flags);
1584
1585 mb[0] = RD_REG_WORD(&reg->mailbox0);
1586 mb[2] = RD_REG_WORD(&reg->mailbox2);
1587 mb[3] = RD_REG_WORD(&reg->mailbox3);
1588
1589 WRT_REG_DWORD(&reg->hccr,
1590 HCCRX_CLR_RISC_INT);
1591 RD_REG_DWORD(&reg->hccr);
1592 break;
1593 }
1594
1595 /* Clear this intr; it wasn't a mailbox intr */
1596 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
1597 RD_REG_DWORD(&reg->hccr);
1598 }
1599 udelay(5);
1600 }
1601
1602 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1603 rval = mb[0] & MBS_MASK;
1604 fw->code_ram[cnt] = (mb[3] << 16) | mb[2];
1605 } else {
1606 rval = QLA_FUNCTION_FAILED;
1607 }
1608 }
1609
1610 if (rval == QLA_SUCCESS) {
1611 /* External Memory. */
1612 risc_address = 0x100000;
1613 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
1614 WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED);
1615 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
1616 }
1617 for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS;
1618 cnt++, risc_address++) {
1619 WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
1620 WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
1621 RD_REG_WORD(&reg->mailbox8);
1622 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
1623
1624 for (timer = 6000000; timer; timer--) {
1625 /* Check for pending interrupts. */
1626 stat = RD_REG_DWORD(&reg->host_status);
1627 if (stat & HSRX_RISC_INT) {
1628 stat &= 0xff;
1629
1630 if (stat == 0x1 || stat == 0x2 ||
1631 stat == 0x10 || stat == 0x11) {
1632 set_bit(MBX_INTERRUPT,
1633 &ha->mbx_cmd_flags);
1634
1635 mb[0] = RD_REG_WORD(&reg->mailbox0);
1636 mb[2] = RD_REG_WORD(&reg->mailbox2);
1637 mb[3] = RD_REG_WORD(&reg->mailbox3);
1638
1639 WRT_REG_DWORD(&reg->hccr,
1640 HCCRX_CLR_RISC_INT);
1641 RD_REG_DWORD(&reg->hccr);
1642 break;
1643 }
1644
1645 /* Clear this intr; it wasn't a mailbox intr */
1646 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
1647 RD_REG_DWORD(&reg->hccr);
1648 }
1649 udelay(5);
1650 }
1651
1652 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1653 rval = mb[0] & MBS_MASK;
1654 fw->ext_mem[cnt] = (mb[3] << 16) | mb[2];
1655 } else {
1656 rval = QLA_FUNCTION_FAILED;
1657 }
1658 }
1659
1660 if (rval != QLA_SUCCESS) {
1661 qla_printk(KERN_WARNING, ha,
1662 "Failed to dump firmware (%x)!!!\n", rval);
1663 ha->fw_dumped = 0;
1664
1665 } else {
1666 qla_printk(KERN_INFO, ha,
1667 "Firmware dump saved to temp buffer (%ld/%p).\n",
1668 ha->host_no, ha->fw_dump24);
1669 ha->fw_dumped = 1;
1670 }
1671
1672qla24xx_fw_dump_failed:
1673 if (!hardware_locked)
1674 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1675}
1676
1677void
1678qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
1679{
1680 uint32_t cnt;
1681 char *uiter;
1682 struct qla24xx_fw_dump *fw;
1683 uint32_t ext_mem_cnt;
1684
1685 uiter = ha->fw_dump_buffer;
1686 fw = ha->fw_dump24;
1687
1688 qla_uprintf(&uiter, "ISP FW Version %d.%02d.%02d Attributes %04x\n",
1689 ha->fw_major_version, ha->fw_minor_version,
1690 ha->fw_subminor_version, ha->fw_attributes);
1691
1692 qla_uprintf(&uiter, "\nHCCR Register\n%04x\n", fw->hccr);
1693
1694 qla_uprintf(&uiter, "\nHost Interface Registers");
1695 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) {
1696 if (cnt % 8 == 0)
1697 qla_uprintf(&uiter, "\n");
1698
1699 qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]);
1700 }
1701
1702 qla_uprintf(&uiter, "\n\nMailbox Registers");
1703 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) {
1704 if (cnt % 8 == 0)
1705 qla_uprintf(&uiter, "\n");
1706
1707 qla_uprintf(&uiter, "%08x ", fw->mailbox_reg[cnt]);
1708 }
1709
1710 qla_uprintf(&uiter, "\n\nXSEQ GP Registers");
1711 for (cnt = 0; cnt < sizeof(fw->xseq_gp_reg) / 4; cnt++) {
1712 if (cnt % 8 == 0)
1713 qla_uprintf(&uiter, "\n");
1714
1715 qla_uprintf(&uiter, "%08x ", fw->xseq_gp_reg[cnt]);
1716 }
1717
1718 qla_uprintf(&uiter, "\n\nXSEQ-0 Registers");
1719 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) {
1720 if (cnt % 8 == 0)
1721 qla_uprintf(&uiter, "\n");
1722
1723 qla_uprintf(&uiter, "%08x ", fw->xseq_0_reg[cnt]);
1724 }
1725
1726 qla_uprintf(&uiter, "\n\nXSEQ-1 Registers");
1727 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) {
1728 if (cnt % 8 == 0)
1729 qla_uprintf(&uiter, "\n");
1730
1731 qla_uprintf(&uiter, "%08x ", fw->xseq_1_reg[cnt]);
1732 }
1733
1734 qla_uprintf(&uiter, "\n\nRSEQ GP Registers");
1735 for (cnt = 0; cnt < sizeof(fw->rseq_gp_reg) / 4; cnt++) {
1736 if (cnt % 8 == 0)
1737 qla_uprintf(&uiter, "\n");
1738
1739 qla_uprintf(&uiter, "%08x ", fw->rseq_gp_reg[cnt]);
1740 }
1741
1742 qla_uprintf(&uiter, "\n\nRSEQ-0 Registers");
1743 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) {
1744 if (cnt % 8 == 0)
1745 qla_uprintf(&uiter, "\n");
1746
1747 qla_uprintf(&uiter, "%08x ", fw->rseq_0_reg[cnt]);
1748 }
1749
1750 qla_uprintf(&uiter, "\n\nRSEQ-1 Registers");
1751 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) {
1752 if (cnt % 8 == 0)
1753 qla_uprintf(&uiter, "\n");
1754
1755 qla_uprintf(&uiter, "%08x ", fw->rseq_1_reg[cnt]);
1756 }
1757
1758 qla_uprintf(&uiter, "\n\nRSEQ-2 Registers");
1759 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) {
1760 if (cnt % 8 == 0)
1761 qla_uprintf(&uiter, "\n");
1762
1763 qla_uprintf(&uiter, "%08x ", fw->rseq_2_reg[cnt]);
1764 }
1765
1766 qla_uprintf(&uiter, "\n\nCommand DMA Registers");
1767 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) {
1768 if (cnt % 8 == 0)
1769 qla_uprintf(&uiter, "\n");
1770
1771 qla_uprintf(&uiter, "%08x ", fw->cmd_dma_reg[cnt]);
1772 }
1773
1774 qla_uprintf(&uiter, "\n\nRequest0 Queue DMA Channel Registers");
1775 for (cnt = 0; cnt < sizeof(fw->req0_dma_reg) / 4; cnt++) {
1776 if (cnt % 8 == 0)
1777 qla_uprintf(&uiter, "\n");
1778
1779 qla_uprintf(&uiter, "%08x ", fw->req0_dma_reg[cnt]);
1780 }
1781
1782 qla_uprintf(&uiter, "\n\nResponse0 Queue DMA Channel Registers");
1783 for (cnt = 0; cnt < sizeof(fw->resp0_dma_reg) / 4; cnt++) {
1784 if (cnt % 8 == 0)
1785 qla_uprintf(&uiter, "\n");
1786
1787 qla_uprintf(&uiter, "%08x ", fw->resp0_dma_reg[cnt]);
1788 }
1789
1790 qla_uprintf(&uiter, "\n\nRequest1 Queue DMA Channel Registers");
1791 for (cnt = 0; cnt < sizeof(fw->req1_dma_reg) / 4; cnt++) {
1792 if (cnt % 8 == 0)
1793 qla_uprintf(&uiter, "\n");
1794
1795 qla_uprintf(&uiter, "%08x ", fw->req1_dma_reg[cnt]);
1796 }
1797
1798 qla_uprintf(&uiter, "\n\nXMT0 Data DMA Registers");
1799 for (cnt = 0; cnt < sizeof(fw->xmt0_dma_reg) / 4; cnt++) {
1800 if (cnt % 8 == 0)
1801 qla_uprintf(&uiter, "\n");
1802
1803 qla_uprintf(&uiter, "%08x ", fw->xmt0_dma_reg[cnt]);
1804 }
1805
1806 qla_uprintf(&uiter, "\n\nXMT1 Data DMA Registers");
1807 for (cnt = 0; cnt < sizeof(fw->xmt1_dma_reg) / 4; cnt++) {
1808 if (cnt % 8 == 0)
1809 qla_uprintf(&uiter, "\n");
1810
1811 qla_uprintf(&uiter, "%08x ", fw->xmt1_dma_reg[cnt]);
1812 }
1813
1814 qla_uprintf(&uiter, "\n\nXMT2 Data DMA Registers");
1815 for (cnt = 0; cnt < sizeof(fw->xmt2_dma_reg) / 4; cnt++) {
1816 if (cnt % 8 == 0)
1817 qla_uprintf(&uiter, "\n");
1818
1819 qla_uprintf(&uiter, "%08x ", fw->xmt2_dma_reg[cnt]);
1820 }
1821
1822 qla_uprintf(&uiter, "\n\nXMT3 Data DMA Registers");
1823 for (cnt = 0; cnt < sizeof(fw->xmt3_dma_reg) / 4; cnt++) {
1824 if (cnt % 8 == 0)
1825 qla_uprintf(&uiter, "\n");
1826
1827 qla_uprintf(&uiter, "%08x ", fw->xmt3_dma_reg[cnt]);
1828 }
1829
1830 qla_uprintf(&uiter, "\n\nXMT4 Data DMA Registers");
1831 for (cnt = 0; cnt < sizeof(fw->xmt4_dma_reg) / 4; cnt++) {
1832 if (cnt % 8 == 0)
1833 qla_uprintf(&uiter, "\n");
1834
1835 qla_uprintf(&uiter, "%08x ", fw->xmt4_dma_reg[cnt]);
1836 }
1837
1838 qla_uprintf(&uiter, "\n\nXMT Data DMA Common Registers");
1839 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) {
1840 if (cnt % 8 == 0)
1841 qla_uprintf(&uiter, "\n");
1842
1843 qla_uprintf(&uiter, "%08x ", fw->xmt_data_dma_reg[cnt]);
1844 }
1845
1846 qla_uprintf(&uiter, "\n\nRCV Thread 0 Data DMA Registers");
1847 for (cnt = 0; cnt < sizeof(fw->rcvt0_data_dma_reg) / 4; cnt++) {
1848 if (cnt % 8 == 0)
1849 qla_uprintf(&uiter, "\n");
1850
1851 qla_uprintf(&uiter, "%08x ", fw->rcvt0_data_dma_reg[cnt]);
1852 }
1853
1854 qla_uprintf(&uiter, "\n\nRCV Thread 1 Data DMA Registers");
1855 for (cnt = 0; cnt < sizeof(fw->rcvt1_data_dma_reg) / 4; cnt++) {
1856 if (cnt % 8 == 0)
1857 qla_uprintf(&uiter, "\n");
1858
1859 qla_uprintf(&uiter, "%08x ", fw->rcvt1_data_dma_reg[cnt]);
1860 }
1861
1862 qla_uprintf(&uiter, "\n\nRISC GP Registers");
1863 for (cnt = 0; cnt < sizeof(fw->risc_gp_reg) / 4; cnt++) {
1864 if (cnt % 8 == 0)
1865 qla_uprintf(&uiter, "\n");
1866
1867 qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]);
1868 }
1869
1870 qla_uprintf(&uiter, "\n\nShadow Registers");
1871 for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) {
1872 if (cnt % 8 == 0)
1873 qla_uprintf(&uiter, "\n");
1874
1875 qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]);
1876 }
1877
1878 qla_uprintf(&uiter, "\n\nLMC Registers");
1879 for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) {
1880 if (cnt % 8 == 0)
1881 qla_uprintf(&uiter, "\n");
1882
1883 qla_uprintf(&uiter, "%08x ", fw->lmc_reg[cnt]);
1884 }
1885
1886 qla_uprintf(&uiter, "\n\nFPM Hardware Registers");
1887 for (cnt = 0; cnt < sizeof(fw->fpm_hdw_reg) / 4; cnt++) {
1888 if (cnt % 8 == 0)
1889 qla_uprintf(&uiter, "\n");
1890
1891 qla_uprintf(&uiter, "%08x ", fw->fpm_hdw_reg[cnt]);
1892 }
1893
1894 qla_uprintf(&uiter, "\n\nFB Hardware Registers");
1895 for (cnt = 0; cnt < sizeof(fw->fb_hdw_reg) / 4; cnt++) {
1896 if (cnt % 8 == 0)
1897 qla_uprintf(&uiter, "\n");
1898
1899 qla_uprintf(&uiter, "%08x ", fw->fb_hdw_reg[cnt]);
1900 }
1901
1902 qla_uprintf(&uiter, "\n\nCode RAM");
1903 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
1904 if (cnt % 8 == 0) {
1905 qla_uprintf(&uiter, "\n%08x: ", cnt + 0x20000);
1906 }
1907 qla_uprintf(&uiter, "%08x ", fw->code_ram[cnt]);
1908 }
1909
1910 qla_uprintf(&uiter, "\n\nExternal Memory");
1911 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
1912 for (cnt = 0; cnt < ext_mem_cnt; cnt++) {
1913 if (cnt % 8 == 0) {
1914 qla_uprintf(&uiter, "\n%08x: ", cnt + 0x100000);
1915 }
1916 qla_uprintf(&uiter, "%08x ", fw->ext_mem[cnt]);
1917 }
1918
1919 qla_uprintf(&uiter, "\n[<==END] ISP Debug Dump");
1920}
1921
979 1922
980/****************************************************************************/ 1923/****************************************************************************/
981/* Driver Debug Functions. */ 1924/* Driver Debug Functions. */
982/****************************************************************************/ 1925/****************************************************************************/
983 1926
984void 1927void
985qla2x00_dump_regs(scsi_qla_host_t *ha) 1928qla2x00_dump_regs(scsi_qla_host_t *ha)
986{ 1929{
987 device_reg_t __iomem *reg = ha->iobase; 1930 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
988 1931
989 printk("Mailbox registers:\n"); 1932 printk("Mailbox registers:\n");
990 printk("scsi(%ld): mbox 0 0x%04x \n", 1933 printk("scsi(%ld): mbox 0 0x%04x \n",
@@ -1003,7 +1946,7 @@ qla2x00_dump_regs(scsi_qla_host_t *ha)
1003 1946
1004 1947
1005void 1948void
1006qla2x00_dump_buffer(uint8_t * b, uint32_t size) 1949qla2x00_dump_buffer(uint8_t * b, uint32_t size)
1007{ 1950{
1008 uint32_t cnt; 1951 uint32_t cnt;
1009 uint8_t c; 1952 uint8_t c;
@@ -1029,11 +1972,11 @@ qla2x00_dump_buffer(uint8_t * b, uint32_t size)
1029/************************************************************************** 1972/**************************************************************************
1030 * qla2x00_print_scsi_cmd 1973 * qla2x00_print_scsi_cmd
1031 * Dumps out info about the scsi cmd and srb. 1974 * Dumps out info about the scsi cmd and srb.
1032 * Input 1975 * Input
1033 * cmd : struct scsi_cmnd 1976 * cmd : struct scsi_cmnd
1034 **************************************************************************/ 1977 **************************************************************************/
1035void 1978void
1036qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd) 1979qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd)
1037{ 1980{
1038 int i; 1981 int i;
1039 struct scsi_qla_host *ha; 1982 struct scsi_qla_host *ha;
@@ -1056,7 +1999,7 @@ qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd)
1056 cmd->request_buffer, cmd->request_bufflen); 1999 cmd->request_buffer, cmd->request_bufflen);
1057 printk(" tag=%d, transfersize=0x%x\n", 2000 printk(" tag=%d, transfersize=0x%x\n",
1058 cmd->tag, cmd->transfersize); 2001 cmd->tag, cmd->transfersize);
1059 printk(" serial_number=%lx, SP=%p\n", cmd->serial_number, sp); 2002 printk(" serial_number=%lx, SP=%p\n", cmd->serial_number, sp);
1060 printk(" data direction=%d\n", cmd->sc_data_direction); 2003 printk(" data direction=%d\n", cmd->sc_data_direction);
1061 2004
1062 if (!sp) 2005 if (!sp)
@@ -1066,6 +2009,21 @@ qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd)
1066 printk(" state=%d\n", sp->state); 2009 printk(" state=%d\n", sp->state);
1067} 2010}
1068 2011
2012void
2013qla2x00_dump_pkt(void *pkt)
2014{
2015 uint32_t i;
2016 uint8_t *data = (uint8_t *) pkt;
2017
2018 for (i = 0; i < 64; i++) {
2019 if (!(i % 4))
2020 printk("\n%02x: ", i);
2021
2022 printk("%02x ", data[i]);
2023 }
2024 printk("\n");
2025}
2026
1069#if defined(QL_DEBUG_ROUTINES) 2027#if defined(QL_DEBUG_ROUTINES)
1070/* 2028/*
1071 * qla2x00_formatted_dump_buffer 2029 * qla2x00_formatted_dump_buffer
@@ -1078,8 +2036,8 @@ qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd)
1078 * count = number of words. 2036 * count = number of words.
1079 */ 2037 */
1080void 2038void
1081qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer, 2039qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer,
1082 uint8_t wd_size, uint32_t count) 2040 uint8_t wd_size, uint32_t count)
1083{ 2041{
1084 uint32_t cnt; 2042 uint32_t cnt;
1085 uint16_t *buf16; 2043 uint16_t *buf16;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-03 13:27:57 -0500