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-rw-r--r--drivers/scsi/pdc_adma.c741
1 files changed, 741 insertions, 0 deletions
diff --git a/drivers/scsi/pdc_adma.c b/drivers/scsi/pdc_adma.c
new file mode 100644
index 000000000000..665017eda8a6
--- /dev/null
+++ b/drivers/scsi/pdc_adma.c
@@ -0,0 +1,741 @@
1/*
2 * pdc_adma.c - Pacific Digital Corporation ADMA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Mark Lord
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 *
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
29 *
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
43#include <linux/device.h>
44#include "scsi.h"
45#include <scsi/scsi_host.h>
46#include <asm/io.h>
47#include <linux/libata.h>
48
49#define DRV_NAME "pdc_adma"
50#define DRV_VERSION "0.03"
51
52/* macro to calculate base address for ATA regs */
53#define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40))
54
55/* macro to calculate base address for ADMA regs */
56#define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20))
57
58enum {
59 ADMA_PORTS = 2,
60 ADMA_CPB_BYTES = 40,
61 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
62 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
63
64 ADMA_DMA_BOUNDARY = 0xffffffff,
65
66 /* global register offsets */
67 ADMA_MODE_LOCK = 0x00c7,
68
69 /* per-channel register offsets */
70 ADMA_CONTROL = 0x0000, /* ADMA control */
71 ADMA_STATUS = 0x0002, /* ADMA status */
72 ADMA_CPB_COUNT = 0x0004, /* CPB count */
73 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
74 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
75 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
76 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
77 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
78
79 /* ADMA_CONTROL register bits */
80 aNIEN = (1 << 8), /* irq mask: 1==masked */
81 aGO = (1 << 7), /* packet trigger ("Go!") */
82 aRSTADM = (1 << 5), /* ADMA logic reset */
83 aPIOMD4 = 0x0003, /* PIO mode 4 */
84
85 /* ADMA_STATUS register bits */
86 aPSD = (1 << 6),
87 aUIRQ = (1 << 4),
88 aPERR = (1 << 0),
89
90 /* CPB bits */
91 cDONE = (1 << 0),
92 cVLD = (1 << 0),
93 cDAT = (1 << 2),
94 cIEN = (1 << 3),
95
96 /* PRD bits */
97 pORD = (1 << 4),
98 pDIRO = (1 << 5),
99 pEND = (1 << 7),
100
101 /* ATA register flags */
102 rIGN = (1 << 5),
103 rEND = (1 << 7),
104
105 /* ATA register addresses */
106 ADMA_REGS_CONTROL = 0x0e,
107 ADMA_REGS_SECTOR_COUNT = 0x12,
108 ADMA_REGS_LBA_LOW = 0x13,
109 ADMA_REGS_LBA_MID = 0x14,
110 ADMA_REGS_LBA_HIGH = 0x15,
111 ADMA_REGS_DEVICE = 0x16,
112 ADMA_REGS_COMMAND = 0x17,
113
114 /* PCI device IDs */
115 board_1841_idx = 0, /* ADMA 2-port controller */
116};
117
118typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
119
120struct adma_port_priv {
121 u8 *pkt;
122 dma_addr_t pkt_dma;
123 adma_state_t state;
124};
125
126static int adma_ata_init_one (struct pci_dev *pdev,
127 const struct pci_device_id *ent);
128static irqreturn_t adma_intr (int irq, void *dev_instance,
129 struct pt_regs *regs);
130static int adma_port_start(struct ata_port *ap);
131static void adma_host_stop(struct ata_host_set *host_set);
132static void adma_port_stop(struct ata_port *ap);
133static void adma_phy_reset(struct ata_port *ap);
134static void adma_qc_prep(struct ata_queued_cmd *qc);
135static int adma_qc_issue(struct ata_queued_cmd *qc);
136static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
137static void adma_bmdma_stop(struct ata_queued_cmd *qc);
138static u8 adma_bmdma_status(struct ata_port *ap);
139static void adma_irq_clear(struct ata_port *ap);
140static void adma_eng_timeout(struct ata_port *ap);
141
142static Scsi_Host_Template adma_ata_sht = {
143 .module = THIS_MODULE,
144 .name = DRV_NAME,
145 .ioctl = ata_scsi_ioctl,
146 .queuecommand = ata_scsi_queuecmd,
147 .eh_strategy_handler = ata_scsi_error,
148 .can_queue = ATA_DEF_QUEUE,
149 .this_id = ATA_SHT_THIS_ID,
150 .sg_tablesize = LIBATA_MAX_PRD,
151 .max_sectors = ATA_MAX_SECTORS,
152 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
153 .emulated = ATA_SHT_EMULATED,
154 .use_clustering = ENABLE_CLUSTERING,
155 .proc_name = DRV_NAME,
156 .dma_boundary = ADMA_DMA_BOUNDARY,
157 .slave_configure = ata_scsi_slave_config,
158 .bios_param = ata_std_bios_param,
159};
160
161static const struct ata_port_operations adma_ata_ops = {
162 .port_disable = ata_port_disable,
163 .tf_load = ata_tf_load,
164 .tf_read = ata_tf_read,
165 .check_status = ata_check_status,
166 .check_atapi_dma = adma_check_atapi_dma,
167 .exec_command = ata_exec_command,
168 .dev_select = ata_std_dev_select,
169 .phy_reset = adma_phy_reset,
170 .qc_prep = adma_qc_prep,
171 .qc_issue = adma_qc_issue,
172 .eng_timeout = adma_eng_timeout,
173 .irq_handler = adma_intr,
174 .irq_clear = adma_irq_clear,
175 .port_start = adma_port_start,
176 .port_stop = adma_port_stop,
177 .host_stop = adma_host_stop,
178 .bmdma_stop = adma_bmdma_stop,
179 .bmdma_status = adma_bmdma_status,
180};
181
182static struct ata_port_info adma_port_info[] = {
183 /* board_1841_idx */
184 {
185 .sht = &adma_ata_sht,
186 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
187 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO,
188 .pio_mask = 0x10, /* pio4 */
189 .udma_mask = 0x1f, /* udma0-4 */
190 .port_ops = &adma_ata_ops,
191 },
192};
193
194static struct pci_device_id adma_ata_pci_tbl[] = {
195 { PCI_VENDOR_ID_PDC, 0x1841, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
196 board_1841_idx },
197
198 { } /* terminate list */
199};
200
201static struct pci_driver adma_ata_pci_driver = {
202 .name = DRV_NAME,
203 .id_table = adma_ata_pci_tbl,
204 .probe = adma_ata_init_one,
205 .remove = ata_pci_remove_one,
206};
207
208static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
209{
210 return 1; /* ATAPI DMA not yet supported */
211}
212
213static void adma_bmdma_stop(struct ata_queued_cmd *qc)
214{
215 /* nothing */
216}
217
218static u8 adma_bmdma_status(struct ata_port *ap)
219{
220 return 0;
221}
222
223static void adma_irq_clear(struct ata_port *ap)
224{
225 /* nothing */
226}
227
228static void adma_reset_engine(void __iomem *chan)
229{
230 /* reset ADMA to idle state */
231 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
232 udelay(2);
233 writew(aPIOMD4, chan + ADMA_CONTROL);
234 udelay(2);
235}
236
237static void adma_reinit_engine(struct ata_port *ap)
238{
239 struct adma_port_priv *pp = ap->private_data;
240 void __iomem *mmio_base = ap->host_set->mmio_base;
241 void __iomem *chan = ADMA_REGS(mmio_base, ap->port_no);
242
243 /* mask/clear ATA interrupts */
244 writeb(ATA_NIEN, (void __iomem *)ap->ioaddr.ctl_addr);
245 ata_check_status(ap);
246
247 /* reset the ADMA engine */
248 adma_reset_engine(chan);
249
250 /* set in-FIFO threshold to 0x100 */
251 writew(0x100, chan + ADMA_FIFO_IN);
252
253 /* set CPB pointer */
254 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
255
256 /* set out-FIFO threshold to 0x100 */
257 writew(0x100, chan + ADMA_FIFO_OUT);
258
259 /* set CPB count */
260 writew(1, chan + ADMA_CPB_COUNT);
261
262 /* read/discard ADMA status */
263 readb(chan + ADMA_STATUS);
264}
265
266static inline void adma_enter_reg_mode(struct ata_port *ap)
267{
268 void __iomem *chan = ADMA_REGS(ap->host_set->mmio_base, ap->port_no);
269
270 writew(aPIOMD4, chan + ADMA_CONTROL);
271 readb(chan + ADMA_STATUS); /* flush */
272}
273
274static void adma_phy_reset(struct ata_port *ap)
275{
276 struct adma_port_priv *pp = ap->private_data;
277
278 pp->state = adma_state_idle;
279 adma_reinit_engine(ap);
280 ata_port_probe(ap);
281 ata_bus_reset(ap);
282}
283
284static void adma_eng_timeout(struct ata_port *ap)
285{
286 struct adma_port_priv *pp = ap->private_data;
287
288 if (pp->state != adma_state_idle) /* healthy paranoia */
289 pp->state = adma_state_mmio;
290 adma_reinit_engine(ap);
291 ata_eng_timeout(ap);
292}
293
294static int adma_fill_sg(struct ata_queued_cmd *qc)
295{
296 struct scatterlist *sg = qc->sg;
297 struct ata_port *ap = qc->ap;
298 struct adma_port_priv *pp = ap->private_data;
299 u8 *buf = pp->pkt;
300 int nelem, i = (2 + buf[3]) * 8;
301 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
302
303 for (nelem = 0; nelem < qc->n_elem; nelem++,sg++) {
304 u32 addr;
305 u32 len;
306
307 addr = (u32)sg_dma_address(sg);
308 *(__le32 *)(buf + i) = cpu_to_le32(addr);
309 i += 4;
310
311 len = sg_dma_len(sg) >> 3;
312 *(__le32 *)(buf + i) = cpu_to_le32(len);
313 i += 4;
314
315 if ((nelem + 1) == qc->n_elem)
316 pFLAGS |= pEND;
317 buf[i++] = pFLAGS;
318 buf[i++] = qc->dev->dma_mode & 0xf;
319 buf[i++] = 0; /* pPKLW */
320 buf[i++] = 0; /* reserved */
321
322 *(__le32 *)(buf + i)
323 = (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
324 i += 4;
325
326 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", nelem,
327 (unsigned long)addr, len);
328 }
329 return i;
330}
331
332static void adma_qc_prep(struct ata_queued_cmd *qc)
333{
334 struct adma_port_priv *pp = qc->ap->private_data;
335 u8 *buf = pp->pkt;
336 u32 pkt_dma = (u32)pp->pkt_dma;
337 int i = 0;
338
339 VPRINTK("ENTER\n");
340
341 adma_enter_reg_mode(qc->ap);
342 if (qc->tf.protocol != ATA_PROT_DMA) {
343 ata_qc_prep(qc);
344 return;
345 }
346
347 buf[i++] = 0; /* Response flags */
348 buf[i++] = 0; /* reserved */
349 buf[i++] = cVLD | cDAT | cIEN;
350 i++; /* cLEN, gets filled in below */
351
352 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
353 i += 4; /* cNCPB */
354 i += 4; /* cPRD, gets filled in below */
355
356 buf[i++] = 0; /* reserved */
357 buf[i++] = 0; /* reserved */
358 buf[i++] = 0; /* reserved */
359 buf[i++] = 0; /* reserved */
360
361 /* ATA registers; must be a multiple of 4 */
362 buf[i++] = qc->tf.device;
363 buf[i++] = ADMA_REGS_DEVICE;
364 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
365 buf[i++] = qc->tf.hob_nsect;
366 buf[i++] = ADMA_REGS_SECTOR_COUNT;
367 buf[i++] = qc->tf.hob_lbal;
368 buf[i++] = ADMA_REGS_LBA_LOW;
369 buf[i++] = qc->tf.hob_lbam;
370 buf[i++] = ADMA_REGS_LBA_MID;
371 buf[i++] = qc->tf.hob_lbah;
372 buf[i++] = ADMA_REGS_LBA_HIGH;
373 }
374 buf[i++] = qc->tf.nsect;
375 buf[i++] = ADMA_REGS_SECTOR_COUNT;
376 buf[i++] = qc->tf.lbal;
377 buf[i++] = ADMA_REGS_LBA_LOW;
378 buf[i++] = qc->tf.lbam;
379 buf[i++] = ADMA_REGS_LBA_MID;
380 buf[i++] = qc->tf.lbah;
381 buf[i++] = ADMA_REGS_LBA_HIGH;
382 buf[i++] = 0;
383 buf[i++] = ADMA_REGS_CONTROL;
384 buf[i++] = rIGN;
385 buf[i++] = 0;
386 buf[i++] = qc->tf.command;
387 buf[i++] = ADMA_REGS_COMMAND | rEND;
388
389 buf[3] = (i >> 3) - 2; /* cLEN */
390 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
391
392 i = adma_fill_sg(qc);
393 wmb(); /* flush PRDs and pkt to memory */
394#if 0
395 /* dump out CPB + PRDs for debug */
396 {
397 int j, len = 0;
398 static char obuf[2048];
399 for (j = 0; j < i; ++j) {
400 len += sprintf(obuf+len, "%02x ", buf[j]);
401 if ((j & 7) == 7) {
402 printk("%s\n", obuf);
403 len = 0;
404 }
405 }
406 if (len)
407 printk("%s\n", obuf);
408 }
409#endif
410}
411
412static inline void adma_packet_start(struct ata_queued_cmd *qc)
413{
414 struct ata_port *ap = qc->ap;
415 void __iomem *chan = ADMA_REGS(ap->host_set->mmio_base, ap->port_no);
416
417 VPRINTK("ENTER, ap %p\n", ap);
418
419 /* fire up the ADMA engine */
420 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
421}
422
423static int adma_qc_issue(struct ata_queued_cmd *qc)
424{
425 struct adma_port_priv *pp = qc->ap->private_data;
426
427 switch (qc->tf.protocol) {
428 case ATA_PROT_DMA:
429 pp->state = adma_state_pkt;
430 adma_packet_start(qc);
431 return 0;
432
433 case ATA_PROT_ATAPI_DMA:
434 BUG();
435 break;
436
437 default:
438 break;
439 }
440
441 pp->state = adma_state_mmio;
442 return ata_qc_issue_prot(qc);
443}
444
445static inline unsigned int adma_intr_pkt(struct ata_host_set *host_set)
446{
447 unsigned int handled = 0, port_no;
448 u8 __iomem *mmio_base = host_set->mmio_base;
449
450 for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
451 struct ata_port *ap = host_set->ports[port_no];
452 struct adma_port_priv *pp;
453 struct ata_queued_cmd *qc;
454 void __iomem *chan = ADMA_REGS(mmio_base, port_no);
455 u8 status = readb(chan + ADMA_STATUS);
456
457 if (status == 0)
458 continue;
459 handled = 1;
460 adma_enter_reg_mode(ap);
461 if (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))
462 continue;
463 pp = ap->private_data;
464 if (!pp || pp->state != adma_state_pkt)
465 continue;
466 qc = ata_qc_from_tag(ap, ap->active_tag);
467 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
468 unsigned int err_mask = 0;
469
470 if ((status & (aPERR | aPSD | aUIRQ)))
471 err_mask = AC_ERR_OTHER;
472 else if (pp->pkt[0] != cDONE)
473 err_mask = AC_ERR_OTHER;
474
475 ata_qc_complete(qc, err_mask);
476 }
477 }
478 return handled;
479}
480
481static inline unsigned int adma_intr_mmio(struct ata_host_set *host_set)
482{
483 unsigned int handled = 0, port_no;
484
485 for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
486 struct ata_port *ap;
487 ap = host_set->ports[port_no];
488 if (ap && (!(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR)))) {
489 struct ata_queued_cmd *qc;
490 struct adma_port_priv *pp = ap->private_data;
491 if (!pp || pp->state != adma_state_mmio)
492 continue;
493 qc = ata_qc_from_tag(ap, ap->active_tag);
494 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
495
496 /* check main status, clearing INTRQ */
497 u8 status = ata_check_status(ap);
498 if ((status & ATA_BUSY))
499 continue;
500 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
501 ap->id, qc->tf.protocol, status);
502
503 /* complete taskfile transaction */
504 pp->state = adma_state_idle;
505 ata_qc_complete(qc, ac_err_mask(status));
506 handled = 1;
507 }
508 }
509 }
510 return handled;
511}
512
513static irqreturn_t adma_intr(int irq, void *dev_instance, struct pt_regs *regs)
514{
515 struct ata_host_set *host_set = dev_instance;
516 unsigned int handled = 0;
517
518 VPRINTK("ENTER\n");
519
520 spin_lock(&host_set->lock);
521 handled = adma_intr_pkt(host_set) | adma_intr_mmio(host_set);
522 spin_unlock(&host_set->lock);
523
524 VPRINTK("EXIT\n");
525
526 return IRQ_RETVAL(handled);
527}
528
529static void adma_ata_setup_port(struct ata_ioports *port, unsigned long base)
530{
531 port->cmd_addr =
532 port->data_addr = base + 0x000;
533 port->error_addr =
534 port->feature_addr = base + 0x004;
535 port->nsect_addr = base + 0x008;
536 port->lbal_addr = base + 0x00c;
537 port->lbam_addr = base + 0x010;
538 port->lbah_addr = base + 0x014;
539 port->device_addr = base + 0x018;
540 port->status_addr =
541 port->command_addr = base + 0x01c;
542 port->altstatus_addr =
543 port->ctl_addr = base + 0x038;
544}
545
546static int adma_port_start(struct ata_port *ap)
547{
548 struct device *dev = ap->host_set->dev;
549 struct adma_port_priv *pp;
550 int rc;
551
552 rc = ata_port_start(ap);
553 if (rc)
554 return rc;
555 adma_enter_reg_mode(ap);
556 rc = -ENOMEM;
557 pp = kcalloc(1, sizeof(*pp), GFP_KERNEL);
558 if (!pp)
559 goto err_out;
560 pp->pkt = dma_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
561 GFP_KERNEL);
562 if (!pp->pkt)
563 goto err_out_kfree;
564 /* paranoia? */
565 if ((pp->pkt_dma & 7) != 0) {
566 printk("bad alignment for pp->pkt_dma: %08x\n",
567 (u32)pp->pkt_dma);
568 dma_free_coherent(dev, ADMA_PKT_BYTES,
569 pp->pkt, pp->pkt_dma);
570 goto err_out_kfree;
571 }
572 memset(pp->pkt, 0, ADMA_PKT_BYTES);
573 ap->private_data = pp;
574 adma_reinit_engine(ap);
575 return 0;
576
577err_out_kfree:
578 kfree(pp);
579err_out:
580 ata_port_stop(ap);
581 return rc;
582}
583
584static void adma_port_stop(struct ata_port *ap)
585{
586 struct device *dev = ap->host_set->dev;
587 struct adma_port_priv *pp = ap->private_data;
588
589 adma_reset_engine(ADMA_REGS(ap->host_set->mmio_base, ap->port_no));
590 if (pp != NULL) {
591 ap->private_data = NULL;
592 if (pp->pkt != NULL)
593 dma_free_coherent(dev, ADMA_PKT_BYTES,
594 pp->pkt, pp->pkt_dma);
595 kfree(pp);
596 }
597 ata_port_stop(ap);
598}
599
600static void adma_host_stop(struct ata_host_set *host_set)
601{
602 unsigned int port_no;
603
604 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
605 adma_reset_engine(ADMA_REGS(host_set->mmio_base, port_no));
606
607 ata_pci_host_stop(host_set);
608}
609
610static void adma_host_init(unsigned int chip_id,
611 struct ata_probe_ent *probe_ent)
612{
613 unsigned int port_no;
614 void __iomem *mmio_base = probe_ent->mmio_base;
615
616 /* enable/lock aGO operation */
617 writeb(7, mmio_base + ADMA_MODE_LOCK);
618
619 /* reset the ADMA logic */
620 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
621 adma_reset_engine(ADMA_REGS(mmio_base, port_no));
622}
623
624static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
625{
626 int rc;
627
628 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
629 if (rc) {
630 dev_printk(KERN_ERR, &pdev->dev,
631 "32-bit DMA enable failed\n");
632 return rc;
633 }
634 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
635 if (rc) {
636 dev_printk(KERN_ERR, &pdev->dev,
637 "32-bit consistent DMA enable failed\n");
638 return rc;
639 }
640 return 0;
641}
642
643static int adma_ata_init_one(struct pci_dev *pdev,
644 const struct pci_device_id *ent)
645{
646 static int printed_version;
647 struct ata_probe_ent *probe_ent = NULL;
648 void __iomem *mmio_base;
649 unsigned int board_idx = (unsigned int) ent->driver_data;
650 int rc, port_no;
651
652 if (!printed_version++)
653 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
654
655 rc = pci_enable_device(pdev);
656 if (rc)
657 return rc;
658
659 rc = pci_request_regions(pdev, DRV_NAME);
660 if (rc)
661 goto err_out;
662
663 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) {
664 rc = -ENODEV;
665 goto err_out_regions;
666 }
667
668 mmio_base = pci_iomap(pdev, 4, 0);
669 if (mmio_base == NULL) {
670 rc = -ENOMEM;
671 goto err_out_regions;
672 }
673
674 rc = adma_set_dma_masks(pdev, mmio_base);
675 if (rc)
676 goto err_out_iounmap;
677
678 probe_ent = kcalloc(1, sizeof(*probe_ent), GFP_KERNEL);
679 if (probe_ent == NULL) {
680 rc = -ENOMEM;
681 goto err_out_iounmap;
682 }
683
684 probe_ent->dev = pci_dev_to_dev(pdev);
685 INIT_LIST_HEAD(&probe_ent->node);
686
687 probe_ent->sht = adma_port_info[board_idx].sht;
688 probe_ent->host_flags = adma_port_info[board_idx].host_flags;
689 probe_ent->pio_mask = adma_port_info[board_idx].pio_mask;
690 probe_ent->mwdma_mask = adma_port_info[board_idx].mwdma_mask;
691 probe_ent->udma_mask = adma_port_info[board_idx].udma_mask;
692 probe_ent->port_ops = adma_port_info[board_idx].port_ops;
693
694 probe_ent->irq = pdev->irq;
695 probe_ent->irq_flags = SA_SHIRQ;
696 probe_ent->mmio_base = mmio_base;
697 probe_ent->n_ports = ADMA_PORTS;
698
699 for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
700 adma_ata_setup_port(&probe_ent->port[port_no],
701 ADMA_ATA_REGS((unsigned long)mmio_base, port_no));
702 }
703
704 pci_set_master(pdev);
705
706 /* initialize adapter */
707 adma_host_init(board_idx, probe_ent);
708
709 rc = ata_device_add(probe_ent);
710 kfree(probe_ent);
711 if (rc != ADMA_PORTS)
712 goto err_out_iounmap;
713 return 0;
714
715err_out_iounmap:
716 pci_iounmap(pdev, mmio_base);
717err_out_regions:
718 pci_release_regions(pdev);
719err_out:
720 pci_disable_device(pdev);
721 return rc;
722}
723
724static int __init adma_ata_init(void)
725{
726 return pci_module_init(&adma_ata_pci_driver);
727}
728
729static void __exit adma_ata_exit(void)
730{
731 pci_unregister_driver(&adma_ata_pci_driver);
732}
733
734MODULE_AUTHOR("Mark Lord");
735MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
736MODULE_LICENSE("GPL");
737MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
738MODULE_VERSION(DRV_VERSION);
739
740module_init(adma_ata_init);
741module_exit(adma_ata_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 18:43:01 -0500