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-rw-r--r--drivers/scsi/pdc_adma.c737
1 files changed, 737 insertions, 0 deletions
diff --git a/drivers/scsi/pdc_adma.c b/drivers/scsi/pdc_adma.c
new file mode 100644
index 000000000000..ce006a5b4533
--- /dev/null
+++ b/drivers/scsi/pdc_adma.c
@@ -0,0 +1,737 @@
1/*
2 * pdc_adma.c - Pacific Digital Corporation ADMA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Mark Lord
7 *
8 * The contents of this file are subject to the Open
9 * Software License version 1.1 that can be found at
10 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
11 * by reference.
12 *
13 * Alternatively, the contents of this file may be used under the terms
14 * of the GNU General Public License version 2 (the "GPL") as distributed
15 * in the kernel source COPYING file, in which case the provisions of
16 * the GPL are applicable instead of the above. If you wish to allow
17 * the use of your version of this file only under the terms of the
18 * GPL and not to allow others to use your version of this file under
19 * the OSL, indicate your decision by deleting the provisions above and
20 * replace them with the notice and other provisions required by the GPL.
21 * If you do not delete the provisions above, a recipient may use your
22 * version of this file under either the OSL or the GPL.
23 *
24 * Supports ATA disks in single-packet ADMA mode.
25 * Uses PIO for everything else.
26 *
27 * TODO: Use ADMA transfers for ATAPI devices, when possible.
28 * This requires careful attention to a number of quirks of the chip.
29 *
30 */
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/pci.h>
35#include <linux/init.h>
36#include <linux/blkdev.h>
37#include <linux/delay.h>
38#include <linux/interrupt.h>
39#include <linux/sched.h>
40#include "scsi.h"
41#include <scsi/scsi_host.h>
42#include <asm/io.h>
43#include <linux/libata.h>
44
45#define DRV_NAME "pdc_adma"
46#define DRV_VERSION "0.01"
47
48/* macro to calculate base address for ATA regs */
49#define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40))
50
51/* macro to calculate base address for ADMA regs */
52#define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20))
53
54enum {
55 ADMA_PORTS = 2,
56 ADMA_CPB_BYTES = 40,
57 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
58 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
59
60 ADMA_DMA_BOUNDARY = 0xffffffff,
61
62 /* global register offsets */
63 ADMA_MODE_LOCK = 0x00c7,
64
65 /* per-channel register offsets */
66 ADMA_CONTROL = 0x0000, /* ADMA control */
67 ADMA_STATUS = 0x0002, /* ADMA status */
68 ADMA_CPB_COUNT = 0x0004, /* CPB count */
69 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
70 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
71 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
72 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
73 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
74
75 /* ADMA_CONTROL register bits */
76 aNIEN = (1 << 8), /* irq mask: 1==masked */
77 aGO = (1 << 7), /* packet trigger ("Go!") */
78 aRSTADM = (1 << 5), /* ADMA logic reset */
79 aAUTEN = (1 << 3), /* packet trigger ("Go!") */
80 aRSTA = (1 << 2), /* ATA hard reset */
81 aPIOMD4 = 0x0003, /* PIO mode 4 */
82
83 /* ADMA_STATUS register bits */
84 aPSD = (1 << 6),
85 aUIRQ = (1 << 4),
86 aPERR = (1 << 0),
87
88 /* CPB bits */
89 cDONE = (1 << 0),
90 cVLD = (1 << 0),
91 cDAT = (1 << 2),
92 cIEN = (1 << 3),
93
94 /* PRD bits */
95 pORD = (1 << 4),
96 pDIRO = (1 << 5),
97 pEND = (1 << 7),
98
99 /* ATA register flags */
100 rIGN = (1 << 5),
101 rEND = (1 << 7),
102
103 /* ATA register addresses */
104 ADMA_REGS_CONTROL = 0x0e,
105 ADMA_REGS_SECTOR_COUNT = 0x12,
106 ADMA_REGS_LBA_LOW = 0x13,
107 ADMA_REGS_LBA_MID = 0x14,
108 ADMA_REGS_LBA_HIGH = 0x15,
109 ADMA_REGS_DEVICE = 0x16,
110 ADMA_REGS_COMMAND = 0x17,
111
112 /* PCI device IDs */
113 board_1841_idx = 0, /* ADMA 2-port controller */
114};
115
116typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
117
118struct adma_port_priv {
119 u8 *pkt;
120 dma_addr_t pkt_dma;
121 adma_state_t state;
122};
123
124static int adma_ata_init_one (struct pci_dev *pdev,
125 const struct pci_device_id *ent);
126static irqreturn_t adma_intr (int irq, void *dev_instance,
127 struct pt_regs *regs);
128static int adma_port_start(struct ata_port *ap);
129static void adma_host_stop(struct ata_host_set *host_set);
130static void adma_port_stop(struct ata_port *ap);
131static void adma_phy_reset(struct ata_port *ap);
132static void adma_qc_prep(struct ata_queued_cmd *qc);
133static int adma_qc_issue(struct ata_queued_cmd *qc);
134static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
135static void adma_bmdma_stop(struct ata_queued_cmd *qc);
136static u8 adma_bmdma_status(struct ata_port *ap);
137static void adma_irq_clear(struct ata_port *ap);
138static void adma_eng_timeout(struct ata_port *ap);
139
140static Scsi_Host_Template adma_ata_sht = {
141 .module = THIS_MODULE,
142 .name = DRV_NAME,
143 .ioctl = ata_scsi_ioctl,
144 .queuecommand = ata_scsi_queuecmd,
145 .eh_strategy_handler = ata_scsi_error,
146 .can_queue = ATA_DEF_QUEUE,
147 .this_id = ATA_SHT_THIS_ID,
148 .sg_tablesize = LIBATA_MAX_PRD,
149 .max_sectors = ATA_MAX_SECTORS,
150 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
151 .emulated = ATA_SHT_EMULATED,
152 .use_clustering = ENABLE_CLUSTERING,
153 .proc_name = DRV_NAME,
154 .dma_boundary = ADMA_DMA_BOUNDARY,
155 .slave_configure = ata_scsi_slave_config,
156 .bios_param = ata_std_bios_param,
157};
158
159static struct ata_port_operations adma_ata_ops = {
160 .port_disable = ata_port_disable,
161 .tf_load = ata_tf_load,
162 .tf_read = ata_tf_read,
163 .check_status = ata_check_status,
164 .check_atapi_dma = adma_check_atapi_dma,
165 .exec_command = ata_exec_command,
166 .dev_select = ata_std_dev_select,
167 .phy_reset = adma_phy_reset,
168 .qc_prep = adma_qc_prep,
169 .qc_issue = adma_qc_issue,
170 .eng_timeout = adma_eng_timeout,
171 .irq_handler = adma_intr,
172 .irq_clear = adma_irq_clear,
173 .port_start = adma_port_start,
174 .port_stop = adma_port_stop,
175 .host_stop = adma_host_stop,
176 .bmdma_stop = adma_bmdma_stop,
177 .bmdma_status = adma_bmdma_status,
178};
179
180static struct ata_port_info adma_port_info[] = {
181 /* board_1841_idx */
182 {
183 .sht = &adma_ata_sht,
184 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
185 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO,
186 .pio_mask = 0x10, /* pio4 */
187 .udma_mask = 0x1f, /* udma0-4 */
188 .port_ops = &adma_ata_ops,
189 },
190};
191
192static struct pci_device_id adma_ata_pci_tbl[] = {
193 { PCI_VENDOR_ID_PDC, 0x1841, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
194 board_1841_idx },
195
196 { } /* terminate list */
197};
198
199static struct pci_driver adma_ata_pci_driver = {
200 .name = DRV_NAME,
201 .id_table = adma_ata_pci_tbl,
202 .probe = adma_ata_init_one,
203 .remove = ata_pci_remove_one,
204};
205
206static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
207{
208 return 1; /* ATAPI DMA not yet supported */
209}
210
211static void adma_bmdma_stop(struct ata_queued_cmd *qc)
212{
213 /* nothing */
214}
215
216static u8 adma_bmdma_status(struct ata_port *ap)
217{
218 return 0;
219}
220
221static void adma_irq_clear(struct ata_port *ap)
222{
223 /* nothing */
224}
225
226static void adma_reset_engine(void __iomem *chan)
227{
228 /* reset ADMA to idle state */
229 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
230 udelay(2);
231 writew(aPIOMD4, chan + ADMA_CONTROL);
232 udelay(2);
233}
234
235static void adma_reinit_engine(struct ata_port *ap)
236{
237 struct adma_port_priv *pp = ap->private_data;
238 void __iomem *mmio_base = ap->host_set->mmio_base;
239 void __iomem *chan = ADMA_REGS(mmio_base, ap->port_no);
240
241 /* mask/clear ATA interrupts */
242 writeb(ATA_NIEN, (void __iomem *)ap->ioaddr.ctl_addr);
243 ata_check_status(ap);
244
245 /* reset the ADMA engine */
246 adma_reset_engine(chan);
247
248 /* set in-FIFO threshold to 0x100 */
249 writew(0x100, chan + ADMA_FIFO_IN);
250
251 /* set CPB pointer */
252 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
253
254 /* set out-FIFO threshold to 0x100 */
255 writew(0x100, chan + ADMA_FIFO_OUT);
256
257 /* set CPB count */
258 writew(1, chan + ADMA_CPB_COUNT);
259
260 /* read/discard ADMA status */
261 readb(chan + ADMA_STATUS);
262}
263
264static inline void adma_enter_reg_mode(struct ata_port *ap)
265{
266 void __iomem *chan = ADMA_REGS(ap->host_set->mmio_base, ap->port_no);
267
268 writew(aPIOMD4, chan + ADMA_CONTROL);
269 readb(chan + ADMA_STATUS); /* flush */
270}
271
272static void adma_phy_reset(struct ata_port *ap)
273{
274 struct adma_port_priv *pp = ap->private_data;
275
276 pp->state = adma_state_idle;
277 adma_reinit_engine(ap);
278 ata_port_probe(ap);
279 ata_bus_reset(ap);
280}
281
282static void adma_eng_timeout(struct ata_port *ap)
283{
284 struct adma_port_priv *pp = ap->private_data;
285
286 if (pp->state != adma_state_idle) /* healthy paranoia */
287 pp->state = adma_state_mmio;
288 adma_reinit_engine(ap);
289 ata_eng_timeout(ap);
290}
291
292static int adma_fill_sg(struct ata_queued_cmd *qc)
293{
294 struct scatterlist *sg = qc->sg;
295 struct ata_port *ap = qc->ap;
296 struct adma_port_priv *pp = ap->private_data;
297 u8 *buf = pp->pkt;
298 int nelem, i = (2 + buf[3]) * 8;
299 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
300
301 for (nelem = 0; nelem < qc->n_elem; nelem++,sg++) {
302 u32 addr;
303 u32 len;
304
305 addr = (u32)sg_dma_address(sg);
306 *(__le32 *)(buf + i) = cpu_to_le32(addr);
307 i += 4;
308
309 len = sg_dma_len(sg) >> 3;
310 *(__le32 *)(buf + i) = cpu_to_le32(len);
311 i += 4;
312
313 if ((nelem + 1) == qc->n_elem)
314 pFLAGS |= pEND;
315 buf[i++] = pFLAGS;
316 buf[i++] = qc->dev->dma_mode & 0xf;
317 buf[i++] = 0; /* pPKLW */
318 buf[i++] = 0; /* reserved */
319
320 *(__le32 *)(buf + i)
321 = (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
322 i += 4;
323
324 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", nelem,
325 (unsigned long)addr, len);
326 }
327 return i;
328}
329
330static void adma_qc_prep(struct ata_queued_cmd *qc)
331{
332 struct adma_port_priv *pp = qc->ap->private_data;
333 u8 *buf = pp->pkt;
334 u32 pkt_dma = (u32)pp->pkt_dma;
335 int i = 0;
336
337 VPRINTK("ENTER\n");
338
339 adma_enter_reg_mode(qc->ap);
340 if (qc->tf.protocol != ATA_PROT_DMA) {
341 ata_qc_prep(qc);
342 return;
343 }
344
345 buf[i++] = 0; /* Response flags */
346 buf[i++] = 0; /* reserved */
347 buf[i++] = cVLD | cDAT | cIEN;
348 i++; /* cLEN, gets filled in below */
349
350 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
351 i += 4; /* cNCPB */
352 i += 4; /* cPRD, gets filled in below */
353
354 buf[i++] = 0; /* reserved */
355 buf[i++] = 0; /* reserved */
356 buf[i++] = 0; /* reserved */
357 buf[i++] = 0; /* reserved */
358
359 /* ATA registers; must be a multiple of 4 */
360 buf[i++] = qc->tf.device;
361 buf[i++] = ADMA_REGS_DEVICE;
362 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
363 buf[i++] = qc->tf.hob_nsect;
364 buf[i++] = ADMA_REGS_SECTOR_COUNT;
365 buf[i++] = qc->tf.hob_lbal;
366 buf[i++] = ADMA_REGS_LBA_LOW;
367 buf[i++] = qc->tf.hob_lbam;
368 buf[i++] = ADMA_REGS_LBA_MID;
369 buf[i++] = qc->tf.hob_lbah;
370 buf[i++] = ADMA_REGS_LBA_HIGH;
371 }
372 buf[i++] = qc->tf.nsect;
373 buf[i++] = ADMA_REGS_SECTOR_COUNT;
374 buf[i++] = qc->tf.lbal;
375 buf[i++] = ADMA_REGS_LBA_LOW;
376 buf[i++] = qc->tf.lbam;
377 buf[i++] = ADMA_REGS_LBA_MID;
378 buf[i++] = qc->tf.lbah;
379 buf[i++] = ADMA_REGS_LBA_HIGH;
380 buf[i++] = 0;
381 buf[i++] = ADMA_REGS_CONTROL;
382 buf[i++] = rIGN;
383 buf[i++] = 0;
384 buf[i++] = qc->tf.command;
385 buf[i++] = ADMA_REGS_COMMAND | rEND;
386
387 buf[3] = (i >> 3) - 2; /* cLEN */
388 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
389
390 i = adma_fill_sg(qc);
391 wmb(); /* flush PRDs and pkt to memory */
392#if 0
393 /* dump out CPB + PRDs for debug */
394 {
395 int j, len = 0;
396 static char obuf[2048];
397 for (j = 0; j < i; ++j) {
398 len += sprintf(obuf+len, "%02x ", buf[j]);
399 if ((j & 7) == 7) {
400 printk("%s\n", obuf);
401 len = 0;
402 }
403 }
404 if (len)
405 printk("%s\n", obuf);
406 }
407#endif
408}
409
410static inline void adma_packet_start(struct ata_queued_cmd *qc)
411{
412 struct ata_port *ap = qc->ap;
413 void __iomem *chan = ADMA_REGS(ap->host_set->mmio_base, ap->port_no);
414
415 VPRINTK("ENTER, ap %p\n", ap);
416
417 /* fire up the ADMA engine */
418 writew(aPIOMD4 | aGO | aAUTEN, chan + ADMA_CONTROL);
419}
420
421static int adma_qc_issue(struct ata_queued_cmd *qc)
422{
423 struct adma_port_priv *pp = qc->ap->private_data;
424
425 switch (qc->tf.protocol) {
426 case ATA_PROT_DMA:
427 pp->state = adma_state_pkt;
428 adma_packet_start(qc);
429 return 0;
430
431 case ATA_PROT_ATAPI_DMA:
432 BUG();
433 break;
434
435 default:
436 break;
437 }
438
439 pp->state = adma_state_mmio;
440 return ata_qc_issue_prot(qc);
441}
442
443static inline unsigned int adma_intr_pkt(struct ata_host_set *host_set)
444{
445 unsigned int handled = 0, port_no;
446 u8 __iomem *mmio_base = host_set->mmio_base;
447
448 for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
449 struct ata_port *ap = host_set->ports[port_no];
450 struct adma_port_priv *pp;
451 struct ata_queued_cmd *qc;
452 void __iomem *chan = ADMA_REGS(mmio_base, port_no);
453 u8 drv_stat, status = readb(chan + ADMA_STATUS);
454
455 if (status == 0)
456 continue;
457 handled = 1;
458 adma_enter_reg_mode(ap);
459 if ((ap->flags & ATA_FLAG_PORT_DISABLED))
460 continue;
461 pp = ap->private_data;
462 if (!pp || pp->state != adma_state_pkt)
463 continue;
464 qc = ata_qc_from_tag(ap, ap->active_tag);
465 drv_stat = 0;
466 if ((status & (aPERR | aPSD | aUIRQ)))
467 drv_stat = ATA_ERR;
468 else if (pp->pkt[0] != cDONE)
469 drv_stat = ATA_ERR;
470 ata_qc_complete(qc, drv_stat);
471 }
472 return handled;
473}
474
475static inline unsigned int adma_intr_mmio(struct ata_host_set *host_set)
476{
477 unsigned int handled = 0, port_no;
478
479 for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
480 struct ata_port *ap;
481 ap = host_set->ports[port_no];
482 if (ap && (!(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR)))) {
483 struct ata_queued_cmd *qc;
484 struct adma_port_priv *pp = ap->private_data;
485 if (!pp || pp->state != adma_state_mmio)
486 continue;
487 qc = ata_qc_from_tag(ap, ap->active_tag);
488 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
489
490 /* check main status, clearing INTRQ */
491 u8 status = ata_chk_status(ap);
492 if ((status & ATA_BUSY))
493 continue;
494 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
495 ap->id, qc->tf.protocol, status);
496
497 /* complete taskfile transaction */
498 pp->state = adma_state_idle;
499 ata_qc_complete(qc, status);
500 handled = 1;
501 }
502 }
503 }
504 return handled;
505}
506
507static irqreturn_t adma_intr(int irq, void *dev_instance, struct pt_regs *regs)
508{
509 struct ata_host_set *host_set = dev_instance;
510 unsigned int handled = 0;
511
512 VPRINTK("ENTER\n");
513
514 spin_lock(&host_set->lock);
515 handled = adma_intr_pkt(host_set) | adma_intr_mmio(host_set);
516 spin_unlock(&host_set->lock);
517
518 VPRINTK("EXIT\n");
519
520 return IRQ_RETVAL(handled);
521}
522
523static void adma_ata_setup_port(struct ata_ioports *port, unsigned long base)
524{
525 port->cmd_addr =
526 port->data_addr = base + 0x000;
527 port->error_addr =
528 port->feature_addr = base + 0x004;
529 port->nsect_addr = base + 0x008;
530 port->lbal_addr = base + 0x00c;
531 port->lbam_addr = base + 0x010;
532 port->lbah_addr = base + 0x014;
533 port->device_addr = base + 0x018;
534 port->status_addr =
535 port->command_addr = base + 0x01c;
536 port->altstatus_addr =
537 port->ctl_addr = base + 0x038;
538}
539
540static int adma_port_start(struct ata_port *ap)
541{
542 struct device *dev = ap->host_set->dev;
543 struct adma_port_priv *pp;
544 int rc;
545
546 rc = ata_port_start(ap);
547 if (rc)
548 return rc;
549 adma_enter_reg_mode(ap);
550 rc = -ENOMEM;
551 pp = kcalloc(1, sizeof(*pp), GFP_KERNEL);
552 if (!pp)
553 goto err_out;
554 pp->pkt = dma_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
555 GFP_KERNEL);
556 if (!pp->pkt)
557 goto err_out_kfree;
558 /* paranoia? */
559 if ((pp->pkt_dma & 7) != 0) {
560 printk("bad alignment for pp->pkt_dma: %08x\n",
561 (u32)pp->pkt_dma);
562 goto err_out_kfree2;
563 }
564 memset(pp->pkt, 0, ADMA_PKT_BYTES);
565 ap->private_data = pp;
566 adma_reinit_engine(ap);
567 return 0;
568
569err_out_kfree2:
570 kfree(pp);
571err_out_kfree:
572 kfree(pp);
573err_out:
574 ata_port_stop(ap);
575 return rc;
576}
577
578static void adma_port_stop(struct ata_port *ap)
579{
580 struct device *dev = ap->host_set->dev;
581 struct adma_port_priv *pp = ap->private_data;
582
583 adma_reset_engine(ADMA_REGS(ap->host_set->mmio_base, ap->port_no));
584 if (pp != NULL) {
585 ap->private_data = NULL;
586 if (pp->pkt != NULL)
587 dma_free_coherent(dev, ADMA_PKT_BYTES,
588 pp->pkt, pp->pkt_dma);
589 kfree(pp);
590 }
591 ata_port_stop(ap);
592}
593
594static void adma_host_stop(struct ata_host_set *host_set)
595{
596 unsigned int port_no;
597
598 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
599 adma_reset_engine(ADMA_REGS(host_set->mmio_base, port_no));
600
601 ata_pci_host_stop(host_set);
602}
603
604static void adma_host_init(unsigned int chip_id,
605 struct ata_probe_ent *probe_ent)
606{
607 unsigned int port_no;
608 void __iomem *mmio_base = probe_ent->mmio_base;
609
610 /* enable/lock aGO operation */
611 writeb(7, mmio_base + ADMA_MODE_LOCK);
612
613 /* reset the ADMA logic */
614 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
615 adma_reset_engine(ADMA_REGS(mmio_base, port_no));
616}
617
618static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
619{
620 int rc;
621
622 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
623 if (rc) {
624 printk(KERN_ERR DRV_NAME
625 "(%s): 32-bit DMA enable failed\n",
626 pci_name(pdev));
627 return rc;
628 }
629 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
630 if (rc) {
631 printk(KERN_ERR DRV_NAME
632 "(%s): 32-bit consistent DMA enable failed\n",
633 pci_name(pdev));
634 return rc;
635 }
636 return 0;
637}
638
639static int adma_ata_init_one(struct pci_dev *pdev,
640 const struct pci_device_id *ent)
641{
642 static int printed_version;
643 struct ata_probe_ent *probe_ent = NULL;
644 void __iomem *mmio_base;
645 unsigned int board_idx = (unsigned int) ent->driver_data;
646 int rc, port_no;
647
648 if (!printed_version++)
649 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
650
651 rc = pci_enable_device(pdev);
652 if (rc)
653 return rc;
654
655 rc = pci_request_regions(pdev, DRV_NAME);
656 if (rc)
657 goto err_out;
658
659 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) {
660 rc = -ENODEV;
661 goto err_out_regions;
662 }
663
664 mmio_base = pci_iomap(pdev, 4, 0);
665 if (mmio_base == NULL) {
666 rc = -ENOMEM;
667 goto err_out_regions;
668 }
669
670 rc = adma_set_dma_masks(pdev, mmio_base);
671 if (rc)
672 goto err_out_iounmap;
673
674 probe_ent = kcalloc(1, sizeof(*probe_ent), GFP_KERNEL);
675 if (probe_ent == NULL) {
676 rc = -ENOMEM;
677 goto err_out_iounmap;
678 }
679
680 probe_ent->dev = pci_dev_to_dev(pdev);
681 INIT_LIST_HEAD(&probe_ent->node);
682
683 probe_ent->sht = adma_port_info[board_idx].sht;
684 probe_ent->host_flags = adma_port_info[board_idx].host_flags;
685 probe_ent->pio_mask = adma_port_info[board_idx].pio_mask;
686 probe_ent->mwdma_mask = adma_port_info[board_idx].mwdma_mask;
687 probe_ent->udma_mask = adma_port_info[board_idx].udma_mask;
688 probe_ent->port_ops = adma_port_info[board_idx].port_ops;
689
690 probe_ent->irq = pdev->irq;
691 probe_ent->irq_flags = SA_SHIRQ;
692 probe_ent->mmio_base = mmio_base;
693 probe_ent->n_ports = ADMA_PORTS;
694
695 for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
696 adma_ata_setup_port(&probe_ent->port[port_no],
697 ADMA_ATA_REGS((unsigned long)mmio_base, port_no));
698 }
699
700 pci_set_master(pdev);
701
702 /* initialize adapter */
703 adma_host_init(board_idx, probe_ent);
704
705 rc = ata_device_add(probe_ent);
706 kfree(probe_ent);
707 if (rc != ADMA_PORTS)
708 goto err_out_iounmap;
709 return 0;
710
711err_out_iounmap:
712 pci_iounmap(pdev, mmio_base);
713err_out_regions:
714 pci_release_regions(pdev);
715err_out:
716 pci_disable_device(pdev);
717 return rc;
718}
719
720static int __init adma_ata_init(void)
721{
722 return pci_module_init(&adma_ata_pci_driver);
723}
724
725static void __exit adma_ata_exit(void)
726{
727 pci_unregister_driver(&adma_ata_pci_driver);
728}
729
730MODULE_AUTHOR("Mark Lord");
731MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
732MODULE_LICENSE("GPL");
733MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
734MODULE_VERSION(DRV_VERSION);
735
736module_init(adma_ata_init);
737module_exit(adma_ata_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 22:57:02 -0500