diff options
Diffstat (limited to 'drivers/scsi/mvsas')
-rw-r--r-- | drivers/scsi/mvsas/mv_94xx.c | 267 | ||||
-rw-r--r-- | drivers/scsi/mvsas/mv_94xx.h | 58 | ||||
-rw-r--r-- | drivers/scsi/mvsas/mv_init.c | 3 | ||||
-rw-r--r-- | drivers/scsi/mvsas/mv_sas.h | 68 |
4 files changed, 382 insertions, 14 deletions
diff --git a/drivers/scsi/mvsas/mv_94xx.c b/drivers/scsi/mvsas/mv_94xx.c index 9d60c7c19b32..3f2ad934c917 100644 --- a/drivers/scsi/mvsas/mv_94xx.c +++ b/drivers/scsi/mvsas/mv_94xx.c | |||
@@ -48,6 +48,216 @@ static void mvs_94xx_detect_porttype(struct mvs_info *mvi, int i) | |||
48 | } | 48 | } |
49 | } | 49 | } |
50 | 50 | ||
51 | void set_phy_tuning(struct mvs_info *mvi, int phy_id, | ||
52 | struct phy_tuning phy_tuning) | ||
53 | { | ||
54 | u32 tmp, setting_0 = 0, setting_1 = 0; | ||
55 | u8 i; | ||
56 | |||
57 | /* Remap information for B0 chip: | ||
58 | * | ||
59 | * R0Ch -> R118h[15:0] (Adapted DFE F3 - F5 coefficient) | ||
60 | * R0Dh -> R118h[31:16] (Generation 1 Setting 0) | ||
61 | * R0Eh -> R11Ch[15:0] (Generation 1 Setting 1) | ||
62 | * R0Fh -> R11Ch[31:16] (Generation 2 Setting 0) | ||
63 | * R10h -> R120h[15:0] (Generation 2 Setting 1) | ||
64 | * R11h -> R120h[31:16] (Generation 3 Setting 0) | ||
65 | * R12h -> R124h[15:0] (Generation 3 Setting 1) | ||
66 | * R13h -> R124h[31:16] (Generation 4 Setting 0 (Reserved)) | ||
67 | */ | ||
68 | |||
69 | /* A0 has a different set of registers */ | ||
70 | if (mvi->pdev->revision == VANIR_A0_REV) | ||
71 | return; | ||
72 | |||
73 | for (i = 0; i < 3; i++) { | ||
74 | /* loop 3 times, set Gen 1, Gen 2, Gen 3 */ | ||
75 | switch (i) { | ||
76 | case 0: | ||
77 | setting_0 = GENERATION_1_SETTING; | ||
78 | setting_1 = GENERATION_1_2_SETTING; | ||
79 | break; | ||
80 | case 1: | ||
81 | setting_0 = GENERATION_1_2_SETTING; | ||
82 | setting_1 = GENERATION_2_3_SETTING; | ||
83 | break; | ||
84 | case 2: | ||
85 | setting_0 = GENERATION_2_3_SETTING; | ||
86 | setting_1 = GENERATION_3_4_SETTING; | ||
87 | break; | ||
88 | } | ||
89 | |||
90 | /* Set: | ||
91 | * | ||
92 | * Transmitter Emphasis Enable | ||
93 | * Transmitter Emphasis Amplitude | ||
94 | * Transmitter Amplitude | ||
95 | */ | ||
96 | mvs_write_port_vsr_addr(mvi, phy_id, setting_0); | ||
97 | tmp = mvs_read_port_vsr_data(mvi, phy_id); | ||
98 | tmp &= ~(0xFBE << 16); | ||
99 | tmp |= (((phy_tuning.trans_emp_en << 11) | | ||
100 | (phy_tuning.trans_emp_amp << 7) | | ||
101 | (phy_tuning.trans_amp << 1)) << 16); | ||
102 | mvs_write_port_vsr_data(mvi, phy_id, tmp); | ||
103 | |||
104 | /* Set Transmitter Amplitude Adjust */ | ||
105 | mvs_write_port_vsr_addr(mvi, phy_id, setting_1); | ||
106 | tmp = mvs_read_port_vsr_data(mvi, phy_id); | ||
107 | tmp &= ~(0xC000); | ||
108 | tmp |= (phy_tuning.trans_amp_adj << 14); | ||
109 | mvs_write_port_vsr_data(mvi, phy_id, tmp); | ||
110 | } | ||
111 | } | ||
112 | |||
113 | void set_phy_ffe_tuning(struct mvs_info *mvi, int phy_id, | ||
114 | struct ffe_control ffe) | ||
115 | { | ||
116 | u32 tmp; | ||
117 | |||
118 | /* Don't run this if A0/B0 */ | ||
119 | if ((mvi->pdev->revision == VANIR_A0_REV) | ||
120 | || (mvi->pdev->revision == VANIR_B0_REV)) | ||
121 | return; | ||
122 | |||
123 | /* FFE Resistor and Capacitor */ | ||
124 | /* R10Ch DFE Resolution Control/Squelch and FFE Setting | ||
125 | * | ||
126 | * FFE_FORCE [7] | ||
127 | * FFE_RES_SEL [6:4] | ||
128 | * FFE_CAP_SEL [3:0] | ||
129 | */ | ||
130 | mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_FFE_CONTROL); | ||
131 | tmp = mvs_read_port_vsr_data(mvi, phy_id); | ||
132 | tmp &= ~0xFF; | ||
133 | |||
134 | /* Read from HBA_Info_Page */ | ||
135 | tmp |= ((0x1 << 7) | | ||
136 | (ffe.ffe_rss_sel << 4) | | ||
137 | (ffe.ffe_cap_sel << 0)); | ||
138 | |||
139 | mvs_write_port_vsr_data(mvi, phy_id, tmp); | ||
140 | |||
141 | /* R064h PHY Mode Register 1 | ||
142 | * | ||
143 | * DFE_DIS 18 | ||
144 | */ | ||
145 | mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL); | ||
146 | tmp = mvs_read_port_vsr_data(mvi, phy_id); | ||
147 | tmp &= ~0x40001; | ||
148 | /* Hard coding */ | ||
149 | /* No defines in HBA_Info_Page */ | ||
150 | tmp |= (0 << 18); | ||
151 | mvs_write_port_vsr_data(mvi, phy_id, tmp); | ||
152 | |||
153 | /* R110h DFE F0-F1 Coefficient Control/DFE Update Control | ||
154 | * | ||
155 | * DFE_UPDATE_EN [11:6] | ||
156 | * DFE_FX_FORCE [5:0] | ||
157 | */ | ||
158 | mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_DFE_UPDATE_CRTL); | ||
159 | tmp = mvs_read_port_vsr_data(mvi, phy_id); | ||
160 | tmp &= ~0xFFF; | ||
161 | /* Hard coding */ | ||
162 | /* No defines in HBA_Info_Page */ | ||
163 | tmp |= ((0x3F << 6) | (0x0 << 0)); | ||
164 | mvs_write_port_vsr_data(mvi, phy_id, tmp); | ||
165 | |||
166 | /* R1A0h Interface and Digital Reference Clock Control/Reserved_50h | ||
167 | * | ||
168 | * FFE_TRAIN_EN 3 | ||
169 | */ | ||
170 | mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL); | ||
171 | tmp = mvs_read_port_vsr_data(mvi, phy_id); | ||
172 | tmp &= ~0x8; | ||
173 | /* Hard coding */ | ||
174 | /* No defines in HBA_Info_Page */ | ||
175 | tmp |= (0 << 3); | ||
176 | mvs_write_port_vsr_data(mvi, phy_id, tmp); | ||
177 | } | ||
178 | |||
179 | /*Notice: this function must be called when phy is disabled*/ | ||
180 | void set_phy_rate(struct mvs_info *mvi, int phy_id, u8 rate) | ||
181 | { | ||
182 | union reg_phy_cfg phy_cfg, phy_cfg_tmp; | ||
183 | mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); | ||
184 | phy_cfg_tmp.v = mvs_read_port_vsr_data(mvi, phy_id); | ||
185 | phy_cfg.v = 0; | ||
186 | phy_cfg.u.disable_phy = phy_cfg_tmp.u.disable_phy; | ||
187 | phy_cfg.u.sas_support = 1; | ||
188 | phy_cfg.u.sata_support = 1; | ||
189 | phy_cfg.u.sata_host_mode = 1; | ||
190 | |||
191 | switch (rate) { | ||
192 | case 0x0: | ||
193 | /* support 1.5 Gbps */ | ||
194 | phy_cfg.u.speed_support = 1; | ||
195 | phy_cfg.u.snw_3_support = 0; | ||
196 | phy_cfg.u.tx_lnk_parity = 1; | ||
197 | phy_cfg.u.tx_spt_phs_lnk_rate = 0x30; | ||
198 | break; | ||
199 | case 0x1: | ||
200 | |||
201 | /* support 1.5, 3.0 Gbps */ | ||
202 | phy_cfg.u.speed_support = 3; | ||
203 | phy_cfg.u.tx_spt_phs_lnk_rate = 0x3c; | ||
204 | phy_cfg.u.tx_lgcl_lnk_rate = 0x08; | ||
205 | break; | ||
206 | case 0x2: | ||
207 | default: | ||
208 | /* support 1.5, 3.0, 6.0 Gbps */ | ||
209 | phy_cfg.u.speed_support = 7; | ||
210 | phy_cfg.u.snw_3_support = 1; | ||
211 | phy_cfg.u.tx_lnk_parity = 1; | ||
212 | phy_cfg.u.tx_spt_phs_lnk_rate = 0x3f; | ||
213 | phy_cfg.u.tx_lgcl_lnk_rate = 0x09; | ||
214 | break; | ||
215 | } | ||
216 | mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v); | ||
217 | } | ||
218 | |||
219 | static void __devinit | ||
220 | mvs_94xx_config_reg_from_hba(struct mvs_info *mvi, int phy_id) | ||
221 | { | ||
222 | u32 temp; | ||
223 | temp = (u32)(*(u32 *)&mvi->hba_info_param.phy_tuning[phy_id]); | ||
224 | if (temp == 0xFFFFFFFFL) { | ||
225 | mvi->hba_info_param.phy_tuning[phy_id].trans_emp_amp = 0x6; | ||
226 | mvi->hba_info_param.phy_tuning[phy_id].trans_amp = 0x1A; | ||
227 | mvi->hba_info_param.phy_tuning[phy_id].trans_amp_adj = 0x3; | ||
228 | } | ||
229 | |||
230 | temp = (u8)(*(u8 *)&mvi->hba_info_param.ffe_ctl[phy_id]); | ||
231 | if (temp == 0xFFL) { | ||
232 | switch (mvi->pdev->revision) { | ||
233 | case VANIR_A0_REV: | ||
234 | case VANIR_B0_REV: | ||
235 | mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7; | ||
236 | mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0x7; | ||
237 | break; | ||
238 | case VANIR_C0_REV: | ||
239 | case VANIR_C1_REV: | ||
240 | case VANIR_C2_REV: | ||
241 | default: | ||
242 | mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7; | ||
243 | mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0xC; | ||
244 | break; | ||
245 | } | ||
246 | } | ||
247 | |||
248 | temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]); | ||
249 | if (temp == 0xFFL) | ||
250 | /*set default phy_rate = 6Gbps*/ | ||
251 | mvi->hba_info_param.phy_rate[phy_id] = 0x2; | ||
252 | |||
253 | set_phy_tuning(mvi, phy_id, | ||
254 | mvi->hba_info_param.phy_tuning[phy_id]); | ||
255 | set_phy_ffe_tuning(mvi, phy_id, | ||
256 | mvi->hba_info_param.ffe_ctl[phy_id]); | ||
257 | set_phy_rate(mvi, phy_id, | ||
258 | mvi->hba_info_param.phy_rate[phy_id]); | ||
259 | } | ||
260 | |||
51 | static void __devinit mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id) | 261 | static void __devinit mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id) |
52 | { | 262 | { |
53 | void __iomem *regs = mvi->regs; | 263 | void __iomem *regs = mvi->regs; |
@@ -90,12 +300,25 @@ static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id) | |||
90 | 300 | ||
91 | static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id) | 301 | static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id) |
92 | { | 302 | { |
93 | mvs_write_port_vsr_addr(mvi, phy_id, 0x1B4); | 303 | u32 tmp; |
94 | mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1); | 304 | u8 revision = 0; |
95 | mvs_write_port_vsr_addr(mvi, phy_id, 0x104); | 305 | |
96 | mvs_write_port_vsr_data(mvi, phy_id, 0x00018080); | 306 | revision = mvi->pdev->revision; |
307 | if (revision == VANIR_A0_REV) { | ||
308 | mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA); | ||
309 | mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1); | ||
310 | } | ||
311 | if (revision == VANIR_B0_REV) { | ||
312 | mvs_write_port_vsr_addr(mvi, phy_id, CMD_APP_MEM_CTL); | ||
313 | mvs_write_port_vsr_data(mvi, phy_id, 0x08001006); | ||
314 | mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA); | ||
315 | mvs_write_port_vsr_data(mvi, phy_id, 0x0000705f); | ||
316 | } | ||
317 | |||
97 | mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); | 318 | mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); |
98 | mvs_write_port_vsr_data(mvi, phy_id, 0x00207fff); | 319 | tmp = mvs_read_port_vsr_data(mvi, phy_id); |
320 | tmp |= bit(0); | ||
321 | mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff); | ||
99 | } | 322 | } |
100 | 323 | ||
101 | static int __devinit mvs_94xx_init(struct mvs_info *mvi) | 324 | static int __devinit mvs_94xx_init(struct mvs_info *mvi) |
@@ -103,7 +326,9 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi) | |||
103 | void __iomem *regs = mvi->regs; | 326 | void __iomem *regs = mvi->regs; |
104 | int i; | 327 | int i; |
105 | u32 tmp, cctl; | 328 | u32 tmp, cctl; |
329 | u8 revision; | ||
106 | 330 | ||
331 | revision = mvi->pdev->revision; | ||
107 | mvs_show_pcie_usage(mvi); | 332 | mvs_show_pcie_usage(mvi); |
108 | if (mvi->flags & MVF_FLAG_SOC) { | 333 | if (mvi->flags & MVF_FLAG_SOC) { |
109 | tmp = mr32(MVS_PHY_CTL); | 334 | tmp = mr32(MVS_PHY_CTL); |
@@ -133,6 +358,28 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi) | |||
133 | msleep(100); | 358 | msleep(100); |
134 | } | 359 | } |
135 | 360 | ||
361 | /* disable Multiplexing, enable phy implemented */ | ||
362 | mw32(MVS_PORTS_IMP, 0xFF); | ||
363 | |||
364 | if (revision == VANIR_A0_REV) { | ||
365 | mw32(MVS_PA_VSR_ADDR, CMD_CMWK_OOB_DET); | ||
366 | mw32(MVS_PA_VSR_PORT, 0x00018080); | ||
367 | } | ||
368 | mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE2); | ||
369 | if (revision == VANIR_A0_REV || revision == VANIR_B0_REV) | ||
370 | /* set 6G/3G/1.5G, multiplexing, without SSC */ | ||
371 | mw32(MVS_PA_VSR_PORT, 0x0084d4fe); | ||
372 | else | ||
373 | /* set 6G/3G/1.5G, multiplexing, with and without SSC */ | ||
374 | mw32(MVS_PA_VSR_PORT, 0x0084fffe); | ||
375 | |||
376 | if (revision == VANIR_B0_REV) { | ||
377 | mw32(MVS_PA_VSR_ADDR, CMD_APP_MEM_CTL); | ||
378 | mw32(MVS_PA_VSR_PORT, 0x08001006); | ||
379 | mw32(MVS_PA_VSR_ADDR, CMD_HOST_RD_DATA); | ||
380 | mw32(MVS_PA_VSR_PORT, 0x0000705f); | ||
381 | } | ||
382 | |||
136 | /* reset control */ | 383 | /* reset control */ |
137 | mw32(MVS_PCS, 0); /* MVS_PCS */ | 384 | mw32(MVS_PCS, 0); /* MVS_PCS */ |
138 | mw32(MVS_STP_REG_SET_0, 0); | 385 | mw32(MVS_STP_REG_SET_0, 0); |
@@ -141,15 +388,6 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi) | |||
141 | /* init phys */ | 388 | /* init phys */ |
142 | mvs_phy_hacks(mvi); | 389 | mvs_phy_hacks(mvi); |
143 | 390 | ||
144 | /* disable Multiplexing, enable phy implemented */ | ||
145 | mw32(MVS_PORTS_IMP, 0xFF); | ||
146 | |||
147 | |||
148 | mw32(MVS_PA_VSR_ADDR, 0x00000104); | ||
149 | mw32(MVS_PA_VSR_PORT, 0x00018080); | ||
150 | mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE8); | ||
151 | mw32(MVS_PA_VSR_PORT, 0x0084ffff); | ||
152 | |||
153 | /* set LED blink when IO*/ | 391 | /* set LED blink when IO*/ |
154 | mw32(MVS_PA_VSR_ADDR, 0x00000030); | 392 | mw32(MVS_PA_VSR_ADDR, 0x00000030); |
155 | tmp = mr32(MVS_PA_VSR_PORT); | 393 | tmp = mr32(MVS_PA_VSR_PORT); |
@@ -178,6 +416,7 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi) | |||
178 | (mvi->phy[i].dev_sas_addr)); | 416 | (mvi->phy[i].dev_sas_addr)); |
179 | 417 | ||
180 | mvs_94xx_enable_xmt(mvi, i); | 418 | mvs_94xx_enable_xmt(mvi, i); |
419 | mvs_94xx_config_reg_from_hba(mvi, i); | ||
181 | mvs_94xx_phy_enable(mvi, i); | 420 | mvs_94xx_phy_enable(mvi, i); |
182 | 421 | ||
183 | mvs_94xx_phy_reset(mvi, i, 1); | 422 | mvs_94xx_phy_reset(mvi, i, 1); |
diff --git a/drivers/scsi/mvsas/mv_94xx.h b/drivers/scsi/mvsas/mv_94xx.h index 8835befe2c0e..33af2a1fb729 100644 --- a/drivers/scsi/mvsas/mv_94xx.h +++ b/drivers/scsi/mvsas/mv_94xx.h | |||
@@ -30,6 +30,14 @@ | |||
30 | 30 | ||
31 | #define MAX_LINK_RATE SAS_LINK_RATE_6_0_GBPS | 31 | #define MAX_LINK_RATE SAS_LINK_RATE_6_0_GBPS |
32 | 32 | ||
33 | enum VANIR_REVISION_ID { | ||
34 | VANIR_A0_REV = 0xA0, | ||
35 | VANIR_B0_REV = 0x01, | ||
36 | VANIR_C0_REV = 0x02, | ||
37 | VANIR_C1_REV = 0x03, | ||
38 | VANIR_C2_REV = 0xC2, | ||
39 | }; | ||
40 | |||
33 | enum hw_registers { | 41 | enum hw_registers { |
34 | MVS_GBL_CTL = 0x04, /* global control */ | 42 | MVS_GBL_CTL = 0x04, /* global control */ |
35 | MVS_GBL_INT_STAT = 0x00, /* global irq status */ | 43 | MVS_GBL_INT_STAT = 0x00, /* global irq status */ |
@@ -126,6 +134,10 @@ enum sas_sata_vsp_regs { | |||
126 | VSR_PHY_MODE11 = 0x0B * 4, /* Phy Mode */ | 134 | VSR_PHY_MODE11 = 0x0B * 4, /* Phy Mode */ |
127 | VSR_PHY_VS0 = 0x0C * 4, /* Vednor Specific 0 */ | 135 | VSR_PHY_VS0 = 0x0C * 4, /* Vednor Specific 0 */ |
128 | VSR_PHY_VS1 = 0x0D * 4, /* Vednor Specific 1 */ | 136 | VSR_PHY_VS1 = 0x0D * 4, /* Vednor Specific 1 */ |
137 | |||
138 | VSR_PHY_FFE_CONTROL = 0x10C, | ||
139 | VSR_PHY_DFE_UPDATE_CRTL = 0x110, | ||
140 | VSR_REF_CLOCK_CRTL = 0x1A0, | ||
129 | }; | 141 | }; |
130 | 142 | ||
131 | enum chip_register_bits { | 143 | enum chip_register_bits { |
@@ -169,6 +181,41 @@ enum pci_interrupt_cause { | |||
169 | IRQ_PCIE_ERR = (1 << 31), | 181 | IRQ_PCIE_ERR = (1 << 31), |
170 | }; | 182 | }; |
171 | 183 | ||
184 | union reg_phy_cfg { | ||
185 | u32 v; | ||
186 | struct { | ||
187 | u32 phy_reset:1; | ||
188 | u32 sas_support:1; | ||
189 | u32 sata_support:1; | ||
190 | u32 sata_host_mode:1; | ||
191 | /* | ||
192 | * bit 2: 6Gbps support | ||
193 | * bit 1: 3Gbps support | ||
194 | * bit 0: 1.5Gbps support | ||
195 | */ | ||
196 | u32 speed_support:3; | ||
197 | u32 snw_3_support:1; | ||
198 | u32 tx_lnk_parity:1; | ||
199 | /* | ||
200 | * bit 5: G1 (1.5Gbps) Without SSC | ||
201 | * bit 4: G1 (1.5Gbps) with SSC | ||
202 | * bit 3: G2 (3.0Gbps) Without SSC | ||
203 | * bit 2: G2 (3.0Gbps) with SSC | ||
204 | * bit 1: G3 (6.0Gbps) without SSC | ||
205 | * bit 0: G3 (6.0Gbps) with SSC | ||
206 | */ | ||
207 | u32 tx_spt_phs_lnk_rate:6; | ||
208 | /* 8h: 1.5Gbps 9h: 3Gbps Ah: 6Gbps */ | ||
209 | u32 tx_lgcl_lnk_rate:4; | ||
210 | u32 tx_ssc_type:1; | ||
211 | u32 sata_spin_up_spt:1; | ||
212 | u32 sata_spin_up_en:1; | ||
213 | u32 bypass_oob:1; | ||
214 | u32 disable_phy:1; | ||
215 | u32 rsvd:8; | ||
216 | } u; | ||
217 | }; | ||
218 | |||
172 | #define MAX_SG_ENTRY 255 | 219 | #define MAX_SG_ENTRY 255 |
173 | 220 | ||
174 | struct mvs_prd_imt { | 221 | struct mvs_prd_imt { |
@@ -185,6 +232,17 @@ struct mvs_prd { | |||
185 | struct mvs_prd_imt im_len; | 232 | struct mvs_prd_imt im_len; |
186 | } __attribute__ ((packed)); | 233 | } __attribute__ ((packed)); |
187 | 234 | ||
235 | /* | ||
236 | * these registers are accessed through port vendor | ||
237 | * specific address/data registers | ||
238 | */ | ||
239 | enum sas_sata_phy_regs { | ||
240 | GENERATION_1_SETTING = 0x118, | ||
241 | GENERATION_1_2_SETTING = 0x11C, | ||
242 | GENERATION_2_3_SETTING = 0x120, | ||
243 | GENERATION_3_4_SETTING = 0x124, | ||
244 | }; | ||
245 | |||
188 | #define SPI_CTRL_REG_94XX 0xc800 | 246 | #define SPI_CTRL_REG_94XX 0xc800 |
189 | #define SPI_ADDR_REG_94XX 0xc804 | 247 | #define SPI_ADDR_REG_94XX 0xc804 |
190 | #define SPI_WR_DATA_REG_94XX 0xc808 | 248 | #define SPI_WR_DATA_REG_94XX 0xc808 |
diff --git a/drivers/scsi/mvsas/mv_init.c b/drivers/scsi/mvsas/mv_init.c index 90b636611cde..9f1cccc2a3ed 100644 --- a/drivers/scsi/mvsas/mv_init.c +++ b/drivers/scsi/mvsas/mv_init.c | |||
@@ -569,6 +569,9 @@ static int __devinit mvs_pci_init(struct pci_dev *pdev, | |||
569 | goto err_out_regions; | 569 | goto err_out_regions; |
570 | } | 570 | } |
571 | 571 | ||
572 | memset(&mvi->hba_info_param, 0xFF, | ||
573 | sizeof(struct hba_info_page)); | ||
574 | |||
572 | mvs_init_sas_add(mvi); | 575 | mvs_init_sas_add(mvi); |
573 | 576 | ||
574 | mvi->instance = nhost; | 577 | mvi->instance = nhost; |
diff --git a/drivers/scsi/mvsas/mv_sas.h b/drivers/scsi/mvsas/mv_sas.h index f96100d7aee1..ccd622f7f841 100644 --- a/drivers/scsi/mvsas/mv_sas.h +++ b/drivers/scsi/mvsas/mv_sas.h | |||
@@ -250,6 +250,73 @@ struct mvs_device { | |||
250 | u16 reserved; | 250 | u16 reserved; |
251 | }; | 251 | }; |
252 | 252 | ||
253 | /* Generate PHY tunning parameters */ | ||
254 | struct phy_tuning { | ||
255 | /* 1 bit, transmitter emphasis enable */ | ||
256 | u8 trans_emp_en:1; | ||
257 | /* 4 bits, transmitter emphasis amplitude */ | ||
258 | u8 trans_emp_amp:4; | ||
259 | /* 3 bits, reserved space */ | ||
260 | u8 Reserved_2bit_1:3; | ||
261 | /* 5 bits, transmitter amplitude */ | ||
262 | u8 trans_amp:5; | ||
263 | /* 2 bits, transmitter amplitude adjust */ | ||
264 | u8 trans_amp_adj:2; | ||
265 | /* 1 bit, reserved space */ | ||
266 | u8 resv_2bit_2:1; | ||
267 | /* 2 bytes, reserved space */ | ||
268 | u8 reserved[2]; | ||
269 | }; | ||
270 | |||
271 | struct ffe_control { | ||
272 | /* 4 bits, FFE Capacitor Select (value range 0~F) */ | ||
273 | u8 ffe_cap_sel:4; | ||
274 | /* 3 bits, FFE Resistor Select (value range 0~7) */ | ||
275 | u8 ffe_rss_sel:3; | ||
276 | /* 1 bit reserve*/ | ||
277 | u8 reserved:1; | ||
278 | }; | ||
279 | |||
280 | /* | ||
281 | * HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes. | ||
282 | * The data area is valid only Signature="MRVL". | ||
283 | * If any member fills with 0xFF, the member is invalid. | ||
284 | */ | ||
285 | struct hba_info_page { | ||
286 | /* Dword 0 */ | ||
287 | /* 4 bytes, structure signature,should be "MRVL" at first initial */ | ||
288 | u8 signature[4]; | ||
289 | |||
290 | /* Dword 1-13 */ | ||
291 | u32 reserved1[13]; | ||
292 | |||
293 | /* Dword 14-29 */ | ||
294 | /* 64 bytes, SAS address for each port */ | ||
295 | u64 sas_addr[8]; | ||
296 | |||
297 | /* Dword 30-31 */ | ||
298 | /* 8 bytes for vanir 8 port PHY FFE seeting | ||
299 | * BIT 0~3 : FFE Capacitor select(value range 0~F) | ||
300 | * BIT 4~6 : FFE Resistor select(value range 0~7) | ||
301 | * BIT 7: reserve. | ||
302 | */ | ||
303 | |||
304 | struct ffe_control ffe_ctl[8]; | ||
305 | /* Dword 32 -43 */ | ||
306 | u32 reserved2[12]; | ||
307 | |||
308 | /* Dword 44-45 */ | ||
309 | /* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */ | ||
310 | u8 phy_rate[8]; | ||
311 | |||
312 | /* Dword 46-53 */ | ||
313 | /* 32 bytes, PHY tuning parameters for each PHY*/ | ||
314 | struct phy_tuning phy_tuning[8]; | ||
315 | |||
316 | /* Dword 54-63 */ | ||
317 | u32 reserved3[10]; | ||
318 | }; /* total 256 bytes */ | ||
319 | |||
253 | struct mvs_slot_info { | 320 | struct mvs_slot_info { |
254 | struct list_head entry; | 321 | struct list_head entry; |
255 | union { | 322 | union { |
@@ -338,6 +405,7 @@ struct mvs_info { | |||
338 | u32 flashsectSize; | 405 | u32 flashsectSize; |
339 | 406 | ||
340 | void *addon; | 407 | void *addon; |
408 | struct hba_info_page hba_info_param; | ||
341 | struct mvs_device devices[MVS_MAX_DEVICES]; | 409 | struct mvs_device devices[MVS_MAX_DEVICES]; |
342 | #ifndef DISABLE_HOTPLUG_DMA_FIX | 410 | #ifndef DISABLE_HOTPLUG_DMA_FIX |
343 | void *bulk_buffer; | 411 | void *bulk_buffer; |