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1/*
2 * Copyright (c) 2000-2012 LSI Corporation.
3 *
4 *
5 * Name: mpi2_ioc.h
6 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
7 * Creation Date: October 11, 2006
8 *
9 * mpi2_ioc.h Version: 02.00.21
10 *
11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
12 * prefix are for use only on MPI v2.5 products, and must not be used
13 * with MPI v2.0 products. Unless otherwise noted, names beginning with
14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
15 *
16 * Version History
17 * ---------------
18 *
19 * Date Version Description
20 * -------- -------- ------------------------------------------------------
21 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
22 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
23 * MaxTargets.
24 * Added TotalImageSize field to FWDownload Request.
25 * Added reserved words to FWUpload Request.
26 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
27 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
28 * request and replaced it with
29 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
30 * Replaced the MinReplyQueueDepth field of the IOCFacts
31 * reply with MaxReplyDescriptorPostQueueDepth.
32 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
33 * depth for the Reply Descriptor Post Queue.
34 * Added SASAddress field to Initiator Device Table
35 * Overflow Event data.
36 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
37 * for SAS Initiator Device Status Change Event data.
38 * Modified Reason Code defines for SAS Topology Change
39 * List Event data, including adding a bit for PHY Vacant
40 * status, and adding a mask for the Reason Code.
41 * Added define for
42 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
43 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
44 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
45 * the IOCFacts Reply.
46 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
47 * Moved MPI2_VERSION_UNION to mpi2.h.
48 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
49 * instead of enables, and added SASBroadcastPrimitiveMasks
50 * field.
51 * Added Log Entry Added Event and related structure.
52 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
53 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
54 * Added MaxVolumes and MaxPersistentEntries fields to
55 * IOCFacts reply.
56 * Added ProtocalFlags and IOCCapabilities fields to
57 * MPI2_FW_IMAGE_HEADER.
58 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
59 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
60 * a U16 (from a U32).
61 * Removed extra 's' from EventMasks name.
62 * 06-27-08 02.00.08 Fixed an offset in a comment.
63 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
64 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
65 * renamed MinReplyFrameSize to ReplyFrameSize.
66 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
67 * Added two new RAIDOperation values for Integrated RAID
68 * Operations Status Event data.
69 * Added four new IR Configuration Change List Event data
70 * ReasonCode values.
71 * Added two new ReasonCode defines for SAS Device Status
72 * Change Event data.
73 * Added three new DiscoveryStatus bits for the SAS
74 * Discovery event data.
75 * Added Multiplexing Status Change bit to the PhyStatus
76 * field of the SAS Topology Change List event data.
77 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
78 * BootFlags are now product-specific.
79 * Added defines for the indivdual signature bytes
80 * for MPI2_INIT_IMAGE_FOOTER.
81 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
82 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
83 * define.
84 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
85 * define.
86 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
87 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
88 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
89 * Added two new reason codes for SAS Device Status Change
90 * Event.
91 * Added new event: SAS PHY Counter.
92 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
93 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
94 * Added new product id family for 2208.
95 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
96 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
97 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
98 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
99 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
100 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
101 * Added Host Based Discovery Phy Event data.
102 * Added defines for ProductID Product field
103 * (MPI2_FW_HEADER_PID_).
104 * Modified values for SAS ProductID Family
105 * (MPI2_FW_HEADER_PID_FAMILY_).
106 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
107 * Added PowerManagementControl Request structures and
108 * defines.
109 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
110 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
111 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
112 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added
113 * SASNotifyPrimitiveMasks field to
114 * MPI2_EVENT_NOTIFICATION_REQUEST.
115 * Added Temperature Threshold Event.
116 * Added Host Message Event.
117 * Added Send Host Message request and reply.
118 * 05-25-11 02.00.18 For Extended Image Header, added
119 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
120 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
121 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
122 * 08-24-11 02.00.19 Added PhysicalPort field to
123 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
124 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
125 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5.
126 * 03-29-12 02.00.21 Added a product specific range to event values.
127 * --------------------------------------------------------------------------
128 */
129
130#ifndef MPI2_IOC_H
131#define MPI2_IOC_H
132
133/*****************************************************************************
134*
135* IOC Messages
136*
137*****************************************************************************/
138
139/****************************************************************************
140* IOCInit message
141****************************************************************************/
142
143/*IOCInit Request message */
144typedef struct _MPI2_IOC_INIT_REQUEST {
145 U8 WhoInit; /*0x00 */
146 U8 Reserved1; /*0x01 */
147 U8 ChainOffset; /*0x02 */
148 U8 Function; /*0x03 */
149 U16 Reserved2; /*0x04 */
150 U8 Reserved3; /*0x06 */
151 U8 MsgFlags; /*0x07 */
152 U8 VP_ID; /*0x08 */
153 U8 VF_ID; /*0x09 */
154 U16 Reserved4; /*0x0A */
155 U16 MsgVersion; /*0x0C */
156 U16 HeaderVersion; /*0x0E */
157 U32 Reserved5; /*0x10 */
158 U16 Reserved6; /*0x14 */
159 U8 Reserved7; /*0x16 */
160 U8 HostMSIxVectors; /*0x17 */
161 U16 Reserved8; /*0x18 */
162 U16 SystemRequestFrameSize; /*0x1A */
163 U16 ReplyDescriptorPostQueueDepth; /*0x1C */
164 U16 ReplyFreeQueueDepth; /*0x1E */
165 U32 SenseBufferAddressHigh; /*0x20 */
166 U32 SystemReplyAddressHigh; /*0x24 */
167 U64 SystemRequestFrameBaseAddress; /*0x28 */
168 U64 ReplyDescriptorPostQueueAddress; /*0x30 */
169 U64 ReplyFreeQueueAddress; /*0x38 */
170 U64 TimeStamp; /*0x40 */
171} MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST,
172 Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t;
173
174/*WhoInit values */
175#define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
176#define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
177#define MPI2_WHOINIT_ROM_BIOS (0x02)
178#define MPI2_WHOINIT_PCI_PEER (0x03)
179#define MPI2_WHOINIT_HOST_DRIVER (0x04)
180#define MPI2_WHOINIT_MANUFACTURER (0x05)
181
182/*MsgVersion */
183#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
184#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
185#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
186#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
187
188/*HeaderVersion */
189#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
190#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
191#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
192#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
193
194/*minimum depth for the Reply Descriptor Post Queue */
195#define MPI2_RDPQ_DEPTH_MIN (16)
196
197/*IOCInit Reply message */
198typedef struct _MPI2_IOC_INIT_REPLY {
199 U8 WhoInit; /*0x00 */
200 U8 Reserved1; /*0x01 */
201 U8 MsgLength; /*0x02 */
202 U8 Function; /*0x03 */
203 U16 Reserved2; /*0x04 */
204 U8 Reserved3; /*0x06 */
205 U8 MsgFlags; /*0x07 */
206 U8 VP_ID; /*0x08 */
207 U8 VF_ID; /*0x09 */
208 U16 Reserved4; /*0x0A */
209 U16 Reserved5; /*0x0C */
210 U16 IOCStatus; /*0x0E */
211 U32 IOCLogInfo; /*0x10 */
212} MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY,
213 Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t;
214
215/****************************************************************************
216* IOCFacts message
217****************************************************************************/
218
219/*IOCFacts Request message */
220typedef struct _MPI2_IOC_FACTS_REQUEST {
221 U16 Reserved1; /*0x00 */
222 U8 ChainOffset; /*0x02 */
223 U8 Function; /*0x03 */
224 U16 Reserved2; /*0x04 */
225 U8 Reserved3; /*0x06 */
226 U8 MsgFlags; /*0x07 */
227 U8 VP_ID; /*0x08 */
228 U8 VF_ID; /*0x09 */
229 U16 Reserved4; /*0x0A */
230} MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST,
231 Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t;
232
233/*IOCFacts Reply message */
234typedef struct _MPI2_IOC_FACTS_REPLY {
235 U16 MsgVersion; /*0x00 */
236 U8 MsgLength; /*0x02 */
237 U8 Function; /*0x03 */
238 U16 HeaderVersion; /*0x04 */
239 U8 IOCNumber; /*0x06 */
240 U8 MsgFlags; /*0x07 */
241 U8 VP_ID; /*0x08 */
242 U8 VF_ID; /*0x09 */
243 U16 Reserved1; /*0x0A */
244 U16 IOCExceptions; /*0x0C */
245 U16 IOCStatus; /*0x0E */
246 U32 IOCLogInfo; /*0x10 */
247 U8 MaxChainDepth; /*0x14 */
248 U8 WhoInit; /*0x15 */
249 U8 NumberOfPorts; /*0x16 */
250 U8 MaxMSIxVectors; /*0x17 */
251 U16 RequestCredit; /*0x18 */
252 U16 ProductID; /*0x1A */
253 U32 IOCCapabilities; /*0x1C */
254 MPI2_VERSION_UNION FWVersion; /*0x20 */
255 U16 IOCRequestFrameSize; /*0x24 */
256 U16 IOCMaxChainSegmentSize; /*0x26 */
257 U16 MaxInitiators; /*0x28 */
258 U16 MaxTargets; /*0x2A */
259 U16 MaxSasExpanders; /*0x2C */
260 U16 MaxEnclosures; /*0x2E */
261 U16 ProtocolFlags; /*0x30 */
262 U16 HighPriorityCredit; /*0x32 */
263 U16 MaxReplyDescriptorPostQueueDepth; /*0x34 */
264 U8 ReplyFrameSize; /*0x36 */
265 U8 MaxVolumes; /*0x37 */
266 U16 MaxDevHandle; /*0x38 */
267 U16 MaxPersistentEntries; /*0x3A */
268 U16 MinDevHandle; /*0x3C */
269 U16 Reserved4; /*0x3E */
270} MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY,
271 Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t;
272
273/*MsgVersion */
274#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
275#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
276#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
277#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
278
279/*HeaderVersion */
280#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
281#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
282#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
283#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
284
285/*IOCExceptions */
286#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
287
288#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
289#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
290#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
291#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
292#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
293
294#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
295#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
296#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
297#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
298#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
299
300/*defines for WhoInit field are after the IOCInit Request */
301
302/*ProductID field uses MPI2_FW_HEADER_PID_ */
303
304/*IOCCapabilities */
305#define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000)
306#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
307#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
308#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
309#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
310#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
311#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
312#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
313#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
314#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
315#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
316#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
317#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
318#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
319
320/*ProtocolFlags */
321#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
322#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
323
324/****************************************************************************
325* PortFacts message
326****************************************************************************/
327
328/*PortFacts Request message */
329typedef struct _MPI2_PORT_FACTS_REQUEST {
330 U16 Reserved1; /*0x00 */
331 U8 ChainOffset; /*0x02 */
332 U8 Function; /*0x03 */
333 U16 Reserved2; /*0x04 */
334 U8 PortNumber; /*0x06 */
335 U8 MsgFlags; /*0x07 */
336 U8 VP_ID; /*0x08 */
337 U8 VF_ID; /*0x09 */
338 U16 Reserved3; /*0x0A */
339} MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST,
340 Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t;
341
342/*PortFacts Reply message */
343typedef struct _MPI2_PORT_FACTS_REPLY {
344 U16 Reserved1; /*0x00 */
345 U8 MsgLength; /*0x02 */
346 U8 Function; /*0x03 */
347 U16 Reserved2; /*0x04 */
348 U8 PortNumber; /*0x06 */
349 U8 MsgFlags; /*0x07 */
350 U8 VP_ID; /*0x08 */
351 U8 VF_ID; /*0x09 */
352 U16 Reserved3; /*0x0A */
353 U16 Reserved4; /*0x0C */
354 U16 IOCStatus; /*0x0E */
355 U32 IOCLogInfo; /*0x10 */
356 U8 Reserved5; /*0x14 */
357 U8 PortType; /*0x15 */
358 U16 Reserved6; /*0x16 */
359 U16 MaxPostedCmdBuffers; /*0x18 */
360 U16 Reserved7; /*0x1A */
361} MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY,
362 Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t;
363
364/*PortType values */
365#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
366#define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
367#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
368#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
369#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
370
371/****************************************************************************
372* PortEnable message
373****************************************************************************/
374
375/*PortEnable Request message */
376typedef struct _MPI2_PORT_ENABLE_REQUEST {
377 U16 Reserved1; /*0x00 */
378 U8 ChainOffset; /*0x02 */
379 U8 Function; /*0x03 */
380 U8 Reserved2; /*0x04 */
381 U8 PortFlags; /*0x05 */
382 U8 Reserved3; /*0x06 */
383 U8 MsgFlags; /*0x07 */
384 U8 VP_ID; /*0x08 */
385 U8 VF_ID; /*0x09 */
386 U16 Reserved4; /*0x0A */
387} MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST,
388 Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t;
389
390/*PortEnable Reply message */
391typedef struct _MPI2_PORT_ENABLE_REPLY {
392 U16 Reserved1; /*0x00 */
393 U8 MsgLength; /*0x02 */
394 U8 Function; /*0x03 */
395 U8 Reserved2; /*0x04 */
396 U8 PortFlags; /*0x05 */
397 U8 Reserved3; /*0x06 */
398 U8 MsgFlags; /*0x07 */
399 U8 VP_ID; /*0x08 */
400 U8 VF_ID; /*0x09 */
401 U16 Reserved4; /*0x0A */
402 U16 Reserved5; /*0x0C */
403 U16 IOCStatus; /*0x0E */
404 U32 IOCLogInfo; /*0x10 */
405} MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY,
406 Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t;
407
408/****************************************************************************
409* EventNotification message
410****************************************************************************/
411
412/*EventNotification Request message */
413#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
414
415typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST {
416 U16 Reserved1; /*0x00 */
417 U8 ChainOffset; /*0x02 */
418 U8 Function; /*0x03 */
419 U16 Reserved2; /*0x04 */
420 U8 Reserved3; /*0x06 */
421 U8 MsgFlags; /*0x07 */
422 U8 VP_ID; /*0x08 */
423 U8 VF_ID; /*0x09 */
424 U16 Reserved4; /*0x0A */
425 U32 Reserved5; /*0x0C */
426 U32 Reserved6; /*0x10 */
427 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; /*0x14 */
428 U16 SASBroadcastPrimitiveMasks; /*0x24 */
429 U16 SASNotifyPrimitiveMasks; /*0x26 */
430 U32 Reserved8; /*0x28 */
431} MPI2_EVENT_NOTIFICATION_REQUEST,
432 *PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
433 Mpi2EventNotificationRequest_t,
434 *pMpi2EventNotificationRequest_t;
435
436/*EventNotification Reply message */
437typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {
438 U16 EventDataLength; /*0x00 */
439 U8 MsgLength; /*0x02 */
440 U8 Function; /*0x03 */
441 U16 Reserved1; /*0x04 */
442 U8 AckRequired; /*0x06 */
443 U8 MsgFlags; /*0x07 */
444 U8 VP_ID; /*0x08 */
445 U8 VF_ID; /*0x09 */
446 U16 Reserved2; /*0x0A */
447 U16 Reserved3; /*0x0C */
448 U16 IOCStatus; /*0x0E */
449 U32 IOCLogInfo; /*0x10 */
450 U16 Event; /*0x14 */
451 U16 Reserved4; /*0x16 */
452 U32 EventContext; /*0x18 */
453 U32 EventData[1]; /*0x1C */
454} MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY,
455 Mpi2EventNotificationReply_t,
456 *pMpi2EventNotificationReply_t;
457
458/*AckRequired */
459#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
460#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
461
462/*Event */
463#define MPI2_EVENT_LOG_DATA (0x0001)
464#define MPI2_EVENT_STATE_CHANGE (0x0002)
465#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
466#define MPI2_EVENT_EVENT_CHANGE (0x000A)
467#define MPI2_EVENT_TASK_SET_FULL (0x000E) /*obsolete */
468#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
469#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
470#define MPI2_EVENT_SAS_DISCOVERY (0x0016)
471#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
472#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
473#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
474#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
475#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
476#define MPI2_EVENT_IR_VOLUME (0x001E)
477#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
478#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
479#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
480#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
481#define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
482#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
483#define MPI2_EVENT_SAS_QUIESCE (0x0025)
484#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
485#define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
486#define MPI2_EVENT_HOST_MESSAGE (0x0028)
487#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029)
488#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
489#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
490
491/*Log Entry Added Event data */
492
493/*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
494#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
495
496typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED {
497 U64 TimeStamp; /*0x00 */
498 U32 Reserved1; /*0x08 */
499 U16 LogSequence; /*0x0C */
500 U16 LogEntryQualifier; /*0x0E */
501 U8 VP_ID; /*0x10 */
502 U8 VF_ID; /*0x11 */
503 U16 Reserved2; /*0x12 */
504 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH]; /*0x14 */
505} MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
506 *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
507 Mpi2EventDataLogEntryAdded_t,
508 *pMpi2EventDataLogEntryAdded_t;
509
510/*GPIO Interrupt Event data */
511
512typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
513 U8 GPIONum; /*0x00 */
514 U8 Reserved1; /*0x01 */
515 U16 Reserved2; /*0x02 */
516} MPI2_EVENT_DATA_GPIO_INTERRUPT,
517 *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
518 Mpi2EventDataGpioInterrupt_t,
519 *pMpi2EventDataGpioInterrupt_t;
520
521/*Temperature Threshold Event data */
522
523typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
524 U16 Status; /*0x00 */
525 U8 SensorNum; /*0x02 */
526 U8 Reserved1; /*0x03 */
527 U16 CurrentTemperature; /*0x04 */
528 U16 Reserved2; /*0x06 */
529 U32 Reserved3; /*0x08 */
530 U32 Reserved4; /*0x0C */
531} MPI2_EVENT_DATA_TEMPERATURE,
532 *PTR_MPI2_EVENT_DATA_TEMPERATURE,
533 Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t;
534
535/*Temperature Threshold Event data Status bits */
536#define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008)
537#define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004)
538#define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002)
539#define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001)
540
541/*Host Message Event data */
542
543typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
544 U8 SourceVF_ID; /*0x00 */
545 U8 Reserved1; /*0x01 */
546 U16 Reserved2; /*0x02 */
547 U32 Reserved3; /*0x04 */
548 U32 HostData[1]; /*0x08 */
549} MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
550 Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t;
551
552/*Power Performance Change Event */
553
554typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE {
555 U8 CurrentPowerMode; /*0x00 */
556 U8 PreviousPowerMode; /*0x01 */
557 U16 Reserved1; /*0x02 */
558} MPI2_EVENT_DATA_POWER_PERF_CHANGE,
559 *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
560 Mpi2EventDataPowerPerfChange_t,
561 *pMpi2EventDataPowerPerfChange_t;
562
563/*defines for CurrentPowerMode and PreviousPowerMode fields */
564#define MPI2_EVENT_PM_INIT_MASK (0xC0)
565#define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00)
566#define MPI2_EVENT_PM_INIT_HOST (0x40)
567#define MPI2_EVENT_PM_INIT_IO_UNIT (0x80)
568#define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0)
569
570#define MPI2_EVENT_PM_MODE_MASK (0x07)
571#define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00)
572#define MPI2_EVENT_PM_MODE_UNKNOWN (0x01)
573#define MPI2_EVENT_PM_MODE_FULL_POWER (0x04)
574#define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05)
575#define MPI2_EVENT_PM_MODE_STANDBY (0x06)
576
577/*Hard Reset Received Event data */
578
579typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED {
580 U8 Reserved1; /*0x00 */
581 U8 Port; /*0x01 */
582 U16 Reserved2; /*0x02 */
583} MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
584 *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
585 Mpi2EventDataHardResetReceived_t,
586 *pMpi2EventDataHardResetReceived_t;
587
588/*Task Set Full Event data */
589/* this event is obsolete */
590
591typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL {
592 U16 DevHandle; /*0x00 */
593 U16 CurrentDepth; /*0x02 */
594} MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
595 Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t;
596
597/*SAS Device Status Change Event data */
598
599typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE {
600 U16 TaskTag; /*0x00 */
601 U8 ReasonCode; /*0x02 */
602 U8 PhysicalPort; /*0x03 */
603 U8 ASC; /*0x04 */
604 U8 ASCQ; /*0x05 */
605 U16 DevHandle; /*0x06 */
606 U32 Reserved2; /*0x08 */
607 U64 SASAddress; /*0x0C */
608 U8 LUN[8]; /*0x14 */
609} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
610 *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
611 Mpi2EventDataSasDeviceStatusChange_t,
612 *pMpi2EventDataSasDeviceStatusChange_t;
613
614/*SAS Device Status Change Event data ReasonCode values */
615#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
616#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
617#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
618#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
619#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
620#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
621#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
622#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
623#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
624#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
625#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
626#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
627#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
628
629/*Integrated RAID Operation Status Event data */
630
631typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS {
632 U16 VolDevHandle; /*0x00 */
633 U16 Reserved1; /*0x02 */
634 U8 RAIDOperation; /*0x04 */
635 U8 PercentComplete; /*0x05 */
636 U16 Reserved2; /*0x06 */
637 U32 Resereved3; /*0x08 */
638} MPI2_EVENT_DATA_IR_OPERATION_STATUS,
639 *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
640 Mpi2EventDataIrOperationStatus_t,
641 *pMpi2EventDataIrOperationStatus_t;
642
643/*Integrated RAID Operation Status Event data RAIDOperation values */
644#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
645#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
646#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
647#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
648#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
649
650/*Integrated RAID Volume Event data */
651
652typedef struct _MPI2_EVENT_DATA_IR_VOLUME {
653 U16 VolDevHandle; /*0x00 */
654 U8 ReasonCode; /*0x02 */
655 U8 Reserved1; /*0x03 */
656 U32 NewValue; /*0x04 */
657 U32 PreviousValue; /*0x08 */
658} MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME,
659 Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t;
660
661/*Integrated RAID Volume Event data ReasonCode values */
662#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
663#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
664#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
665
666/*Integrated RAID Physical Disk Event data */
667
668typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK {
669 U16 Reserved1; /*0x00 */
670 U8 ReasonCode; /*0x02 */
671 U8 PhysDiskNum; /*0x03 */
672 U16 PhysDiskDevHandle; /*0x04 */
673 U16 Reserved2; /*0x06 */
674 U16 Slot; /*0x08 */
675 U16 EnclosureHandle; /*0x0A */
676 U32 NewValue; /*0x0C */
677 U32 PreviousValue; /*0x10 */
678} MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
679 *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
680 Mpi2EventDataIrPhysicalDisk_t,
681 *pMpi2EventDataIrPhysicalDisk_t;
682
683/*Integrated RAID Physical Disk Event data ReasonCode values */
684#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
685#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
686#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
687
688/*Integrated RAID Configuration Change List Event data */
689
690/*
691 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
692 *one and check NumElements at runtime.
693 */
694#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
695#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
696#endif
697
698typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT {
699 U16 ElementFlags; /*0x00 */
700 U16 VolDevHandle; /*0x02 */
701 U8 ReasonCode; /*0x04 */
702 U8 PhysDiskNum; /*0x05 */
703 U16 PhysDiskDevHandle; /*0x06 */
704} MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
705 Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t;
706
707/*IR Configuration Change List Event data ElementFlags values */
708#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
709#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
710#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
711#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
712
713/*IR Configuration Change List Event data ReasonCode values */
714#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
715#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
716#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
717#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
718#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
719#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
720#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
721#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
722#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
723
724typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST {
725 U8 NumElements; /*0x00 */
726 U8 Reserved1; /*0x01 */
727 U8 Reserved2; /*0x02 */
728 U8 ConfigNum; /*0x03 */
729 U32 Flags; /*0x04 */
730 MPI2_EVENT_IR_CONFIG_ELEMENT
731 ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];/*0x08 */
732} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
733 *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
734 Mpi2EventDataIrConfigChangeList_t,
735 *pMpi2EventDataIrConfigChangeList_t;
736
737/*IR Configuration Change List Event data Flags values */
738#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
739
740/*SAS Discovery Event data */
741
742typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY {
743 U8 Flags; /*0x00 */
744 U8 ReasonCode; /*0x01 */
745 U8 PhysicalPort; /*0x02 */
746 U8 Reserved1; /*0x03 */
747 U32 DiscoveryStatus; /*0x04 */
748} MPI2_EVENT_DATA_SAS_DISCOVERY,
749 *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
750 Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t;
751
752/*SAS Discovery Event data Flags values */
753#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
754#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
755
756/*SAS Discovery Event data ReasonCode values */
757#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
758#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
759
760/*SAS Discovery Event data DiscoveryStatus values */
761#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
762#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
763#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
764#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
765#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
766#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
767#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
768#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
769#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
770#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
771#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
772#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
773#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
774#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
775#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
776#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
777#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
778#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
779#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
780#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
781
782/*SAS Broadcast Primitive Event data */
783
784typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE {
785 U8 PhyNum; /*0x00 */
786 U8 Port; /*0x01 */
787 U8 PortWidth; /*0x02 */
788 U8 Primitive; /*0x03 */
789} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
790 *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
791 Mpi2EventDataSasBroadcastPrimitive_t,
792 *pMpi2EventDataSasBroadcastPrimitive_t;
793
794/*defines for the Primitive field */
795#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
796#define MPI2_EVENT_PRIMITIVE_SES (0x02)
797#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
798#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
799#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
800#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
801#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
802#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
803
804/*SAS Notify Primitive Event data */
805
806typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
807 U8 PhyNum; /*0x00 */
808 U8 Port; /*0x01 */
809 U8 Reserved1; /*0x02 */
810 U8 Primitive; /*0x03 */
811} MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
812 *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
813 Mpi2EventDataSasNotifyPrimitive_t,
814 *pMpi2EventDataSasNotifyPrimitive_t;
815
816/*defines for the Primitive field */
817#define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01)
818#define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02)
819#define MPI2_EVENT_NOTIFY_RESERVED1 (0x03)
820#define MPI2_EVENT_NOTIFY_RESERVED2 (0x04)
821
822/*SAS Initiator Device Status Change Event data */
823
824typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE {
825 U8 ReasonCode; /*0x00 */
826 U8 PhysicalPort; /*0x01 */
827 U16 DevHandle; /*0x02 */
828 U64 SASAddress; /*0x04 */
829} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
830 *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
831 Mpi2EventDataSasInitDevStatusChange_t,
832 *pMpi2EventDataSasInitDevStatusChange_t;
833
834/*SAS Initiator Device Status Change event ReasonCode values */
835#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
836#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
837
838/*SAS Initiator Device Table Overflow Event data */
839
840typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW {
841 U16 MaxInit; /*0x00 */
842 U16 CurrentInit; /*0x02 */
843 U64 SASAddress; /*0x04 */
844} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
845 *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
846 Mpi2EventDataSasInitTableOverflow_t,
847 *pMpi2EventDataSasInitTableOverflow_t;
848
849/*SAS Topology Change List Event data */
850
851/*
852 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
853 *one and check NumEntries at runtime.
854 */
855#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
856#define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
857#endif
858
859typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY {
860 U16 AttachedDevHandle; /*0x00 */
861 U8 LinkRate; /*0x02 */
862 U8 PhyStatus; /*0x03 */
863} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
864 Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t;
865
866typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST {
867 U16 EnclosureHandle; /*0x00 */
868 U16 ExpanderDevHandle; /*0x02 */
869 U8 NumPhys; /*0x04 */
870 U8 Reserved1; /*0x05 */
871 U16 Reserved2; /*0x06 */
872 U8 NumEntries; /*0x08 */
873 U8 StartPhyNum; /*0x09 */
874 U8 ExpStatus; /*0x0A */
875 U8 PhysicalPort; /*0x0B */
876 MPI2_EVENT_SAS_TOPO_PHY_ENTRY
877 PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /*0x0C */
878} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
879 *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
880 Mpi2EventDataSasTopologyChangeList_t,
881 *pMpi2EventDataSasTopologyChangeList_t;
882
883/*values for the ExpStatus field */
884#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
885#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
886#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
887#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
888#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
889
890/*defines for the LinkRate field */
891#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
892#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
893#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
894#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
895
896#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
897#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
898#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
899#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
900#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
901#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
902#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
903#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
904#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
905#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
906#define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B)
907
908/*values for the PhyStatus field */
909#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
910#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
911/*values for the PhyStatus ReasonCode sub-field */
912#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
913#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
914#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
915#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
916#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
917#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
918
919/*SAS Enclosure Device Status Change Event data */
920
921typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE {
922 U16 EnclosureHandle; /*0x00 */
923 U8 ReasonCode; /*0x02 */
924 U8 PhysicalPort; /*0x03 */
925 U64 EnclosureLogicalID; /*0x04 */
926 U16 NumSlots; /*0x0C */
927 U16 StartSlot; /*0x0E */
928 U32 PhyBits; /*0x10 */
929} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
930 *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
931 Mpi2EventDataSasEnclDevStatusChange_t,
932 *pMpi2EventDataSasEnclDevStatusChange_t;
933
934/*SAS Enclosure Device Status Change event ReasonCode values */
935#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
936#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
937
938/*SAS PHY Counter Event data */
939
940typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
941 U64 TimeStamp; /*0x00 */
942 U32 Reserved1; /*0x08 */
943 U8 PhyEventCode; /*0x0C */
944 U8 PhyNum; /*0x0D */
945 U16 Reserved2; /*0x0E */
946 U32 PhyEventInfo; /*0x10 */
947 U8 CounterType; /*0x14 */
948 U8 ThresholdWindow; /*0x15 */
949 U8 TimeUnits; /*0x16 */
950 U8 Reserved3; /*0x17 */
951 U32 EventThreshold; /*0x18 */
952 U16 ThresholdFlags; /*0x1C */
953 U16 Reserved4; /*0x1E */
954} MPI2_EVENT_DATA_SAS_PHY_COUNTER,
955 *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
956 Mpi2EventDataSasPhyCounter_t,
957 *pMpi2EventDataSasPhyCounter_t;
958
959/*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h
960 *for the PhyEventCode field */
961
962/*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h
963 *for the CounterType field */
964
965/*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h
966 *for the TimeUnits field */
967
968/*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h
969 *for the ThresholdFlags field */
970
971/*SAS Quiesce Event data */
972
973typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
974 U8 ReasonCode; /*0x00 */
975 U8 Reserved1; /*0x01 */
976 U16 Reserved2; /*0x02 */
977 U32 Reserved3; /*0x04 */
978} MPI2_EVENT_DATA_SAS_QUIESCE,
979 *PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
980 Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t;
981
982/*SAS Quiesce Event data ReasonCode values */
983#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
984#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
985
986/*Host Based Discovery Phy Event data */
987
988typedef struct _MPI2_EVENT_HBD_PHY_SAS {
989 U8 Flags; /*0x00 */
990 U8 NegotiatedLinkRate; /*0x01 */
991 U8 PhyNum; /*0x02 */
992 U8 PhysicalPort; /*0x03 */
993 U32 Reserved1; /*0x04 */
994 U8 InitialFrame[28]; /*0x08 */
995} MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS,
996 Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t;
997
998/*values for the Flags field */
999#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
1000#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
1001
1002/*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h
1003 *for the NegotiatedLinkRate field */
1004
1005typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1006 MPI2_EVENT_HBD_PHY_SAS Sas;
1007} MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1008 Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t;
1009
1010typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1011 U8 DescriptorType; /*0x00 */
1012 U8 Reserved1; /*0x01 */
1013 U16 Reserved2; /*0x02 */
1014 U32 Reserved3; /*0x04 */
1015 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /*0x08 */
1016} MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY,
1017 Mpi2EventDataHbdPhy_t,
1018 *pMpi2EventDataMpi2EventDataHbdPhy_t;
1019
1020/*values for the DescriptorType field */
1021#define MPI2_EVENT_HBD_DT_SAS (0x01)
1022
1023/****************************************************************************
1024* EventAck message
1025****************************************************************************/
1026
1027/*EventAck Request message */
1028typedef struct _MPI2_EVENT_ACK_REQUEST {
1029 U16 Reserved1; /*0x00 */
1030 U8 ChainOffset; /*0x02 */
1031 U8 Function; /*0x03 */
1032 U16 Reserved2; /*0x04 */
1033 U8 Reserved3; /*0x06 */
1034 U8 MsgFlags; /*0x07 */
1035 U8 VP_ID; /*0x08 */
1036 U8 VF_ID; /*0x09 */
1037 U16 Reserved4; /*0x0A */
1038 U16 Event; /*0x0C */
1039 U16 Reserved5; /*0x0E */
1040 U32 EventContext; /*0x10 */
1041} MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST,
1042 Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t;
1043
1044/*EventAck Reply message */
1045typedef struct _MPI2_EVENT_ACK_REPLY {
1046 U16 Reserved1; /*0x00 */
1047 U8 MsgLength; /*0x02 */
1048 U8 Function; /*0x03 */
1049 U16 Reserved2; /*0x04 */
1050 U8 Reserved3; /*0x06 */
1051 U8 MsgFlags; /*0x07 */
1052 U8 VP_ID; /*0x08 */
1053 U8 VF_ID; /*0x09 */
1054 U16 Reserved4; /*0x0A */
1055 U16 Reserved5; /*0x0C */
1056 U16 IOCStatus; /*0x0E */
1057 U32 IOCLogInfo; /*0x10 */
1058} MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY,
1059 Mpi2EventAckReply_t, *pMpi2EventAckReply_t;
1060
1061/****************************************************************************
1062* SendHostMessage message
1063****************************************************************************/
1064
1065/*SendHostMessage Request message */
1066typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1067 U16 HostDataLength; /*0x00 */
1068 U8 ChainOffset; /*0x02 */
1069 U8 Function; /*0x03 */
1070 U16 Reserved1; /*0x04 */
1071 U8 Reserved2; /*0x06 */
1072 U8 MsgFlags; /*0x07 */
1073 U8 VP_ID; /*0x08 */
1074 U8 VF_ID; /*0x09 */
1075 U16 Reserved3; /*0x0A */
1076 U8 Reserved4; /*0x0C */
1077 U8 DestVF_ID; /*0x0D */
1078 U16 Reserved5; /*0x0E */
1079 U32 Reserved6; /*0x10 */
1080 U32 Reserved7; /*0x14 */
1081 U32 Reserved8; /*0x18 */
1082 U32 Reserved9; /*0x1C */
1083 U32 Reserved10; /*0x20 */
1084 U32 HostData[1]; /*0x24 */
1085} MPI2_SEND_HOST_MESSAGE_REQUEST,
1086 *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1087 Mpi2SendHostMessageRequest_t,
1088 *pMpi2SendHostMessageRequest_t;
1089
1090/*SendHostMessage Reply message */
1091typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1092 U16 HostDataLength; /*0x00 */
1093 U8 MsgLength; /*0x02 */
1094 U8 Function; /*0x03 */
1095 U16 Reserved1; /*0x04 */
1096 U8 Reserved2; /*0x06 */
1097 U8 MsgFlags; /*0x07 */
1098 U8 VP_ID; /*0x08 */
1099 U8 VF_ID; /*0x09 */
1100 U16 Reserved3; /*0x0A */
1101 U16 Reserved4; /*0x0C */
1102 U16 IOCStatus; /*0x0E */
1103 U32 IOCLogInfo; /*0x10 */
1104} MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1105 Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t;
1106
1107/****************************************************************************
1108* FWDownload message
1109****************************************************************************/
1110
1111/*MPI v2.0 FWDownload Request message */
1112typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
1113 U8 ImageType; /*0x00 */
1114 U8 Reserved1; /*0x01 */
1115 U8 ChainOffset; /*0x02 */
1116 U8 Function; /*0x03 */
1117 U16 Reserved2; /*0x04 */
1118 U8 Reserved3; /*0x06 */
1119 U8 MsgFlags; /*0x07 */
1120 U8 VP_ID; /*0x08 */
1121 U8 VF_ID; /*0x09 */
1122 U16 Reserved4; /*0x0A */
1123 U32 TotalImageSize; /*0x0C */
1124 U32 Reserved5; /*0x10 */
1125 MPI2_MPI_SGE_UNION SGL; /*0x14 */
1126} MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST,
1127 Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest;
1128
1129#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1130
1131#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1132#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1133#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1134#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1135#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1136#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1137#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1138#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1139#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1140
1141/*MPI v2.0 FWDownload TransactionContext Element */
1142typedef struct _MPI2_FW_DOWNLOAD_TCSGE {
1143 U8 Reserved1; /*0x00 */
1144 U8 ContextSize; /*0x01 */
1145 U8 DetailsLength; /*0x02 */
1146 U8 Flags; /*0x03 */
1147 U32 Reserved2; /*0x04 */
1148 U32 ImageOffset; /*0x08 */
1149 U32 ImageSize; /*0x0C */
1150} MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE,
1151 Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t;
1152
1153/*MPI v2.5 FWDownload Request message */
1154typedef struct _MPI25_FW_DOWNLOAD_REQUEST {
1155 U8 ImageType; /*0x00 */
1156 U8 Reserved1; /*0x01 */
1157 U8 ChainOffset; /*0x02 */
1158 U8 Function; /*0x03 */
1159 U16 Reserved2; /*0x04 */
1160 U8 Reserved3; /*0x06 */
1161 U8 MsgFlags; /*0x07 */
1162 U8 VP_ID; /*0x08 */
1163 U8 VF_ID; /*0x09 */
1164 U16 Reserved4; /*0x0A */
1165 U32 TotalImageSize; /*0x0C */
1166 U32 Reserved5; /*0x10 */
1167 U32 Reserved6; /*0x14 */
1168 U32 ImageOffset; /*0x18 */
1169 U32 ImageSize; /*0x1C */
1170 MPI25_SGE_IO_UNION SGL; /*0x20 */
1171} MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST,
1172 Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest;
1173
1174/*FWDownload Reply message */
1175typedef struct _MPI2_FW_DOWNLOAD_REPLY {
1176 U8 ImageType; /*0x00 */
1177 U8 Reserved1; /*0x01 */
1178 U8 MsgLength; /*0x02 */
1179 U8 Function; /*0x03 */
1180 U16 Reserved2; /*0x04 */
1181 U8 Reserved3; /*0x06 */
1182 U8 MsgFlags; /*0x07 */
1183 U8 VP_ID; /*0x08 */
1184 U8 VF_ID; /*0x09 */
1185 U16 Reserved4; /*0x0A */
1186 U16 Reserved5; /*0x0C */
1187 U16 IOCStatus; /*0x0E */
1188 U32 IOCLogInfo; /*0x10 */
1189} MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY,
1190 Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t;
1191
1192/****************************************************************************
1193* FWUpload message
1194****************************************************************************/
1195
1196/*MPI v2.0 FWUpload Request message */
1197typedef struct _MPI2_FW_UPLOAD_REQUEST {
1198 U8 ImageType; /*0x00 */
1199 U8 Reserved1; /*0x01 */
1200 U8 ChainOffset; /*0x02 */
1201 U8 Function; /*0x03 */
1202 U16 Reserved2; /*0x04 */
1203 U8 Reserved3; /*0x06 */
1204 U8 MsgFlags; /*0x07 */
1205 U8 VP_ID; /*0x08 */
1206 U8 VF_ID; /*0x09 */
1207 U16 Reserved4; /*0x0A */
1208 U32 Reserved5; /*0x0C */
1209 U32 Reserved6; /*0x10 */
1210 MPI2_MPI_SGE_UNION SGL; /*0x14 */
1211} MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST,
1212 Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t;
1213
1214#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1215#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1216#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1217#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1218#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1219#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1220#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1221#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1222#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1223#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1224
1225/*MPI v2.0 FWUpload TransactionContext Element */
1226typedef struct _MPI2_FW_UPLOAD_TCSGE {
1227 U8 Reserved1; /*0x00 */
1228 U8 ContextSize; /*0x01 */
1229 U8 DetailsLength; /*0x02 */
1230 U8 Flags; /*0x03 */
1231 U32 Reserved2; /*0x04 */
1232 U32 ImageOffset; /*0x08 */
1233 U32 ImageSize; /*0x0C */
1234} MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE,
1235 Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t;
1236
1237/*MPI v2.5 FWUpload Request message */
1238typedef struct _MPI25_FW_UPLOAD_REQUEST {
1239 U8 ImageType; /*0x00 */
1240 U8 Reserved1; /*0x01 */
1241 U8 ChainOffset; /*0x02 */
1242 U8 Function; /*0x03 */
1243 U16 Reserved2; /*0x04 */
1244 U8 Reserved3; /*0x06 */
1245 U8 MsgFlags; /*0x07 */
1246 U8 VP_ID; /*0x08 */
1247 U8 VF_ID; /*0x09 */
1248 U16 Reserved4; /*0x0A */
1249 U32 Reserved5; /*0x0C */
1250 U32 Reserved6; /*0x10 */
1251 U32 Reserved7; /*0x14 */
1252 U32 ImageOffset; /*0x18 */
1253 U32 ImageSize; /*0x1C */
1254 MPI25_SGE_IO_UNION SGL; /*0x20 */
1255} MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST,
1256 Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t;
1257
1258/*FWUpload Reply message */
1259typedef struct _MPI2_FW_UPLOAD_REPLY {
1260 U8 ImageType; /*0x00 */
1261 U8 Reserved1; /*0x01 */
1262 U8 MsgLength; /*0x02 */
1263 U8 Function; /*0x03 */
1264 U16 Reserved2; /*0x04 */
1265 U8 Reserved3; /*0x06 */
1266 U8 MsgFlags; /*0x07 */
1267 U8 VP_ID; /*0x08 */
1268 U8 VF_ID; /*0x09 */
1269 U16 Reserved4; /*0x0A */
1270 U16 Reserved5; /*0x0C */
1271 U16 IOCStatus; /*0x0E */
1272 U32 IOCLogInfo; /*0x10 */
1273 U32 ActualImageSize; /*0x14 */
1274} MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY,
1275 Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t;
1276
1277/*FW Image Header */
1278typedef struct _MPI2_FW_IMAGE_HEADER {
1279 U32 Signature; /*0x00 */
1280 U32 Signature0; /*0x04 */
1281 U32 Signature1; /*0x08 */
1282 U32 Signature2; /*0x0C */
1283 MPI2_VERSION_UNION MPIVersion; /*0x10 */
1284 MPI2_VERSION_UNION FWVersion; /*0x14 */
1285 MPI2_VERSION_UNION NVDATAVersion; /*0x18 */
1286 MPI2_VERSION_UNION PackageVersion; /*0x1C */
1287 U16 VendorID; /*0x20 */
1288 U16 ProductID; /*0x22 */
1289 U16 ProtocolFlags; /*0x24 */
1290 U16 Reserved26; /*0x26 */
1291 U32 IOCCapabilities; /*0x28 */
1292 U32 ImageSize; /*0x2C */
1293 U32 NextImageHeaderOffset; /*0x30 */
1294 U32 Checksum; /*0x34 */
1295 U32 Reserved38; /*0x38 */
1296 U32 Reserved3C; /*0x3C */
1297 U32 Reserved40; /*0x40 */
1298 U32 Reserved44; /*0x44 */
1299 U32 Reserved48; /*0x48 */
1300 U32 Reserved4C; /*0x4C */
1301 U32 Reserved50; /*0x50 */
1302 U32 Reserved54; /*0x54 */
1303 U32 Reserved58; /*0x58 */
1304 U32 Reserved5C; /*0x5C */
1305 U32 Reserved60; /*0x60 */
1306 U32 FirmwareVersionNameWhat; /*0x64 */
1307 U8 FirmwareVersionName[32]; /*0x68 */
1308 U32 VendorNameWhat; /*0x88 */
1309 U8 VendorName[32]; /*0x8C */
1310 U32 PackageNameWhat; /*0x88 */
1311 U8 PackageName[32]; /*0x8C */
1312 U32 ReservedD0; /*0xD0 */
1313 U32 ReservedD4; /*0xD4 */
1314 U32 ReservedD8; /*0xD8 */
1315 U32 ReservedDC; /*0xDC */
1316 U32 ReservedE0; /*0xE0 */
1317 U32 ReservedE4; /*0xE4 */
1318 U32 ReservedE8; /*0xE8 */
1319 U32 ReservedEC; /*0xEC */
1320 U32 ReservedF0; /*0xF0 */
1321 U32 ReservedF4; /*0xF4 */
1322 U32 ReservedF8; /*0xF8 */
1323 U32 ReservedFC; /*0xFC */
1324} MPI2_FW_IMAGE_HEADER, *PTR_MPI2_FW_IMAGE_HEADER,
1325 Mpi2FWImageHeader_t, *pMpi2FWImageHeader_t;
1326
1327/*Signature field */
1328#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1329#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1330#define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1331
1332/*Signature0 field */
1333#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1334#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1335
1336/*Signature1 field */
1337#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1338#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1339
1340/*Signature2 field */
1341#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1342#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1343
1344/*defines for using the ProductID field */
1345#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1346#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1347
1348#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1349#define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1350#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1351#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1352
1353#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1354/*SAS ProductID Family bits */
1355#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1356#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1357#define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021)
1358
1359/*use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1360
1361/*use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1362
1363#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1364#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1365#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1366
1367#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1368
1369#define MPI2_FW_HEADER_SIZE (0x100)
1370
1371/*Extended Image Header */
1372typedef struct _MPI2_EXT_IMAGE_HEADER {
1373 U8 ImageType; /*0x00 */
1374 U8 Reserved1; /*0x01 */
1375 U16 Reserved2; /*0x02 */
1376 U32 Checksum; /*0x04 */
1377 U32 ImageSize; /*0x08 */
1378 U32 NextImageHeaderOffset; /*0x0C */
1379 U32 PackageVersion; /*0x10 */
1380 U32 Reserved3; /*0x14 */
1381 U32 Reserved4; /*0x18 */
1382 U32 Reserved5; /*0x1C */
1383 U8 IdentifyString[32]; /*0x20 */
1384} MPI2_EXT_IMAGE_HEADER, *PTR_MPI2_EXT_IMAGE_HEADER,
1385 Mpi2ExtImageHeader_t, *pMpi2ExtImageHeader_t;
1386
1387/*useful offsets */
1388#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1389#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1390#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1391
1392#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1393
1394/*defines for the ImageType field */
1395#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1396#define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1397#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1398#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1399#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1400#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1401#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1402#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1403#define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80)
1404#define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF)
1405
1406#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC)
1407
1408/*FLASH Layout Extended Image Data */
1409
1410/*
1411 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1412 *one and check RegionsPerLayout at runtime.
1413 */
1414#ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1415#define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1416#endif
1417
1418/*
1419 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1420 *one and check NumberOfLayouts at runtime.
1421 */
1422#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1423#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1424#endif
1425
1426typedef struct _MPI2_FLASH_REGION {
1427 U8 RegionType; /*0x00 */
1428 U8 Reserved1; /*0x01 */
1429 U16 Reserved2; /*0x02 */
1430 U32 RegionOffset; /*0x04 */
1431 U32 RegionSize; /*0x08 */
1432 U32 Reserved3; /*0x0C */
1433} MPI2_FLASH_REGION, *PTR_MPI2_FLASH_REGION,
1434 Mpi2FlashRegion_t, *pMpi2FlashRegion_t;
1435
1436typedef struct _MPI2_FLASH_LAYOUT {
1437 U32 FlashSize; /*0x00 */
1438 U32 Reserved1; /*0x04 */
1439 U32 Reserved2; /*0x08 */
1440 U32 Reserved3; /*0x0C */
1441 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS]; /*0x10 */
1442} MPI2_FLASH_LAYOUT, *PTR_MPI2_FLASH_LAYOUT,
1443 Mpi2FlashLayout_t, *pMpi2FlashLayout_t;
1444
1445typedef struct _MPI2_FLASH_LAYOUT_DATA {
1446 U8 ImageRevision; /*0x00 */
1447 U8 Reserved1; /*0x01 */
1448 U8 SizeOfRegion; /*0x02 */
1449 U8 Reserved2; /*0x03 */
1450 U16 NumberOfLayouts; /*0x04 */
1451 U16 RegionsPerLayout; /*0x06 */
1452 U16 MinimumSectorAlignment; /*0x08 */
1453 U16 Reserved3; /*0x0A */
1454 U32 Reserved4; /*0x0C */
1455 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS]; /*0x10 */
1456} MPI2_FLASH_LAYOUT_DATA, *PTR_MPI2_FLASH_LAYOUT_DATA,
1457 Mpi2FlashLayoutData_t, *pMpi2FlashLayoutData_t;
1458
1459/*defines for the RegionType field */
1460#define MPI2_FLASH_REGION_UNUSED (0x00)
1461#define MPI2_FLASH_REGION_FIRMWARE (0x01)
1462#define MPI2_FLASH_REGION_BIOS (0x02)
1463#define MPI2_FLASH_REGION_NVDATA (0x03)
1464#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1465#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1466#define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1467#define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1468#define MPI2_FLASH_REGION_MEGARAID (0x09)
1469#define MPI2_FLASH_REGION_INIT (0x0A)
1470
1471/*ImageRevision */
1472#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1473
1474/*Supported Devices Extended Image Data */
1475
1476/*
1477 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1478 *one and check NumberOfDevices at runtime.
1479 */
1480#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1481#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1482#endif
1483
1484typedef struct _MPI2_SUPPORTED_DEVICE {
1485 U16 DeviceID; /*0x00 */
1486 U16 VendorID; /*0x02 */
1487 U16 DeviceIDMask; /*0x04 */
1488 U16 Reserved1; /*0x06 */
1489 U8 LowPCIRev; /*0x08 */
1490 U8 HighPCIRev; /*0x09 */
1491 U16 Reserved2; /*0x0A */
1492 U32 Reserved3; /*0x0C */
1493} MPI2_SUPPORTED_DEVICE, *PTR_MPI2_SUPPORTED_DEVICE,
1494 Mpi2SupportedDevice_t, *pMpi2SupportedDevice_t;
1495
1496typedef struct _MPI2_SUPPORTED_DEVICES_DATA {
1497 U8 ImageRevision; /*0x00 */
1498 U8 Reserved1; /*0x01 */
1499 U8 NumberOfDevices; /*0x02 */
1500 U8 Reserved2; /*0x03 */
1501 U32 Reserved3; /*0x04 */
1502 MPI2_SUPPORTED_DEVICE
1503 SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES];/*0x08 */
1504} MPI2_SUPPORTED_DEVICES_DATA, *PTR_MPI2_SUPPORTED_DEVICES_DATA,
1505 Mpi2SupportedDevicesData_t, *pMpi2SupportedDevicesData_t;
1506
1507/*ImageRevision */
1508#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1509
1510/*Init Extended Image Data */
1511
1512typedef struct _MPI2_INIT_IMAGE_FOOTER {
1513 U32 BootFlags; /*0x00 */
1514 U32 ImageSize; /*0x04 */
1515 U32 Signature0; /*0x08 */
1516 U32 Signature1; /*0x0C */
1517 U32 Signature2; /*0x10 */
1518 U32 ResetVector; /*0x14 */
1519} MPI2_INIT_IMAGE_FOOTER, *PTR_MPI2_INIT_IMAGE_FOOTER,
1520 Mpi2InitImageFooter_t, *pMpi2InitImageFooter_t;
1521
1522/*defines for the BootFlags field */
1523#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1524
1525/*defines for the ImageSize field */
1526#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1527
1528/*defines for the Signature0 field */
1529#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1530#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1531
1532/*defines for the Signature1 field */
1533#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1534#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1535
1536/*defines for the Signature2 field */
1537#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1538#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1539
1540/*Signature fields as individual bytes */
1541#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1542#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1543#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1544#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1545
1546#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1547#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1548#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1549#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1550
1551#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1552#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1553#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1554#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1555
1556/*defines for the ResetVector field */
1557#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1558
1559/****************************************************************************
1560* PowerManagementControl message
1561****************************************************************************/
1562
1563/*PowerManagementControl Request message */
1564typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1565 U8 Feature; /*0x00 */
1566 U8 Reserved1; /*0x01 */
1567 U8 ChainOffset; /*0x02 */
1568 U8 Function; /*0x03 */
1569 U16 Reserved2; /*0x04 */
1570 U8 Reserved3; /*0x06 */
1571 U8 MsgFlags; /*0x07 */
1572 U8 VP_ID; /*0x08 */
1573 U8 VF_ID; /*0x09 */
1574 U16 Reserved4; /*0x0A */
1575 U8 Parameter1; /*0x0C */
1576 U8 Parameter2; /*0x0D */
1577 U8 Parameter3; /*0x0E */
1578 U8 Parameter4; /*0x0F */
1579 U32 Reserved5; /*0x10 */
1580 U32 Reserved6; /*0x14 */
1581} MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1582 Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t;
1583
1584/*defines for the Feature field */
1585#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1586#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1587#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /*obsolete */
1588#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1589#define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05)
1590#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1591#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1592
1593/*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1594/*Parameter1 contains a PHY number */
1595/*Parameter2 indicates power condition action using these defines */
1596#define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1597#define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1598#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1599/*Parameter3 and Parameter4 are reserved */
1600
1601/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1602 * Feature */
1603/*Parameter1 contains SAS port width modulation group number */
1604/*Parameter2 indicates IOC action using these defines */
1605#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1606#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1607#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1608/*Parameter3 indicates desired modulation level using these defines */
1609#define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1610#define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1611#define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1612#define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1613/*Parameter4 is reserved */
1614
1615/*this next set (_PCIE_LINK) is obsolete */
1616/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1617/*Parameter1 indicates desired PCIe link speed using these defines */
1618#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /*obsolete */
1619#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /*obsolete */
1620#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /*obsolete */
1621/*Parameter2 indicates desired PCIe link width using these defines */
1622#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /*obsolete */
1623#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /*obsolete */
1624#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /*obsolete */
1625#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /*obsolete */
1626/*Parameter3 and Parameter4 are reserved */
1627
1628/*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1629/*Parameter1 indicates desired IOC hardware clock speed using these defines */
1630#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
1631#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
1632#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
1633#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
1634/*Parameter2, Parameter3, and Parameter4 are reserved */
1635
1636/*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/
1637/*Parameter1 indicates host action regarding global power management mode */
1638#define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01)
1639#define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02)
1640#define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03)
1641/*Parameter2 indicates the requested global power management mode */
1642#define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01)
1643#define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08)
1644#define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40)
1645/*Parameter3 and Parameter4 are reserved */
1646
1647/*PowerManagementControl Reply message */
1648typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1649 U8 Feature; /*0x00 */
1650 U8 Reserved1; /*0x01 */
1651 U8 MsgLength; /*0x02 */
1652 U8 Function; /*0x03 */
1653 U16 Reserved2; /*0x04 */
1654 U8 Reserved3; /*0x06 */
1655 U8 MsgFlags; /*0x07 */
1656 U8 VP_ID; /*0x08 */
1657 U8 VF_ID; /*0x09 */
1658 U16 Reserved4; /*0x0A */
1659 U16 Reserved5; /*0x0C */
1660 U16 IOCStatus; /*0x0E */
1661 U32 IOCLogInfo; /*0x10 */
1662} MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1663 Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t;
1664
1665#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 20:21:19 -0500