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1/*
2 * Copyright (c) 2000-2009 LSI Corporation.
3 *
4 *
5 * Name: mpi2_ioc.h
6 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
7 * Creation Date: October 11, 2006
8 *
9 * mpi2_ioc.h Version: 02.00.10
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
18 * MaxTargets.
19 * Added TotalImageSize field to FWDownload Request.
20 * Added reserved words to FWUpload Request.
21 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
22 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
23 * request and replaced it with
24 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
25 * Replaced the MinReplyQueueDepth field of the IOCFacts
26 * reply with MaxReplyDescriptorPostQueueDepth.
27 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
28 * depth for the Reply Descriptor Post Queue.
29 * Added SASAddress field to Initiator Device Table
30 * Overflow Event data.
31 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
32 * for SAS Initiator Device Status Change Event data.
33 * Modified Reason Code defines for SAS Topology Change
34 * List Event data, including adding a bit for PHY Vacant
35 * status, and adding a mask for the Reason Code.
36 * Added define for
37 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
38 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
39 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
40 * the IOCFacts Reply.
41 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
42 * Moved MPI2_VERSION_UNION to mpi2.h.
43 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
44 * instead of enables, and added SASBroadcastPrimitiveMasks
45 * field.
46 * Added Log Entry Added Event and related structure.
47 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
48 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
49 * Added MaxVolumes and MaxPersistentEntries fields to
50 * IOCFacts reply.
51 * Added ProtocalFlags and IOCCapabilities fields to
52 * MPI2_FW_IMAGE_HEADER.
53 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
54 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
55 * a U16 (from a U32).
56 * Removed extra 's' from EventMasks name.
57 * 06-27-08 02.00.08 Fixed an offset in a comment.
58 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
59 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
60 * renamed MinReplyFrameSize to ReplyFrameSize.
61 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
62 * Added two new RAIDOperation values for Integrated RAID
63 * Operations Status Event data.
64 * Added four new IR Configuration Change List Event data
65 * ReasonCode values.
66 * Added two new ReasonCode defines for SAS Device Status
67 * Change Event data.
68 * Added three new DiscoveryStatus bits for the SAS
69 * Discovery event data.
70 * Added Multiplexing Status Change bit to the PhyStatus
71 * field of the SAS Topology Change List event data.
72 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
73 * BootFlags are now product-specific.
74 * Added defines for the indivdual signature bytes
75 * for MPI2_INIT_IMAGE_FOOTER.
76 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
77 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
78 * define.
79 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
80 * define.
81 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
82 * --------------------------------------------------------------------------
83 */
84
85#ifndef MPI2_IOC_H
86#define MPI2_IOC_H
87
88/*****************************************************************************
89*
90* IOC Messages
91*
92*****************************************************************************/
93
94/****************************************************************************
95* IOCInit message
96****************************************************************************/
97
98/* IOCInit Request message */
99typedef struct _MPI2_IOC_INIT_REQUEST
100{
101 U8 WhoInit; /* 0x00 */
102 U8 Reserved1; /* 0x01 */
103 U8 ChainOffset; /* 0x02 */
104 U8 Function; /* 0x03 */
105 U16 Reserved2; /* 0x04 */
106 U8 Reserved3; /* 0x06 */
107 U8 MsgFlags; /* 0x07 */
108 U8 VP_ID; /* 0x08 */
109 U8 VF_ID; /* 0x09 */
110 U16 Reserved4; /* 0x0A */
111 U16 MsgVersion; /* 0x0C */
112 U16 HeaderVersion; /* 0x0E */
113 U32 Reserved5; /* 0x10 */
114 U32 Reserved6; /* 0x14 */
115 U16 Reserved7; /* 0x18 */
116 U16 SystemRequestFrameSize; /* 0x1A */
117 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
118 U16 ReplyFreeQueueDepth; /* 0x1E */
119 U32 SenseBufferAddressHigh; /* 0x20 */
120 U32 SystemReplyAddressHigh; /* 0x24 */
121 U64 SystemRequestFrameBaseAddress; /* 0x28 */
122 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
123 U64 ReplyFreeQueueAddress; /* 0x38 */
124 U64 TimeStamp; /* 0x40 */
125} MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
126 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
127
128/* WhoInit values */
129#define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
130#define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
131#define MPI2_WHOINIT_ROM_BIOS (0x02)
132#define MPI2_WHOINIT_PCI_PEER (0x03)
133#define MPI2_WHOINIT_HOST_DRIVER (0x04)
134#define MPI2_WHOINIT_MANUFACTURER (0x05)
135
136/* MsgVersion */
137#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
138#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
139#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
140#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
141
142/* HeaderVersion */
143#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
144#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
145#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
146#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
147
148/* minimum depth for the Reply Descriptor Post Queue */
149#define MPI2_RDPQ_DEPTH_MIN (16)
150
151
152/* IOCInit Reply message */
153typedef struct _MPI2_IOC_INIT_REPLY
154{
155 U8 WhoInit; /* 0x00 */
156 U8 Reserved1; /* 0x01 */
157 U8 MsgLength; /* 0x02 */
158 U8 Function; /* 0x03 */
159 U16 Reserved2; /* 0x04 */
160 U8 Reserved3; /* 0x06 */
161 U8 MsgFlags; /* 0x07 */
162 U8 VP_ID; /* 0x08 */
163 U8 VF_ID; /* 0x09 */
164 U16 Reserved4; /* 0x0A */
165 U16 Reserved5; /* 0x0C */
166 U16 IOCStatus; /* 0x0E */
167 U32 IOCLogInfo; /* 0x10 */
168} MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
169 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
170
171
172/****************************************************************************
173* IOCFacts message
174****************************************************************************/
175
176/* IOCFacts Request message */
177typedef struct _MPI2_IOC_FACTS_REQUEST
178{
179 U16 Reserved1; /* 0x00 */
180 U8 ChainOffset; /* 0x02 */
181 U8 Function; /* 0x03 */
182 U16 Reserved2; /* 0x04 */
183 U8 Reserved3; /* 0x06 */
184 U8 MsgFlags; /* 0x07 */
185 U8 VP_ID; /* 0x08 */
186 U8 VF_ID; /* 0x09 */
187 U16 Reserved4; /* 0x0A */
188} MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
189 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
190
191
192/* IOCFacts Reply message */
193typedef struct _MPI2_IOC_FACTS_REPLY
194{
195 U16 MsgVersion; /* 0x00 */
196 U8 MsgLength; /* 0x02 */
197 U8 Function; /* 0x03 */
198 U16 HeaderVersion; /* 0x04 */
199 U8 IOCNumber; /* 0x06 */
200 U8 MsgFlags; /* 0x07 */
201 U8 VP_ID; /* 0x08 */
202 U8 VF_ID; /* 0x09 */
203 U16 Reserved1; /* 0x0A */
204 U16 IOCExceptions; /* 0x0C */
205 U16 IOCStatus; /* 0x0E */
206 U32 IOCLogInfo; /* 0x10 */
207 U8 MaxChainDepth; /* 0x14 */
208 U8 WhoInit; /* 0x15 */
209 U8 NumberOfPorts; /* 0x16 */
210 U8 Reserved2; /* 0x17 */
211 U16 RequestCredit; /* 0x18 */
212 U16 ProductID; /* 0x1A */
213 U32 IOCCapabilities; /* 0x1C */
214 MPI2_VERSION_UNION FWVersion; /* 0x20 */
215 U16 IOCRequestFrameSize; /* 0x24 */
216 U16 Reserved3; /* 0x26 */
217 U16 MaxInitiators; /* 0x28 */
218 U16 MaxTargets; /* 0x2A */
219 U16 MaxSasExpanders; /* 0x2C */
220 U16 MaxEnclosures; /* 0x2E */
221 U16 ProtocolFlags; /* 0x30 */
222 U16 HighPriorityCredit; /* 0x32 */
223 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
224 U8 ReplyFrameSize; /* 0x36 */
225 U8 MaxVolumes; /* 0x37 */
226 U16 MaxDevHandle; /* 0x38 */
227 U16 MaxPersistentEntries; /* 0x3A */
228 U32 Reserved4; /* 0x3C */
229} MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
230 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
231
232/* MsgVersion */
233#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
234#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
235#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
236#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
237
238/* HeaderVersion */
239#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
240#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
241#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
242#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
243
244/* IOCExceptions */
245#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
246
247#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
248#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
249#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
250#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
251#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
252
253#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
254#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
255#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
256#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
257#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
258
259/* defines for WhoInit field are after the IOCInit Request */
260
261/* ProductID field uses MPI2_FW_HEADER_PID_ */
262
263/* IOCCapabilities */
264#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
265#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
266#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
267#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
268#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
269#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
270#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
271#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
272#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
273
274/* ProtocolFlags */
275#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
276#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
277
278
279/****************************************************************************
280* PortFacts message
281****************************************************************************/
282
283/* PortFacts Request message */
284typedef struct _MPI2_PORT_FACTS_REQUEST
285{
286 U16 Reserved1; /* 0x00 */
287 U8 ChainOffset; /* 0x02 */
288 U8 Function; /* 0x03 */
289 U16 Reserved2; /* 0x04 */
290 U8 PortNumber; /* 0x06 */
291 U8 MsgFlags; /* 0x07 */
292 U8 VP_ID; /* 0x08 */
293 U8 VF_ID; /* 0x09 */
294 U16 Reserved3; /* 0x0A */
295} MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
296 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
297
298/* PortFacts Reply message */
299typedef struct _MPI2_PORT_FACTS_REPLY
300{
301 U16 Reserved1; /* 0x00 */
302 U8 MsgLength; /* 0x02 */
303 U8 Function; /* 0x03 */
304 U16 Reserved2; /* 0x04 */
305 U8 PortNumber; /* 0x06 */
306 U8 MsgFlags; /* 0x07 */
307 U8 VP_ID; /* 0x08 */
308 U8 VF_ID; /* 0x09 */
309 U16 Reserved3; /* 0x0A */
310 U16 Reserved4; /* 0x0C */
311 U16 IOCStatus; /* 0x0E */
312 U32 IOCLogInfo; /* 0x10 */
313 U8 Reserved5; /* 0x14 */
314 U8 PortType; /* 0x15 */
315 U16 Reserved6; /* 0x16 */
316 U16 MaxPostedCmdBuffers; /* 0x18 */
317 U16 Reserved7; /* 0x1A */
318} MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
319 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
320
321/* PortType values */
322#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
323#define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
324#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
325#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
326#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
327
328
329/****************************************************************************
330* PortEnable message
331****************************************************************************/
332
333/* PortEnable Request message */
334typedef struct _MPI2_PORT_ENABLE_REQUEST
335{
336 U16 Reserved1; /* 0x00 */
337 U8 ChainOffset; /* 0x02 */
338 U8 Function; /* 0x03 */
339 U8 Reserved2; /* 0x04 */
340 U8 PortFlags; /* 0x05 */
341 U8 Reserved3; /* 0x06 */
342 U8 MsgFlags; /* 0x07 */
343 U8 VP_ID; /* 0x08 */
344 U8 VF_ID; /* 0x09 */
345 U16 Reserved4; /* 0x0A */
346} MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
347 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
348
349
350/* PortEnable Reply message */
351typedef struct _MPI2_PORT_ENABLE_REPLY
352{
353 U16 Reserved1; /* 0x00 */
354 U8 MsgLength; /* 0x02 */
355 U8 Function; /* 0x03 */
356 U8 Reserved2; /* 0x04 */
357 U8 PortFlags; /* 0x05 */
358 U8 Reserved3; /* 0x06 */
359 U8 MsgFlags; /* 0x07 */
360 U8 VP_ID; /* 0x08 */
361 U8 VF_ID; /* 0x09 */
362 U16 Reserved4; /* 0x0A */
363 U16 Reserved5; /* 0x0C */
364 U16 IOCStatus; /* 0x0E */
365 U32 IOCLogInfo; /* 0x10 */
366} MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
367 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
368
369
370/****************************************************************************
371* EventNotification message
372****************************************************************************/
373
374/* EventNotification Request message */
375#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
376
377typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
378{
379 U16 Reserved1; /* 0x00 */
380 U8 ChainOffset; /* 0x02 */
381 U8 Function; /* 0x03 */
382 U16 Reserved2; /* 0x04 */
383 U8 Reserved3; /* 0x06 */
384 U8 MsgFlags; /* 0x07 */
385 U8 VP_ID; /* 0x08 */
386 U8 VF_ID; /* 0x09 */
387 U16 Reserved4; /* 0x0A */
388 U32 Reserved5; /* 0x0C */
389 U32 Reserved6; /* 0x10 */
390 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
391 U16 SASBroadcastPrimitiveMasks; /* 0x24 */
392 U16 Reserved7; /* 0x26 */
393 U32 Reserved8; /* 0x28 */
394} MPI2_EVENT_NOTIFICATION_REQUEST,
395 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
396 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
397
398
399/* EventNotification Reply message */
400typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
401{
402 U16 EventDataLength; /* 0x00 */
403 U8 MsgLength; /* 0x02 */
404 U8 Function; /* 0x03 */
405 U16 Reserved1; /* 0x04 */
406 U8 AckRequired; /* 0x06 */
407 U8 MsgFlags; /* 0x07 */
408 U8 VP_ID; /* 0x08 */
409 U8 VF_ID; /* 0x09 */
410 U16 Reserved2; /* 0x0A */
411 U16 Reserved3; /* 0x0C */
412 U16 IOCStatus; /* 0x0E */
413 U32 IOCLogInfo; /* 0x10 */
414 U16 Event; /* 0x14 */
415 U16 Reserved4; /* 0x16 */
416 U32 EventContext; /* 0x18 */
417 U32 EventData[1]; /* 0x1C */
418} MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
419 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
420
421/* AckRequired */
422#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
423#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
424
425/* Event */
426#define MPI2_EVENT_LOG_DATA (0x0001)
427#define MPI2_EVENT_STATE_CHANGE (0x0002)
428#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
429#define MPI2_EVENT_EVENT_CHANGE (0x000A)
430#define MPI2_EVENT_TASK_SET_FULL (0x000E)
431#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
432#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
433#define MPI2_EVENT_SAS_DISCOVERY (0x0016)
434#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
435#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
436#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
437#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
438#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
439#define MPI2_EVENT_IR_VOLUME (0x001E)
440#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
441#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
442#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
443
444
445/* Log Entry Added Event data */
446
447/* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
448#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
449
450typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
451{
452 U64 TimeStamp; /* 0x00 */
453 U32 Reserved1; /* 0x08 */
454 U16 LogSequence; /* 0x0C */
455 U16 LogEntryQualifier; /* 0x0E */
456 U8 VP_ID; /* 0x10 */
457 U8 VF_ID; /* 0x11 */
458 U16 Reserved2; /* 0x12 */
459 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
460} MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
461 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
462 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
463
464/* Hard Reset Received Event data */
465
466typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
467{
468 U8 Reserved1; /* 0x00 */
469 U8 Port; /* 0x01 */
470 U16 Reserved2; /* 0x02 */
471} MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
472 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
473 Mpi2EventDataHardResetReceived_t,
474 MPI2_POINTER pMpi2EventDataHardResetReceived_t;
475
476/* Task Set Full Event data */
477
478typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
479{
480 U16 DevHandle; /* 0x00 */
481 U16 CurrentDepth; /* 0x02 */
482} MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
483 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
484
485
486/* SAS Device Status Change Event data */
487
488typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
489{
490 U16 TaskTag; /* 0x00 */
491 U8 ReasonCode; /* 0x02 */
492 U8 Reserved1; /* 0x03 */
493 U8 ASC; /* 0x04 */
494 U8 ASCQ; /* 0x05 */
495 U16 DevHandle; /* 0x06 */
496 U32 Reserved2; /* 0x08 */
497 U64 SASAddress; /* 0x0C */
498 U8 LUN[8]; /* 0x14 */
499} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
500 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
501 Mpi2EventDataSasDeviceStatusChange_t,
502 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
503
504/* SAS Device Status Change Event data ReasonCode values */
505#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
506#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
507#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
508#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
509#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
510#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
511#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
512#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
513#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
514#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
515#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
516
517
518/* Integrated RAID Operation Status Event data */
519
520typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
521{
522 U16 VolDevHandle; /* 0x00 */
523 U16 Reserved1; /* 0x02 */
524 U8 RAIDOperation; /* 0x04 */
525 U8 PercentComplete; /* 0x05 */
526 U16 Reserved2; /* 0x06 */
527 U32 Resereved3; /* 0x08 */
528} MPI2_EVENT_DATA_IR_OPERATION_STATUS,
529 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
530 Mpi2EventDataIrOperationStatus_t,
531 MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
532
533/* Integrated RAID Operation Status Event data RAIDOperation values */
534#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
535#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
536#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
537#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
538#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
539
540
541/* Integrated RAID Volume Event data */
542
543typedef struct _MPI2_EVENT_DATA_IR_VOLUME
544{
545 U16 VolDevHandle; /* 0x00 */
546 U8 ReasonCode; /* 0x02 */
547 U8 Reserved1; /* 0x03 */
548 U32 NewValue; /* 0x04 */
549 U32 PreviousValue; /* 0x08 */
550} MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
551 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
552
553/* Integrated RAID Volume Event data ReasonCode values */
554#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
555#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
556#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
557
558
559/* Integrated RAID Physical Disk Event data */
560
561typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
562{
563 U16 Reserved1; /* 0x00 */
564 U8 ReasonCode; /* 0x02 */
565 U8 PhysDiskNum; /* 0x03 */
566 U16 PhysDiskDevHandle; /* 0x04 */
567 U16 Reserved2; /* 0x06 */
568 U16 Slot; /* 0x08 */
569 U16 EnclosureHandle; /* 0x0A */
570 U32 NewValue; /* 0x0C */
571 U32 PreviousValue; /* 0x10 */
572} MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
573 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
574 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
575
576/* Integrated RAID Physical Disk Event data ReasonCode values */
577#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
578#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
579#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
580
581
582/* Integrated RAID Configuration Change List Event data */
583
584/*
585 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
586 * one and check NumElements at runtime.
587 */
588#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
589#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
590#endif
591
592typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
593{
594 U16 ElementFlags; /* 0x00 */
595 U16 VolDevHandle; /* 0x02 */
596 U8 ReasonCode; /* 0x04 */
597 U8 PhysDiskNum; /* 0x05 */
598 U16 PhysDiskDevHandle; /* 0x06 */
599} MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
600 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
601
602/* IR Configuration Change List Event data ElementFlags values */
603#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
604#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
605#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
606#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
607
608/* IR Configuration Change List Event data ReasonCode values */
609#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
610#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
611#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
612#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
613#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
614#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
615#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
616#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
617#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
618
619typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
620{
621 U8 NumElements; /* 0x00 */
622 U8 Reserved1; /* 0x01 */
623 U8 Reserved2; /* 0x02 */
624 U8 ConfigNum; /* 0x03 */
625 U32 Flags; /* 0x04 */
626 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */
627} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
628 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
629 Mpi2EventDataIrConfigChangeList_t,
630 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
631
632/* IR Configuration Change List Event data Flags values */
633#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
634
635
636/* SAS Discovery Event data */
637
638typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
639{
640 U8 Flags; /* 0x00 */
641 U8 ReasonCode; /* 0x01 */
642 U8 PhysicalPort; /* 0x02 */
643 U8 Reserved1; /* 0x03 */
644 U32 DiscoveryStatus; /* 0x04 */
645} MPI2_EVENT_DATA_SAS_DISCOVERY,
646 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
647 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
648
649/* SAS Discovery Event data Flags values */
650#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
651#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
652
653/* SAS Discovery Event data ReasonCode values */
654#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
655#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
656
657/* SAS Discovery Event data DiscoveryStatus values */
658#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
659#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
660#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
661#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
662#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
663#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
664#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
665#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
666#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
667#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
668#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
669#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
670#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
671#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
672#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
673#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
674#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
675#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
676#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
677#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
678
679
680/* SAS Broadcast Primitive Event data */
681
682typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
683{
684 U8 PhyNum; /* 0x00 */
685 U8 Port; /* 0x01 */
686 U8 PortWidth; /* 0x02 */
687 U8 Primitive; /* 0x03 */
688} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
689 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
690 Mpi2EventDataSasBroadcastPrimitive_t,
691 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
692
693/* defines for the Primitive field */
694#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
695#define MPI2_EVENT_PRIMITIVE_SES (0x02)
696#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
697#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
698#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
699#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
700#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
701#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
702
703
704/* SAS Initiator Device Status Change Event data */
705
706typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
707{
708 U8 ReasonCode; /* 0x00 */
709 U8 PhysicalPort; /* 0x01 */
710 U16 DevHandle; /* 0x02 */
711 U64 SASAddress; /* 0x04 */
712} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
713 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
714 Mpi2EventDataSasInitDevStatusChange_t,
715 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
716
717/* SAS Initiator Device Status Change event ReasonCode values */
718#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
719#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
720
721
722/* SAS Initiator Device Table Overflow Event data */
723
724typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
725{
726 U16 MaxInit; /* 0x00 */
727 U16 CurrentInit; /* 0x02 */
728 U64 SASAddress; /* 0x04 */
729} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
730 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
731 Mpi2EventDataSasInitTableOverflow_t,
732 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
733
734
735/* SAS Topology Change List Event data */
736
737/*
738 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
739 * one and check NumEntries at runtime.
740 */
741#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
742#define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
743#endif
744
745typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
746{
747 U16 AttachedDevHandle; /* 0x00 */
748 U8 LinkRate; /* 0x02 */
749 U8 PhyStatus; /* 0x03 */
750} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
751 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
752
753typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
754{
755 U16 EnclosureHandle; /* 0x00 */
756 U16 ExpanderDevHandle; /* 0x02 */
757 U8 NumPhys; /* 0x04 */
758 U8 Reserved1; /* 0x05 */
759 U16 Reserved2; /* 0x06 */
760 U8 NumEntries; /* 0x08 */
761 U8 StartPhyNum; /* 0x09 */
762 U8 ExpStatus; /* 0x0A */
763 U8 PhysicalPort; /* 0x0B */
764 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
765} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
766 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
767 Mpi2EventDataSasTopologyChangeList_t,
768 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
769
770/* values for the ExpStatus field */
771#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
772#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
773#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
774#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
775
776/* defines for the LinkRate field */
777#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
778#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
779#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
780#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
781
782#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
783#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
784#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
785#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
786#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
787#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
788#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
789#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
790#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
791
792/* values for the PhyStatus field */
793#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
794#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
795/* values for the PhyStatus ReasonCode sub-field */
796#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
797#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
798#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
799#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
800#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
801#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
802
803
804/* SAS Enclosure Device Status Change Event data */
805
806typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
807{
808 U16 EnclosureHandle; /* 0x00 */
809 U8 ReasonCode; /* 0x02 */
810 U8 PhysicalPort; /* 0x03 */
811 U64 EnclosureLogicalID; /* 0x04 */
812 U16 NumSlots; /* 0x0C */
813 U16 StartSlot; /* 0x0E */
814 U32 PhyBits; /* 0x10 */
815} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
816 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
817 Mpi2EventDataSasEnclDevStatusChange_t,
818 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
819
820/* SAS Enclosure Device Status Change event ReasonCode values */
821#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
822#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
823
824
825/****************************************************************************
826* EventAck message
827****************************************************************************/
828
829/* EventAck Request message */
830typedef struct _MPI2_EVENT_ACK_REQUEST
831{
832 U16 Reserved1; /* 0x00 */
833 U8 ChainOffset; /* 0x02 */
834 U8 Function; /* 0x03 */
835 U16 Reserved2; /* 0x04 */
836 U8 Reserved3; /* 0x06 */
837 U8 MsgFlags; /* 0x07 */
838 U8 VP_ID; /* 0x08 */
839 U8 VF_ID; /* 0x09 */
840 U16 Reserved4; /* 0x0A */
841 U16 Event; /* 0x0C */
842 U16 Reserved5; /* 0x0E */
843 U32 EventContext; /* 0x10 */
844} MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
845 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
846
847
848/* EventAck Reply message */
849typedef struct _MPI2_EVENT_ACK_REPLY
850{
851 U16 Reserved1; /* 0x00 */
852 U8 MsgLength; /* 0x02 */
853 U8 Function; /* 0x03 */
854 U16 Reserved2; /* 0x04 */
855 U8 Reserved3; /* 0x06 */
856 U8 MsgFlags; /* 0x07 */
857 U8 VP_ID; /* 0x08 */
858 U8 VF_ID; /* 0x09 */
859 U16 Reserved4; /* 0x0A */
860 U16 Reserved5; /* 0x0C */
861 U16 IOCStatus; /* 0x0E */
862 U32 IOCLogInfo; /* 0x10 */
863} MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
864 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
865
866
867/****************************************************************************
868* FWDownload message
869****************************************************************************/
870
871/* FWDownload Request message */
872typedef struct _MPI2_FW_DOWNLOAD_REQUEST
873{
874 U8 ImageType; /* 0x00 */
875 U8 Reserved1; /* 0x01 */
876 U8 ChainOffset; /* 0x02 */
877 U8 Function; /* 0x03 */
878 U16 Reserved2; /* 0x04 */
879 U8 Reserved3; /* 0x06 */
880 U8 MsgFlags; /* 0x07 */
881 U8 VP_ID; /* 0x08 */
882 U8 VF_ID; /* 0x09 */
883 U16 Reserved4; /* 0x0A */
884 U32 TotalImageSize; /* 0x0C */
885 U32 Reserved5; /* 0x10 */
886 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
887} MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
888 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
889
890#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
891
892#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
893#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
894#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
895#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
896#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
897#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
898#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
899
900/* FWDownload TransactionContext Element */
901typedef struct _MPI2_FW_DOWNLOAD_TCSGE
902{
903 U8 Reserved1; /* 0x00 */
904 U8 ContextSize; /* 0x01 */
905 U8 DetailsLength; /* 0x02 */
906 U8 Flags; /* 0x03 */
907 U32 Reserved2; /* 0x04 */
908 U32 ImageOffset; /* 0x08 */
909 U32 ImageSize; /* 0x0C */
910} MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
911 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
912
913/* FWDownload Reply message */
914typedef struct _MPI2_FW_DOWNLOAD_REPLY
915{
916 U8 ImageType; /* 0x00 */
917 U8 Reserved1; /* 0x01 */
918 U8 MsgLength; /* 0x02 */
919 U8 Function; /* 0x03 */
920 U16 Reserved2; /* 0x04 */
921 U8 Reserved3; /* 0x06 */
922 U8 MsgFlags; /* 0x07 */
923 U8 VP_ID; /* 0x08 */
924 U8 VF_ID; /* 0x09 */
925 U16 Reserved4; /* 0x0A */
926 U16 Reserved5; /* 0x0C */
927 U16 IOCStatus; /* 0x0E */
928 U32 IOCLogInfo; /* 0x10 */
929} MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
930 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
931
932
933/****************************************************************************
934* FWUpload message
935****************************************************************************/
936
937/* FWUpload Request message */
938typedef struct _MPI2_FW_UPLOAD_REQUEST
939{
940 U8 ImageType; /* 0x00 */
941 U8 Reserved1; /* 0x01 */
942 U8 ChainOffset; /* 0x02 */
943 U8 Function; /* 0x03 */
944 U16 Reserved2; /* 0x04 */
945 U8 Reserved3; /* 0x06 */
946 U8 MsgFlags; /* 0x07 */
947 U8 VP_ID; /* 0x08 */
948 U8 VF_ID; /* 0x09 */
949 U16 Reserved4; /* 0x0A */
950 U32 Reserved5; /* 0x0C */
951 U32 Reserved6; /* 0x10 */
952 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
953} MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
954 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
955
956#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
957#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
958#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
959#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
960#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
961#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
962#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
963#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
964#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
965#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
966
967typedef struct _MPI2_FW_UPLOAD_TCSGE
968{
969 U8 Reserved1; /* 0x00 */
970 U8 ContextSize; /* 0x01 */
971 U8 DetailsLength; /* 0x02 */
972 U8 Flags; /* 0x03 */
973 U32 Reserved2; /* 0x04 */
974 U32 ImageOffset; /* 0x08 */
975 U32 ImageSize; /* 0x0C */
976} MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
977 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
978
979/* FWUpload Reply message */
980typedef struct _MPI2_FW_UPLOAD_REPLY
981{
982 U8 ImageType; /* 0x00 */
983 U8 Reserved1; /* 0x01 */
984 U8 MsgLength; /* 0x02 */
985 U8 Function; /* 0x03 */
986 U16 Reserved2; /* 0x04 */
987 U8 Reserved3; /* 0x06 */
988 U8 MsgFlags; /* 0x07 */
989 U8 VP_ID; /* 0x08 */
990 U8 VF_ID; /* 0x09 */
991 U16 Reserved4; /* 0x0A */
992 U16 Reserved5; /* 0x0C */
993 U16 IOCStatus; /* 0x0E */
994 U32 IOCLogInfo; /* 0x10 */
995 U32 ActualImageSize; /* 0x14 */
996} MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
997 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
998
999
1000/* FW Image Header */
1001typedef struct _MPI2_FW_IMAGE_HEADER
1002{
1003 U32 Signature; /* 0x00 */
1004 U32 Signature0; /* 0x04 */
1005 U32 Signature1; /* 0x08 */
1006 U32 Signature2; /* 0x0C */
1007 MPI2_VERSION_UNION MPIVersion; /* 0x10 */
1008 MPI2_VERSION_UNION FWVersion; /* 0x14 */
1009 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */
1010 MPI2_VERSION_UNION PackageVersion; /* 0x1C */
1011 U16 VendorID; /* 0x20 */
1012 U16 ProductID; /* 0x22 */
1013 U16 ProtocolFlags; /* 0x24 */
1014 U16 Reserved26; /* 0x26 */
1015 U32 IOCCapabilities; /* 0x28 */
1016 U32 ImageSize; /* 0x2C */
1017 U32 NextImageHeaderOffset; /* 0x30 */
1018 U32 Checksum; /* 0x34 */
1019 U32 Reserved38; /* 0x38 */
1020 U32 Reserved3C; /* 0x3C */
1021 U32 Reserved40; /* 0x40 */
1022 U32 Reserved44; /* 0x44 */
1023 U32 Reserved48; /* 0x48 */
1024 U32 Reserved4C; /* 0x4C */
1025 U32 Reserved50; /* 0x50 */
1026 U32 Reserved54; /* 0x54 */
1027 U32 Reserved58; /* 0x58 */
1028 U32 Reserved5C; /* 0x5C */
1029 U32 Reserved60; /* 0x60 */
1030 U32 FirmwareVersionNameWhat; /* 0x64 */
1031 U8 FirmwareVersionName[32]; /* 0x68 */
1032 U32 VendorNameWhat; /* 0x88 */
1033 U8 VendorName[32]; /* 0x8C */
1034 U32 PackageNameWhat; /* 0x88 */
1035 U8 PackageName[32]; /* 0x8C */
1036 U32 ReservedD0; /* 0xD0 */
1037 U32 ReservedD4; /* 0xD4 */
1038 U32 ReservedD8; /* 0xD8 */
1039 U32 ReservedDC; /* 0xDC */
1040 U32 ReservedE0; /* 0xE0 */
1041 U32 ReservedE4; /* 0xE4 */
1042 U32 ReservedE8; /* 0xE8 */
1043 U32 ReservedEC; /* 0xEC */
1044 U32 ReservedF0; /* 0xF0 */
1045 U32 ReservedF4; /* 0xF4 */
1046 U32 ReservedF8; /* 0xF8 */
1047 U32 ReservedFC; /* 0xFC */
1048} MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1049 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1050
1051/* Signature field */
1052#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1053#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1054#define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1055
1056/* Signature0 field */
1057#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1058#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1059
1060/* Signature1 field */
1061#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1062#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1063
1064/* Signature2 field */
1065#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1066#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1067
1068
1069/* defines for using the ProductID field */
1070#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1071#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1072
1073#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1074#define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1075
1076#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1077/* SAS */
1078#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0010)
1079
1080/* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1081
1082/* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1083
1084
1085#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1086#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1087#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1088
1089#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1090
1091#define MPI2_FW_HEADER_SIZE (0x100)
1092
1093
1094/* Extended Image Header */
1095typedef struct _MPI2_EXT_IMAGE_HEADER
1096
1097{
1098 U8 ImageType; /* 0x00 */
1099 U8 Reserved1; /* 0x01 */
1100 U16 Reserved2; /* 0x02 */
1101 U32 Checksum; /* 0x04 */
1102 U32 ImageSize; /* 0x08 */
1103 U32 NextImageHeaderOffset; /* 0x0C */
1104 U32 PackageVersion; /* 0x10 */
1105 U32 Reserved3; /* 0x14 */
1106 U32 Reserved4; /* 0x18 */
1107 U32 Reserved5; /* 0x1C */
1108 U8 IdentifyString[32]; /* 0x20 */
1109} MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1110 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1111
1112/* useful offsets */
1113#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1114#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1115#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1116
1117#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1118
1119/* defines for the ImageType field */
1120#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1121#define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1122#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1123#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1124#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1125#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1126#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1127#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1128
1129#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID)
1130
1131
1132
1133/* FLASH Layout Extended Image Data */
1134
1135/*
1136 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1137 * one and check RegionsPerLayout at runtime.
1138 */
1139#ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1140#define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1141#endif
1142
1143/*
1144 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1145 * one and check NumberOfLayouts at runtime.
1146 */
1147#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1148#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1149#endif
1150
1151typedef struct _MPI2_FLASH_REGION
1152{
1153 U8 RegionType; /* 0x00 */
1154 U8 Reserved1; /* 0x01 */
1155 U16 Reserved2; /* 0x02 */
1156 U32 RegionOffset; /* 0x04 */
1157 U32 RegionSize; /* 0x08 */
1158 U32 Reserved3; /* 0x0C */
1159} MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1160 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1161
1162typedef struct _MPI2_FLASH_LAYOUT
1163{
1164 U32 FlashSize; /* 0x00 */
1165 U32 Reserved1; /* 0x04 */
1166 U32 Reserved2; /* 0x08 */
1167 U32 Reserved3; /* 0x0C */
1168 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1169} MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1170 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1171
1172typedef struct _MPI2_FLASH_LAYOUT_DATA
1173{
1174 U8 ImageRevision; /* 0x00 */
1175 U8 Reserved1; /* 0x01 */
1176 U8 SizeOfRegion; /* 0x02 */
1177 U8 Reserved2; /* 0x03 */
1178 U16 NumberOfLayouts; /* 0x04 */
1179 U16 RegionsPerLayout; /* 0x06 */
1180 U16 MinimumSectorAlignment; /* 0x08 */
1181 U16 Reserved3; /* 0x0A */
1182 U32 Reserved4; /* 0x0C */
1183 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1184} MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1185 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1186
1187/* defines for the RegionType field */
1188#define MPI2_FLASH_REGION_UNUSED (0x00)
1189#define MPI2_FLASH_REGION_FIRMWARE (0x01)
1190#define MPI2_FLASH_REGION_BIOS (0x02)
1191#define MPI2_FLASH_REGION_NVDATA (0x03)
1192#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1193#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1194#define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1195#define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1196#define MPI2_FLASH_REGION_MEGARAID (0x09)
1197#define MPI2_FLASH_REGION_INIT (0x0A)
1198
1199/* ImageRevision */
1200#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1201
1202
1203
1204/* Supported Devices Extended Image Data */
1205
1206/*
1207 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1208 * one and check NumberOfDevices at runtime.
1209 */
1210#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1211#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1212#endif
1213
1214typedef struct _MPI2_SUPPORTED_DEVICE
1215{
1216 U16 DeviceID; /* 0x00 */
1217 U16 VendorID; /* 0x02 */
1218 U16 DeviceIDMask; /* 0x04 */
1219 U16 Reserved1; /* 0x06 */
1220 U8 LowPCIRev; /* 0x08 */
1221 U8 HighPCIRev; /* 0x09 */
1222 U16 Reserved2; /* 0x0A */
1223 U32 Reserved3; /* 0x0C */
1224} MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1225 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1226
1227typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1228{
1229 U8 ImageRevision; /* 0x00 */
1230 U8 Reserved1; /* 0x01 */
1231 U8 NumberOfDevices; /* 0x02 */
1232 U8 Reserved2; /* 0x03 */
1233 U32 Reserved3; /* 0x04 */
1234 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1235} MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1236 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1237
1238/* ImageRevision */
1239#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1240
1241
1242/* Init Extended Image Data */
1243
1244typedef struct _MPI2_INIT_IMAGE_FOOTER
1245
1246{
1247 U32 BootFlags; /* 0x00 */
1248 U32 ImageSize; /* 0x04 */
1249 U32 Signature0; /* 0x08 */
1250 U32 Signature1; /* 0x0C */
1251 U32 Signature2; /* 0x10 */
1252 U32 ResetVector; /* 0x14 */
1253} MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1254 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1255
1256/* defines for the BootFlags field */
1257#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1258
1259/* defines for the ImageSize field */
1260#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1261
1262/* defines for the Signature0 field */
1263#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1264#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1265
1266/* defines for the Signature1 field */
1267#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1268#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1269
1270/* defines for the Signature2 field */
1271#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1272#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1273
1274/* Signature fields as individual bytes */
1275#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1276#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1277#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1278#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1279
1280#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1281#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1282#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1283#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1284
1285#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1286#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1287#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1288#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1289
1290/* defines for the ResetVector field */
1291#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1292
1293
1294#endif
1295
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 12:54:26 -0500