diff options
Diffstat (limited to 'drivers/scsi/lpfc/lpfc_sli.c')
-rw-r--r-- | drivers/scsi/lpfc/lpfc_sli.c | 55 |
1 files changed, 39 insertions, 16 deletions
diff --git a/drivers/scsi/lpfc/lpfc_sli.c b/drivers/scsi/lpfc/lpfc_sli.c index bbbd8ba5c1a7..34dd87f542c2 100644 --- a/drivers/scsi/lpfc/lpfc_sli.c +++ b/drivers/scsi/lpfc/lpfc_sli.c | |||
@@ -1677,6 +1677,8 @@ lpfc_sli_chk_mbx_command(uint8_t mbxCommand) | |||
1677 | case MBX_RESUME_RPI: | 1677 | case MBX_RESUME_RPI: |
1678 | case MBX_READ_EVENT_LOG_STATUS: | 1678 | case MBX_READ_EVENT_LOG_STATUS: |
1679 | case MBX_READ_EVENT_LOG: | 1679 | case MBX_READ_EVENT_LOG: |
1680 | case MBX_SECURITY_MGMT: | ||
1681 | case MBX_AUTH_PORT: | ||
1680 | ret = mbxCommand; | 1682 | ret = mbxCommand; |
1681 | break; | 1683 | break; |
1682 | default: | 1684 | default: |
@@ -1781,6 +1783,13 @@ lpfc_sli_def_mbox_cmpl(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmb) | |||
1781 | pmb->context2 = NULL; | 1783 | pmb->context2 = NULL; |
1782 | } | 1784 | } |
1783 | 1785 | ||
1786 | /* Check security permission status on INIT_LINK mailbox command */ | ||
1787 | if ((pmb->u.mb.mbxCommand == MBX_INIT_LINK) && | ||
1788 | (pmb->u.mb.mbxStatus == MBXERR_SEC_NO_PERMISSION)) | ||
1789 | lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI, | ||
1790 | "2860 SLI authentication is required " | ||
1791 | "for INIT_LINK but has not done yet\n"); | ||
1792 | |||
1784 | if (bf_get(lpfc_mqe_command, &pmb->u.mqe) == MBX_SLI4_CONFIG) | 1793 | if (bf_get(lpfc_mqe_command, &pmb->u.mqe) == MBX_SLI4_CONFIG) |
1785 | lpfc_sli4_mbox_cmd_free(phba, pmb); | 1794 | lpfc_sli4_mbox_cmd_free(phba, pmb); |
1786 | else | 1795 | else |
@@ -3658,11 +3667,15 @@ lpfc_sli_chipset_init(struct lpfc_hba *phba) | |||
3658 | i = 0; | 3667 | i = 0; |
3659 | while ((status & (HS_FFRDY | HS_MBRDY)) != (HS_FFRDY | HS_MBRDY)) { | 3668 | while ((status & (HS_FFRDY | HS_MBRDY)) != (HS_FFRDY | HS_MBRDY)) { |
3660 | 3669 | ||
3661 | /* Check every 100ms for 5 retries, then every 500ms for 5, then | 3670 | /* Check every 10ms for 10 retries, then every 100ms for 90 |
3662 | * every 2.5 sec for 5, then reset board and every 2.5 sec for | 3671 | * retries, then every 1 sec for 50 retires for a total of |
3663 | * 4. | 3672 | * ~60 seconds before reset the board again and check every |
3673 | * 1 sec for 50 retries. The up to 60 seconds before the | ||
3674 | * board ready is required by the Falcon FIPS zeroization | ||
3675 | * complete, and any reset the board in between shall cause | ||
3676 | * restart of zeroization, further delay the board ready. | ||
3664 | */ | 3677 | */ |
3665 | if (i++ >= 20) { | 3678 | if (i++ >= 200) { |
3666 | /* Adapter failed to init, timeout, status reg | 3679 | /* Adapter failed to init, timeout, status reg |
3667 | <status> */ | 3680 | <status> */ |
3668 | lpfc_printf_log(phba, KERN_ERR, LOG_INIT, | 3681 | lpfc_printf_log(phba, KERN_ERR, LOG_INIT, |
@@ -3690,16 +3703,15 @@ lpfc_sli_chipset_init(struct lpfc_hba *phba) | |||
3690 | return -EIO; | 3703 | return -EIO; |
3691 | } | 3704 | } |
3692 | 3705 | ||
3693 | if (i <= 5) { | 3706 | if (i <= 10) |
3694 | msleep(10); | 3707 | msleep(10); |
3695 | } else if (i <= 10) { | 3708 | else if (i <= 100) |
3696 | msleep(500); | 3709 | msleep(100); |
3697 | } else { | 3710 | else |
3698 | msleep(2500); | 3711 | msleep(1000); |
3699 | } | ||
3700 | 3712 | ||
3701 | if (i == 15) { | 3713 | if (i == 150) { |
3702 | /* Do post */ | 3714 | /* Do post */ |
3703 | phba->pport->port_state = LPFC_VPORT_UNKNOWN; | 3715 | phba->pport->port_state = LPFC_VPORT_UNKNOWN; |
3704 | lpfc_sli_brdrestart(phba); | 3716 | lpfc_sli_brdrestart(phba); |
3705 | } | 3717 | } |
@@ -5950,6 +5962,8 @@ lpfc_sli4_iocb2wqe(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq, | |||
5950 | uint8_t command_type = ELS_COMMAND_NON_FIP; | 5962 | uint8_t command_type = ELS_COMMAND_NON_FIP; |
5951 | uint8_t cmnd; | 5963 | uint8_t cmnd; |
5952 | uint16_t xritag; | 5964 | uint16_t xritag; |
5965 | uint16_t abrt_iotag; | ||
5966 | struct lpfc_iocbq *abrtiocbq; | ||
5953 | struct ulp_bde64 *bpl = NULL; | 5967 | struct ulp_bde64 *bpl = NULL; |
5954 | uint32_t els_id = ELS_ID_DEFAULT; | 5968 | uint32_t els_id = ELS_ID_DEFAULT; |
5955 | int numBdes, i; | 5969 | int numBdes, i; |
@@ -6162,9 +6176,17 @@ lpfc_sli4_iocb2wqe(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq, | |||
6162 | case CMD_ABORT_XRI_CX: | 6176 | case CMD_ABORT_XRI_CX: |
6163 | /* words 0-2 memcpy should be 0 rserved */ | 6177 | /* words 0-2 memcpy should be 0 rserved */ |
6164 | /* port will send abts */ | 6178 | /* port will send abts */ |
6165 | if (iocbq->iocb.ulpCommand == CMD_CLOSE_XRI_CN) | 6179 | abrt_iotag = iocbq->iocb.un.acxri.abortContextTag; |
6180 | if (abrt_iotag != 0 && abrt_iotag <= phba->sli.last_iotag) { | ||
6181 | abrtiocbq = phba->sli.iocbq_lookup[abrt_iotag]; | ||
6182 | fip = abrtiocbq->iocb_flag & LPFC_FIP_ELS_ID_MASK; | ||
6183 | } else | ||
6184 | fip = 0; | ||
6185 | |||
6186 | if ((iocbq->iocb.ulpCommand == CMD_CLOSE_XRI_CN) || fip) | ||
6166 | /* | 6187 | /* |
6167 | * The link is down so the fw does not need to send abts | 6188 | * The link is down, or the command was ELS_FIP |
6189 | * so the fw does not need to send abts | ||
6168 | * on the wire. | 6190 | * on the wire. |
6169 | */ | 6191 | */ |
6170 | bf_set(abort_cmd_ia, &wqe->abort_cmd, 1); | 6192 | bf_set(abort_cmd_ia, &wqe->abort_cmd, 1); |
@@ -7895,7 +7917,7 @@ lpfc_sli_eratt_read(struct lpfc_hba *phba) | |||
7895 | /* Check if there is a deferred error condition is active */ | 7917 | /* Check if there is a deferred error condition is active */ |
7896 | if ((HS_FFER1 & phba->work_hs) && | 7918 | if ((HS_FFER1 & phba->work_hs) && |
7897 | ((HS_FFER2 | HS_FFER3 | HS_FFER4 | HS_FFER5 | | 7919 | ((HS_FFER2 | HS_FFER3 | HS_FFER4 | HS_FFER5 | |
7898 | HS_FFER6 | HS_FFER7) & phba->work_hs)) { | 7920 | HS_FFER6 | HS_FFER7 | HS_FFER8) & phba->work_hs)) { |
7899 | phba->hba_flag |= DEFER_ERATT; | 7921 | phba->hba_flag |= DEFER_ERATT; |
7900 | /* Clear all interrupt enable conditions */ | 7922 | /* Clear all interrupt enable conditions */ |
7901 | writel(0, phba->HCregaddr); | 7923 | writel(0, phba->HCregaddr); |
@@ -8211,7 +8233,8 @@ lpfc_sli_sp_intr_handler(int irq, void *dev_id) | |||
8211 | */ | 8233 | */ |
8212 | if ((HS_FFER1 & phba->work_hs) && | 8234 | if ((HS_FFER1 & phba->work_hs) && |
8213 | ((HS_FFER2 | HS_FFER3 | HS_FFER4 | HS_FFER5 | | 8235 | ((HS_FFER2 | HS_FFER3 | HS_FFER4 | HS_FFER5 | |
8214 | HS_FFER6 | HS_FFER7) & phba->work_hs)) { | 8236 | HS_FFER6 | HS_FFER7 | HS_FFER8) & |
8237 | phba->work_hs)) { | ||
8215 | phba->hba_flag |= DEFER_ERATT; | 8238 | phba->hba_flag |= DEFER_ERATT; |
8216 | /* Clear all interrupt enable conditions */ | 8239 | /* Clear all interrupt enable conditions */ |
8217 | writel(0, phba->HCregaddr); | 8240 | writel(0, phba->HCregaddr); |