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-rw-r--r--drivers/scsi/lpfc/lpfc_hw.h558
1 files changed, 489 insertions, 69 deletions
diff --git a/drivers/scsi/lpfc/lpfc_hw.h b/drivers/scsi/lpfc/lpfc_hw.h
index 2623a9bc7775..c2fb59f595f3 100644
--- a/drivers/scsi/lpfc/lpfc_hw.h
+++ b/drivers/scsi/lpfc/lpfc_hw.h
@@ -59,6 +59,12 @@
59#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 59#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 60#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
61 61
62#define SLI2_IOCB_CMD_SIZE 32
63#define SLI2_IOCB_RSP_SIZE 32
64#define SLI3_IOCB_CMD_SIZE 128
65#define SLI3_IOCB_RSP_SIZE 64
66
67
62/* Common Transport structures and definitions */ 68/* Common Transport structures and definitions */
63 69
64union CtRevisionId { 70union CtRevisionId {
@@ -79,6 +85,9 @@ union CtCommandResponse {
79 uint32_t word; 85 uint32_t word;
80}; 86};
81 87
88#define FC4_FEATURE_INIT 0x2
89#define FC4_FEATURE_TARGET 0x1
90
82struct lpfc_sli_ct_request { 91struct lpfc_sli_ct_request {
83 /* Structure is in Big Endian format */ 92 /* Structure is in Big Endian format */
84 union CtRevisionId RevisionId; 93 union CtRevisionId RevisionId;
@@ -121,20 +130,6 @@ struct lpfc_sli_ct_request {
121 130
122 uint32_t rsvd[7]; 131 uint32_t rsvd[7];
123 } rft; 132 } rft;
124 struct rff {
125 uint32_t PortId;
126 uint8_t reserved[2];
127#ifdef __BIG_ENDIAN_BITFIELD
128 uint8_t feature_res:6;
129 uint8_t feature_init:1;
130 uint8_t feature_tgt:1;
131#else /* __LITTLE_ENDIAN_BITFIELD */
132 uint8_t feature_tgt:1;
133 uint8_t feature_init:1;
134 uint8_t feature_res:6;
135#endif
136 uint8_t type_code; /* type=8 for FCP */
137 } rff;
138 struct rnn { 133 struct rnn {
139 uint32_t PortId; /* For RNN_ID requests */ 134 uint32_t PortId; /* For RNN_ID requests */
140 uint8_t wwnn[8]; 135 uint8_t wwnn[8];
@@ -144,15 +139,42 @@ struct lpfc_sli_ct_request {
144 uint8_t len; 139 uint8_t len;
145 uint8_t symbname[255]; 140 uint8_t symbname[255];
146 } rsnn; 141 } rsnn;
142 struct rspn { /* For RSPN_ID requests */
143 uint32_t PortId;
144 uint8_t len;
145 uint8_t symbname[255];
146 } rspn;
147 struct gff {
148 uint32_t PortId;
149 } gff;
150 struct gff_acc {
151 uint8_t fbits[128];
152 } gff_acc;
153#define FCP_TYPE_FEATURE_OFFSET 4
154 struct rff {
155 uint32_t PortId;
156 uint8_t reserved[2];
157 uint8_t fbits;
158 uint8_t type_code; /* type=8 for FCP */
159 } rff;
147 } un; 160 } un;
148}; 161};
149 162
150#define SLI_CT_REVISION 1 163#define SLI_CT_REVISION 1
151#define GID_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 260) 164#define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
152#define RFT_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 228) 165 sizeof(struct gid))
153#define RFF_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 235) 166#define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
154#define RNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 252) 167 sizeof(struct gff))
155#define RSNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request)) 168#define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
169 sizeof(struct rft))
170#define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
171 sizeof(struct rff))
172#define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
173 sizeof(struct rnn))
174#define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
175 sizeof(struct rsnn))
176#define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
177 sizeof(struct rspn))
156 178
157/* 179/*
158 * FsType Definitions 180 * FsType Definitions
@@ -227,6 +249,7 @@ struct lpfc_sli_ct_request {
227#define SLI_CTNS_GFT_ID 0x0117 249#define SLI_CTNS_GFT_ID 0x0117
228#define SLI_CTNS_GSPN_ID 0x0118 250#define SLI_CTNS_GSPN_ID 0x0118
229#define SLI_CTNS_GPT_ID 0x011A 251#define SLI_CTNS_GPT_ID 0x011A
252#define SLI_CTNS_GFF_ID 0x011F
230#define SLI_CTNS_GID_PN 0x0121 253#define SLI_CTNS_GID_PN 0x0121
231#define SLI_CTNS_GID_NN 0x0131 254#define SLI_CTNS_GID_NN 0x0131
232#define SLI_CTNS_GIP_NN 0x0135 255#define SLI_CTNS_GIP_NN 0x0135
@@ -240,9 +263,9 @@ struct lpfc_sli_ct_request {
240#define SLI_CTNS_RNN_ID 0x0213 263#define SLI_CTNS_RNN_ID 0x0213
241#define SLI_CTNS_RCS_ID 0x0214 264#define SLI_CTNS_RCS_ID 0x0214
242#define SLI_CTNS_RFT_ID 0x0217 265#define SLI_CTNS_RFT_ID 0x0217
243#define SLI_CTNS_RFF_ID 0x021F
244#define SLI_CTNS_RSPN_ID 0x0218 266#define SLI_CTNS_RSPN_ID 0x0218
245#define SLI_CTNS_RPT_ID 0x021A 267#define SLI_CTNS_RPT_ID 0x021A
268#define SLI_CTNS_RFF_ID 0x021F
246#define SLI_CTNS_RIP_NN 0x0235 269#define SLI_CTNS_RIP_NN 0x0235
247#define SLI_CTNS_RIPA_NN 0x0236 270#define SLI_CTNS_RIPA_NN 0x0236
248#define SLI_CTNS_RSNN_NN 0x0239 271#define SLI_CTNS_RSNN_NN 0x0239
@@ -311,9 +334,9 @@ struct csp {
311 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 334 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
312 335
313#ifdef __BIG_ENDIAN_BITFIELD 336#ifdef __BIG_ENDIAN_BITFIELD
314 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 337 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
315 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 338 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
316 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 339 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
317 uint16_t fPort:1; /* FC Word 1, bit 28 */ 340 uint16_t fPort:1; /* FC Word 1, bit 28 */
318 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 341 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
319 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 342 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
@@ -332,9 +355,9 @@ struct csp {
332 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 355 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
333 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 356 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
334 uint16_t fPort:1; /* FC Word 1, bit 28 */ 357 uint16_t fPort:1; /* FC Word 1, bit 28 */
335 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 358 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
336 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 359 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
337 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 360 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
338 361
339 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 362 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
340 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 363 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
@@ -1255,7 +1278,9 @@ typedef struct { /* FireFly BIU registers */
1255#define MBX_KILL_BOARD 0x24 1278#define MBX_KILL_BOARD 0x24
1256#define MBX_CONFIG_FARP 0x25 1279#define MBX_CONFIG_FARP 0x25
1257#define MBX_BEACON 0x2A 1280#define MBX_BEACON 0x2A
1281#define MBX_HEARTBEAT 0x31
1258 1282
1283#define MBX_CONFIG_HBQ 0x7C
1259#define MBX_LOAD_AREA 0x81 1284#define MBX_LOAD_AREA 0x81
1260#define MBX_RUN_BIU_DIAG64 0x84 1285#define MBX_RUN_BIU_DIAG64 0x84
1261#define MBX_CONFIG_PORT 0x88 1286#define MBX_CONFIG_PORT 0x88
@@ -1263,6 +1288,10 @@ typedef struct { /* FireFly BIU registers */
1263#define MBX_READ_RPI64 0x8F 1288#define MBX_READ_RPI64 0x8F
1264#define MBX_REG_LOGIN64 0x93 1289#define MBX_REG_LOGIN64 0x93
1265#define MBX_READ_LA64 0x95 1290#define MBX_READ_LA64 0x95
1291#define MBX_REG_VPI 0x96
1292#define MBX_UNREG_VPI 0x97
1293#define MBX_REG_VNPID 0x96
1294#define MBX_UNREG_VNPID 0x97
1266 1295
1267#define MBX_FLASH_WR_ULA 0x98 1296#define MBX_FLASH_WR_ULA 0x98
1268#define MBX_SET_DEBUG 0x99 1297#define MBX_SET_DEBUG 0x99
@@ -1335,6 +1364,10 @@ typedef struct { /* FireFly BIU registers */
1335#define CMD_FCP_TRECEIVE64_CX 0xA1 1364#define CMD_FCP_TRECEIVE64_CX 0xA1
1336#define CMD_FCP_TRSP64_CX 0xA3 1365#define CMD_FCP_TRSP64_CX 0xA3
1337 1366
1367#define CMD_IOCB_RCV_SEQ64_CX 0xB5
1368#define CMD_IOCB_RCV_ELS64_CX 0xB7
1369#define CMD_IOCB_RCV_CONT64_CX 0xBB
1370
1338#define CMD_GEN_REQUEST64_CR 0xC2 1371#define CMD_GEN_REQUEST64_CR 0xC2
1339#define CMD_GEN_REQUEST64_CX 0xC3 1372#define CMD_GEN_REQUEST64_CX 0xC3
1340 1373
@@ -1561,6 +1594,7 @@ typedef struct {
1561#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 1594#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1562#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 1595#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1563#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 1596#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
1597#define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
1564#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 1598#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1565 1599
1566#define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 1600#define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
@@ -1744,8 +1778,6 @@ typedef struct {
1744#define LMT_4Gb 0x040 1778#define LMT_4Gb 0x040
1745#define LMT_8Gb 0x080 1779#define LMT_8Gb 0x080
1746#define LMT_10Gb 0x100 1780#define LMT_10Gb 0x100
1747
1748
1749 uint32_t rsvd2; 1781 uint32_t rsvd2;
1750 uint32_t rsvd3; 1782 uint32_t rsvd3;
1751 uint32_t max_xri; 1783 uint32_t max_xri;
@@ -1754,7 +1786,10 @@ typedef struct {
1754 uint32_t avail_xri; 1786 uint32_t avail_xri;
1755 uint32_t avail_iocb; 1787 uint32_t avail_iocb;
1756 uint32_t avail_rpi; 1788 uint32_t avail_rpi;
1757 uint32_t default_rpi; 1789 uint32_t max_vpi;
1790 uint32_t rsvd4;
1791 uint32_t rsvd5;
1792 uint32_t avail_vpi;
1758} READ_CONFIG_VAR; 1793} READ_CONFIG_VAR;
1759 1794
1760/* Structure for MB Command READ_RCONFIG (12) */ 1795/* Structure for MB Command READ_RCONFIG (12) */
@@ -1818,6 +1853,13 @@ typedef struct {
1818 structure */ 1853 structure */
1819 struct ulp_bde64 sp64; 1854 struct ulp_bde64 sp64;
1820 } un; 1855 } un;
1856#ifdef __BIG_ENDIAN_BITFIELD
1857 uint16_t rsvd3;
1858 uint16_t vpi;
1859#else /* __LITTLE_ENDIAN_BITFIELD */
1860 uint16_t vpi;
1861 uint16_t rsvd3;
1862#endif
1821} READ_SPARM_VAR; 1863} READ_SPARM_VAR;
1822 1864
1823/* Structure for MB Command READ_STATUS (14) */ 1865/* Structure for MB Command READ_STATUS (14) */
@@ -1918,11 +1960,17 @@ typedef struct {
1918#ifdef __BIG_ENDIAN_BITFIELD 1960#ifdef __BIG_ENDIAN_BITFIELD
1919 uint32_t cv:1; 1961 uint32_t cv:1;
1920 uint32_t rr:1; 1962 uint32_t rr:1;
1921 uint32_t rsvd1:29; 1963 uint32_t rsvd2:2;
1964 uint32_t v3req:1;
1965 uint32_t v3rsp:1;
1966 uint32_t rsvd1:25;
1922 uint32_t rv:1; 1967 uint32_t rv:1;
1923#else /* __LITTLE_ENDIAN_BITFIELD */ 1968#else /* __LITTLE_ENDIAN_BITFIELD */
1924 uint32_t rv:1; 1969 uint32_t rv:1;
1925 uint32_t rsvd1:29; 1970 uint32_t rsvd1:25;
1971 uint32_t v3rsp:1;
1972 uint32_t v3req:1;
1973 uint32_t rsvd2:2;
1926 uint32_t rr:1; 1974 uint32_t rr:1;
1927 uint32_t cv:1; 1975 uint32_t cv:1;
1928#endif 1976#endif
@@ -1972,8 +2020,8 @@ typedef struct {
1972 uint8_t sli1FwName[16]; 2020 uint8_t sli1FwName[16];
1973 uint32_t sli2FwRev; 2021 uint32_t sli2FwRev;
1974 uint8_t sli2FwName[16]; 2022 uint8_t sli2FwName[16];
1975 uint32_t rsvd2; 2023 uint32_t sli3Feat;
1976 uint32_t RandomData[7]; 2024 uint32_t RandomData[6];
1977} READ_REV_VAR; 2025} READ_REV_VAR;
1978 2026
1979/* Structure for MB Command READ_LINK_STAT (18) */ 2027/* Structure for MB Command READ_LINK_STAT (18) */
@@ -2013,6 +2061,14 @@ typedef struct {
2013 struct ulp_bde64 sp64; 2061 struct ulp_bde64 sp64;
2014 } un; 2062 } un;
2015 2063
2064#ifdef __BIG_ENDIAN_BITFIELD
2065 uint16_t rsvd6;
2066 uint16_t vpi;
2067#else /* __LITTLE_ENDIAN_BITFIELD */
2068 uint16_t vpi;
2069 uint16_t rsvd6;
2070#endif
2071
2016} REG_LOGIN_VAR; 2072} REG_LOGIN_VAR;
2017 2073
2018/* Word 30 contents for REG_LOGIN */ 2074/* Word 30 contents for REG_LOGIN */
@@ -2037,16 +2093,78 @@ typedef struct {
2037#ifdef __BIG_ENDIAN_BITFIELD 2093#ifdef __BIG_ENDIAN_BITFIELD
2038 uint16_t rsvd1; 2094 uint16_t rsvd1;
2039 uint16_t rpi; 2095 uint16_t rpi;
2096 uint32_t rsvd2;
2097 uint32_t rsvd3;
2098 uint32_t rsvd4;
2099 uint32_t rsvd5;
2100 uint16_t rsvd6;
2101 uint16_t vpi;
2040#else /* __LITTLE_ENDIAN_BITFIELD */ 2102#else /* __LITTLE_ENDIAN_BITFIELD */
2041 uint16_t rpi; 2103 uint16_t rpi;
2042 uint16_t rsvd1; 2104 uint16_t rsvd1;
2105 uint32_t rsvd2;
2106 uint32_t rsvd3;
2107 uint32_t rsvd4;
2108 uint32_t rsvd5;
2109 uint16_t vpi;
2110 uint16_t rsvd6;
2043#endif 2111#endif
2044} UNREG_LOGIN_VAR; 2112} UNREG_LOGIN_VAR;
2045 2113
2114/* Structure for MB Command REG_VPI (0x96) */
2115typedef struct {
2116#ifdef __BIG_ENDIAN_BITFIELD
2117 uint32_t rsvd1;
2118 uint32_t rsvd2:8;
2119 uint32_t sid:24;
2120 uint32_t rsvd3;
2121 uint32_t rsvd4;
2122 uint32_t rsvd5;
2123 uint16_t rsvd6;
2124 uint16_t vpi;
2125#else /* __LITTLE_ENDIAN */
2126 uint32_t rsvd1;
2127 uint32_t sid:24;
2128 uint32_t rsvd2:8;
2129 uint32_t rsvd3;
2130 uint32_t rsvd4;
2131 uint32_t rsvd5;
2132 uint16_t vpi;
2133 uint16_t rsvd6;
2134#endif
2135} REG_VPI_VAR;
2136
2137/* Structure for MB Command UNREG_VPI (0x97) */
2138typedef struct {
2139 uint32_t rsvd1;
2140 uint32_t rsvd2;
2141 uint32_t rsvd3;
2142 uint32_t rsvd4;
2143 uint32_t rsvd5;
2144#ifdef __BIG_ENDIAN_BITFIELD
2145 uint16_t rsvd6;
2146 uint16_t vpi;
2147#else /* __LITTLE_ENDIAN */
2148 uint16_t vpi;
2149 uint16_t rsvd6;
2150#endif
2151} UNREG_VPI_VAR;
2152
2046/* Structure for MB Command UNREG_D_ID (0x23) */ 2153/* Structure for MB Command UNREG_D_ID (0x23) */
2047 2154
2048typedef struct { 2155typedef struct {
2049 uint32_t did; 2156 uint32_t did;
2157 uint32_t rsvd2;
2158 uint32_t rsvd3;
2159 uint32_t rsvd4;
2160 uint32_t rsvd5;
2161#ifdef __BIG_ENDIAN_BITFIELD
2162 uint16_t rsvd6;
2163 uint16_t vpi;
2164#else
2165 uint16_t vpi;
2166 uint16_t rsvd6;
2167#endif
2050} UNREG_D_ID_VAR; 2168} UNREG_D_ID_VAR;
2051 2169
2052/* Structure for MB Command READ_LA (21) */ 2170/* Structure for MB Command READ_LA (21) */
@@ -2178,13 +2296,240 @@ typedef struct {
2178#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2296#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2179#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2297#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2180 2298
2181/* Structure for MB Command CONFIG_PORT (0x88) */ 2299struct hbq_mask {
2300#ifdef __BIG_ENDIAN_BITFIELD
2301 uint8_t tmatch;
2302 uint8_t tmask;
2303 uint8_t rctlmatch;
2304 uint8_t rctlmask;
2305#else /* __LITTLE_ENDIAN */
2306 uint8_t rctlmask;
2307 uint8_t rctlmatch;
2308 uint8_t tmask;
2309 uint8_t tmatch;
2310#endif
2311};
2312
2313
2314/* Structure for MB Command CONFIG_HBQ (7c) */
2315
2316struct config_hbq_var {
2317#ifdef __BIG_ENDIAN_BITFIELD
2318 uint32_t rsvd1 :7;
2319 uint32_t recvNotify :1; /* Receive Notification */
2320 uint32_t numMask :8; /* # Mask Entries */
2321 uint32_t profile :8; /* Selection Profile */
2322 uint32_t rsvd2 :8;
2323#else /* __LITTLE_ENDIAN */
2324 uint32_t rsvd2 :8;
2325 uint32_t profile :8; /* Selection Profile */
2326 uint32_t numMask :8; /* # Mask Entries */
2327 uint32_t recvNotify :1; /* Receive Notification */
2328 uint32_t rsvd1 :7;
2329#endif
2330
2331#ifdef __BIG_ENDIAN_BITFIELD
2332 uint32_t hbqId :16;
2333 uint32_t rsvd3 :12;
2334 uint32_t ringMask :4;
2335#else /* __LITTLE_ENDIAN */
2336 uint32_t ringMask :4;
2337 uint32_t rsvd3 :12;
2338 uint32_t hbqId :16;
2339#endif
2340
2341#ifdef __BIG_ENDIAN_BITFIELD
2342 uint32_t entry_count :16;
2343 uint32_t rsvd4 :8;
2344 uint32_t headerLen :8;
2345#else /* __LITTLE_ENDIAN */
2346 uint32_t headerLen :8;
2347 uint32_t rsvd4 :8;
2348 uint32_t entry_count :16;
2349#endif
2350
2351 uint32_t hbqaddrLow;
2352 uint32_t hbqaddrHigh;
2353
2354#ifdef __BIG_ENDIAN_BITFIELD
2355 uint32_t rsvd5 :31;
2356 uint32_t logEntry :1;
2357#else /* __LITTLE_ENDIAN */
2358 uint32_t logEntry :1;
2359 uint32_t rsvd5 :31;
2360#endif
2361
2362 uint32_t rsvd6; /* w7 */
2363 uint32_t rsvd7; /* w8 */
2364 uint32_t rsvd8; /* w9 */
2365
2366 struct hbq_mask hbqMasks[6];
2367
2368
2369 union {
2370 uint32_t allprofiles[12];
2371
2372 struct {
2373 #ifdef __BIG_ENDIAN_BITFIELD
2374 uint32_t seqlenoff :16;
2375 uint32_t maxlen :16;
2376 #else /* __LITTLE_ENDIAN */
2377 uint32_t maxlen :16;
2378 uint32_t seqlenoff :16;
2379 #endif
2380 #ifdef __BIG_ENDIAN_BITFIELD
2381 uint32_t rsvd1 :28;
2382 uint32_t seqlenbcnt :4;
2383 #else /* __LITTLE_ENDIAN */
2384 uint32_t seqlenbcnt :4;
2385 uint32_t rsvd1 :28;
2386 #endif
2387 uint32_t rsvd[10];
2388 } profile2;
2389
2390 struct {
2391 #ifdef __BIG_ENDIAN_BITFIELD
2392 uint32_t seqlenoff :16;
2393 uint32_t maxlen :16;
2394 #else /* __LITTLE_ENDIAN */
2395 uint32_t maxlen :16;
2396 uint32_t seqlenoff :16;
2397 #endif
2398 #ifdef __BIG_ENDIAN_BITFIELD
2399 uint32_t cmdcodeoff :28;
2400 uint32_t rsvd1 :12;
2401 uint32_t seqlenbcnt :4;
2402 #else /* __LITTLE_ENDIAN */
2403 uint32_t seqlenbcnt :4;
2404 uint32_t rsvd1 :12;
2405 uint32_t cmdcodeoff :28;
2406 #endif
2407 uint32_t cmdmatch[8];
2408
2409 uint32_t rsvd[2];
2410 } profile3;
2411
2412 struct {
2413 #ifdef __BIG_ENDIAN_BITFIELD
2414 uint32_t seqlenoff :16;
2415 uint32_t maxlen :16;
2416 #else /* __LITTLE_ENDIAN */
2417 uint32_t maxlen :16;
2418 uint32_t seqlenoff :16;
2419 #endif
2420 #ifdef __BIG_ENDIAN_BITFIELD
2421 uint32_t cmdcodeoff :28;
2422 uint32_t rsvd1 :12;
2423 uint32_t seqlenbcnt :4;
2424 #else /* __LITTLE_ENDIAN */
2425 uint32_t seqlenbcnt :4;
2426 uint32_t rsvd1 :12;
2427 uint32_t cmdcodeoff :28;
2428 #endif
2429 uint32_t cmdmatch[8];
2430
2431 uint32_t rsvd[2];
2432 } profile5;
2433
2434 } profiles;
2182 2435
2436};
2437
2438
2439
2440/* Structure for MB Command CONFIG_PORT (0x88) */
2183typedef struct { 2441typedef struct {
2184 uint32_t pcbLen; 2442#ifdef __BIG_ENDIAN_BITFIELD
2443 uint32_t cBE : 1;
2444 uint32_t cET : 1;
2445 uint32_t cHpcb : 1;
2446 uint32_t cMA : 1;
2447 uint32_t sli_mode : 4;
2448 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2449 * config block */
2450#else /* __LITTLE_ENDIAN */
2451 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2452 * config block */
2453 uint32_t sli_mode : 4;
2454 uint32_t cMA : 1;
2455 uint32_t cHpcb : 1;
2456 uint32_t cET : 1;
2457 uint32_t cBE : 1;
2458#endif
2459
2185 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 2460 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2186 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 2461 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
2187 uint32_t hbainit[5]; 2462 uint32_t hbainit[6];
2463
2464#ifdef __BIG_ENDIAN_BITFIELD
2465 uint32_t rsvd : 24; /* Reserved */
2466 uint32_t cmv : 1; /* Configure Max VPIs */
2467 uint32_t ccrp : 1; /* Config Command Ring Polling */
2468 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2469 uint32_t chbs : 1; /* Cofigure Host Backing store */
2470 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2471 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2472 uint32_t cmx : 1; /* Configure Max XRIs */
2473 uint32_t cmr : 1; /* Configure Max RPIs */
2474#else /* __LITTLE_ENDIAN */
2475 uint32_t cmr : 1; /* Configure Max RPIs */
2476 uint32_t cmx : 1; /* Configure Max XRIs */
2477 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2478 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2479 uint32_t chbs : 1; /* Cofigure Host Backing store */
2480 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2481 uint32_t ccrp : 1; /* Config Command Ring Polling */
2482 uint32_t cmv : 1; /* Configure Max VPIs */
2483 uint32_t rsvd : 24; /* Reserved */
2484#endif
2485#ifdef __BIG_ENDIAN_BITFIELD
2486 uint32_t rsvd2 : 24; /* Reserved */
2487 uint32_t gmv : 1; /* Grant Max VPIs */
2488 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2489 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2490 uint32_t ghbs : 1; /* Grant Host Backing Store */
2491 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2492 uint32_t gerbm : 1; /* Grant ERBM Request */
2493 uint32_t gmx : 1; /* Grant Max XRIs */
2494 uint32_t gmr : 1; /* Grant Max RPIs */
2495#else /* __LITTLE_ENDIAN */
2496 uint32_t gmr : 1; /* Grant Max RPIs */
2497 uint32_t gmx : 1; /* Grant Max XRIs */
2498 uint32_t gerbm : 1; /* Grant ERBM Request */
2499 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2500 uint32_t ghbs : 1; /* Grant Host Backing Store */
2501 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2502 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2503 uint32_t gmv : 1; /* Grant Max VPIs */
2504 uint32_t rsvd2 : 24; /* Reserved */
2505#endif
2506
2507#ifdef __BIG_ENDIAN_BITFIELD
2508 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2509 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2510#else /* __LITTLE_ENDIAN */
2511 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2512 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2513#endif
2514
2515#ifdef __BIG_ENDIAN_BITFIELD
2516 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2517 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */
2518#else /* __LITTLE_ENDIAN */
2519 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */
2520 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2521#endif
2522
2523 uint32_t rsvd4; /* Reserved */
2524
2525#ifdef __BIG_ENDIAN_BITFIELD
2526 uint32_t rsvd5 : 16; /* Reserved */
2527 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2528#else /* __LITTLE_ENDIAN */
2529 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2530 uint32_t rsvd5 : 16; /* Reserved */
2531#endif
2532
2188} CONFIG_PORT_VAR; 2533} CONFIG_PORT_VAR;
2189 2534
2190/* SLI-2 Port Control Block */ 2535/* SLI-2 Port Control Block */
@@ -2262,33 +2607,40 @@ typedef struct {
2262#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 2607#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2263 2608
2264typedef union { 2609typedef union {
2265 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; 2610 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
2266 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 2611 * feature/max ring number
2267 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 2612 */
2268 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 2613 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2269 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 2614 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2270 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 2615 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
2616 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2617 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
2271 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 2618 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
2272 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 2619 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2273 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 2620 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
2274 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 2621 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2275 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 2622 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2276 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 2623 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2277 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 2624 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2278 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 2625 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2279 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 2626 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
2280 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 2627 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2281 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 2628 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2282 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 2629 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2283 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 2630 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
2284 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 2631 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2285 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 2632 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
2286 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */ 2633 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
2287 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 2634 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
2288 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 2635 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2289 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 2636 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2290 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) NEW_FEATURE */ 2637 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
2291 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 2638 * NEW_FEATURE
2639 */
2640 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
2641 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
2642 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
2643 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
2292} MAILVARIANTS; 2644} MAILVARIANTS;
2293 2645
2294/* 2646/*
@@ -2305,14 +2657,27 @@ struct lpfc_pgp {
2305 __le32 rspPutInx; 2657 __le32 rspPutInx;
2306}; 2658};
2307 2659
2308typedef struct _SLI2_DESC { 2660struct sli2_desc {
2309 struct lpfc_hgp host[MAX_RINGS];
2310 uint32_t unused1[16]; 2661 uint32_t unused1[16];
2662 struct lpfc_hgp host[MAX_RINGS];
2663 struct lpfc_pgp port[MAX_RINGS];
2664};
2665
2666struct sli3_desc {
2667 struct lpfc_hgp host[MAX_RINGS];
2668 uint32_t reserved[8];
2669 uint32_t hbq_put[16];
2670};
2671
2672struct sli3_pgp {
2311 struct lpfc_pgp port[MAX_RINGS]; 2673 struct lpfc_pgp port[MAX_RINGS];
2312} SLI2_DESC; 2674 uint32_t hbq_get[16];
2675};
2313 2676
2314typedef union { 2677typedef union {
2315 SLI2_DESC s2; 2678 struct sli2_desc s2;
2679 struct sli3_desc s3;
2680 struct sli3_pgp s3_pgp;
2316} SLI_VAR; 2681} SLI_VAR;
2317 2682
2318typedef struct { 2683typedef struct {
@@ -2618,6 +2983,25 @@ typedef struct {
2618 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 2983 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2619} FCPT_FIELDS64; 2984} FCPT_FIELDS64;
2620 2985
2986/* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
2987 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
2988
2989struct rcv_sli3 {
2990 uint32_t word8Rsvd;
2991#ifdef __BIG_ENDIAN_BITFIELD
2992 uint16_t vpi;
2993 uint16_t word9Rsvd;
2994#else /* __LITTLE_ENDIAN */
2995 uint16_t word9Rsvd;
2996 uint16_t vpi;
2997#endif
2998 uint32_t word10Rsvd;
2999 uint32_t acc_len; /* accumulated length */
3000 struct ulp_bde64 bde2;
3001};
3002
3003
3004
2621typedef struct _IOCB { /* IOCB structure */ 3005typedef struct _IOCB { /* IOCB structure */
2622 union { 3006 union {
2623 GENERIC_RSP grsp; /* Generic response */ 3007 GENERIC_RSP grsp; /* Generic response */
@@ -2632,8 +3016,8 @@ typedef struct _IOCB { /* IOCB structure */
2632 3016
2633 /* SLI-2 structures */ 3017 /* SLI-2 structures */
2634 3018
2635 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 3019 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
2636 bde_64s */ 3020 * bde_64s */
2637 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 3021 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
2638 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 3022 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
2639 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 3023 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
@@ -2695,9 +3079,20 @@ typedef struct _IOCB { /* IOCB structure */
2695 uint32_t ulpTimeout:8; 3079 uint32_t ulpTimeout:8;
2696#endif 3080#endif
2697 3081
3082 union {
3083 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3084 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3085 } unsli3;
3086
3087#define ulpCt_h ulpXS
3088#define ulpCt_l ulpFCP2Rcvy
3089
3090#define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3091#define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
2698#define PARM_UNUSED 0 /* PU field (Word 4) not used */ 3092#define PARM_UNUSED 0 /* PU field (Word 4) not used */
2699#define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 3093#define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
2700#define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 3094#define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
3095#define PARM_NPIV_DID 3
2701#define CLASS1 0 /* Class 1 */ 3096#define CLASS1 0 /* Class 1 */
2702#define CLASS2 1 /* Class 2 */ 3097#define CLASS2 1 /* Class 2 */
2703#define CLASS3 2 /* Class 3 */ 3098#define CLASS3 2 /* Class 3 */
@@ -2718,39 +3113,51 @@ typedef struct _IOCB { /* IOCB structure */
2718#define IOSTAT_RSVD2 0xC 3113#define IOSTAT_RSVD2 0xC
2719#define IOSTAT_RSVD3 0xD 3114#define IOSTAT_RSVD3 0xD
2720#define IOSTAT_RSVD4 0xE 3115#define IOSTAT_RSVD4 0xE
2721#define IOSTAT_RSVD5 0xF 3116#define IOSTAT_NEED_BUFFER 0xF
2722#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 3117#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
2723#define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 3118#define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
2724#define IOSTAT_CNT 0x11 3119#define IOSTAT_CNT 0x11
2725 3120
2726} IOCB_t; 3121} IOCB_t;
2727 3122
3123/* Structure used for a single HBQ entry */
3124struct lpfc_hbq_entry {
3125 struct ulp_bde64 bde;
3126 uint32_t buffer_tag;
3127};
3128
2728 3129
2729#define SLI1_SLIM_SIZE (4 * 1024) 3130#define SLI1_SLIM_SIZE (4 * 1024)
2730 3131
2731/* Up to 498 IOCBs will fit into 16k 3132/* Up to 498 IOCBs will fit into 16k
2732 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 3133 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
2733 */ 3134 */
2734#define SLI2_SLIM_SIZE (16 * 1024) 3135#define SLI2_SLIM_SIZE (64 * 1024)
2735 3136
2736/* Maximum IOCBs that will fit in SLI2 slim */ 3137/* Maximum IOCBs that will fit in SLI2 slim */
2737#define MAX_SLI2_IOCB 498 3138#define MAX_SLI2_IOCB 498
3139#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3140 (sizeof(MAILBOX_t) + sizeof(PCB_t)))
3141
3142/* HBQ entries are 4 words each = 4k */
3143#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3144 lpfc_sli_hbq_count())
2738 3145
2739struct lpfc_sli2_slim { 3146struct lpfc_sli2_slim {
2740 MAILBOX_t mbx; 3147 MAILBOX_t mbx;
2741 PCB_t pcb; 3148 PCB_t pcb;
2742 IOCB_t IOCBs[MAX_SLI2_IOCB]; 3149 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
2743}; 3150};
2744 3151
2745/******************************************************************* 3152/*
2746This macro check PCI device to allow special handling for LC HBAs. 3153 * This function checks PCI device to allow special handling for LC HBAs.
2747 3154 *
2748Parameters: 3155 * Parameters:
2749device : struct pci_dev 's device field 3156 * device : struct pci_dev 's device field
2750 3157 *
2751return 1 => TRUE 3158 * return 1 => TRUE
2752 0 => FALSE 3159 * 0 => FALSE
2753 *******************************************************************/ 3160 */
2754static inline int 3161static inline int
2755lpfc_is_LC_HBA(unsigned short device) 3162lpfc_is_LC_HBA(unsigned short device)
2756{ 3163{
@@ -2766,3 +3173,16 @@ lpfc_is_LC_HBA(unsigned short device)
2766 else 3173 else
2767 return 0; 3174 return 0;
2768} 3175}
3176
3177/*
3178 * Determine if an IOCB failed because of a link event or firmware reset.
3179 */
3180
3181static inline int
3182lpfc_error_lost_link(IOCB_t *iocbp)
3183{
3184 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3185 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3186 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3187 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
3188}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-15 18:44:43 -0500