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Diffstat (limited to 'drivers/scsi/ips.c')
-rw-r--r--drivers/scsi/ips.c326
1 files changed, 154 insertions, 172 deletions
diff --git a/drivers/scsi/ips.c b/drivers/scsi/ips.c
index 5c5a9b2628fc..7505cca8e68e 100644
--- a/drivers/scsi/ips.c
+++ b/drivers/scsi/ips.c
@@ -389,17 +389,17 @@ static struct pci_device_id ips_pci_table[] = {
389MODULE_DEVICE_TABLE( pci, ips_pci_table ); 389MODULE_DEVICE_TABLE( pci, ips_pci_table );
390 390
391static char ips_hot_plug_name[] = "ips"; 391static char ips_hot_plug_name[] = "ips";
392 392
393static int __devinit ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent); 393static int __devinit ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
394static void __devexit ips_remove_device(struct pci_dev *pci_dev); 394static void __devexit ips_remove_device(struct pci_dev *pci_dev);
395 395
396static struct pci_driver ips_pci_driver = { 396static struct pci_driver ips_pci_driver = {
397 .name = ips_hot_plug_name, 397 .name = ips_hot_plug_name,
398 .id_table = ips_pci_table, 398 .id_table = ips_pci_table,
399 .probe = ips_insert_device, 399 .probe = ips_insert_device,
400 .remove = __devexit_p(ips_remove_device), 400 .remove = __devexit_p(ips_remove_device),
401}; 401};
402 402
403 403
404/* 404/*
405 * Necessary forward function protoypes 405 * Necessary forward function protoypes
@@ -587,7 +587,7 @@ static void
587ips_setup_funclist(ips_ha_t * ha) 587ips_setup_funclist(ips_ha_t * ha)
588{ 588{
589 589
590 /* 590 /*
591 * Setup Functions 591 * Setup Functions
592 */ 592 */
593 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) { 593 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
@@ -702,12 +702,8 @@ ips_release(struct Scsi_Host *sh)
702 /* free extra memory */ 702 /* free extra memory */
703 ips_free(ha); 703 ips_free(ha);
704 704
705 /* Free I/O Region */
706 if (ha->io_addr)
707 release_region(ha->io_addr, ha->io_len);
708
709 /* free IRQ */ 705 /* free IRQ */
710 free_irq(ha->irq, ha); 706 free_irq(ha->pcidev->irq, ha);
711 707
712 scsi_host_put(sh); 708 scsi_host_put(sh);
713 709
@@ -1637,7 +1633,7 @@ ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr)
1637 return (IPS_FAILURE); 1633 return (IPS_FAILURE);
1638 } 1634 }
1639 1635
1640 if (ha->device_id == IPS_DEVICEID_COPPERHEAD && 1636 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
1641 pt->CoppCP.cmd.flashfw.op_code == 1637 pt->CoppCP.cmd.flashfw.op_code ==
1642 IPS_CMD_RW_BIOSFW) { 1638 IPS_CMD_RW_BIOSFW) {
1643 ret = ips_flash_copperhead(ha, pt, scb); 1639 ret = ips_flash_copperhead(ha, pt, scb);
@@ -2021,7 +2017,7 @@ ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
2021 pt->ExtendedStatus = scb->extended_status; 2017 pt->ExtendedStatus = scb->extended_status;
2022 pt->AdapterType = ha->ad_type; 2018 pt->AdapterType = ha->ad_type;
2023 2019
2024 if (ha->device_id == IPS_DEVICEID_COPPERHEAD && 2020 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
2025 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD || 2021 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2026 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW)) 2022 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2027 ips_free_flash_copperhead(ha); 2023 ips_free_flash_copperhead(ha);
@@ -2075,13 +2071,13 @@ ips_host_info(ips_ha_t * ha, char *ptr, off_t offset, int len)
2075 ha->mem_ptr); 2071 ha->mem_ptr);
2076 } 2072 }
2077 2073
2078 copy_info(&info, "\tIRQ number : %d\n", ha->irq); 2074 copy_info(&info, "\tIRQ number : %d\n", ha->pcidev->irq);
2079 2075
2080 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */ 2076 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2081 /* That keeps everything happy for "text" operations on the proc file. */ 2077 /* That keeps everything happy for "text" operations on the proc file. */
2082 2078
2083 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) { 2079 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2084 if (ha->nvram->bios_low[3] == 0) { 2080 if (ha->nvram->bios_low[3] == 0) {
2085 copy_info(&info, 2081 copy_info(&info,
2086 "\tBIOS Version : %c%c%c%c%c%c%c\n", 2082 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2087 ha->nvram->bios_high[0], ha->nvram->bios_high[1], 2083 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
@@ -2232,31 +2228,31 @@ ips_identify_controller(ips_ha_t * ha)
2232{ 2228{
2233 METHOD_TRACE("ips_identify_controller", 1); 2229 METHOD_TRACE("ips_identify_controller", 1);
2234 2230
2235 switch (ha->device_id) { 2231 switch (ha->pcidev->device) {
2236 case IPS_DEVICEID_COPPERHEAD: 2232 case IPS_DEVICEID_COPPERHEAD:
2237 if (ha->revision_id <= IPS_REVID_SERVERAID) { 2233 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) {
2238 ha->ad_type = IPS_ADTYPE_SERVERAID; 2234 ha->ad_type = IPS_ADTYPE_SERVERAID;
2239 } else if (ha->revision_id == IPS_REVID_SERVERAID2) { 2235 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) {
2240 ha->ad_type = IPS_ADTYPE_SERVERAID2; 2236 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2241 } else if (ha->revision_id == IPS_REVID_NAVAJO) { 2237 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) {
2242 ha->ad_type = IPS_ADTYPE_NAVAJO; 2238 ha->ad_type = IPS_ADTYPE_NAVAJO;
2243 } else if ((ha->revision_id == IPS_REVID_SERVERAID2) 2239 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2)
2244 && (ha->slot_num == 0)) { 2240 && (ha->slot_num == 0)) {
2245 ha->ad_type = IPS_ADTYPE_KIOWA; 2241 ha->ad_type = IPS_ADTYPE_KIOWA;
2246 } else if ((ha->revision_id >= IPS_REVID_CLARINETP1) && 2242 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) &&
2247 (ha->revision_id <= IPS_REVID_CLARINETP3)) { 2243 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) {
2248 if (ha->enq->ucMaxPhysicalDevices == 15) 2244 if (ha->enq->ucMaxPhysicalDevices == 15)
2249 ha->ad_type = IPS_ADTYPE_SERVERAID3L; 2245 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2250 else 2246 else
2251 ha->ad_type = IPS_ADTYPE_SERVERAID3; 2247 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2252 } else if ((ha->revision_id >= IPS_REVID_TROMBONE32) && 2248 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) &&
2253 (ha->revision_id <= IPS_REVID_TROMBONE64)) { 2249 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) {
2254 ha->ad_type = IPS_ADTYPE_SERVERAID4H; 2250 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2255 } 2251 }
2256 break; 2252 break;
2257 2253
2258 case IPS_DEVICEID_MORPHEUS: 2254 case IPS_DEVICEID_MORPHEUS:
2259 switch (ha->subdevice_id) { 2255 switch (ha->pcidev->subsystem_device) {
2260 case IPS_SUBDEVICEID_4L: 2256 case IPS_SUBDEVICEID_4L:
2261 ha->ad_type = IPS_ADTYPE_SERVERAID4L; 2257 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2262 break; 2258 break;
@@ -2285,7 +2281,7 @@ ips_identify_controller(ips_ha_t * ha)
2285 break; 2281 break;
2286 2282
2287 case IPS_DEVICEID_MARCO: 2283 case IPS_DEVICEID_MARCO:
2288 switch (ha->subdevice_id) { 2284 switch (ha->pcidev->subsystem_device) {
2289 case IPS_SUBDEVICEID_6M: 2285 case IPS_SUBDEVICEID_6M:
2290 ha->ad_type = IPS_ADTYPE_SERVERAID6M; 2286 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2291 break; 2287 break;
@@ -2332,20 +2328,20 @@ ips_get_bios_version(ips_ha_t * ha, int intr)
2332 2328
2333 strncpy(ha->bios_version, " ?", 8); 2329 strncpy(ha->bios_version, " ?", 8);
2334 2330
2335 if (ha->device_id == IPS_DEVICEID_COPPERHEAD) { 2331 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) {
2336 if (IPS_USE_MEMIO(ha)) { 2332 if (IPS_USE_MEMIO(ha)) {
2337 /* Memory Mapped I/O */ 2333 /* Memory Mapped I/O */
2338 2334
2339 /* test 1st byte */ 2335 /* test 1st byte */
2340 writel(0, ha->mem_ptr + IPS_REG_FLAP); 2336 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2341 if (ha->revision_id == IPS_REVID_TROMBONE64) 2337 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2342 udelay(25); /* 25 us */ 2338 udelay(25); /* 25 us */
2343 2339
2344 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) 2340 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2345 return; 2341 return;
2346 2342
2347 writel(1, ha->mem_ptr + IPS_REG_FLAP); 2343 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2348 if (ha->revision_id == IPS_REVID_TROMBONE64) 2344 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2349 udelay(25); /* 25 us */ 2345 udelay(25); /* 25 us */
2350 2346
2351 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) 2347 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
@@ -2353,20 +2349,20 @@ ips_get_bios_version(ips_ha_t * ha, int intr)
2353 2349
2354 /* Get Major version */ 2350 /* Get Major version */
2355 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP); 2351 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2356 if (ha->revision_id == IPS_REVID_TROMBONE64) 2352 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2357 udelay(25); /* 25 us */ 2353 udelay(25); /* 25 us */
2358 2354
2359 major = readb(ha->mem_ptr + IPS_REG_FLDP); 2355 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2360 2356
2361 /* Get Minor version */ 2357 /* Get Minor version */
2362 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP); 2358 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2363 if (ha->revision_id == IPS_REVID_TROMBONE64) 2359 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2364 udelay(25); /* 25 us */ 2360 udelay(25); /* 25 us */
2365 minor = readb(ha->mem_ptr + IPS_REG_FLDP); 2361 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2366 2362
2367 /* Get SubMinor version */ 2363 /* Get SubMinor version */
2368 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP); 2364 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2369 if (ha->revision_id == IPS_REVID_TROMBONE64) 2365 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2370 udelay(25); /* 25 us */ 2366 udelay(25); /* 25 us */
2371 subminor = readb(ha->mem_ptr + IPS_REG_FLDP); 2367 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2372 2368
@@ -2375,14 +2371,14 @@ ips_get_bios_version(ips_ha_t * ha, int intr)
2375 2371
2376 /* test 1st byte */ 2372 /* test 1st byte */
2377 outl(0, ha->io_addr + IPS_REG_FLAP); 2373 outl(0, ha->io_addr + IPS_REG_FLAP);
2378 if (ha->revision_id == IPS_REVID_TROMBONE64) 2374 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2379 udelay(25); /* 25 us */ 2375 udelay(25); /* 25 us */
2380 2376
2381 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) 2377 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2382 return; 2378 return;
2383 2379
2384 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP); 2380 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
2385 if (ha->revision_id == IPS_REVID_TROMBONE64) 2381 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2386 udelay(25); /* 25 us */ 2382 udelay(25); /* 25 us */
2387 2383
2388 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) 2384 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
@@ -2390,21 +2386,21 @@ ips_get_bios_version(ips_ha_t * ha, int intr)
2390 2386
2391 /* Get Major version */ 2387 /* Get Major version */
2392 outl(cpu_to_le32(0x1FF), ha->io_addr + IPS_REG_FLAP); 2388 outl(cpu_to_le32(0x1FF), ha->io_addr + IPS_REG_FLAP);
2393 if (ha->revision_id == IPS_REVID_TROMBONE64) 2389 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2394 udelay(25); /* 25 us */ 2390 udelay(25); /* 25 us */
2395 2391
2396 major = inb(ha->io_addr + IPS_REG_FLDP); 2392 major = inb(ha->io_addr + IPS_REG_FLDP);
2397 2393
2398 /* Get Minor version */ 2394 /* Get Minor version */
2399 outl(cpu_to_le32(0x1FE), ha->io_addr + IPS_REG_FLAP); 2395 outl(cpu_to_le32(0x1FE), ha->io_addr + IPS_REG_FLAP);
2400 if (ha->revision_id == IPS_REVID_TROMBONE64) 2396 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2401 udelay(25); /* 25 us */ 2397 udelay(25); /* 25 us */
2402 2398
2403 minor = inb(ha->io_addr + IPS_REG_FLDP); 2399 minor = inb(ha->io_addr + IPS_REG_FLDP);
2404 2400
2405 /* Get SubMinor version */ 2401 /* Get SubMinor version */
2406 outl(cpu_to_le32(0x1FD), ha->io_addr + IPS_REG_FLAP); 2402 outl(cpu_to_le32(0x1FD), ha->io_addr + IPS_REG_FLAP);
2407 if (ha->revision_id == IPS_REVID_TROMBONE64) 2403 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2408 udelay(25); /* 25 us */ 2404 udelay(25); /* 25 us */
2409 2405
2410 subminor = inb(ha->io_addr + IPS_REG_FLDP); 2406 subminor = inb(ha->io_addr + IPS_REG_FLDP);
@@ -2740,8 +2736,6 @@ ips_next(ips_ha_t * ha, int intr)
2740 SC->result = DID_OK; 2736 SC->result = DID_OK;
2741 SC->host_scribble = NULL; 2737 SC->host_scribble = NULL;
2742 2738
2743 memset(SC->sense_buffer, 0, sizeof (SC->sense_buffer));
2744
2745 scb->target_id = SC->device->id; 2739 scb->target_id = SC->device->id;
2746 scb->lun = SC->device->lun; 2740 scb->lun = SC->device->lun;
2747 scb->bus = SC->device->channel; 2741 scb->bus = SC->device->channel;
@@ -2780,10 +2774,11 @@ ips_next(ips_ha_t * ha, int intr)
2780 scb->dcdb.cmd_attribute = 2774 scb->dcdb.cmd_attribute =
2781 ips_command_direction[scb->scsi_cmd->cmnd[0]]; 2775 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2782 2776
2783 /* Allow a WRITE BUFFER Command to Have no Data */ 2777 /* Allow a WRITE BUFFER Command to Have no Data */
2784 /* This is Used by Tape Flash Utilites */ 2778 /* This is Used by Tape Flash Utilites */
2785 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) && (scb->data_len == 0)) 2779 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) &&
2786 scb->dcdb.cmd_attribute = 0; 2780 (scb->data_len == 0))
2781 scb->dcdb.cmd_attribute = 0;
2787 2782
2788 if (!(scb->dcdb.cmd_attribute & 0x3)) 2783 if (!(scb->dcdb.cmd_attribute & 0x3))
2789 scb->dcdb.transfer_length = 0; 2784 scb->dcdb.transfer_length = 0;
@@ -3404,7 +3399,7 @@ ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3404 3399
3405 /* Restrict access to physical DASD */ 3400 /* Restrict access to physical DASD */
3406 if (scb->scsi_cmd->cmnd[0] == INQUIRY) { 3401 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3407 ips_scmd_buf_read(scb->scsi_cmd, 3402 ips_scmd_buf_read(scb->scsi_cmd,
3408 &inquiryData, sizeof (inquiryData)); 3403 &inquiryData, sizeof (inquiryData));
3409 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) { 3404 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) {
3410 errcode = DID_TIME_OUT; 3405 errcode = DID_TIME_OUT;
@@ -3438,13 +3433,11 @@ ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3438 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; 3433 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3439 memcpy(scb->scsi_cmd->sense_buffer, 3434 memcpy(scb->scsi_cmd->sense_buffer,
3440 tapeDCDB->sense_info, 3435 tapeDCDB->sense_info,
3441 sizeof (scb->scsi_cmd-> 3436 SCSI_SENSE_BUFFERSIZE);
3442 sense_buffer));
3443 } else { 3437 } else {
3444 memcpy(scb->scsi_cmd->sense_buffer, 3438 memcpy(scb->scsi_cmd->sense_buffer,
3445 scb->dcdb.sense_info, 3439 scb->dcdb.sense_info,
3446 sizeof (scb->scsi_cmd-> 3440 SCSI_SENSE_BUFFERSIZE);
3447 sense_buffer));
3448 } 3441 }
3449 device_error = 2; /* check condition */ 3442 device_error = 2; /* check condition */
3450 } 3443 }
@@ -3824,7 +3817,6 @@ ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3824 /* attempted, a Check Condition occurred, and Sense */ 3817 /* attempted, a Check Condition occurred, and Sense */
3825 /* Data indicating an Invalid CDB OpCode is returned. */ 3818 /* Data indicating an Invalid CDB OpCode is returned. */
3826 sp = (char *) scb->scsi_cmd->sense_buffer; 3819 sp = (char *) scb->scsi_cmd->sense_buffer;
3827 memset(sp, 0, sizeof (scb->scsi_cmd->sense_buffer));
3828 3820
3829 sp[0] = 0x70; /* Error Code */ 3821 sp[0] = 0x70; /* Error Code */
3830 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */ 3822 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
@@ -4090,10 +4082,10 @@ ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
4090 scb->scsi_cmd->result = errcode << 16; 4082 scb->scsi_cmd->result = errcode << 16;
4091 } else { /* bus == 0 */ 4083 } else { /* bus == 0 */
4092 /* restrict access to physical drives */ 4084 /* restrict access to physical drives */
4093 if (scb->scsi_cmd->cmnd[0] == INQUIRY) { 4085 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
4094 ips_scmd_buf_read(scb->scsi_cmd, 4086 ips_scmd_buf_read(scb->scsi_cmd,
4095 &inquiryData, sizeof (inquiryData)); 4087 &inquiryData, sizeof (inquiryData));
4096 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) 4088 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK)
4097 scb->scsi_cmd->result = DID_TIME_OUT << 16; 4089 scb->scsi_cmd->result = DID_TIME_OUT << 16;
4098 } 4090 }
4099 } /* else */ 4091 } /* else */
@@ -4393,8 +4385,6 @@ ips_free(ips_ha_t * ha)
4393 ha->mem_ptr = NULL; 4385 ha->mem_ptr = NULL;
4394 } 4386 }
4395 4387
4396 if (ha->mem_addr)
4397 release_mem_region(ha->mem_addr, ha->mem_len);
4398 ha->mem_addr = 0; 4388 ha->mem_addr = 0;
4399 4389
4400 } 4390 }
@@ -4661,8 +4651,8 @@ ips_isinit_morpheus(ips_ha_t * ha)
4661 uint32_t bits; 4651 uint32_t bits;
4662 4652
4663 METHOD_TRACE("ips_is_init_morpheus", 1); 4653 METHOD_TRACE("ips_is_init_morpheus", 1);
4664 4654
4665 if (ips_isintr_morpheus(ha)) 4655 if (ips_isintr_morpheus(ha))
4666 ips_flush_and_reset(ha); 4656 ips_flush_and_reset(ha);
4667 4657
4668 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); 4658 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
@@ -4686,7 +4676,7 @@ ips_isinit_morpheus(ips_ha_t * ha)
4686/* state ( was trying to INIT and an interrupt was already pending ) ... */ 4676/* state ( was trying to INIT and an interrupt was already pending ) ... */
4687/* */ 4677/* */
4688/****************************************************************************/ 4678/****************************************************************************/
4689static void 4679static void
4690ips_flush_and_reset(ips_ha_t *ha) 4680ips_flush_and_reset(ips_ha_t *ha)
4691{ 4681{
4692 ips_scb_t *scb; 4682 ips_scb_t *scb;
@@ -4718,9 +4708,9 @@ ips_flush_and_reset(ips_ha_t *ha)
4718 if (ret == IPS_SUCCESS) { 4708 if (ret == IPS_SUCCESS) {
4719 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */ 4709 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */
4720 done = 0; 4710 done = 0;
4721 4711
4722 while ((time > 0) && (!done)) { 4712 while ((time > 0) && (!done)) {
4723 done = ips_poll_for_flush_complete(ha); 4713 done = ips_poll_for_flush_complete(ha);
4724 /* This may look evil, but it's only done during extremely rare start-up conditions ! */ 4714 /* This may look evil, but it's only done during extremely rare start-up conditions ! */
4725 udelay(1000); 4715 udelay(1000);
4726 time--; 4716 time--;
@@ -4749,17 +4739,17 @@ static int
4749ips_poll_for_flush_complete(ips_ha_t * ha) 4739ips_poll_for_flush_complete(ips_ha_t * ha)
4750{ 4740{
4751 IPS_STATUS cstatus; 4741 IPS_STATUS cstatus;
4752 4742
4753 while (TRUE) { 4743 while (TRUE) {
4754 cstatus.value = (*ha->func.statupd) (ha); 4744 cstatus.value = (*ha->func.statupd) (ha);
4755 4745
4756 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */ 4746 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */
4757 break; 4747 break;
4758 4748
4759 /* Success is when we see the Flush Command ID */ 4749 /* Success is when we see the Flush Command ID */
4760 if (cstatus.fields.command_id == IPS_MAX_CMDS ) 4750 if (cstatus.fields.command_id == IPS_MAX_CMDS)
4761 return 1; 4751 return 1;
4762 } 4752 }
4763 4753
4764 return 0; 4754 return 0;
4765} 4755}
@@ -4903,7 +4893,7 @@ ips_init_copperhead(ips_ha_t * ha)
4903 /* Enable busmastering */ 4893 /* Enable busmastering */
4904 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR); 4894 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4905 4895
4906 if (ha->revision_id == IPS_REVID_TROMBONE64) 4896 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4907 /* fix for anaconda64 */ 4897 /* fix for anaconda64 */
4908 outl(0, ha->io_addr + IPS_REG_NDAE); 4898 outl(0, ha->io_addr + IPS_REG_NDAE);
4909 4899
@@ -4997,7 +4987,7 @@ ips_init_copperhead_memio(ips_ha_t * ha)
4997 /* Enable busmastering */ 4987 /* Enable busmastering */
4998 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR); 4988 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4999 4989
5000 if (ha->revision_id == IPS_REVID_TROMBONE64) 4990 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
5001 /* fix for anaconda64 */ 4991 /* fix for anaconda64 */
5002 writel(0, ha->mem_ptr + IPS_REG_NDAE); 4992 writel(0, ha->mem_ptr + IPS_REG_NDAE);
5003 4993
@@ -5142,7 +5132,7 @@ ips_reset_copperhead(ips_ha_t * ha)
5142 METHOD_TRACE("ips_reset_copperhead", 1); 5132 METHOD_TRACE("ips_reset_copperhead", 1);
5143 5133
5144 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d", 5134 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5145 ips_name, ha->host_num, ha->io_addr, ha->irq); 5135 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq);
5146 5136
5147 reset_counter = 0; 5137 reset_counter = 0;
5148 5138
@@ -5187,7 +5177,7 @@ ips_reset_copperhead_memio(ips_ha_t * ha)
5187 METHOD_TRACE("ips_reset_copperhead_memio", 1); 5177 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5188 5178
5189 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d", 5179 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5190 ips_name, ha->host_num, ha->mem_addr, ha->irq); 5180 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5191 5181
5192 reset_counter = 0; 5182 reset_counter = 0;
5193 5183
@@ -5233,7 +5223,7 @@ ips_reset_morpheus(ips_ha_t * ha)
5233 METHOD_TRACE("ips_reset_morpheus", 1); 5223 METHOD_TRACE("ips_reset_morpheus", 1);
5234 5224
5235 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d", 5225 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5236 ips_name, ha->host_num, ha->mem_addr, ha->irq); 5226 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5237 5227
5238 reset_counter = 0; 5228 reset_counter = 0;
5239 5229
@@ -5920,7 +5910,7 @@ ips_read_config(ips_ha_t * ha, int intr)
5920 5910
5921 return (0); 5911 return (0);
5922 } 5912 }
5923 5913
5924 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf)); 5914 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5925 return (1); 5915 return (1);
5926} 5916}
@@ -5959,7 +5949,7 @@ ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5959 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr; 5949 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5960 if (write) 5950 if (write)
5961 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram)); 5951 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
5962 5952
5963 /* issue the command */ 5953 /* issue the command */
5964 if (((ret = 5954 if (((ret =
5965 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5955 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
@@ -6196,32 +6186,32 @@ ips_erase_bios(ips_ha_t * ha)
6196 6186
6197 /* Clear the status register */ 6187 /* Clear the status register */
6198 outl(0, ha->io_addr + IPS_REG_FLAP); 6188 outl(0, ha->io_addr + IPS_REG_FLAP);
6199 if (ha->revision_id == IPS_REVID_TROMBONE64) 6189 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6200 udelay(25); /* 25 us */ 6190 udelay(25); /* 25 us */
6201 6191
6202 outb(0x50, ha->io_addr + IPS_REG_FLDP); 6192 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6203 if (ha->revision_id == IPS_REVID_TROMBONE64) 6193 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6204 udelay(25); /* 25 us */ 6194 udelay(25); /* 25 us */
6205 6195
6206 /* Erase Setup */ 6196 /* Erase Setup */
6207 outb(0x20, ha->io_addr + IPS_REG_FLDP); 6197 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6208 if (ha->revision_id == IPS_REVID_TROMBONE64) 6198 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6209 udelay(25); /* 25 us */ 6199 udelay(25); /* 25 us */
6210 6200
6211 /* Erase Confirm */ 6201 /* Erase Confirm */
6212 outb(0xD0, ha->io_addr + IPS_REG_FLDP); 6202 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6213 if (ha->revision_id == IPS_REVID_TROMBONE64) 6203 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6214 udelay(25); /* 25 us */ 6204 udelay(25); /* 25 us */
6215 6205
6216 /* Erase Status */ 6206 /* Erase Status */
6217 outb(0x70, ha->io_addr + IPS_REG_FLDP); 6207 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6218 if (ha->revision_id == IPS_REVID_TROMBONE64) 6208 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6219 udelay(25); /* 25 us */ 6209 udelay(25); /* 25 us */
6220 6210
6221 timeout = 80000; /* 80 seconds */ 6211 timeout = 80000; /* 80 seconds */
6222 6212
6223 while (timeout > 0) { 6213 while (timeout > 0) {
6224 if (ha->revision_id == IPS_REVID_TROMBONE64) { 6214 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6225 outl(0, ha->io_addr + IPS_REG_FLAP); 6215 outl(0, ha->io_addr + IPS_REG_FLAP);
6226 udelay(25); /* 25 us */ 6216 udelay(25); /* 25 us */
6227 } 6217 }
@@ -6241,13 +6231,13 @@ ips_erase_bios(ips_ha_t * ha)
6241 6231
6242 /* try to suspend the erase */ 6232 /* try to suspend the erase */
6243 outb(0xB0, ha->io_addr + IPS_REG_FLDP); 6233 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6244 if (ha->revision_id == IPS_REVID_TROMBONE64) 6234 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6245 udelay(25); /* 25 us */ 6235 udelay(25); /* 25 us */
6246 6236
6247 /* wait for 10 seconds */ 6237 /* wait for 10 seconds */
6248 timeout = 10000; 6238 timeout = 10000;
6249 while (timeout > 0) { 6239 while (timeout > 0) {
6250 if (ha->revision_id == IPS_REVID_TROMBONE64) { 6240 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6251 outl(0, ha->io_addr + IPS_REG_FLAP); 6241 outl(0, ha->io_addr + IPS_REG_FLAP);
6252 udelay(25); /* 25 us */ 6242 udelay(25); /* 25 us */
6253 } 6243 }
@@ -6277,12 +6267,12 @@ ips_erase_bios(ips_ha_t * ha)
6277 /* Otherwise, we were successful */ 6267 /* Otherwise, we were successful */
6278 /* clear status */ 6268 /* clear status */
6279 outb(0x50, ha->io_addr + IPS_REG_FLDP); 6269 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6280 if (ha->revision_id == IPS_REVID_TROMBONE64) 6270 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6281 udelay(25); /* 25 us */ 6271 udelay(25); /* 25 us */
6282 6272
6283 /* enable reads */ 6273 /* enable reads */
6284 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6274 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6285 if (ha->revision_id == IPS_REVID_TROMBONE64) 6275 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6286 udelay(25); /* 25 us */ 6276 udelay(25); /* 25 us */
6287 6277
6288 return (0); 6278 return (0);
@@ -6308,32 +6298,32 @@ ips_erase_bios_memio(ips_ha_t * ha)
6308 6298
6309 /* Clear the status register */ 6299 /* Clear the status register */
6310 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6300 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6311 if (ha->revision_id == IPS_REVID_TROMBONE64) 6301 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6312 udelay(25); /* 25 us */ 6302 udelay(25); /* 25 us */
6313 6303
6314 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); 6304 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6315 if (ha->revision_id == IPS_REVID_TROMBONE64) 6305 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6316 udelay(25); /* 25 us */ 6306 udelay(25); /* 25 us */
6317 6307
6318 /* Erase Setup */ 6308 /* Erase Setup */
6319 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP); 6309 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6320 if (ha->revision_id == IPS_REVID_TROMBONE64) 6310 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6321 udelay(25); /* 25 us */ 6311 udelay(25); /* 25 us */
6322 6312
6323 /* Erase Confirm */ 6313 /* Erase Confirm */
6324 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP); 6314 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6325 if (ha->revision_id == IPS_REVID_TROMBONE64) 6315 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6326 udelay(25); /* 25 us */ 6316 udelay(25); /* 25 us */
6327 6317
6328 /* Erase Status */ 6318 /* Erase Status */
6329 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP); 6319 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6330 if (ha->revision_id == IPS_REVID_TROMBONE64) 6320 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6331 udelay(25); /* 25 us */ 6321 udelay(25); /* 25 us */
6332 6322
6333 timeout = 80000; /* 80 seconds */ 6323 timeout = 80000; /* 80 seconds */
6334 6324
6335 while (timeout > 0) { 6325 while (timeout > 0) {
6336 if (ha->revision_id == IPS_REVID_TROMBONE64) { 6326 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6337 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6327 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6338 udelay(25); /* 25 us */ 6328 udelay(25); /* 25 us */
6339 } 6329 }
@@ -6353,13 +6343,13 @@ ips_erase_bios_memio(ips_ha_t * ha)
6353 6343
6354 /* try to suspend the erase */ 6344 /* try to suspend the erase */
6355 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP); 6345 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6356 if (ha->revision_id == IPS_REVID_TROMBONE64) 6346 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6357 udelay(25); /* 25 us */ 6347 udelay(25); /* 25 us */
6358 6348
6359 /* wait for 10 seconds */ 6349 /* wait for 10 seconds */
6360 timeout = 10000; 6350 timeout = 10000;
6361 while (timeout > 0) { 6351 while (timeout > 0) {
6362 if (ha->revision_id == IPS_REVID_TROMBONE64) { 6352 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6363 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6353 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6364 udelay(25); /* 25 us */ 6354 udelay(25); /* 25 us */
6365 } 6355 }
@@ -6389,12 +6379,12 @@ ips_erase_bios_memio(ips_ha_t * ha)
6389 /* Otherwise, we were successful */ 6379 /* Otherwise, we were successful */
6390 /* clear status */ 6380 /* clear status */
6391 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); 6381 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6392 if (ha->revision_id == IPS_REVID_TROMBONE64) 6382 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6393 udelay(25); /* 25 us */ 6383 udelay(25); /* 25 us */
6394 6384
6395 /* enable reads */ 6385 /* enable reads */
6396 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6386 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6397 if (ha->revision_id == IPS_REVID_TROMBONE64) 6387 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6398 udelay(25); /* 25 us */ 6388 udelay(25); /* 25 us */
6399 6389
6400 return (0); 6390 return (0);
@@ -6423,21 +6413,21 @@ ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6423 for (i = 0; i < buffersize; i++) { 6413 for (i = 0; i < buffersize; i++) {
6424 /* write a byte */ 6414 /* write a byte */
6425 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP); 6415 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6426 if (ha->revision_id == IPS_REVID_TROMBONE64) 6416 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6427 udelay(25); /* 25 us */ 6417 udelay(25); /* 25 us */
6428 6418
6429 outb(0x40, ha->io_addr + IPS_REG_FLDP); 6419 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6430 if (ha->revision_id == IPS_REVID_TROMBONE64) 6420 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6431 udelay(25); /* 25 us */ 6421 udelay(25); /* 25 us */
6432 6422
6433 outb(buffer[i], ha->io_addr + IPS_REG_FLDP); 6423 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6434 if (ha->revision_id == IPS_REVID_TROMBONE64) 6424 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6435 udelay(25); /* 25 us */ 6425 udelay(25); /* 25 us */
6436 6426
6437 /* wait up to one second */ 6427 /* wait up to one second */
6438 timeout = 1000; 6428 timeout = 1000;
6439 while (timeout > 0) { 6429 while (timeout > 0) {
6440 if (ha->revision_id == IPS_REVID_TROMBONE64) { 6430 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6441 outl(0, ha->io_addr + IPS_REG_FLAP); 6431 outl(0, ha->io_addr + IPS_REG_FLAP);
6442 udelay(25); /* 25 us */ 6432 udelay(25); /* 25 us */
6443 } 6433 }
@@ -6454,11 +6444,11 @@ ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6454 if (timeout == 0) { 6444 if (timeout == 0) {
6455 /* timeout error */ 6445 /* timeout error */
6456 outl(0, ha->io_addr + IPS_REG_FLAP); 6446 outl(0, ha->io_addr + IPS_REG_FLAP);
6457 if (ha->revision_id == IPS_REVID_TROMBONE64) 6447 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6458 udelay(25); /* 25 us */ 6448 udelay(25); /* 25 us */
6459 6449
6460 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6450 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6461 if (ha->revision_id == IPS_REVID_TROMBONE64) 6451 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6462 udelay(25); /* 25 us */ 6452 udelay(25); /* 25 us */
6463 6453
6464 return (1); 6454 return (1);
@@ -6468,11 +6458,11 @@ ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6468 if (status & 0x18) { 6458 if (status & 0x18) {
6469 /* programming error */ 6459 /* programming error */
6470 outl(0, ha->io_addr + IPS_REG_FLAP); 6460 outl(0, ha->io_addr + IPS_REG_FLAP);
6471 if (ha->revision_id == IPS_REVID_TROMBONE64) 6461 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6472 udelay(25); /* 25 us */ 6462 udelay(25); /* 25 us */
6473 6463
6474 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6464 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6475 if (ha->revision_id == IPS_REVID_TROMBONE64) 6465 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6476 udelay(25); /* 25 us */ 6466 udelay(25); /* 25 us */
6477 6467
6478 return (1); 6468 return (1);
@@ -6481,11 +6471,11 @@ ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6481 6471
6482 /* Enable reading */ 6472 /* Enable reading */
6483 outl(0, ha->io_addr + IPS_REG_FLAP); 6473 outl(0, ha->io_addr + IPS_REG_FLAP);
6484 if (ha->revision_id == IPS_REVID_TROMBONE64) 6474 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6485 udelay(25); /* 25 us */ 6475 udelay(25); /* 25 us */
6486 6476
6487 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6477 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6488 if (ha->revision_id == IPS_REVID_TROMBONE64) 6478 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6489 udelay(25); /* 25 us */ 6479 udelay(25); /* 25 us */
6490 6480
6491 return (0); 6481 return (0);
@@ -6514,21 +6504,21 @@ ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6514 for (i = 0; i < buffersize; i++) { 6504 for (i = 0; i < buffersize; i++) {
6515 /* write a byte */ 6505 /* write a byte */
6516 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); 6506 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6517 if (ha->revision_id == IPS_REVID_TROMBONE64) 6507 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6518 udelay(25); /* 25 us */ 6508 udelay(25); /* 25 us */
6519 6509
6520 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP); 6510 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6521 if (ha->revision_id == IPS_REVID_TROMBONE64) 6511 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6522 udelay(25); /* 25 us */ 6512 udelay(25); /* 25 us */
6523 6513
6524 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP); 6514 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6525 if (ha->revision_id == IPS_REVID_TROMBONE64) 6515 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6526 udelay(25); /* 25 us */ 6516 udelay(25); /* 25 us */
6527 6517
6528 /* wait up to one second */ 6518 /* wait up to one second */
6529 timeout = 1000; 6519 timeout = 1000;
6530 while (timeout > 0) { 6520 while (timeout > 0) {
6531 if (ha->revision_id == IPS_REVID_TROMBONE64) { 6521 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6532 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6522 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6533 udelay(25); /* 25 us */ 6523 udelay(25); /* 25 us */
6534 } 6524 }
@@ -6545,11 +6535,11 @@ ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6545 if (timeout == 0) { 6535 if (timeout == 0) {
6546 /* timeout error */ 6536 /* timeout error */
6547 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6537 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6548 if (ha->revision_id == IPS_REVID_TROMBONE64) 6538 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6549 udelay(25); /* 25 us */ 6539 udelay(25); /* 25 us */
6550 6540
6551 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6541 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6552 if (ha->revision_id == IPS_REVID_TROMBONE64) 6542 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6553 udelay(25); /* 25 us */ 6543 udelay(25); /* 25 us */
6554 6544
6555 return (1); 6545 return (1);
@@ -6559,11 +6549,11 @@ ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6559 if (status & 0x18) { 6549 if (status & 0x18) {
6560 /* programming error */ 6550 /* programming error */
6561 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6551 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6562 if (ha->revision_id == IPS_REVID_TROMBONE64) 6552 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6563 udelay(25); /* 25 us */ 6553 udelay(25); /* 25 us */
6564 6554
6565 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6555 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6566 if (ha->revision_id == IPS_REVID_TROMBONE64) 6556 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6567 udelay(25); /* 25 us */ 6557 udelay(25); /* 25 us */
6568 6558
6569 return (1); 6559 return (1);
@@ -6572,11 +6562,11 @@ ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6572 6562
6573 /* Enable reading */ 6563 /* Enable reading */
6574 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6564 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6575 if (ha->revision_id == IPS_REVID_TROMBONE64) 6565 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6576 udelay(25); /* 25 us */ 6566 udelay(25); /* 25 us */
6577 6567
6578 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6568 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6579 if (ha->revision_id == IPS_REVID_TROMBONE64) 6569 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6580 udelay(25); /* 25 us */ 6570 udelay(25); /* 25 us */
6581 6571
6582 return (0); 6572 return (0);
@@ -6601,14 +6591,14 @@ ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6601 6591
6602 /* test 1st byte */ 6592 /* test 1st byte */
6603 outl(0, ha->io_addr + IPS_REG_FLAP); 6593 outl(0, ha->io_addr + IPS_REG_FLAP);
6604 if (ha->revision_id == IPS_REVID_TROMBONE64) 6594 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6605 udelay(25); /* 25 us */ 6595 udelay(25); /* 25 us */
6606 6596
6607 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) 6597 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6608 return (1); 6598 return (1);
6609 6599
6610 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP); 6600 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
6611 if (ha->revision_id == IPS_REVID_TROMBONE64) 6601 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6612 udelay(25); /* 25 us */ 6602 udelay(25); /* 25 us */
6613 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) 6603 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6614 return (1); 6604 return (1);
@@ -6617,7 +6607,7 @@ ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6617 for (i = 2; i < buffersize; i++) { 6607 for (i = 2; i < buffersize; i++) {
6618 6608
6619 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP); 6609 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6620 if (ha->revision_id == IPS_REVID_TROMBONE64) 6610 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6621 udelay(25); /* 25 us */ 6611 udelay(25); /* 25 us */
6622 6612
6623 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP); 6613 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
@@ -6650,14 +6640,14 @@ ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6650 6640
6651 /* test 1st byte */ 6641 /* test 1st byte */
6652 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6642 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6653 if (ha->revision_id == IPS_REVID_TROMBONE64) 6643 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6654 udelay(25); /* 25 us */ 6644 udelay(25); /* 25 us */
6655 6645
6656 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) 6646 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6657 return (1); 6647 return (1);
6658 6648
6659 writel(1, ha->mem_ptr + IPS_REG_FLAP); 6649 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6660 if (ha->revision_id == IPS_REVID_TROMBONE64) 6650 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6661 udelay(25); /* 25 us */ 6651 udelay(25); /* 25 us */
6662 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) 6652 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6663 return (1); 6653 return (1);
@@ -6666,7 +6656,7 @@ ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6666 for (i = 2; i < buffersize; i++) { 6656 for (i = 2; i < buffersize; i++) {
6667 6657
6668 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); 6658 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6669 if (ha->revision_id == IPS_REVID_TROMBONE64) 6659 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6670 udelay(25); /* 25 us */ 6660 udelay(25); /* 25 us */
6671 6661
6672 checksum = 6662 checksum =
@@ -6837,24 +6827,18 @@ ips_register_scsi(int index)
6837 } 6827 }
6838 ha = IPS_HA(sh); 6828 ha = IPS_HA(sh);
6839 memcpy(ha, oldha, sizeof (ips_ha_t)); 6829 memcpy(ha, oldha, sizeof (ips_ha_t));
6840 free_irq(oldha->irq, oldha); 6830 free_irq(oldha->pcidev->irq, oldha);
6841 /* Install the interrupt handler with the new ha */ 6831 /* Install the interrupt handler with the new ha */
6842 if (request_irq(ha->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) { 6832 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
6843 IPS_PRINTK(KERN_WARNING, ha->pcidev, 6833 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6844 "Unable to install interrupt handler\n"); 6834 "Unable to install interrupt handler\n");
6845 scsi_host_put(sh); 6835 goto err_out_sh;
6846 return -1;
6847 } 6836 }
6848 6837
6849 kfree(oldha); 6838 kfree(oldha);
6850 ips_sh[index] = sh;
6851 ips_ha[index] = ha;
6852 6839
6853 /* Store away needed values for later use */ 6840 /* Store away needed values for later use */
6854 sh->io_port = ha->io_addr;
6855 sh->n_io_port = ha->io_addr ? 255 : 0;
6856 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr; 6841 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
6857 sh->irq = ha->irq;
6858 sh->sg_tablesize = sh->hostt->sg_tablesize; 6842 sh->sg_tablesize = sh->hostt->sg_tablesize;
6859 sh->can_queue = sh->hostt->can_queue; 6843 sh->can_queue = sh->hostt->can_queue;
6860 sh->cmd_per_lun = sh->hostt->cmd_per_lun; 6844 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
@@ -6867,10 +6851,21 @@ ips_register_scsi(int index)
6867 sh->max_channel = ha->nbus - 1; 6851 sh->max_channel = ha->nbus - 1;
6868 sh->can_queue = ha->max_cmds - 1; 6852 sh->can_queue = ha->max_cmds - 1;
6869 6853
6870 scsi_add_host(sh, NULL); 6854 if (scsi_add_host(sh, &ha->pcidev->dev))
6855 goto err_out;
6856
6857 ips_sh[index] = sh;
6858 ips_ha[index] = ha;
6859
6871 scsi_scan_host(sh); 6860 scsi_scan_host(sh);
6872 6861
6873 return 0; 6862 return 0;
6863
6864err_out:
6865 free_irq(ha->pcidev->irq, ha);
6866err_out_sh:
6867 scsi_host_put(sh);
6868 return -1;
6874} 6869}
6875 6870
6876/*---------------------------------------------------------------------------*/ 6871/*---------------------------------------------------------------------------*/
@@ -6882,20 +6877,14 @@ ips_register_scsi(int index)
6882static void __devexit 6877static void __devexit
6883ips_remove_device(struct pci_dev *pci_dev) 6878ips_remove_device(struct pci_dev *pci_dev)
6884{ 6879{
6885 int i; 6880 struct Scsi_Host *sh = pci_get_drvdata(pci_dev);
6886 struct Scsi_Host *sh;
6887 ips_ha_t *ha;
6888 6881
6889 for (i = 0; i < IPS_MAX_ADAPTERS; i++) { 6882 pci_set_drvdata(pci_dev, NULL);
6890 ha = ips_ha[i]; 6883
6891 if (ha) { 6884 ips_release(sh);
6892 if ((pci_dev->bus->number == ha->pcidev->bus->number) && 6885
6893 (pci_dev->devfn == ha->pcidev->devfn)) { 6886 pci_release_regions(pci_dev);
6894 sh = ips_sh[i]; 6887 pci_disable_device(pci_dev);
6895 ips_release(sh);
6896 }
6897 }
6898 }
6899} 6888}
6900 6889
6901/****************************************************************************/ 6890/****************************************************************************/
@@ -6949,12 +6938,17 @@ module_exit(ips_module_exit);
6949static int __devinit 6938static int __devinit
6950ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent) 6939ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
6951{ 6940{
6952 int uninitialized_var(index); 6941 int index = -1;
6953 int rc; 6942 int rc;
6954 6943
6955 METHOD_TRACE("ips_insert_device", 1); 6944 METHOD_TRACE("ips_insert_device", 1);
6956 if (pci_enable_device(pci_dev)) 6945 rc = pci_enable_device(pci_dev);
6957 return -1; 6946 if (rc)
6947 return rc;
6948
6949 rc = pci_request_regions(pci_dev, "ips");
6950 if (rc)
6951 goto err_out;
6958 6952
6959 rc = ips_init_phase1(pci_dev, &index); 6953 rc = ips_init_phase1(pci_dev, &index);
6960 if (rc == SUCCESS) 6954 if (rc == SUCCESS)
@@ -6970,6 +6964,19 @@ ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
6970 ips_num_controllers++; 6964 ips_num_controllers++;
6971 6965
6972 ips_next_controller = ips_num_controllers; 6966 ips_next_controller = ips_num_controllers;
6967
6968 if (rc < 0) {
6969 rc = -ENODEV;
6970 goto err_out_regions;
6971 }
6972
6973 pci_set_drvdata(pci_dev, ips_sh[index]);
6974 return 0;
6975
6976err_out_regions:
6977 pci_release_regions(pci_dev);
6978err_out:
6979 pci_disable_device(pci_dev);
6973 return rc; 6980 return rc;
6974} 6981}
6975 6982
@@ -6992,8 +6999,6 @@ ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
6992 uint32_t mem_len; 6999 uint32_t mem_len;
6993 uint8_t bus; 7000 uint8_t bus;
6994 uint8_t func; 7001 uint8_t func;
6995 uint8_t irq;
6996 uint16_t subdevice_id;
6997 int j; 7002 int j;
6998 int index; 7003 int index;
6999 dma_addr_t dma_address; 7004 dma_addr_t dma_address;
@@ -7004,7 +7009,7 @@ ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
7004 METHOD_TRACE("ips_init_phase1", 1); 7009 METHOD_TRACE("ips_init_phase1", 1);
7005 index = IPS_MAX_ADAPTERS; 7010 index = IPS_MAX_ADAPTERS;
7006 for (j = 0; j < IPS_MAX_ADAPTERS; j++) { 7011 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
7007 if (ips_ha[j] == 0) { 7012 if (ips_ha[j] == NULL) {
7008 index = j; 7013 index = j;
7009 break; 7014 break;
7010 } 7015 }
@@ -7014,7 +7019,6 @@ ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
7014 return -1; 7019 return -1;
7015 7020
7016 /* stuff that we get in dev */ 7021 /* stuff that we get in dev */
7017 irq = pci_dev->irq;
7018 bus = pci_dev->bus->number; 7022 bus = pci_dev->bus->number;
7019 func = pci_dev->devfn; 7023 func = pci_dev->devfn;
7020 7024
@@ -7042,34 +7046,17 @@ ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
7042 uint32_t base; 7046 uint32_t base;
7043 uint32_t offs; 7047 uint32_t offs;
7044 7048
7045 if (!request_mem_region(mem_addr, mem_len, "ips")) {
7046 IPS_PRINTK(KERN_WARNING, pci_dev,
7047 "Couldn't allocate IO Memory space %x len %d.\n",
7048 mem_addr, mem_len);
7049 return -1;
7050 }
7051
7052 base = mem_addr & PAGE_MASK; 7049 base = mem_addr & PAGE_MASK;
7053 offs = mem_addr - base; 7050 offs = mem_addr - base;
7054 ioremap_ptr = ioremap(base, PAGE_SIZE); 7051 ioremap_ptr = ioremap(base, PAGE_SIZE);
7052 if (!ioremap_ptr)
7053 return -1;
7055 mem_ptr = ioremap_ptr + offs; 7054 mem_ptr = ioremap_ptr + offs;
7056 } else { 7055 } else {
7057 ioremap_ptr = NULL; 7056 ioremap_ptr = NULL;
7058 mem_ptr = NULL; 7057 mem_ptr = NULL;
7059 } 7058 }
7060 7059
7061 /* setup I/O mapped area (if applicable) */
7062 if (io_addr) {
7063 if (!request_region(io_addr, io_len, "ips")) {
7064 IPS_PRINTK(KERN_WARNING, pci_dev,
7065 "Couldn't allocate IO space %x len %d.\n",
7066 io_addr, io_len);
7067 return -1;
7068 }
7069 }
7070
7071 subdevice_id = pci_dev->subsystem_device;
7072
7073 /* found a controller */ 7060 /* found a controller */
7074 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL); 7061 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL);
7075 if (ha == NULL) { 7062 if (ha == NULL) {
@@ -7078,13 +7065,11 @@ ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
7078 return -1; 7065 return -1;
7079 } 7066 }
7080 7067
7081
7082 ips_sh[index] = NULL; 7068 ips_sh[index] = NULL;
7083 ips_ha[index] = ha; 7069 ips_ha[index] = ha;
7084 ha->active = 1; 7070 ha->active = 1;
7085 7071
7086 /* Store info in HA structure */ 7072 /* Store info in HA structure */
7087 ha->irq = irq;
7088 ha->io_addr = io_addr; 7073 ha->io_addr = io_addr;
7089 ha->io_len = io_len; 7074 ha->io_len = io_len;
7090 ha->mem_addr = mem_addr; 7075 ha->mem_addr = mem_addr;
@@ -7092,10 +7077,7 @@ ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
7092 ha->mem_ptr = mem_ptr; 7077 ha->mem_ptr = mem_ptr;
7093 ha->ioremap_ptr = ioremap_ptr; 7078 ha->ioremap_ptr = ioremap_ptr;
7094 ha->host_num = (uint32_t) index; 7079 ha->host_num = (uint32_t) index;
7095 ha->revision_id = pci_dev->revision;
7096 ha->slot_num = PCI_SLOT(pci_dev->devfn); 7080 ha->slot_num = PCI_SLOT(pci_dev->devfn);
7097 ha->device_id = pci_dev->device;
7098 ha->subdevice_id = subdevice_id;
7099 ha->pcidev = pci_dev; 7081 ha->pcidev = pci_dev;
7100 7082
7101 /* 7083 /*
@@ -7240,7 +7222,7 @@ ips_init_phase2(int index)
7240 } 7222 }
7241 7223
7242 /* Install the interrupt handler */ 7224 /* Install the interrupt handler */
7243 if (request_irq(ha->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) { 7225 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
7244 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7226 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7245 "Unable to install interrupt handler\n"); 7227 "Unable to install interrupt handler\n");
7246 return ips_abort_init(ha, index); 7228 return ips_abort_init(ha, index);
@@ -7253,14 +7235,14 @@ ips_init_phase2(int index)
7253 if (!ips_allocatescbs(ha)) { 7235 if (!ips_allocatescbs(ha)) {
7254 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7236 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7255 "Unable to allocate a CCB\n"); 7237 "Unable to allocate a CCB\n");
7256 free_irq(ha->irq, ha); 7238 free_irq(ha->pcidev->irq, ha);
7257 return ips_abort_init(ha, index); 7239 return ips_abort_init(ha, index);
7258 } 7240 }
7259 7241
7260 if (!ips_hainit(ha)) { 7242 if (!ips_hainit(ha)) {
7261 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7243 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7262 "Unable to initialize controller\n"); 7244 "Unable to initialize controller\n");
7263 free_irq(ha->irq, ha); 7245 free_irq(ha->pcidev->irq, ha);
7264 return ips_abort_init(ha, index); 7246 return ips_abort_init(ha, index);
7265 } 7247 }
7266 /* Free the temporary SCB */ 7248 /* Free the temporary SCB */
@@ -7270,7 +7252,7 @@ ips_init_phase2(int index)
7270 if (!ips_allocatescbs(ha)) { 7252 if (!ips_allocatescbs(ha)) {
7271 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7253 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7272 "Unable to allocate CCBs\n"); 7254 "Unable to allocate CCBs\n");
7273 free_irq(ha->irq, ha); 7255 free_irq(ha->pcidev->irq, ha);
7274 return ips_abort_init(ha, index); 7256 return ips_abort_init(ha, index);
7275 } 7257 }
7276 7258