diff options
Diffstat (limited to 'drivers/scsi/ips.c')
-rw-r--r-- | drivers/scsi/ips.c | 178 |
1 files changed, 83 insertions, 95 deletions
diff --git a/drivers/scsi/ips.c b/drivers/scsi/ips.c index 5c5a9b2628fc..595a91afca0e 100644 --- a/drivers/scsi/ips.c +++ b/drivers/scsi/ips.c | |||
@@ -707,7 +707,7 @@ ips_release(struct Scsi_Host *sh) | |||
707 | release_region(ha->io_addr, ha->io_len); | 707 | release_region(ha->io_addr, ha->io_len); |
708 | 708 | ||
709 | /* free IRQ */ | 709 | /* free IRQ */ |
710 | free_irq(ha->irq, ha); | 710 | free_irq(ha->pcidev->irq, ha); |
711 | 711 | ||
712 | scsi_host_put(sh); | 712 | scsi_host_put(sh); |
713 | 713 | ||
@@ -1637,7 +1637,7 @@ ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr) | |||
1637 | return (IPS_FAILURE); | 1637 | return (IPS_FAILURE); |
1638 | } | 1638 | } |
1639 | 1639 | ||
1640 | if (ha->device_id == IPS_DEVICEID_COPPERHEAD && | 1640 | if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD && |
1641 | pt->CoppCP.cmd.flashfw.op_code == | 1641 | pt->CoppCP.cmd.flashfw.op_code == |
1642 | IPS_CMD_RW_BIOSFW) { | 1642 | IPS_CMD_RW_BIOSFW) { |
1643 | ret = ips_flash_copperhead(ha, pt, scb); | 1643 | ret = ips_flash_copperhead(ha, pt, scb); |
@@ -2021,7 +2021,7 @@ ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb) | |||
2021 | pt->ExtendedStatus = scb->extended_status; | 2021 | pt->ExtendedStatus = scb->extended_status; |
2022 | pt->AdapterType = ha->ad_type; | 2022 | pt->AdapterType = ha->ad_type; |
2023 | 2023 | ||
2024 | if (ha->device_id == IPS_DEVICEID_COPPERHEAD && | 2024 | if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD && |
2025 | (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD || | 2025 | (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD || |
2026 | scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW)) | 2026 | scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW)) |
2027 | ips_free_flash_copperhead(ha); | 2027 | ips_free_flash_copperhead(ha); |
@@ -2075,7 +2075,7 @@ ips_host_info(ips_ha_t * ha, char *ptr, off_t offset, int len) | |||
2075 | ha->mem_ptr); | 2075 | ha->mem_ptr); |
2076 | } | 2076 | } |
2077 | 2077 | ||
2078 | copy_info(&info, "\tIRQ number : %d\n", ha->irq); | 2078 | copy_info(&info, "\tIRQ number : %d\n", ha->pcidev->irq); |
2079 | 2079 | ||
2080 | /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */ | 2080 | /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */ |
2081 | /* That keeps everything happy for "text" operations on the proc file. */ | 2081 | /* That keeps everything happy for "text" operations on the proc file. */ |
@@ -2232,31 +2232,31 @@ ips_identify_controller(ips_ha_t * ha) | |||
2232 | { | 2232 | { |
2233 | METHOD_TRACE("ips_identify_controller", 1); | 2233 | METHOD_TRACE("ips_identify_controller", 1); |
2234 | 2234 | ||
2235 | switch (ha->device_id) { | 2235 | switch (ha->pcidev->device) { |
2236 | case IPS_DEVICEID_COPPERHEAD: | 2236 | case IPS_DEVICEID_COPPERHEAD: |
2237 | if (ha->revision_id <= IPS_REVID_SERVERAID) { | 2237 | if (ha->pcidev->revision <= IPS_REVID_SERVERAID) { |
2238 | ha->ad_type = IPS_ADTYPE_SERVERAID; | 2238 | ha->ad_type = IPS_ADTYPE_SERVERAID; |
2239 | } else if (ha->revision_id == IPS_REVID_SERVERAID2) { | 2239 | } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) { |
2240 | ha->ad_type = IPS_ADTYPE_SERVERAID2; | 2240 | ha->ad_type = IPS_ADTYPE_SERVERAID2; |
2241 | } else if (ha->revision_id == IPS_REVID_NAVAJO) { | 2241 | } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) { |
2242 | ha->ad_type = IPS_ADTYPE_NAVAJO; | 2242 | ha->ad_type = IPS_ADTYPE_NAVAJO; |
2243 | } else if ((ha->revision_id == IPS_REVID_SERVERAID2) | 2243 | } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2) |
2244 | && (ha->slot_num == 0)) { | 2244 | && (ha->slot_num == 0)) { |
2245 | ha->ad_type = IPS_ADTYPE_KIOWA; | 2245 | ha->ad_type = IPS_ADTYPE_KIOWA; |
2246 | } else if ((ha->revision_id >= IPS_REVID_CLARINETP1) && | 2246 | } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) && |
2247 | (ha->revision_id <= IPS_REVID_CLARINETP3)) { | 2247 | (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) { |
2248 | if (ha->enq->ucMaxPhysicalDevices == 15) | 2248 | if (ha->enq->ucMaxPhysicalDevices == 15) |
2249 | ha->ad_type = IPS_ADTYPE_SERVERAID3L; | 2249 | ha->ad_type = IPS_ADTYPE_SERVERAID3L; |
2250 | else | 2250 | else |
2251 | ha->ad_type = IPS_ADTYPE_SERVERAID3; | 2251 | ha->ad_type = IPS_ADTYPE_SERVERAID3; |
2252 | } else if ((ha->revision_id >= IPS_REVID_TROMBONE32) && | 2252 | } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) && |
2253 | (ha->revision_id <= IPS_REVID_TROMBONE64)) { | 2253 | (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) { |
2254 | ha->ad_type = IPS_ADTYPE_SERVERAID4H; | 2254 | ha->ad_type = IPS_ADTYPE_SERVERAID4H; |
2255 | } | 2255 | } |
2256 | break; | 2256 | break; |
2257 | 2257 | ||
2258 | case IPS_DEVICEID_MORPHEUS: | 2258 | case IPS_DEVICEID_MORPHEUS: |
2259 | switch (ha->subdevice_id) { | 2259 | switch (ha->pcidev->subsystem_device) { |
2260 | case IPS_SUBDEVICEID_4L: | 2260 | case IPS_SUBDEVICEID_4L: |
2261 | ha->ad_type = IPS_ADTYPE_SERVERAID4L; | 2261 | ha->ad_type = IPS_ADTYPE_SERVERAID4L; |
2262 | break; | 2262 | break; |
@@ -2285,7 +2285,7 @@ ips_identify_controller(ips_ha_t * ha) | |||
2285 | break; | 2285 | break; |
2286 | 2286 | ||
2287 | case IPS_DEVICEID_MARCO: | 2287 | case IPS_DEVICEID_MARCO: |
2288 | switch (ha->subdevice_id) { | 2288 | switch (ha->pcidev->subsystem_device) { |
2289 | case IPS_SUBDEVICEID_6M: | 2289 | case IPS_SUBDEVICEID_6M: |
2290 | ha->ad_type = IPS_ADTYPE_SERVERAID6M; | 2290 | ha->ad_type = IPS_ADTYPE_SERVERAID6M; |
2291 | break; | 2291 | break; |
@@ -2332,20 +2332,20 @@ ips_get_bios_version(ips_ha_t * ha, int intr) | |||
2332 | 2332 | ||
2333 | strncpy(ha->bios_version, " ?", 8); | 2333 | strncpy(ha->bios_version, " ?", 8); |
2334 | 2334 | ||
2335 | if (ha->device_id == IPS_DEVICEID_COPPERHEAD) { | 2335 | if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) { |
2336 | if (IPS_USE_MEMIO(ha)) { | 2336 | if (IPS_USE_MEMIO(ha)) { |
2337 | /* Memory Mapped I/O */ | 2337 | /* Memory Mapped I/O */ |
2338 | 2338 | ||
2339 | /* test 1st byte */ | 2339 | /* test 1st byte */ |
2340 | writel(0, ha->mem_ptr + IPS_REG_FLAP); | 2340 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
2341 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 2341 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2342 | udelay(25); /* 25 us */ | 2342 | udelay(25); /* 25 us */ |
2343 | 2343 | ||
2344 | if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) | 2344 | if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) |
2345 | return; | 2345 | return; |
2346 | 2346 | ||
2347 | writel(1, ha->mem_ptr + IPS_REG_FLAP); | 2347 | writel(1, ha->mem_ptr + IPS_REG_FLAP); |
2348 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 2348 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2349 | udelay(25); /* 25 us */ | 2349 | udelay(25); /* 25 us */ |
2350 | 2350 | ||
2351 | if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) | 2351 | if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) |
@@ -2353,20 +2353,20 @@ ips_get_bios_version(ips_ha_t * ha, int intr) | |||
2353 | 2353 | ||
2354 | /* Get Major version */ | 2354 | /* Get Major version */ |
2355 | writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP); | 2355 | writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP); |
2356 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 2356 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2357 | udelay(25); /* 25 us */ | 2357 | udelay(25); /* 25 us */ |
2358 | 2358 | ||
2359 | major = readb(ha->mem_ptr + IPS_REG_FLDP); | 2359 | major = readb(ha->mem_ptr + IPS_REG_FLDP); |
2360 | 2360 | ||
2361 | /* Get Minor version */ | 2361 | /* Get Minor version */ |
2362 | writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP); | 2362 | writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP); |
2363 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 2363 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2364 | udelay(25); /* 25 us */ | 2364 | udelay(25); /* 25 us */ |
2365 | minor = readb(ha->mem_ptr + IPS_REG_FLDP); | 2365 | minor = readb(ha->mem_ptr + IPS_REG_FLDP); |
2366 | 2366 | ||
2367 | /* Get SubMinor version */ | 2367 | /* Get SubMinor version */ |
2368 | writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP); | 2368 | writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP); |
2369 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 2369 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2370 | udelay(25); /* 25 us */ | 2370 | udelay(25); /* 25 us */ |
2371 | subminor = readb(ha->mem_ptr + IPS_REG_FLDP); | 2371 | subminor = readb(ha->mem_ptr + IPS_REG_FLDP); |
2372 | 2372 | ||
@@ -2375,14 +2375,14 @@ ips_get_bios_version(ips_ha_t * ha, int intr) | |||
2375 | 2375 | ||
2376 | /* test 1st byte */ | 2376 | /* test 1st byte */ |
2377 | outl(0, ha->io_addr + IPS_REG_FLAP); | 2377 | outl(0, ha->io_addr + IPS_REG_FLAP); |
2378 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 2378 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2379 | udelay(25); /* 25 us */ | 2379 | udelay(25); /* 25 us */ |
2380 | 2380 | ||
2381 | if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) | 2381 | if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) |
2382 | return; | 2382 | return; |
2383 | 2383 | ||
2384 | outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP); | 2384 | outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP); |
2385 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 2385 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2386 | udelay(25); /* 25 us */ | 2386 | udelay(25); /* 25 us */ |
2387 | 2387 | ||
2388 | if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) | 2388 | if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) |
@@ -2390,21 +2390,21 @@ ips_get_bios_version(ips_ha_t * ha, int intr) | |||
2390 | 2390 | ||
2391 | /* Get Major version */ | 2391 | /* Get Major version */ |
2392 | outl(cpu_to_le32(0x1FF), ha->io_addr + IPS_REG_FLAP); | 2392 | outl(cpu_to_le32(0x1FF), ha->io_addr + IPS_REG_FLAP); |
2393 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 2393 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2394 | udelay(25); /* 25 us */ | 2394 | udelay(25); /* 25 us */ |
2395 | 2395 | ||
2396 | major = inb(ha->io_addr + IPS_REG_FLDP); | 2396 | major = inb(ha->io_addr + IPS_REG_FLDP); |
2397 | 2397 | ||
2398 | /* Get Minor version */ | 2398 | /* Get Minor version */ |
2399 | outl(cpu_to_le32(0x1FE), ha->io_addr + IPS_REG_FLAP); | 2399 | outl(cpu_to_le32(0x1FE), ha->io_addr + IPS_REG_FLAP); |
2400 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 2400 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2401 | udelay(25); /* 25 us */ | 2401 | udelay(25); /* 25 us */ |
2402 | 2402 | ||
2403 | minor = inb(ha->io_addr + IPS_REG_FLDP); | 2403 | minor = inb(ha->io_addr + IPS_REG_FLDP); |
2404 | 2404 | ||
2405 | /* Get SubMinor version */ | 2405 | /* Get SubMinor version */ |
2406 | outl(cpu_to_le32(0x1FD), ha->io_addr + IPS_REG_FLAP); | 2406 | outl(cpu_to_le32(0x1FD), ha->io_addr + IPS_REG_FLAP); |
2407 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 2407 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
2408 | udelay(25); /* 25 us */ | 2408 | udelay(25); /* 25 us */ |
2409 | 2409 | ||
2410 | subminor = inb(ha->io_addr + IPS_REG_FLDP); | 2410 | subminor = inb(ha->io_addr + IPS_REG_FLDP); |
@@ -4903,7 +4903,7 @@ ips_init_copperhead(ips_ha_t * ha) | |||
4903 | /* Enable busmastering */ | 4903 | /* Enable busmastering */ |
4904 | outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR); | 4904 | outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR); |
4905 | 4905 | ||
4906 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 4906 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
4907 | /* fix for anaconda64 */ | 4907 | /* fix for anaconda64 */ |
4908 | outl(0, ha->io_addr + IPS_REG_NDAE); | 4908 | outl(0, ha->io_addr + IPS_REG_NDAE); |
4909 | 4909 | ||
@@ -4997,7 +4997,7 @@ ips_init_copperhead_memio(ips_ha_t * ha) | |||
4997 | /* Enable busmastering */ | 4997 | /* Enable busmastering */ |
4998 | writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR); | 4998 | writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR); |
4999 | 4999 | ||
5000 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 5000 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
5001 | /* fix for anaconda64 */ | 5001 | /* fix for anaconda64 */ |
5002 | writel(0, ha->mem_ptr + IPS_REG_NDAE); | 5002 | writel(0, ha->mem_ptr + IPS_REG_NDAE); |
5003 | 5003 | ||
@@ -5142,7 +5142,7 @@ ips_reset_copperhead(ips_ha_t * ha) | |||
5142 | METHOD_TRACE("ips_reset_copperhead", 1); | 5142 | METHOD_TRACE("ips_reset_copperhead", 1); |
5143 | 5143 | ||
5144 | DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d", | 5144 | DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d", |
5145 | ips_name, ha->host_num, ha->io_addr, ha->irq); | 5145 | ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq); |
5146 | 5146 | ||
5147 | reset_counter = 0; | 5147 | reset_counter = 0; |
5148 | 5148 | ||
@@ -5187,7 +5187,7 @@ ips_reset_copperhead_memio(ips_ha_t * ha) | |||
5187 | METHOD_TRACE("ips_reset_copperhead_memio", 1); | 5187 | METHOD_TRACE("ips_reset_copperhead_memio", 1); |
5188 | 5188 | ||
5189 | DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d", | 5189 | DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d", |
5190 | ips_name, ha->host_num, ha->mem_addr, ha->irq); | 5190 | ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq); |
5191 | 5191 | ||
5192 | reset_counter = 0; | 5192 | reset_counter = 0; |
5193 | 5193 | ||
@@ -5233,7 +5233,7 @@ ips_reset_morpheus(ips_ha_t * ha) | |||
5233 | METHOD_TRACE("ips_reset_morpheus", 1); | 5233 | METHOD_TRACE("ips_reset_morpheus", 1); |
5234 | 5234 | ||
5235 | DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d", | 5235 | DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d", |
5236 | ips_name, ha->host_num, ha->mem_addr, ha->irq); | 5236 | ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq); |
5237 | 5237 | ||
5238 | reset_counter = 0; | 5238 | reset_counter = 0; |
5239 | 5239 | ||
@@ -6196,32 +6196,32 @@ ips_erase_bios(ips_ha_t * ha) | |||
6196 | 6196 | ||
6197 | /* Clear the status register */ | 6197 | /* Clear the status register */ |
6198 | outl(0, ha->io_addr + IPS_REG_FLAP); | 6198 | outl(0, ha->io_addr + IPS_REG_FLAP); |
6199 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6199 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6200 | udelay(25); /* 25 us */ | 6200 | udelay(25); /* 25 us */ |
6201 | 6201 | ||
6202 | outb(0x50, ha->io_addr + IPS_REG_FLDP); | 6202 | outb(0x50, ha->io_addr + IPS_REG_FLDP); |
6203 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6203 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6204 | udelay(25); /* 25 us */ | 6204 | udelay(25); /* 25 us */ |
6205 | 6205 | ||
6206 | /* Erase Setup */ | 6206 | /* Erase Setup */ |
6207 | outb(0x20, ha->io_addr + IPS_REG_FLDP); | 6207 | outb(0x20, ha->io_addr + IPS_REG_FLDP); |
6208 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6208 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6209 | udelay(25); /* 25 us */ | 6209 | udelay(25); /* 25 us */ |
6210 | 6210 | ||
6211 | /* Erase Confirm */ | 6211 | /* Erase Confirm */ |
6212 | outb(0xD0, ha->io_addr + IPS_REG_FLDP); | 6212 | outb(0xD0, ha->io_addr + IPS_REG_FLDP); |
6213 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6213 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6214 | udelay(25); /* 25 us */ | 6214 | udelay(25); /* 25 us */ |
6215 | 6215 | ||
6216 | /* Erase Status */ | 6216 | /* Erase Status */ |
6217 | outb(0x70, ha->io_addr + IPS_REG_FLDP); | 6217 | outb(0x70, ha->io_addr + IPS_REG_FLDP); |
6218 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6218 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6219 | udelay(25); /* 25 us */ | 6219 | udelay(25); /* 25 us */ |
6220 | 6220 | ||
6221 | timeout = 80000; /* 80 seconds */ | 6221 | timeout = 80000; /* 80 seconds */ |
6222 | 6222 | ||
6223 | while (timeout > 0) { | 6223 | while (timeout > 0) { |
6224 | if (ha->revision_id == IPS_REVID_TROMBONE64) { | 6224 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { |
6225 | outl(0, ha->io_addr + IPS_REG_FLAP); | 6225 | outl(0, ha->io_addr + IPS_REG_FLAP); |
6226 | udelay(25); /* 25 us */ | 6226 | udelay(25); /* 25 us */ |
6227 | } | 6227 | } |
@@ -6241,13 +6241,13 @@ ips_erase_bios(ips_ha_t * ha) | |||
6241 | 6241 | ||
6242 | /* try to suspend the erase */ | 6242 | /* try to suspend the erase */ |
6243 | outb(0xB0, ha->io_addr + IPS_REG_FLDP); | 6243 | outb(0xB0, ha->io_addr + IPS_REG_FLDP); |
6244 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6244 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6245 | udelay(25); /* 25 us */ | 6245 | udelay(25); /* 25 us */ |
6246 | 6246 | ||
6247 | /* wait for 10 seconds */ | 6247 | /* wait for 10 seconds */ |
6248 | timeout = 10000; | 6248 | timeout = 10000; |
6249 | while (timeout > 0) { | 6249 | while (timeout > 0) { |
6250 | if (ha->revision_id == IPS_REVID_TROMBONE64) { | 6250 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { |
6251 | outl(0, ha->io_addr + IPS_REG_FLAP); | 6251 | outl(0, ha->io_addr + IPS_REG_FLAP); |
6252 | udelay(25); /* 25 us */ | 6252 | udelay(25); /* 25 us */ |
6253 | } | 6253 | } |
@@ -6277,12 +6277,12 @@ ips_erase_bios(ips_ha_t * ha) | |||
6277 | /* Otherwise, we were successful */ | 6277 | /* Otherwise, we were successful */ |
6278 | /* clear status */ | 6278 | /* clear status */ |
6279 | outb(0x50, ha->io_addr + IPS_REG_FLDP); | 6279 | outb(0x50, ha->io_addr + IPS_REG_FLDP); |
6280 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6280 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6281 | udelay(25); /* 25 us */ | 6281 | udelay(25); /* 25 us */ |
6282 | 6282 | ||
6283 | /* enable reads */ | 6283 | /* enable reads */ |
6284 | outb(0xFF, ha->io_addr + IPS_REG_FLDP); | 6284 | outb(0xFF, ha->io_addr + IPS_REG_FLDP); |
6285 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6285 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6286 | udelay(25); /* 25 us */ | 6286 | udelay(25); /* 25 us */ |
6287 | 6287 | ||
6288 | return (0); | 6288 | return (0); |
@@ -6308,32 +6308,32 @@ ips_erase_bios_memio(ips_ha_t * ha) | |||
6308 | 6308 | ||
6309 | /* Clear the status register */ | 6309 | /* Clear the status register */ |
6310 | writel(0, ha->mem_ptr + IPS_REG_FLAP); | 6310 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
6311 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6311 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6312 | udelay(25); /* 25 us */ | 6312 | udelay(25); /* 25 us */ |
6313 | 6313 | ||
6314 | writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); | 6314 | writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); |
6315 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6315 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6316 | udelay(25); /* 25 us */ | 6316 | udelay(25); /* 25 us */ |
6317 | 6317 | ||
6318 | /* Erase Setup */ | 6318 | /* Erase Setup */ |
6319 | writeb(0x20, ha->mem_ptr + IPS_REG_FLDP); | 6319 | writeb(0x20, ha->mem_ptr + IPS_REG_FLDP); |
6320 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6320 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6321 | udelay(25); /* 25 us */ | 6321 | udelay(25); /* 25 us */ |
6322 | 6322 | ||
6323 | /* Erase Confirm */ | 6323 | /* Erase Confirm */ |
6324 | writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP); | 6324 | writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP); |
6325 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6325 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6326 | udelay(25); /* 25 us */ | 6326 | udelay(25); /* 25 us */ |
6327 | 6327 | ||
6328 | /* Erase Status */ | 6328 | /* Erase Status */ |
6329 | writeb(0x70, ha->mem_ptr + IPS_REG_FLDP); | 6329 | writeb(0x70, ha->mem_ptr + IPS_REG_FLDP); |
6330 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6330 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6331 | udelay(25); /* 25 us */ | 6331 | udelay(25); /* 25 us */ |
6332 | 6332 | ||
6333 | timeout = 80000; /* 80 seconds */ | 6333 | timeout = 80000; /* 80 seconds */ |
6334 | 6334 | ||
6335 | while (timeout > 0) { | 6335 | while (timeout > 0) { |
6336 | if (ha->revision_id == IPS_REVID_TROMBONE64) { | 6336 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { |
6337 | writel(0, ha->mem_ptr + IPS_REG_FLAP); | 6337 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
6338 | udelay(25); /* 25 us */ | 6338 | udelay(25); /* 25 us */ |
6339 | } | 6339 | } |
@@ -6353,13 +6353,13 @@ ips_erase_bios_memio(ips_ha_t * ha) | |||
6353 | 6353 | ||
6354 | /* try to suspend the erase */ | 6354 | /* try to suspend the erase */ |
6355 | writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP); | 6355 | writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP); |
6356 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6356 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6357 | udelay(25); /* 25 us */ | 6357 | udelay(25); /* 25 us */ |
6358 | 6358 | ||
6359 | /* wait for 10 seconds */ | 6359 | /* wait for 10 seconds */ |
6360 | timeout = 10000; | 6360 | timeout = 10000; |
6361 | while (timeout > 0) { | 6361 | while (timeout > 0) { |
6362 | if (ha->revision_id == IPS_REVID_TROMBONE64) { | 6362 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { |
6363 | writel(0, ha->mem_ptr + IPS_REG_FLAP); | 6363 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
6364 | udelay(25); /* 25 us */ | 6364 | udelay(25); /* 25 us */ |
6365 | } | 6365 | } |
@@ -6389,12 +6389,12 @@ ips_erase_bios_memio(ips_ha_t * ha) | |||
6389 | /* Otherwise, we were successful */ | 6389 | /* Otherwise, we were successful */ |
6390 | /* clear status */ | 6390 | /* clear status */ |
6391 | writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); | 6391 | writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); |
6392 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6392 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6393 | udelay(25); /* 25 us */ | 6393 | udelay(25); /* 25 us */ |
6394 | 6394 | ||
6395 | /* enable reads */ | 6395 | /* enable reads */ |
6396 | writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); | 6396 | writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); |
6397 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6397 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6398 | udelay(25); /* 25 us */ | 6398 | udelay(25); /* 25 us */ |
6399 | 6399 | ||
6400 | return (0); | 6400 | return (0); |
@@ -6423,21 +6423,21 @@ ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, | |||
6423 | for (i = 0; i < buffersize; i++) { | 6423 | for (i = 0; i < buffersize; i++) { |
6424 | /* write a byte */ | 6424 | /* write a byte */ |
6425 | outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP); | 6425 | outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP); |
6426 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6426 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6427 | udelay(25); /* 25 us */ | 6427 | udelay(25); /* 25 us */ |
6428 | 6428 | ||
6429 | outb(0x40, ha->io_addr + IPS_REG_FLDP); | 6429 | outb(0x40, ha->io_addr + IPS_REG_FLDP); |
6430 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6430 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6431 | udelay(25); /* 25 us */ | 6431 | udelay(25); /* 25 us */ |
6432 | 6432 | ||
6433 | outb(buffer[i], ha->io_addr + IPS_REG_FLDP); | 6433 | outb(buffer[i], ha->io_addr + IPS_REG_FLDP); |
6434 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6434 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6435 | udelay(25); /* 25 us */ | 6435 | udelay(25); /* 25 us */ |
6436 | 6436 | ||
6437 | /* wait up to one second */ | 6437 | /* wait up to one second */ |
6438 | timeout = 1000; | 6438 | timeout = 1000; |
6439 | while (timeout > 0) { | 6439 | while (timeout > 0) { |
6440 | if (ha->revision_id == IPS_REVID_TROMBONE64) { | 6440 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { |
6441 | outl(0, ha->io_addr + IPS_REG_FLAP); | 6441 | outl(0, ha->io_addr + IPS_REG_FLAP); |
6442 | udelay(25); /* 25 us */ | 6442 | udelay(25); /* 25 us */ |
6443 | } | 6443 | } |
@@ -6454,11 +6454,11 @@ ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, | |||
6454 | if (timeout == 0) { | 6454 | if (timeout == 0) { |
6455 | /* timeout error */ | 6455 | /* timeout error */ |
6456 | outl(0, ha->io_addr + IPS_REG_FLAP); | 6456 | outl(0, ha->io_addr + IPS_REG_FLAP); |
6457 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6457 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6458 | udelay(25); /* 25 us */ | 6458 | udelay(25); /* 25 us */ |
6459 | 6459 | ||
6460 | outb(0xFF, ha->io_addr + IPS_REG_FLDP); | 6460 | outb(0xFF, ha->io_addr + IPS_REG_FLDP); |
6461 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6461 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6462 | udelay(25); /* 25 us */ | 6462 | udelay(25); /* 25 us */ |
6463 | 6463 | ||
6464 | return (1); | 6464 | return (1); |
@@ -6468,11 +6468,11 @@ ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, | |||
6468 | if (status & 0x18) { | 6468 | if (status & 0x18) { |
6469 | /* programming error */ | 6469 | /* programming error */ |
6470 | outl(0, ha->io_addr + IPS_REG_FLAP); | 6470 | outl(0, ha->io_addr + IPS_REG_FLAP); |
6471 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6471 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6472 | udelay(25); /* 25 us */ | 6472 | udelay(25); /* 25 us */ |
6473 | 6473 | ||
6474 | outb(0xFF, ha->io_addr + IPS_REG_FLDP); | 6474 | outb(0xFF, ha->io_addr + IPS_REG_FLDP); |
6475 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6475 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6476 | udelay(25); /* 25 us */ | 6476 | udelay(25); /* 25 us */ |
6477 | 6477 | ||
6478 | return (1); | 6478 | return (1); |
@@ -6481,11 +6481,11 @@ ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, | |||
6481 | 6481 | ||
6482 | /* Enable reading */ | 6482 | /* Enable reading */ |
6483 | outl(0, ha->io_addr + IPS_REG_FLAP); | 6483 | outl(0, ha->io_addr + IPS_REG_FLAP); |
6484 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6484 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6485 | udelay(25); /* 25 us */ | 6485 | udelay(25); /* 25 us */ |
6486 | 6486 | ||
6487 | outb(0xFF, ha->io_addr + IPS_REG_FLDP); | 6487 | outb(0xFF, ha->io_addr + IPS_REG_FLDP); |
6488 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6488 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6489 | udelay(25); /* 25 us */ | 6489 | udelay(25); /* 25 us */ |
6490 | 6490 | ||
6491 | return (0); | 6491 | return (0); |
@@ -6514,21 +6514,21 @@ ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, | |||
6514 | for (i = 0; i < buffersize; i++) { | 6514 | for (i = 0; i < buffersize; i++) { |
6515 | /* write a byte */ | 6515 | /* write a byte */ |
6516 | writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); | 6516 | writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); |
6517 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6517 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6518 | udelay(25); /* 25 us */ | 6518 | udelay(25); /* 25 us */ |
6519 | 6519 | ||
6520 | writeb(0x40, ha->mem_ptr + IPS_REG_FLDP); | 6520 | writeb(0x40, ha->mem_ptr + IPS_REG_FLDP); |
6521 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6521 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6522 | udelay(25); /* 25 us */ | 6522 | udelay(25); /* 25 us */ |
6523 | 6523 | ||
6524 | writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP); | 6524 | writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP); |
6525 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6525 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6526 | udelay(25); /* 25 us */ | 6526 | udelay(25); /* 25 us */ |
6527 | 6527 | ||
6528 | /* wait up to one second */ | 6528 | /* wait up to one second */ |
6529 | timeout = 1000; | 6529 | timeout = 1000; |
6530 | while (timeout > 0) { | 6530 | while (timeout > 0) { |
6531 | if (ha->revision_id == IPS_REVID_TROMBONE64) { | 6531 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { |
6532 | writel(0, ha->mem_ptr + IPS_REG_FLAP); | 6532 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
6533 | udelay(25); /* 25 us */ | 6533 | udelay(25); /* 25 us */ |
6534 | } | 6534 | } |
@@ -6545,11 +6545,11 @@ ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, | |||
6545 | if (timeout == 0) { | 6545 | if (timeout == 0) { |
6546 | /* timeout error */ | 6546 | /* timeout error */ |
6547 | writel(0, ha->mem_ptr + IPS_REG_FLAP); | 6547 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
6548 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6548 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6549 | udelay(25); /* 25 us */ | 6549 | udelay(25); /* 25 us */ |
6550 | 6550 | ||
6551 | writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); | 6551 | writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); |
6552 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6552 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6553 | udelay(25); /* 25 us */ | 6553 | udelay(25); /* 25 us */ |
6554 | 6554 | ||
6555 | return (1); | 6555 | return (1); |
@@ -6559,11 +6559,11 @@ ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, | |||
6559 | if (status & 0x18) { | 6559 | if (status & 0x18) { |
6560 | /* programming error */ | 6560 | /* programming error */ |
6561 | writel(0, ha->mem_ptr + IPS_REG_FLAP); | 6561 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
6562 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6562 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6563 | udelay(25); /* 25 us */ | 6563 | udelay(25); /* 25 us */ |
6564 | 6564 | ||
6565 | writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); | 6565 | writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); |
6566 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6566 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6567 | udelay(25); /* 25 us */ | 6567 | udelay(25); /* 25 us */ |
6568 | 6568 | ||
6569 | return (1); | 6569 | return (1); |
@@ -6572,11 +6572,11 @@ ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, | |||
6572 | 6572 | ||
6573 | /* Enable reading */ | 6573 | /* Enable reading */ |
6574 | writel(0, ha->mem_ptr + IPS_REG_FLAP); | 6574 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
6575 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6575 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6576 | udelay(25); /* 25 us */ | 6576 | udelay(25); /* 25 us */ |
6577 | 6577 | ||
6578 | writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); | 6578 | writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); |
6579 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6579 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6580 | udelay(25); /* 25 us */ | 6580 | udelay(25); /* 25 us */ |
6581 | 6581 | ||
6582 | return (0); | 6582 | return (0); |
@@ -6601,14 +6601,14 @@ ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, | |||
6601 | 6601 | ||
6602 | /* test 1st byte */ | 6602 | /* test 1st byte */ |
6603 | outl(0, ha->io_addr + IPS_REG_FLAP); | 6603 | outl(0, ha->io_addr + IPS_REG_FLAP); |
6604 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6604 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6605 | udelay(25); /* 25 us */ | 6605 | udelay(25); /* 25 us */ |
6606 | 6606 | ||
6607 | if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) | 6607 | if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) |
6608 | return (1); | 6608 | return (1); |
6609 | 6609 | ||
6610 | outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP); | 6610 | outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP); |
6611 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6611 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6612 | udelay(25); /* 25 us */ | 6612 | udelay(25); /* 25 us */ |
6613 | if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) | 6613 | if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) |
6614 | return (1); | 6614 | return (1); |
@@ -6617,7 +6617,7 @@ ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, | |||
6617 | for (i = 2; i < buffersize; i++) { | 6617 | for (i = 2; i < buffersize; i++) { |
6618 | 6618 | ||
6619 | outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP); | 6619 | outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP); |
6620 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6620 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6621 | udelay(25); /* 25 us */ | 6621 | udelay(25); /* 25 us */ |
6622 | 6622 | ||
6623 | checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP); | 6623 | checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP); |
@@ -6650,14 +6650,14 @@ ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, | |||
6650 | 6650 | ||
6651 | /* test 1st byte */ | 6651 | /* test 1st byte */ |
6652 | writel(0, ha->mem_ptr + IPS_REG_FLAP); | 6652 | writel(0, ha->mem_ptr + IPS_REG_FLAP); |
6653 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6653 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6654 | udelay(25); /* 25 us */ | 6654 | udelay(25); /* 25 us */ |
6655 | 6655 | ||
6656 | if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) | 6656 | if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) |
6657 | return (1); | 6657 | return (1); |
6658 | 6658 | ||
6659 | writel(1, ha->mem_ptr + IPS_REG_FLAP); | 6659 | writel(1, ha->mem_ptr + IPS_REG_FLAP); |
6660 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6660 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6661 | udelay(25); /* 25 us */ | 6661 | udelay(25); /* 25 us */ |
6662 | if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) | 6662 | if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) |
6663 | return (1); | 6663 | return (1); |
@@ -6666,7 +6666,7 @@ ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, | |||
6666 | for (i = 2; i < buffersize; i++) { | 6666 | for (i = 2; i < buffersize; i++) { |
6667 | 6667 | ||
6668 | writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); | 6668 | writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); |
6669 | if (ha->revision_id == IPS_REVID_TROMBONE64) | 6669 | if (ha->pcidev->revision == IPS_REVID_TROMBONE64) |
6670 | udelay(25); /* 25 us */ | 6670 | udelay(25); /* 25 us */ |
6671 | 6671 | ||
6672 | checksum = | 6672 | checksum = |
@@ -6837,9 +6837,9 @@ ips_register_scsi(int index) | |||
6837 | } | 6837 | } |
6838 | ha = IPS_HA(sh); | 6838 | ha = IPS_HA(sh); |
6839 | memcpy(ha, oldha, sizeof (ips_ha_t)); | 6839 | memcpy(ha, oldha, sizeof (ips_ha_t)); |
6840 | free_irq(oldha->irq, oldha); | 6840 | free_irq(oldha->pcidev->irq, oldha); |
6841 | /* Install the interrupt handler with the new ha */ | 6841 | /* Install the interrupt handler with the new ha */ |
6842 | if (request_irq(ha->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) { | 6842 | if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) { |
6843 | IPS_PRINTK(KERN_WARNING, ha->pcidev, | 6843 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
6844 | "Unable to install interrupt handler\n"); | 6844 | "Unable to install interrupt handler\n"); |
6845 | scsi_host_put(sh); | 6845 | scsi_host_put(sh); |
@@ -6851,10 +6851,7 @@ ips_register_scsi(int index) | |||
6851 | ips_ha[index] = ha; | 6851 | ips_ha[index] = ha; |
6852 | 6852 | ||
6853 | /* Store away needed values for later use */ | 6853 | /* Store away needed values for later use */ |
6854 | sh->io_port = ha->io_addr; | ||
6855 | sh->n_io_port = ha->io_addr ? 255 : 0; | ||
6856 | sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr; | 6854 | sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr; |
6857 | sh->irq = ha->irq; | ||
6858 | sh->sg_tablesize = sh->hostt->sg_tablesize; | 6855 | sh->sg_tablesize = sh->hostt->sg_tablesize; |
6859 | sh->can_queue = sh->hostt->can_queue; | 6856 | sh->can_queue = sh->hostt->can_queue; |
6860 | sh->cmd_per_lun = sh->hostt->cmd_per_lun; | 6857 | sh->cmd_per_lun = sh->hostt->cmd_per_lun; |
@@ -6992,8 +6989,6 @@ ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr) | |||
6992 | uint32_t mem_len; | 6989 | uint32_t mem_len; |
6993 | uint8_t bus; | 6990 | uint8_t bus; |
6994 | uint8_t func; | 6991 | uint8_t func; |
6995 | uint8_t irq; | ||
6996 | uint16_t subdevice_id; | ||
6997 | int j; | 6992 | int j; |
6998 | int index; | 6993 | int index; |
6999 | dma_addr_t dma_address; | 6994 | dma_addr_t dma_address; |
@@ -7014,7 +7009,6 @@ ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr) | |||
7014 | return -1; | 7009 | return -1; |
7015 | 7010 | ||
7016 | /* stuff that we get in dev */ | 7011 | /* stuff that we get in dev */ |
7017 | irq = pci_dev->irq; | ||
7018 | bus = pci_dev->bus->number; | 7012 | bus = pci_dev->bus->number; |
7019 | func = pci_dev->devfn; | 7013 | func = pci_dev->devfn; |
7020 | 7014 | ||
@@ -7068,8 +7062,6 @@ ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr) | |||
7068 | } | 7062 | } |
7069 | } | 7063 | } |
7070 | 7064 | ||
7071 | subdevice_id = pci_dev->subsystem_device; | ||
7072 | |||
7073 | /* found a controller */ | 7065 | /* found a controller */ |
7074 | ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL); | 7066 | ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL); |
7075 | if (ha == NULL) { | 7067 | if (ha == NULL) { |
@@ -7084,7 +7076,6 @@ ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr) | |||
7084 | ha->active = 1; | 7076 | ha->active = 1; |
7085 | 7077 | ||
7086 | /* Store info in HA structure */ | 7078 | /* Store info in HA structure */ |
7087 | ha->irq = irq; | ||
7088 | ha->io_addr = io_addr; | 7079 | ha->io_addr = io_addr; |
7089 | ha->io_len = io_len; | 7080 | ha->io_len = io_len; |
7090 | ha->mem_addr = mem_addr; | 7081 | ha->mem_addr = mem_addr; |
@@ -7092,10 +7083,7 @@ ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr) | |||
7092 | ha->mem_ptr = mem_ptr; | 7083 | ha->mem_ptr = mem_ptr; |
7093 | ha->ioremap_ptr = ioremap_ptr; | 7084 | ha->ioremap_ptr = ioremap_ptr; |
7094 | ha->host_num = (uint32_t) index; | 7085 | ha->host_num = (uint32_t) index; |
7095 | ha->revision_id = pci_dev->revision; | ||
7096 | ha->slot_num = PCI_SLOT(pci_dev->devfn); | 7086 | ha->slot_num = PCI_SLOT(pci_dev->devfn); |
7097 | ha->device_id = pci_dev->device; | ||
7098 | ha->subdevice_id = subdevice_id; | ||
7099 | ha->pcidev = pci_dev; | 7087 | ha->pcidev = pci_dev; |
7100 | 7088 | ||
7101 | /* | 7089 | /* |
@@ -7240,7 +7228,7 @@ ips_init_phase2(int index) | |||
7240 | } | 7228 | } |
7241 | 7229 | ||
7242 | /* Install the interrupt handler */ | 7230 | /* Install the interrupt handler */ |
7243 | if (request_irq(ha->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) { | 7231 | if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) { |
7244 | IPS_PRINTK(KERN_WARNING, ha->pcidev, | 7232 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
7245 | "Unable to install interrupt handler\n"); | 7233 | "Unable to install interrupt handler\n"); |
7246 | return ips_abort_init(ha, index); | 7234 | return ips_abort_init(ha, index); |
@@ -7253,14 +7241,14 @@ ips_init_phase2(int index) | |||
7253 | if (!ips_allocatescbs(ha)) { | 7241 | if (!ips_allocatescbs(ha)) { |
7254 | IPS_PRINTK(KERN_WARNING, ha->pcidev, | 7242 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
7255 | "Unable to allocate a CCB\n"); | 7243 | "Unable to allocate a CCB\n"); |
7256 | free_irq(ha->irq, ha); | 7244 | free_irq(ha->pcidev->irq, ha); |
7257 | return ips_abort_init(ha, index); | 7245 | return ips_abort_init(ha, index); |
7258 | } | 7246 | } |
7259 | 7247 | ||
7260 | if (!ips_hainit(ha)) { | 7248 | if (!ips_hainit(ha)) { |
7261 | IPS_PRINTK(KERN_WARNING, ha->pcidev, | 7249 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
7262 | "Unable to initialize controller\n"); | 7250 | "Unable to initialize controller\n"); |
7263 | free_irq(ha->irq, ha); | 7251 | free_irq(ha->pcidev->irq, ha); |
7264 | return ips_abort_init(ha, index); | 7252 | return ips_abort_init(ha, index); |
7265 | } | 7253 | } |
7266 | /* Free the temporary SCB */ | 7254 | /* Free the temporary SCB */ |
@@ -7270,7 +7258,7 @@ ips_init_phase2(int index) | |||
7270 | if (!ips_allocatescbs(ha)) { | 7258 | if (!ips_allocatescbs(ha)) { |
7271 | IPS_PRINTK(KERN_WARNING, ha->pcidev, | 7259 | IPS_PRINTK(KERN_WARNING, ha->pcidev, |
7272 | "Unable to allocate CCBs\n"); | 7260 | "Unable to allocate CCBs\n"); |
7273 | free_irq(ha->irq, ha); | 7261 | free_irq(ha->pcidev->irq, ha); |
7274 | return ips_abort_init(ha, index); | 7262 | return ips_abort_init(ha, index); |
7275 | } | 7263 | } |
7276 | 7264 | ||