aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/scsi/ipr.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/scsi/ipr.h')
-rw-r--r--drivers/scsi/ipr.h467
1 files changed, 363 insertions, 104 deletions
diff --git a/drivers/scsi/ipr.h b/drivers/scsi/ipr.h
index 19bbcf39f0c9..4c267b5e0b96 100644
--- a/drivers/scsi/ipr.h
+++ b/drivers/scsi/ipr.h
@@ -37,8 +37,8 @@
37/* 37/*
38 * Literals 38 * Literals
39 */ 39 */
40#define IPR_DRIVER_VERSION "2.4.3" 40#define IPR_DRIVER_VERSION "2.5.0"
41#define IPR_DRIVER_DATE "(June 10, 2009)" 41#define IPR_DRIVER_DATE "(February 11, 2010)"
42 42
43/* 43/*
44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding 44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
@@ -55,7 +55,9 @@
55#define IPR_NUM_BASE_CMD_BLKS 100 55#define IPR_NUM_BASE_CMD_BLKS 100
56 56
57#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339 57#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
58#define PCI_DEVICE_ID_IBM_SCAMP_E 0x034A 58
59#define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
60#define PCI_DEVICE_ID_IBM_CROC_ASIC_E2 0x034A
59 61
60#define IPR_SUBS_DEV_ID_2780 0x0264 62#define IPR_SUBS_DEV_ID_2780 0x0264
61#define IPR_SUBS_DEV_ID_5702 0x0266 63#define IPR_SUBS_DEV_ID_5702 0x0266
@@ -70,15 +72,24 @@
70#define IPR_SUBS_DEV_ID_572A 0x02C1 72#define IPR_SUBS_DEV_ID_572A 0x02C1
71#define IPR_SUBS_DEV_ID_572B 0x02C2 73#define IPR_SUBS_DEV_ID_572B 0x02C2
72#define IPR_SUBS_DEV_ID_572F 0x02C3 74#define IPR_SUBS_DEV_ID_572F 0x02C3
73#define IPR_SUBS_DEV_ID_574D 0x030B
74#define IPR_SUBS_DEV_ID_574E 0x030A 75#define IPR_SUBS_DEV_ID_574E 0x030A
75#define IPR_SUBS_DEV_ID_575B 0x030D 76#define IPR_SUBS_DEV_ID_575B 0x030D
76#define IPR_SUBS_DEV_ID_575C 0x0338 77#define IPR_SUBS_DEV_ID_575C 0x0338
77#define IPR_SUBS_DEV_ID_575D 0x033E
78#define IPR_SUBS_DEV_ID_57B3 0x033A 78#define IPR_SUBS_DEV_ID_57B3 0x033A
79#define IPR_SUBS_DEV_ID_57B7 0x0360 79#define IPR_SUBS_DEV_ID_57B7 0x0360
80#define IPR_SUBS_DEV_ID_57B8 0x02C2 80#define IPR_SUBS_DEV_ID_57B8 0x02C2
81 81
82#define IPR_SUBS_DEV_ID_57B4 0x033B
83#define IPR_SUBS_DEV_ID_57B2 0x035F
84#define IPR_SUBS_DEV_ID_57C6 0x0357
85
86#define IPR_SUBS_DEV_ID_57B5 0x033C
87#define IPR_SUBS_DEV_ID_57CE 0x035E
88#define IPR_SUBS_DEV_ID_57B1 0x0355
89
90#define IPR_SUBS_DEV_ID_574D 0x0356
91#define IPR_SUBS_DEV_ID_575D 0x035D
92
82#define IPR_NAME "ipr" 93#define IPR_NAME "ipr"
83 94
84/* 95/*
@@ -118,6 +129,10 @@
118#define IPR_NUM_LOG_HCAMS 2 129#define IPR_NUM_LOG_HCAMS 2
119#define IPR_NUM_CFG_CHG_HCAMS 2 130#define IPR_NUM_CFG_CHG_HCAMS 2
120#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS) 131#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
132
133#define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
134#define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
135
121#define IPR_MAX_NUM_TARGETS_PER_BUS 256 136#define IPR_MAX_NUM_TARGETS_PER_BUS 256
122#define IPR_MAX_NUM_LUNS_PER_TARGET 256 137#define IPR_MAX_NUM_LUNS_PER_TARGET 256
123#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8 138#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
@@ -132,13 +147,15 @@
132 147
133/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */ 148/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
134#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \ 149#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
135 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3) 150 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
136 151
137#define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS 152#define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
138#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \ 153#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
139 IPR_NUM_INTERNAL_CMD_BLKS) 154 IPR_NUM_INTERNAL_CMD_BLKS)
140 155
141#define IPR_MAX_PHYSICAL_DEVS 192 156#define IPR_MAX_PHYSICAL_DEVS 192
157#define IPR_DEFAULT_SIS64_DEVS 1024
158#define IPR_MAX_SIS64_DEVS 4096
142 159
143#define IPR_MAX_SGLIST 64 160#define IPR_MAX_SGLIST 64
144#define IPR_IOA_MAX_SECTORS 32767 161#define IPR_IOA_MAX_SECTORS 32767
@@ -173,6 +190,7 @@
173#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01 190#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
174#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02 191#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
175#define IPR_SET_SUPPORTED_DEVICES 0xFB 192#define IPR_SET_SUPPORTED_DEVICES 0xFB
193#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
176#define IPR_IOA_SHUTDOWN 0xF7 194#define IPR_IOA_SHUTDOWN 0xF7
177#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05 195#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
178 196
@@ -221,9 +239,17 @@
221#define IPR_SDT_FMT2_BAR5_SEL 0x5 239#define IPR_SDT_FMT2_BAR5_SEL 0x5
222#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8 240#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
223#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2 241#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
242#define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
224#define IPR_DOORBELL 0x82800000 243#define IPR_DOORBELL 0x82800000
225#define IPR_RUNTIME_RESET 0x40000000 244#define IPR_RUNTIME_RESET 0x40000000
226 245
246#define IPR_IPL_INIT_MIN_STAGE_TIME 5
247#define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
248#define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
249#define IPR_IPL_INIT_STAGE_MASK 0xff000000
250#define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
251#define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
252
227#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0) 253#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
228#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3) 254#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
229#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4) 255#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
@@ -318,27 +344,27 @@ struct ipr_std_inq_data {
318 u8 serial_num[IPR_SERIAL_NUM_LEN]; 344 u8 serial_num[IPR_SERIAL_NUM_LEN];
319}__attribute__ ((packed)); 345}__attribute__ ((packed));
320 346
347#define IPR_RES_TYPE_AF_DASD 0x00
348#define IPR_RES_TYPE_GENERIC_SCSI 0x01
349#define IPR_RES_TYPE_VOLUME_SET 0x02
350#define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
351#define IPR_RES_TYPE_GENERIC_ATA 0x04
352#define IPR_RES_TYPE_ARRAY 0x05
353#define IPR_RES_TYPE_IOAFP 0xff
354
321struct ipr_config_table_entry { 355struct ipr_config_table_entry {
322 u8 proto; 356 u8 proto;
323#define IPR_PROTO_SATA 0x02 357#define IPR_PROTO_SATA 0x02
324#define IPR_PROTO_SATA_ATAPI 0x03 358#define IPR_PROTO_SATA_ATAPI 0x03
325#define IPR_PROTO_SAS_STP 0x06 359#define IPR_PROTO_SAS_STP 0x06
326#define IPR_PROTO_SAS_STP_ATAPI 0x07 360#define IPR_PROTO_SAS_STP_ATAPI 0x07
327 u8 array_id; 361 u8 array_id;
328 u8 flags; 362 u8 flags;
329#define IPR_IS_IOA_RESOURCE 0x80 363#define IPR_IS_IOA_RESOURCE 0x80
330#define IPR_IS_ARRAY_MEMBER 0x20
331#define IPR_IS_HOT_SPARE 0x10
332
333 u8 rsvd_subtype; 364 u8 rsvd_subtype;
334#define IPR_RES_SUBTYPE(res) (((res)->cfgte.rsvd_subtype) & 0x0f) 365
335#define IPR_SUBTYPE_AF_DASD 0 366#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
336#define IPR_SUBTYPE_GENERIC_SCSI 1 367#define IPR_QUEUE_FROZEN_MODEL 0
337#define IPR_SUBTYPE_VOLUME_SET 2
338#define IPR_SUBTYPE_GENERIC_ATA 4
339
340#define IPR_QUEUEING_MODEL(res) ((((res)->cfgte.flags) & 0x70) >> 4)
341#define IPR_QUEUE_FROZEN_MODEL 0
342#define IPR_QUEUE_NACA_MODEL 1 368#define IPR_QUEUE_NACA_MODEL 1
343 369
344 struct ipr_res_addr res_addr; 370 struct ipr_res_addr res_addr;
@@ -347,6 +373,28 @@ struct ipr_config_table_entry {
347 struct ipr_std_inq_data std_inq_data; 373 struct ipr_std_inq_data std_inq_data;
348}__attribute__ ((packed, aligned (4))); 374}__attribute__ ((packed, aligned (4)));
349 375
376struct ipr_config_table_entry64 {
377 u8 res_type;
378 u8 proto;
379 u8 vset_num;
380 u8 array_id;
381 __be16 flags;
382 __be16 res_flags;
383#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
384 __be32 res_handle;
385 u8 dev_id_type;
386 u8 reserved[3];
387 __be64 dev_id;
388 __be64 lun;
389 __be64 lun_wwn[2];
390#define IPR_MAX_RES_PATH_LENGTH 24
391 __be64 res_path;
392 struct ipr_std_inq_data std_inq_data;
393 u8 reserved2[4];
394 __be64 reserved3[2]; // description text
395 u8 reserved4[8];
396}__attribute__ ((packed, aligned (8)));
397
350struct ipr_config_table_hdr { 398struct ipr_config_table_hdr {
351 u8 num_entries; 399 u8 num_entries;
352 u8 flags; 400 u8 flags;
@@ -354,13 +402,35 @@ struct ipr_config_table_hdr {
354 __be16 reserved; 402 __be16 reserved;
355}__attribute__((packed, aligned (4))); 403}__attribute__((packed, aligned (4)));
356 404
405struct ipr_config_table_hdr64 {
406 __be16 num_entries;
407 __be16 reserved;
408 u8 flags;
409 u8 reserved2[11];
410}__attribute__((packed, aligned (4)));
411
357struct ipr_config_table { 412struct ipr_config_table {
358 struct ipr_config_table_hdr hdr; 413 struct ipr_config_table_hdr hdr;
359 struct ipr_config_table_entry dev[IPR_MAX_PHYSICAL_DEVS]; 414 struct ipr_config_table_entry dev[0];
360}__attribute__((packed, aligned (4))); 415}__attribute__((packed, aligned (4)));
361 416
417struct ipr_config_table64 {
418 struct ipr_config_table_hdr64 hdr64;
419 struct ipr_config_table_entry64 dev[0];
420}__attribute__((packed, aligned (8)));
421
422struct ipr_config_table_entry_wrapper {
423 union {
424 struct ipr_config_table_entry *cfgte;
425 struct ipr_config_table_entry64 *cfgte64;
426 } u;
427};
428
362struct ipr_hostrcb_cfg_ch_not { 429struct ipr_hostrcb_cfg_ch_not {
363 struct ipr_config_table_entry cfgte; 430 union {
431 struct ipr_config_table_entry cfgte;
432 struct ipr_config_table_entry64 cfgte64;
433 } u;
364 u8 reserved[936]; 434 u8 reserved[936];
365}__attribute__((packed, aligned (4))); 435}__attribute__((packed, aligned (4)));
366 436
@@ -381,7 +451,7 @@ struct ipr_cmd_pkt {
381#define IPR_RQTYPE_HCAM 0x02 451#define IPR_RQTYPE_HCAM 0x02
382#define IPR_RQTYPE_ATA_PASSTHRU 0x04 452#define IPR_RQTYPE_ATA_PASSTHRU 0x04
383 453
384 u8 luntar_luntrn; 454 u8 reserved2;
385 455
386 u8 flags_hi; 456 u8 flags_hi;
387#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80 457#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
@@ -403,7 +473,7 @@ struct ipr_cmd_pkt {
403 __be16 timeout; 473 __be16 timeout;
404}__attribute__ ((packed, aligned(4))); 474}__attribute__ ((packed, aligned(4)));
405 475
406struct ipr_ioarcb_ata_regs { 476struct ipr_ioarcb_ata_regs { /* 22 bytes */
407 u8 flags; 477 u8 flags;
408#define IPR_ATA_FLAG_PACKET_CMD 0x80 478#define IPR_ATA_FLAG_PACKET_CMD 0x80
409#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40 479#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
@@ -442,28 +512,49 @@ struct ipr_ioadl_desc {
442 __be32 address; 512 __be32 address;
443}__attribute__((packed, aligned (8))); 513}__attribute__((packed, aligned (8)));
444 514
515struct ipr_ioadl64_desc {
516 __be32 flags;
517 __be32 data_len;
518 __be64 address;
519}__attribute__((packed, aligned (16)));
520
521struct ipr_ata64_ioadl {
522 struct ipr_ioarcb_ata_regs regs;
523 u16 reserved[5];
524 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
525}__attribute__((packed, aligned (16)));
526
445struct ipr_ioarcb_add_data { 527struct ipr_ioarcb_add_data {
446 union { 528 union {
447 struct ipr_ioarcb_ata_regs regs; 529 struct ipr_ioarcb_ata_regs regs;
448 struct ipr_ioadl_desc ioadl[5]; 530 struct ipr_ioadl_desc ioadl[5];
449 __be32 add_cmd_parms[10]; 531 __be32 add_cmd_parms[10];
450 }u; 532 } u;
451}__attribute__ ((packed, aligned(4))); 533}__attribute__ ((packed, aligned (4)));
534
535struct ipr_ioarcb_sis64_add_addr_ecb {
536 __be64 ioasa_host_pci_addr;
537 __be64 data_ioadl_addr;
538 __be64 reserved;
539 __be32 ext_control_buf[4];
540}__attribute__((packed, aligned (8)));
452 541
453/* IOA Request Control Block 128 bytes */ 542/* IOA Request Control Block 128 bytes */
454struct ipr_ioarcb { 543struct ipr_ioarcb {
455 __be32 ioarcb_host_pci_addr; 544 union {
456 __be32 reserved; 545 __be32 ioarcb_host_pci_addr;
546 __be64 ioarcb_host_pci_addr64;
547 } a;
457 __be32 res_handle; 548 __be32 res_handle;
458 __be32 host_response_handle; 549 __be32 host_response_handle;
459 __be32 reserved1; 550 __be32 reserved1;
460 __be32 reserved2; 551 __be32 reserved2;
461 __be32 reserved3; 552 __be32 reserved3;
462 553
463 __be32 write_data_transfer_length; 554 __be32 data_transfer_length;
464 __be32 read_data_transfer_length; 555 __be32 read_data_transfer_length;
465 __be32 write_ioadl_addr; 556 __be32 write_ioadl_addr;
466 __be32 write_ioadl_len; 557 __be32 ioadl_len;
467 __be32 read_ioadl_addr; 558 __be32 read_ioadl_addr;
468 __be32 read_ioadl_len; 559 __be32 read_ioadl_len;
469 560
@@ -473,8 +564,14 @@ struct ipr_ioarcb {
473 564
474 struct ipr_cmd_pkt cmd_pkt; 565 struct ipr_cmd_pkt cmd_pkt;
475 566
476 __be32 add_cmd_parms_len; 567 __be16 add_cmd_parms_offset;
477 struct ipr_ioarcb_add_data add_data; 568 __be16 add_cmd_parms_len;
569
570 union {
571 struct ipr_ioarcb_add_data add_data;
572 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
573 } u;
574
478}__attribute__((packed, aligned (4))); 575}__attribute__((packed, aligned (4)));
479 576
480struct ipr_ioasa_vset { 577struct ipr_ioasa_vset {
@@ -676,12 +773,29 @@ struct ipr_hostrcb_device_data_entry_enhanced {
676 struct ipr_ext_vpd cfc_last_with_dev_vpd; 773 struct ipr_ext_vpd cfc_last_with_dev_vpd;
677}__attribute__((packed, aligned (4))); 774}__attribute__((packed, aligned (4)));
678 775
776struct ipr_hostrcb64_device_data_entry_enhanced {
777 struct ipr_ext_vpd vpd;
778 u8 ccin[4];
779 u8 res_path[8];
780 struct ipr_ext_vpd new_vpd;
781 u8 new_ccin[4];
782 struct ipr_ext_vpd ioa_last_with_dev_vpd;
783 struct ipr_ext_vpd cfc_last_with_dev_vpd;
784}__attribute__((packed, aligned (4)));
785
679struct ipr_hostrcb_array_data_entry { 786struct ipr_hostrcb_array_data_entry {
680 struct ipr_vpd vpd; 787 struct ipr_vpd vpd;
681 struct ipr_res_addr expected_dev_res_addr; 788 struct ipr_res_addr expected_dev_res_addr;
682 struct ipr_res_addr dev_res_addr; 789 struct ipr_res_addr dev_res_addr;
683}__attribute__((packed, aligned (4))); 790}__attribute__((packed, aligned (4)));
684 791
792struct ipr_hostrcb64_array_data_entry {
793 struct ipr_ext_vpd vpd;
794 u8 ccin[4];
795 u8 expected_res_path[8];
796 u8 res_path[8];
797}__attribute__((packed, aligned (4)));
798
685struct ipr_hostrcb_array_data_entry_enhanced { 799struct ipr_hostrcb_array_data_entry_enhanced {
686 struct ipr_ext_vpd vpd; 800 struct ipr_ext_vpd vpd;
687 u8 ccin[4]; 801 u8 ccin[4];
@@ -733,6 +847,14 @@ struct ipr_hostrcb_type_13_error {
733 struct ipr_hostrcb_device_data_entry_enhanced dev[3]; 847 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
734}__attribute__((packed, aligned (4))); 848}__attribute__((packed, aligned (4)));
735 849
850struct ipr_hostrcb_type_23_error {
851 struct ipr_ext_vpd ioa_vpd;
852 struct ipr_ext_vpd cfc_vpd;
853 __be32 errors_detected;
854 __be32 errors_logged;
855 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
856}__attribute__((packed, aligned (4)));
857
736struct ipr_hostrcb_type_04_error { 858struct ipr_hostrcb_type_04_error {
737 struct ipr_vpd ioa_vpd; 859 struct ipr_vpd ioa_vpd;
738 struct ipr_vpd cfc_vpd; 860 struct ipr_vpd cfc_vpd;
@@ -760,6 +882,22 @@ struct ipr_hostrcb_type_14_error {
760 struct ipr_hostrcb_array_data_entry_enhanced array_member[18]; 882 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
761}__attribute__((packed, aligned (4))); 883}__attribute__((packed, aligned (4)));
762 884
885struct ipr_hostrcb_type_24_error {
886 struct ipr_ext_vpd ioa_vpd;
887 struct ipr_ext_vpd cfc_vpd;
888 u8 reserved[2];
889 u8 exposed_mode_adn;
890#define IPR_INVALID_ARRAY_DEV_NUM 0xff
891 u8 array_id;
892 u8 last_res_path[8];
893 u8 protection_level[8];
894 struct ipr_ext_vpd array_vpd;
895 u8 description[16];
896 u8 reserved2[3];
897 u8 num_entries;
898 struct ipr_hostrcb64_array_data_entry array_member[32];
899}__attribute__((packed, aligned (4)));
900
763struct ipr_hostrcb_type_07_error { 901struct ipr_hostrcb_type_07_error {
764 u8 failure_reason[64]; 902 u8 failure_reason[64];
765 struct ipr_vpd vpd; 903 struct ipr_vpd vpd;
@@ -797,6 +935,22 @@ struct ipr_hostrcb_config_element {
797 __be32 wwid[2]; 935 __be32 wwid[2];
798}__attribute__((packed, aligned (4))); 936}__attribute__((packed, aligned (4)));
799 937
938struct ipr_hostrcb64_config_element {
939 __be16 length;
940 u8 descriptor_id;
941#define IPR_DESCRIPTOR_MASK 0xC0
942#define IPR_DESCRIPTOR_SIS64 0x00
943
944 u8 reserved;
945 u8 type_status;
946
947 u8 reserved2[2];
948 u8 link_rate;
949
950 u8 res_path[8];
951 __be32 wwid[2];
952}__attribute__((packed, aligned (8)));
953
800struct ipr_hostrcb_fabric_desc { 954struct ipr_hostrcb_fabric_desc {
801 __be16 length; 955 __be16 length;
802 u8 ioa_port; 956 u8 ioa_port;
@@ -818,6 +972,20 @@ struct ipr_hostrcb_fabric_desc {
818 struct ipr_hostrcb_config_element elem[1]; 972 struct ipr_hostrcb_config_element elem[1];
819}__attribute__((packed, aligned (4))); 973}__attribute__((packed, aligned (4)));
820 974
975struct ipr_hostrcb64_fabric_desc {
976 __be16 length;
977 u8 descriptor_id;
978
979 u8 reserved;
980 u8 path_state;
981
982 u8 reserved2[2];
983 u8 res_path[8];
984 u8 reserved3[6];
985 __be16 num_entries;
986 struct ipr_hostrcb64_config_element elem[1];
987}__attribute__((packed, aligned (8)));
988
821#define for_each_fabric_cfg(fabric, cfg) \ 989#define for_each_fabric_cfg(fabric, cfg) \
822 for (cfg = (fabric)->elem; \ 990 for (cfg = (fabric)->elem; \
823 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \ 991 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
@@ -830,10 +998,17 @@ struct ipr_hostrcb_type_20_error {
830 struct ipr_hostrcb_fabric_desc desc[1]; 998 struct ipr_hostrcb_fabric_desc desc[1];
831}__attribute__((packed, aligned (4))); 999}__attribute__((packed, aligned (4)));
832 1000
1001struct ipr_hostrcb_type_30_error {
1002 u8 failure_reason[64];
1003 u8 reserved[3];
1004 u8 num_entries;
1005 struct ipr_hostrcb64_fabric_desc desc[1];
1006}__attribute__((packed, aligned (4)));
1007
833struct ipr_hostrcb_error { 1008struct ipr_hostrcb_error {
834 __be32 failing_dev_ioasc; 1009 __be32 fd_ioasc;
835 struct ipr_res_addr failing_dev_res_addr; 1010 struct ipr_res_addr fd_res_addr;
836 __be32 failing_dev_res_handle; 1011 __be32 fd_res_handle;
837 __be32 prc; 1012 __be32 prc;
838 union { 1013 union {
839 struct ipr_hostrcb_type_ff_error type_ff_error; 1014 struct ipr_hostrcb_type_ff_error type_ff_error;
@@ -850,6 +1025,26 @@ struct ipr_hostrcb_error {
850 } u; 1025 } u;
851}__attribute__((packed, aligned (4))); 1026}__attribute__((packed, aligned (4)));
852 1027
1028struct ipr_hostrcb64_error {
1029 __be32 fd_ioasc;
1030 __be32 ioa_fw_level;
1031 __be32 fd_res_handle;
1032 __be32 prc;
1033 __be64 fd_dev_id;
1034 __be64 fd_lun;
1035 u8 fd_res_path[8];
1036 __be64 time_stamp;
1037 u8 reserved[2];
1038 union {
1039 struct ipr_hostrcb_type_ff_error type_ff_error;
1040 struct ipr_hostrcb_type_12_error type_12_error;
1041 struct ipr_hostrcb_type_17_error type_17_error;
1042 struct ipr_hostrcb_type_23_error type_23_error;
1043 struct ipr_hostrcb_type_24_error type_24_error;
1044 struct ipr_hostrcb_type_30_error type_30_error;
1045 } u;
1046}__attribute__((packed, aligned (8)));
1047
853struct ipr_hostrcb_raw { 1048struct ipr_hostrcb_raw {
854 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)]; 1049 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
855}__attribute__((packed, aligned (4))); 1050}__attribute__((packed, aligned (4)));
@@ -887,7 +1082,11 @@ struct ipr_hcam {
887#define IPR_HOST_RCB_OVERLAY_ID_16 0x16 1082#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
888#define IPR_HOST_RCB_OVERLAY_ID_17 0x17 1083#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
889#define IPR_HOST_RCB_OVERLAY_ID_20 0x20 1084#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
890#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF 1085#define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1086#define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1087#define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1088#define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1089#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
891 1090
892 u8 reserved1[3]; 1091 u8 reserved1[3];
893 __be32 ilid; 1092 __be32 ilid;
@@ -897,6 +1096,7 @@ struct ipr_hcam {
897 1096
898 union { 1097 union {
899 struct ipr_hostrcb_error error; 1098 struct ipr_hostrcb_error error;
1099 struct ipr_hostrcb64_error error64;
900 struct ipr_hostrcb_cfg_ch_not ccn; 1100 struct ipr_hostrcb_cfg_ch_not ccn;
901 struct ipr_hostrcb_raw raw; 1101 struct ipr_hostrcb_raw raw;
902 } u; 1102 } u;
@@ -907,14 +1107,14 @@ struct ipr_hostrcb {
907 dma_addr_t hostrcb_dma; 1107 dma_addr_t hostrcb_dma;
908 struct list_head queue; 1108 struct list_head queue;
909 struct ipr_ioa_cfg *ioa_cfg; 1109 struct ipr_ioa_cfg *ioa_cfg;
1110 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
910}; 1111};
911 1112
912/* IPR smart dump table structures */ 1113/* IPR smart dump table structures */
913struct ipr_sdt_entry { 1114struct ipr_sdt_entry {
914 __be32 bar_str_offset; 1115 __be32 start_token;
915 __be32 end_offset; 1116 __be32 end_token;
916 u8 entry_byte; 1117 u8 reserved[4];
917 u8 reserved[3];
918 1118
919 u8 flags; 1119 u8 flags;
920#define IPR_SDT_ENDIAN 0x80 1120#define IPR_SDT_ENDIAN 0x80
@@ -960,28 +1160,48 @@ struct ipr_sata_port {
960}; 1160};
961 1161
962struct ipr_resource_entry { 1162struct ipr_resource_entry {
963 struct ipr_config_table_entry cfgte;
964 u8 needs_sync_complete:1; 1163 u8 needs_sync_complete:1;
965 u8 in_erp:1; 1164 u8 in_erp:1;
966 u8 add_to_ml:1; 1165 u8 add_to_ml:1;
967 u8 del_from_ml:1; 1166 u8 del_from_ml:1;
968 u8 resetting_device:1; 1167 u8 resetting_device:1;
969 1168
1169 u32 bus; /* AKA channel */
1170 u32 target; /* AKA id */
1171 u32 lun;
1172#define IPR_ARRAY_VIRTUAL_BUS 0x1
1173#define IPR_VSET_VIRTUAL_BUS 0x2
1174#define IPR_IOAFP_VIRTUAL_BUS 0x3
1175
1176#define IPR_GET_RES_PHYS_LOC(res) \
1177 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1178
1179 u8 ata_class;
1180
1181 u8 flags;
1182 __be16 res_flags;
1183
1184 __be32 type;
1185
1186 u8 qmodel;
1187 struct ipr_std_inq_data std_inq_data;
1188
1189 __be32 res_handle;
1190 __be64 dev_id;
1191 struct scsi_lun dev_lun;
1192 u8 res_path[8];
1193
1194 struct ipr_ioa_cfg *ioa_cfg;
970 struct scsi_device *sdev; 1195 struct scsi_device *sdev;
971 struct ipr_sata_port *sata_port; 1196 struct ipr_sata_port *sata_port;
972 struct list_head queue; 1197 struct list_head queue;
973}; 1198}; /* struct ipr_resource_entry */
974 1199
975struct ipr_resource_hdr { 1200struct ipr_resource_hdr {
976 u16 num_entries; 1201 u16 num_entries;
977 u16 reserved; 1202 u16 reserved;
978}; 1203};
979 1204
980struct ipr_resource_table {
981 struct ipr_resource_hdr hdr;
982 struct ipr_resource_entry dev[IPR_MAX_PHYSICAL_DEVS];
983};
984
985struct ipr_misc_cbs { 1205struct ipr_misc_cbs {
986 struct ipr_ioa_vpd ioa_vpd; 1206 struct ipr_ioa_vpd ioa_vpd;
987 struct ipr_inquiry_page0 page0_data; 1207 struct ipr_inquiry_page0 page0_data;
@@ -994,27 +1214,51 @@ struct ipr_misc_cbs {
994struct ipr_interrupt_offsets { 1214struct ipr_interrupt_offsets {
995 unsigned long set_interrupt_mask_reg; 1215 unsigned long set_interrupt_mask_reg;
996 unsigned long clr_interrupt_mask_reg; 1216 unsigned long clr_interrupt_mask_reg;
1217 unsigned long clr_interrupt_mask_reg32;
997 unsigned long sense_interrupt_mask_reg; 1218 unsigned long sense_interrupt_mask_reg;
1219 unsigned long sense_interrupt_mask_reg32;
998 unsigned long clr_interrupt_reg; 1220 unsigned long clr_interrupt_reg;
1221 unsigned long clr_interrupt_reg32;
999 1222
1000 unsigned long sense_interrupt_reg; 1223 unsigned long sense_interrupt_reg;
1224 unsigned long sense_interrupt_reg32;
1001 unsigned long ioarrin_reg; 1225 unsigned long ioarrin_reg;
1002 unsigned long sense_uproc_interrupt_reg; 1226 unsigned long sense_uproc_interrupt_reg;
1227 unsigned long sense_uproc_interrupt_reg32;
1003 unsigned long set_uproc_interrupt_reg; 1228 unsigned long set_uproc_interrupt_reg;
1229 unsigned long set_uproc_interrupt_reg32;
1004 unsigned long clr_uproc_interrupt_reg; 1230 unsigned long clr_uproc_interrupt_reg;
1231 unsigned long clr_uproc_interrupt_reg32;
1232
1233 unsigned long init_feedback_reg;
1234
1235 unsigned long dump_addr_reg;
1236 unsigned long dump_data_reg;
1005}; 1237};
1006 1238
1007struct ipr_interrupts { 1239struct ipr_interrupts {
1008 void __iomem *set_interrupt_mask_reg; 1240 void __iomem *set_interrupt_mask_reg;
1009 void __iomem *clr_interrupt_mask_reg; 1241 void __iomem *clr_interrupt_mask_reg;
1242 void __iomem *clr_interrupt_mask_reg32;
1010 void __iomem *sense_interrupt_mask_reg; 1243 void __iomem *sense_interrupt_mask_reg;
1244 void __iomem *sense_interrupt_mask_reg32;
1011 void __iomem *clr_interrupt_reg; 1245 void __iomem *clr_interrupt_reg;
1246 void __iomem *clr_interrupt_reg32;
1012 1247
1013 void __iomem *sense_interrupt_reg; 1248 void __iomem *sense_interrupt_reg;
1249 void __iomem *sense_interrupt_reg32;
1014 void __iomem *ioarrin_reg; 1250 void __iomem *ioarrin_reg;
1015 void __iomem *sense_uproc_interrupt_reg; 1251 void __iomem *sense_uproc_interrupt_reg;
1252 void __iomem *sense_uproc_interrupt_reg32;
1016 void __iomem *set_uproc_interrupt_reg; 1253 void __iomem *set_uproc_interrupt_reg;
1254 void __iomem *set_uproc_interrupt_reg32;
1017 void __iomem *clr_uproc_interrupt_reg; 1255 void __iomem *clr_uproc_interrupt_reg;
1256 void __iomem *clr_uproc_interrupt_reg32;
1257
1258 void __iomem *init_feedback_reg;
1259
1260 void __iomem *dump_addr_reg;
1261 void __iomem *dump_data_reg;
1018}; 1262};
1019 1263
1020struct ipr_chip_cfg_t { 1264struct ipr_chip_cfg_t {
@@ -1029,6 +1273,9 @@ struct ipr_chip_t {
1029 u16 intr_type; 1273 u16 intr_type;
1030#define IPR_USE_LSI 0x00 1274#define IPR_USE_LSI 0x00
1031#define IPR_USE_MSI 0x01 1275#define IPR_USE_MSI 0x01
1276 u16 sis_type;
1277#define IPR_SIS32 0x00
1278#define IPR_SIS64 0x01
1032 const struct ipr_chip_cfg_t *cfg; 1279 const struct ipr_chip_cfg_t *cfg;
1033}; 1280};
1034 1281
@@ -1073,13 +1320,6 @@ enum ipr_sdt_state {
1073 DUMP_OBTAINED 1320 DUMP_OBTAINED
1074}; 1321};
1075 1322
1076enum ipr_cache_state {
1077 CACHE_NONE,
1078 CACHE_DISABLED,
1079 CACHE_ENABLED,
1080 CACHE_INVALID
1081};
1082
1083/* Per-controller data */ 1323/* Per-controller data */
1084struct ipr_ioa_cfg { 1324struct ipr_ioa_cfg {
1085 char eye_catcher[8]; 1325 char eye_catcher[8];
@@ -1099,10 +1339,17 @@ struct ipr_ioa_cfg {
1099 u8 dual_raid:1; 1339 u8 dual_raid:1;
1100 u8 needs_warm_reset:1; 1340 u8 needs_warm_reset:1;
1101 u8 msi_received:1; 1341 u8 msi_received:1;
1342 u8 sis64:1;
1102 1343
1103 u8 revid; 1344 u8 revid;
1104 1345
1105 enum ipr_cache_state cache_state; 1346 /*
1347 * Bitmaps for SIS64 generated target values
1348 */
1349 unsigned long *target_ids;
1350 unsigned long *array_ids;
1351 unsigned long *vset_ids;
1352
1106 u16 type; /* CCIN of the card */ 1353 u16 type; /* CCIN of the card */
1107 1354
1108 u8 log_level; 1355 u8 log_level;
@@ -1133,8 +1380,13 @@ struct ipr_ioa_cfg {
1133 1380
1134 char cfg_table_start[8]; 1381 char cfg_table_start[8];
1135#define IPR_CFG_TBL_START "cfg" 1382#define IPR_CFG_TBL_START "cfg"
1136 struct ipr_config_table *cfg_table; 1383 union {
1384 struct ipr_config_table *cfg_table;
1385 struct ipr_config_table64 *cfg_table64;
1386 } u;
1137 dma_addr_t cfg_table_dma; 1387 dma_addr_t cfg_table_dma;
1388 u32 cfg_table_size;
1389 u32 max_devs_supported;
1138 1390
1139 char resource_table_label[8]; 1391 char resource_table_label[8];
1140#define IPR_RES_TABLE_LABEL "res_tbl" 1392#define IPR_RES_TABLE_LABEL "res_tbl"
@@ -1202,13 +1454,17 @@ struct ipr_ioa_cfg {
1202 char ipr_cmd_label[8]; 1454 char ipr_cmd_label[8];
1203#define IPR_CMD_LABEL "ipr_cmd" 1455#define IPR_CMD_LABEL "ipr_cmd"
1204 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS]; 1456 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
1205 u32 ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS]; 1457 dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1206}; 1458}; /* struct ipr_ioa_cfg */
1207 1459
1208struct ipr_cmnd { 1460struct ipr_cmnd {
1209 struct ipr_ioarcb ioarcb; 1461 struct ipr_ioarcb ioarcb;
1462 union {
1463 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1464 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1465 struct ipr_ata64_ioadl ata_ioadl;
1466 } i;
1210 struct ipr_ioasa ioasa; 1467 struct ipr_ioasa ioasa;
1211 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1212 struct list_head queue; 1468 struct list_head queue;
1213 struct scsi_cmnd *scsi_cmd; 1469 struct scsi_cmnd *scsi_cmd;
1214 struct ata_queued_cmd *qc; 1470 struct ata_queued_cmd *qc;
@@ -1221,7 +1477,7 @@ struct ipr_cmnd {
1221 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE]; 1477 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1222 dma_addr_t sense_buffer_dma; 1478 dma_addr_t sense_buffer_dma;
1223 unsigned short dma_use_sg; 1479 unsigned short dma_use_sg;
1224 dma_addr_t dma_handle; 1480 dma_addr_t dma_addr;
1225 struct ipr_cmnd *sibling; 1481 struct ipr_cmnd *sibling;
1226 union { 1482 union {
1227 enum ipr_shutdown_type shutdown_type; 1483 enum ipr_shutdown_type shutdown_type;
@@ -1314,8 +1570,6 @@ struct ipr_ioa_dump {
1314 u32 next_page_index; 1570 u32 next_page_index;
1315 u32 page_offset; 1571 u32 page_offset;
1316 u32 format; 1572 u32 format;
1317#define IPR_SDT_FMT2 2
1318#define IPR_SDT_UNKNOWN 3
1319}__attribute__((packed, aligned (4))); 1573}__attribute__((packed, aligned (4)));
1320 1574
1321struct ipr_dump { 1575struct ipr_dump {
@@ -1377,6 +1631,13 @@ struct ipr_ucode_image_header {
1377#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__) 1631#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1378#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)) 1632#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1379 1633
1634#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1635 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1636 bus, target, lun, ##__VA_ARGS__)
1637
1638#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1639 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1640
1380#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \ 1641#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1381 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ 1642 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1382 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__) 1643 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
@@ -1384,9 +1645,6 @@ struct ipr_ucode_image_header {
1384#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \ 1645#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1385 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__) 1646 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1386 1647
1387#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1388 ipr_ra_err(ioa_cfg, (res)->cfgte.res_addr, fmt, ##__VA_ARGS__)
1389
1390#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \ 1648#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1391{ \ 1649{ \
1392 if ((res).bus >= IPR_MAX_NUM_BUSES) { \ 1650 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
@@ -1399,14 +1657,21 @@ struct ipr_ucode_image_header {
1399} 1657}
1400 1658
1401#define ipr_hcam_err(hostrcb, fmt, ...) \ 1659#define ipr_hcam_err(hostrcb, fmt, ...) \
1402{ \ 1660{ \
1403 if (ipr_is_device(&(hostrcb)->hcam.u.error.failing_dev_res_addr)) { \ 1661 if (ipr_is_device(hostrcb)) { \
1404 ipr_ra_err((hostrcb)->ioa_cfg, \ 1662 if ((hostrcb)->ioa_cfg->sis64) { \
1405 (hostrcb)->hcam.u.error.failing_dev_res_addr, \ 1663 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1406 fmt, ##__VA_ARGS__); \ 1664 ipr_format_resource_path(&hostrcb->hcam.u.error64.fd_res_path[0], \
1407 } else { \ 1665 &hostrcb->rp_buffer[0]), \
1408 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, ##__VA_ARGS__); \ 1666 __VA_ARGS__); \
1409 } \ 1667 } else { \
1668 ipr_ra_err((hostrcb)->ioa_cfg, \
1669 (hostrcb)->hcam.u.error.fd_res_addr, \
1670 fmt, __VA_ARGS__); \
1671 } \
1672 } else { \
1673 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1674 } \
1410} 1675}
1411 1676
1412#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\ 1677#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
@@ -1432,7 +1697,7 @@ ipr_err("----------------------------------------------------------\n")
1432 **/ 1697 **/
1433static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res) 1698static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1434{ 1699{
1435 return (res->cfgte.flags & IPR_IS_IOA_RESOURCE) ? 1 : 0; 1700 return res->type == IPR_RES_TYPE_IOAFP;
1436} 1701}
1437 1702
1438/** 1703/**
@@ -1444,12 +1709,8 @@ static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1444 **/ 1709 **/
1445static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res) 1710static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1446{ 1711{
1447 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) && 1712 return res->type == IPR_RES_TYPE_AF_DASD ||
1448 !ipr_is_ioa_resource(res) && 1713 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1449 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_AF_DASD)
1450 return 1;
1451 else
1452 return 0;
1453} 1714}
1454 1715
1455/** 1716/**
@@ -1461,12 +1722,7 @@ static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1461 **/ 1722 **/
1462static inline int ipr_is_vset_device(struct ipr_resource_entry *res) 1723static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1463{ 1724{
1464 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) && 1725 return res->type == IPR_RES_TYPE_VOLUME_SET;
1465 !ipr_is_ioa_resource(res) &&
1466 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_VOLUME_SET)
1467 return 1;
1468 else
1469 return 0;
1470} 1726}
1471 1727
1472/** 1728/**
@@ -1478,11 +1734,7 @@ static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1478 **/ 1734 **/
1479static inline int ipr_is_gscsi(struct ipr_resource_entry *res) 1735static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1480{ 1736{
1481 if (!ipr_is_ioa_resource(res) && 1737 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1482 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_SCSI)
1483 return 1;
1484 else
1485 return 0;
1486} 1738}
1487 1739
1488/** 1740/**
@@ -1495,7 +1747,7 @@ static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1495static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res) 1747static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1496{ 1748{
1497 if (ipr_is_af_dasd_device(res) || 1749 if (ipr_is_af_dasd_device(res) ||
1498 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data))) 1750 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1499 return 1; 1751 return 1;
1500 else 1752 else
1501 return 0; 1753 return 0;
@@ -1510,11 +1762,7 @@ static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1510 **/ 1762 **/
1511static inline int ipr_is_gata(struct ipr_resource_entry *res) 1763static inline int ipr_is_gata(struct ipr_resource_entry *res)
1512{ 1764{
1513 if (!ipr_is_ioa_resource(res) && 1765 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1514 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_ATA)
1515 return 1;
1516 else
1517 return 0;
1518} 1766}
1519 1767
1520/** 1768/**
@@ -1526,24 +1774,35 @@ static inline int ipr_is_gata(struct ipr_resource_entry *res)
1526 **/ 1774 **/
1527static inline int ipr_is_naca_model(struct ipr_resource_entry *res) 1775static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1528{ 1776{
1529 if (ipr_is_gscsi(res) && IPR_QUEUEING_MODEL(res) == IPR_QUEUE_NACA_MODEL) 1777 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1530 return 1; 1778 return 1;
1531 return 0; 1779 return 0;
1532} 1780}
1533 1781
1534/** 1782/**
1535 * ipr_is_device - Determine if resource address is that of a device 1783 * ipr_is_device - Determine if the hostrcb structure is related to a device
1536 * @res_addr: resource address struct 1784 * @hostrcb: host resource control blocks struct
1537 * 1785 *
1538 * Return value: 1786 * Return value:
1539 * 1 if AF / 0 if not AF 1787 * 1 if AF / 0 if not AF
1540 **/ 1788 **/
1541static inline int ipr_is_device(struct ipr_res_addr *res_addr) 1789static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1542{ 1790{
1543 if ((res_addr->bus < IPR_MAX_NUM_BUSES) && 1791 struct ipr_res_addr *res_addr;
1544 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1))) 1792 u8 *res_path;
1545 return 1; 1793
1546 1794 if (hostrcb->ioa_cfg->sis64) {
1795 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1796 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1797 res_path[0] == 0x81) && res_path[2] != 0xFF)
1798 return 1;
1799 } else {
1800 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1801
1802 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1803 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1804 return 1;
1805 }
1547 return 0; 1806 return 0;
1548} 1807}
1549 1808