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Diffstat (limited to 'drivers/scsi/hpsa.h')
-rw-r--r--drivers/scsi/hpsa.h15
1 files changed, 11 insertions, 4 deletions
diff --git a/drivers/scsi/hpsa.h b/drivers/scsi/hpsa.h
index 621a1530054a..6d8dcd4dd06b 100644
--- a/drivers/scsi/hpsa.h
+++ b/drivers/scsi/hpsa.h
@@ -127,10 +127,12 @@ struct ctlr_info {
127}; 127};
128#define HPSA_ABORT_MSG 0 128#define HPSA_ABORT_MSG 0
129#define HPSA_DEVICE_RESET_MSG 1 129#define HPSA_DEVICE_RESET_MSG 1
130#define HPSA_BUS_RESET_MSG 2 130#define HPSA_RESET_TYPE_CONTROLLER 0x00
131#define HPSA_HOST_RESET_MSG 3 131#define HPSA_RESET_TYPE_BUS 0x01
132#define HPSA_RESET_TYPE_TARGET 0x03
133#define HPSA_RESET_TYPE_LUN 0x04
132#define HPSA_MSG_SEND_RETRY_LIMIT 10 134#define HPSA_MSG_SEND_RETRY_LIMIT 10
133#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS 1000 135#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
134 136
135/* Maximum time in seconds driver will wait for command completions 137/* Maximum time in seconds driver will wait for command completions
136 * when polling before giving up. 138 * when polling before giving up.
@@ -155,7 +157,7 @@ struct ctlr_info {
155 * HPSA_BOARD_READY_ITERATIONS are derived from those. 157 * HPSA_BOARD_READY_ITERATIONS are derived from those.
156 */ 158 */
157#define HPSA_BOARD_READY_WAIT_SECS (120) 159#define HPSA_BOARD_READY_WAIT_SECS (120)
158#define HPSA_BOARD_NOT_READY_WAIT_SECS (10) 160#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
159#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) 161#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
160#define HPSA_BOARD_READY_POLL_INTERVAL \ 162#define HPSA_BOARD_READY_POLL_INTERVAL \
161 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) 163 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
@@ -212,6 +214,7 @@ static void SA5_submit_command(struct ctlr_info *h,
212 dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr, 214 dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
213 c->Header.Tag.lower); 215 c->Header.Tag.lower);
214 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 216 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
217 (void) readl(h->vaddr + SA5_REQUEST_PORT_OFFSET);
215 h->commands_outstanding++; 218 h->commands_outstanding++;
216 if (h->commands_outstanding > h->max_outstanding) 219 if (h->commands_outstanding > h->max_outstanding)
217 h->max_outstanding = h->commands_outstanding; 220 h->max_outstanding = h->commands_outstanding;
@@ -227,10 +230,12 @@ static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
227 if (val) { /* Turn interrupts on */ 230 if (val) { /* Turn interrupts on */
228 h->interrupts_enabled = 1; 231 h->interrupts_enabled = 1;
229 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 232 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
233 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
230 } else { /* Turn them off */ 234 } else { /* Turn them off */
231 h->interrupts_enabled = 0; 235 h->interrupts_enabled = 0;
232 writel(SA5_INTR_OFF, 236 writel(SA5_INTR_OFF,
233 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 237 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
238 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
234 } 239 }
235} 240}
236 241
@@ -239,10 +244,12 @@ static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
239 if (val) { /* turn on interrupts */ 244 if (val) { /* turn on interrupts */
240 h->interrupts_enabled = 1; 245 h->interrupts_enabled = 1;
241 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 246 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
247 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
242 } else { 248 } else {
243 h->interrupts_enabled = 0; 249 h->interrupts_enabled = 0;
244 writel(SA5_PERF_INTR_OFF, 250 writel(SA5_PERF_INTR_OFF,
245 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 251 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
252 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
246 } 253 }
247} 254}
248 255