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path: root/drivers/scsi/bfa/bfa_hw_ct.c
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Diffstat (limited to 'drivers/scsi/bfa/bfa_hw_ct.c')
-rw-r--r--drivers/scsi/bfa/bfa_hw_ct.c89
1 files changed, 34 insertions, 55 deletions
diff --git a/drivers/scsi/bfa/bfa_hw_ct.c b/drivers/scsi/bfa/bfa_hw_ct.c
index 21018d98a07b..989bbce9b296 100644
--- a/drivers/scsi/bfa/bfa_hw_ct.c
+++ b/drivers/scsi/bfa/bfa_hw_ct.c
@@ -17,29 +17,10 @@
17 17
18#include "bfad_drv.h" 18#include "bfad_drv.h"
19#include "bfa_modules.h" 19#include "bfa_modules.h"
20#include "bfi_ctreg.h" 20#include "bfi_reg.h"
21 21
22BFA_TRC_FILE(HAL, IOCFC_CT); 22BFA_TRC_FILE(HAL, IOCFC_CT);
23 23
24static u32 __ct_msix_err_vec_reg[] = {
25 HOST_MSIX_ERR_INDEX_FN0,
26 HOST_MSIX_ERR_INDEX_FN1,
27 HOST_MSIX_ERR_INDEX_FN2,
28 HOST_MSIX_ERR_INDEX_FN3,
29};
30
31static void
32bfa_hwct_msix_lpu_err_set(struct bfa_s *bfa, bfa_boolean_t msix, int vec)
33{
34 int fn = bfa_ioc_pcifn(&bfa->ioc);
35 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
36
37 if (msix)
38 writel(vec, kva + __ct_msix_err_vec_reg[fn]);
39 else
40 writel(0, kva + __ct_msix_err_vec_reg[fn]);
41}
42
43/* 24/*
44 * Dummy interrupt handler for handling spurious interrupt during chip-reinit. 25 * Dummy interrupt handler for handling spurious interrupt during chip-reinit.
45 */ 26 */
@@ -53,7 +34,7 @@ bfa_hwct_reginit(struct bfa_s *bfa)
53{ 34{
54 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs; 35 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
55 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc); 36 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
56 int i, q, fn = bfa_ioc_pcifn(&bfa->ioc); 37 int fn = bfa_ioc_pcifn(&bfa->ioc);
57 38
58 if (fn == 0) { 39 if (fn == 0) {
59 bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS); 40 bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
@@ -62,26 +43,16 @@ bfa_hwct_reginit(struct bfa_s *bfa)
62 bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS); 43 bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
63 bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK); 44 bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
64 } 45 }
46}
65 47
66 for (i = 0; i < BFI_IOC_MAX_CQS; i++) { 48void
67 /* 49bfa_hwct2_reginit(struct bfa_s *bfa)
68 * CPE registers 50{
69 */ 51 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
70 q = CPE_Q_NUM(fn, i); 52 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
71 bfa_regs->cpe_q_pi[i] = (kva + CPE_PI_PTR_Q(q << 5)); 53
72 bfa_regs->cpe_q_ci[i] = (kva + CPE_CI_PTR_Q(q << 5)); 54 bfa_regs->intr_status = (kva + CT2_HOSTFN_INT_STATUS);
73 bfa_regs->cpe_q_depth[i] = (kva + CPE_DEPTH_Q(q << 5)); 55 bfa_regs->intr_mask = (kva + CT2_HOSTFN_INTR_MASK);
74 bfa_regs->cpe_q_ctrl[i] = (kva + CPE_QCTRL_Q(q << 5));
75
76 /*
77 * RME registers
78 */
79 q = CPE_Q_NUM(fn, i);
80 bfa_regs->rme_q_pi[i] = (kva + RME_PI_PTR_Q(q << 5));
81 bfa_regs->rme_q_ci[i] = (kva + RME_CI_PTR_Q(q << 5));
82 bfa_regs->rme_q_depth[i] = (kva + RME_DEPTH_Q(q << 5));
83 bfa_regs->rme_q_ctrl[i] = (kva + RME_QCTRL_Q(q << 5));
84 }
85} 56}
86 57
87void 58void
@@ -106,9 +77,9 @@ void
106bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap, 77bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
107 u32 *num_vecs, u32 *max_vec_bit) 78 u32 *num_vecs, u32 *max_vec_bit)
108{ 79{
109 *msix_vecs_bmap = (1 << BFA_MSIX_CT_MAX) - 1; 80 *msix_vecs_bmap = (1 << BFI_MSIX_CT_MAX) - 1;
110 *max_vec_bit = (1 << (BFA_MSIX_CT_MAX - 1)); 81 *max_vec_bit = (1 << (BFI_MSIX_CT_MAX - 1));
111 *num_vecs = BFA_MSIX_CT_MAX; 82 *num_vecs = BFI_MSIX_CT_MAX;
112} 83}
113 84
114/* 85/*
@@ -117,7 +88,7 @@ bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
117void 88void
118bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs) 89bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
119{ 90{
120 WARN_ON((nvecs != 1) && (nvecs != BFA_MSIX_CT_MAX)); 91 WARN_ON((nvecs != 1) && (nvecs != BFI_MSIX_CT_MAX));
121 bfa_trc(bfa, nvecs); 92 bfa_trc(bfa, nvecs);
122 93
123 bfa->msix.nvecs = nvecs; 94 bfa->msix.nvecs = nvecs;
@@ -125,7 +96,19 @@ bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
125} 96}
126 97
127void 98void
128bfa_hwct_msix_install(struct bfa_s *bfa) 99bfa_hwct_msix_ctrl_install(struct bfa_s *bfa)
100{
101 if (bfa->msix.nvecs == 0)
102 return;
103
104 if (bfa->msix.nvecs == 1)
105 bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_all;
106 else
107 bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_lpu_err;
108}
109
110void
111bfa_hwct_msix_queue_install(struct bfa_s *bfa)
129{ 112{
130 int i; 113 int i;
131 114
@@ -133,19 +116,16 @@ bfa_hwct_msix_install(struct bfa_s *bfa)
133 return; 116 return;
134 117
135 if (bfa->msix.nvecs == 1) { 118 if (bfa->msix.nvecs == 1) {
136 for (i = 0; i < BFA_MSIX_CT_MAX; i++) 119 for (i = BFI_MSIX_CPE_QMIN_CT; i < BFI_MSIX_CT_MAX; i++)
137 bfa->msix.handler[i] = bfa_msix_all; 120 bfa->msix.handler[i] = bfa_msix_all;
138 return; 121 return;
139 } 122 }
140 123
141 for (i = BFA_MSIX_CPE_Q0; i <= BFA_MSIX_CPE_Q3; i++) 124 for (i = BFI_MSIX_CPE_QMIN_CT; i <= BFI_MSIX_CPE_QMAX_CT; i++)
142 bfa->msix.handler[i] = bfa_msix_reqq; 125 bfa->msix.handler[i] = bfa_msix_reqq;
143 126
144 for (; i <= BFA_MSIX_RME_Q3; i++) 127 for (i = BFI_MSIX_RME_QMIN_CT; i <= BFI_MSIX_RME_QMAX_CT; i++)
145 bfa->msix.handler[i] = bfa_msix_rspq; 128 bfa->msix.handler[i] = bfa_msix_rspq;
146
147 WARN_ON(i != BFA_MSIX_LPU_ERR);
148 bfa->msix.handler[BFA_MSIX_LPU_ERR] = bfa_msix_lpu_err;
149} 129}
150 130
151void 131void
@@ -153,7 +133,7 @@ bfa_hwct_msix_uninstall(struct bfa_s *bfa)
153{ 133{
154 int i; 134 int i;
155 135
156 for (i = 0; i < BFA_MSIX_CT_MAX; i++) 136 for (i = 0; i < BFI_MSIX_CT_MAX; i++)
157 bfa->msix.handler[i] = bfa_hwct_msix_dummy; 137 bfa->msix.handler[i] = bfa_hwct_msix_dummy;
158} 138}
159 139
@@ -164,13 +144,12 @@ void
164bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix) 144bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
165{ 145{
166 bfa_trc(bfa, 0); 146 bfa_trc(bfa, 0);
167 bfa_hwct_msix_lpu_err_set(bfa, msix, BFA_MSIX_LPU_ERR);
168 bfa_ioc_isr_mode_set(&bfa->ioc, msix); 147 bfa_ioc_isr_mode_set(&bfa->ioc, msix);
169} 148}
170 149
171void 150void
172bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end) 151bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
173{ 152{
174 *start = BFA_MSIX_RME_Q0; 153 *start = BFI_MSIX_RME_QMIN_CT;
175 *end = BFA_MSIX_RME_Q3; 154 *end = BFI_MSIX_RME_QMAX_CT;
176} 155}