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-rw-r--r--drivers/scsi/arcmsr/arcmsr.h315
1 files changed, 216 insertions, 99 deletions
diff --git a/drivers/scsi/arcmsr/arcmsr.h b/drivers/scsi/arcmsr/arcmsr.h
index ce5371b3cdd5..475c31ae985c 100644
--- a/drivers/scsi/arcmsr/arcmsr.h
+++ b/drivers/scsi/arcmsr/arcmsr.h
@@ -43,21 +43,27 @@
43******************************************************************************* 43*******************************************************************************
44*/ 44*/
45#include <linux/interrupt.h> 45#include <linux/interrupt.h>
46
47struct device_attribute; 46struct device_attribute;
48/*The limit of outstanding scsi command that firmware can handle*/ 47/*The limit of outstanding scsi command that firmware can handle*/
49#define ARCMSR_MAX_OUTSTANDING_CMD 256 48#define ARCMSR_MAX_OUTSTANDING_CMD 256
50#define ARCMSR_MAX_FREECCB_NUM 320 49#define ARCMSR_MAX_FREECCB_NUM 320
51#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.15 2008/11/03" 50#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.15 2010/02/02"
52#define ARCMSR_SCSI_INITIATOR_ID 255 51#define ARCMSR_SCSI_INITIATOR_ID 255
53#define ARCMSR_MAX_XFER_SECTORS 512 52#define ARCMSR_MAX_XFER_SECTORS 512
54#define ARCMSR_MAX_XFER_SECTORS_B 4096 53#define ARCMSR_MAX_XFER_SECTORS_B 4096
54#define ARCMSR_MAX_XFER_SECTORS_C 304
55#define ARCMSR_MAX_TARGETID 17 55#define ARCMSR_MAX_TARGETID 17
56#define ARCMSR_MAX_TARGETLUN 8 56#define ARCMSR_MAX_TARGETLUN 8
57#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 57#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD
58#define ARCMSR_MAX_QBUFFER 4096 58#define ARCMSR_MAX_QBUFFER 4096
59#define ARCMSR_MAX_SG_ENTRIES 38 59#define ARCMSR_DEFAULT_SG_ENTRIES 38
60#define ARCMSR_MAX_HBB_POSTQUEUE 264 60#define ARCMSR_MAX_HBB_POSTQUEUE 264
61#define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */
62#define ARCMSR_CDB_SG_PAGE_LENGTH 256
63#define SCSI_CMD_ARECA_SPECIFIC 0xE1
64#ifndef PCI_DEVICE_ID_ARECA_1880
65#define PCI_DEVICE_ID_ARECA_1880 0x1880
66 #endif
61/* 67/*
62********************************************************************************** 68**********************************************************************************
63** 69**
@@ -132,35 +138,28 @@ struct CMD_MESSAGE_FIELD
132#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \ 138#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \
133 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE 139 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE
134/* ARECA IOCTL ReturnCode */ 140/* ARECA IOCTL ReturnCode */
135#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 141#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
136#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 142#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
137#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 143#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
138#define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088 144#define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088
139/* 145/*
140************************************************************* 146*************************************************************
141** structure for holding DMA address data 147** structure for holding DMA address data
142************************************************************* 148*************************************************************
143*/ 149*/
150#define IS_DMA64 (sizeof(dma_addr_t) == 8)
144#define IS_SG64_ADDR 0x01000000 /* bit24 */ 151#define IS_SG64_ADDR 0x01000000 /* bit24 */
145struct SG32ENTRY 152struct SG32ENTRY
146{ 153{
147 __le32 length; 154 __le32 length;
148 __le32 address; 155 __le32 address;
149}; 156}__attribute__ ((packed));
150struct SG64ENTRY 157struct SG64ENTRY
151{ 158{
152 __le32 length; 159 __le32 length;
153 __le32 address; 160 __le32 address;
154 __le32 addresshigh; 161 __le32 addresshigh;
155}; 162}__attribute__ ((packed));
156struct SGENTRY_UNION
157{
158 union
159 {
160 struct SG32ENTRY sg32entry;
161 struct SG64ENTRY sg64entry;
162 }u;
163};
164/* 163/*
165******************************************************************** 164********************************************************************
166** Q Buffer of IOP Message Transfer 165** Q Buffer of IOP Message Transfer
@@ -187,6 +186,9 @@ struct FIRMWARE_INFO
187 char model[8]; /*15, 60-67*/ 186 char model[8]; /*15, 60-67*/
188 char firmware_ver[16]; /*17, 68-83*/ 187 char firmware_ver[16]; /*17, 68-83*/
189 char device_map[16]; /*21, 84-99*/ 188 char device_map[16]; /*21, 84-99*/
189 uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
190 uint8_t cfgSerial[16]; /*26,104-119*/
191 uint32_t cfgPicStatus; /*30,120-123*/
190}; 192};
191/* signature of set and get firmware config */ 193/* signature of set and get firmware config */
192#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 194#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
@@ -210,9 +212,15 @@ struct FIRMWARE_INFO
210#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000 212#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
211#define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000 213#define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
212#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000 214#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
213#define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000 215#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000
216#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001
214/* outbound firmware ok */ 217/* outbound firmware ok */
215#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 218#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
219/* ARC-1680 Bus Reset*/
220#define ARCMSR_ARC1680_BUS_RESET 0x00000003
221/* ARC-1880 Bus Reset*/
222#define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024
223#define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080
216 224
217/* 225/*
218************************************************************************ 226************************************************************************
@@ -264,11 +272,66 @@ struct FIRMWARE_INFO
264 272
265/* data tunnel buffer between user space program and its firmware */ 273/* data tunnel buffer between user space program and its firmware */
266/* user space data to iop 128bytes */ 274/* user space data to iop 128bytes */
267#define ARCMSR_IOCTL_WBUFFER 0x0000fe00 275#define ARCMSR_MESSAGE_WBUFFER 0x0000fe00
268/* iop data to user space 128bytes */ 276/* iop data to user space 128bytes */
269#define ARCMSR_IOCTL_RBUFFER 0x0000ff00 277#define ARCMSR_MESSAGE_RBUFFER 0x0000ff00
270/* iop message_rwbuffer for message command */ 278/* iop message_rwbuffer for message command */
271#define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 279#define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00
280/*
281************************************************************************
282** SPEC. for Areca HBC adapter
283************************************************************************
284*/
285#define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12
286#define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20
287/* Host Interrupt Mask */
288#define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/
289#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/
290#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/
291#define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
292/* Host Interrupt Status */
293#define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
294 /*
295 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
296 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
297 */
298#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
299 /*
300 ** Set if Outbound Doorbell register bits 30:1 have a non-zero
301 ** value. This bit clears only when Outbound Doorbell bits
302 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell
303 ** Clear register clears bits in the Outbound Doorbell register.
304 */
305#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
306 /*
307 ** Set whenever the Outbound Post List Producer/Consumer
308 ** Register (FIFO) is not empty. It clears when the Outbound
309 ** Post List FIFO is empty.
310 */
311#define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
312 /*
313 ** This bit indicates a SAS interrupt from a source external to
314 ** the PCIe core. This bit is not maskable.
315 */
316 /* DoorBell*/
317#define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002
318#define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004
319 /*inbound message 0 ready*/
320#define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
321 /*more than 12 request completed in a time*/
322#define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010
323#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002
324 /*outbound DATA WRITE isr door bell clear*/
325#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002
326#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004
327 /*outbound DATA READ isr door bell clear*/
328#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004
329 /*outbound message 0 ready*/
330#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
331 /*outbound message cmd isr door bell clear*/
332#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008
333 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
334#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000
272/* 335/*
273******************************************************************************* 336*******************************************************************************
274** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504) 337** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
@@ -290,7 +353,7 @@ struct ARCMSR_CDB
290#define ARCMSR_CDB_FLAG_HEADQ 0x08 353#define ARCMSR_CDB_FLAG_HEADQ 0x08
291#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 354#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
292 355
293 uint8_t Reserved1; 356 uint8_t msgPages;
294 uint32_t Context; 357 uint32_t Context;
295 uint32_t DataLength; 358 uint32_t DataLength;
296 uint8_t Cdb[16]; 359 uint8_t Cdb[16];
@@ -303,8 +366,8 @@ struct ARCMSR_CDB
303 uint8_t SenseData[15]; 366 uint8_t SenseData[15];
304 union 367 union
305 { 368 {
306 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; 369 struct SG32ENTRY sg32entry[1];
307 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; 370 struct SG64ENTRY sg64entry[1];
308 } u; 371 } u;
309}; 372};
310/* 373/*
@@ -344,15 +407,89 @@ struct MessageUnit_B
344 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 407 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
345 uint32_t postq_index; 408 uint32_t postq_index;
346 uint32_t doneq_index; 409 uint32_t doneq_index;
347 uint32_t __iomem *drv2iop_doorbell_reg; 410 uint32_t __iomem *drv2iop_doorbell;
348 uint32_t __iomem *drv2iop_doorbell_mask_reg; 411 uint32_t __iomem *drv2iop_doorbell_mask;
349 uint32_t __iomem *iop2drv_doorbell_reg; 412 uint32_t __iomem *iop2drv_doorbell;
350 uint32_t __iomem *iop2drv_doorbell_mask_reg; 413 uint32_t __iomem *iop2drv_doorbell_mask;
351 uint32_t __iomem *msgcode_rwbuffer_reg; 414 uint32_t __iomem *message_rwbuffer;
352 uint32_t __iomem *ioctl_wbuffer_reg; 415 uint32_t __iomem *message_wbuffer;
353 uint32_t __iomem *ioctl_rbuffer_reg; 416 uint32_t __iomem *message_rbuffer;
417};
418/*
419*********************************************************************
420** LSI
421*********************************************************************
422*/
423struct MessageUnit_C{
424 uint32_t message_unit_status; /*0000 0003*/
425 uint32_t slave_error_attribute; /*0004 0007*/
426 uint32_t slave_error_address; /*0008 000B*/
427 uint32_t posted_outbound_doorbell; /*000C 000F*/
428 uint32_t master_error_attribute; /*0010 0013*/
429 uint32_t master_error_address_low; /*0014 0017*/
430 uint32_t master_error_address_high; /*0018 001B*/
431 uint32_t hcb_size; /*001C 001F*/
432 uint32_t inbound_doorbell; /*0020 0023*/
433 uint32_t diagnostic_rw_data; /*0024 0027*/
434 uint32_t diagnostic_rw_address_low; /*0028 002B*/
435 uint32_t diagnostic_rw_address_high; /*002C 002F*/
436 uint32_t host_int_status; /*0030 0033*/
437 uint32_t host_int_mask; /*0034 0037*/
438 uint32_t dcr_data; /*0038 003B*/
439 uint32_t dcr_address; /*003C 003F*/
440 uint32_t inbound_queueport; /*0040 0043*/
441 uint32_t outbound_queueport; /*0044 0047*/
442 uint32_t hcb_pci_address_low; /*0048 004B*/
443 uint32_t hcb_pci_address_high; /*004C 004F*/
444 uint32_t iop_int_status; /*0050 0053*/
445 uint32_t iop_int_mask; /*0054 0057*/
446 uint32_t iop_inbound_queue_port; /*0058 005B*/
447 uint32_t iop_outbound_queue_port; /*005C 005F*/
448 uint32_t inbound_free_list_index; /*0060 0063*/
449 uint32_t inbound_post_list_index; /*0064 0067*/
450 uint32_t outbound_free_list_index; /*0068 006B*/
451 uint32_t outbound_post_list_index; /*006C 006F*/
452 uint32_t inbound_doorbell_clear; /*0070 0073*/
453 uint32_t i2o_message_unit_control; /*0074 0077*/
454 uint32_t last_used_message_source_address_low; /*0078 007B*/
455 uint32_t last_used_message_source_address_high; /*007C 007F*/
456 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
457 uint32_t message_dest_address_index; /*0090 0093*/
458 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
459 uint32_t utility_A_int_counter_timer; /*0098 009B*/
460 uint32_t outbound_doorbell; /*009C 009F*/
461 uint32_t outbound_doorbell_clear; /*00A0 00A3*/
462 uint32_t message_source_address_index; /*00A4 00A7*/
463 uint32_t message_done_queue_index; /*00A8 00AB*/
464 uint32_t reserved0; /*00AC 00AF*/
465 uint32_t inbound_msgaddr0; /*00B0 00B3*/
466 uint32_t inbound_msgaddr1; /*00B4 00B7*/
467 uint32_t outbound_msgaddr0; /*00B8 00BB*/
468 uint32_t outbound_msgaddr1; /*00BC 00BF*/
469 uint32_t inbound_queueport_low; /*00C0 00C3*/
470 uint32_t inbound_queueport_high; /*00C4 00C7*/
471 uint32_t outbound_queueport_low; /*00C8 00CB*/
472 uint32_t outbound_queueport_high; /*00CC 00CF*/
473 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
474 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
475 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
476 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
477 uint32_t message_dest_queue_port_low; /*00E0 00E3*/
478 uint32_t message_dest_queue_port_high; /*00E4 00E7*/
479 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
480 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
481 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
482 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
483 uint32_t host_diagnostic; /*00F8 00FB*/
484 uint32_t write_sequence; /*00FC 00FF*/
485 uint32_t reserved1[34]; /*0100 0187*/
486 uint32_t reserved2[1950]; /*0188 1FFF*/
487 uint32_t message_wbuffer[32]; /*2000 207F*/
488 uint32_t reserved3[32]; /*2080 20FF*/
489 uint32_t message_rbuffer[32]; /*2100 217F*/
490 uint32_t reserved4[32]; /*2180 21FF*/
491 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/
354}; 492};
355
356/* 493/*
357******************************************************************************* 494*******************************************************************************
358** Adapter Control Block 495** Adapter Control Block
@@ -370,14 +507,20 @@ struct AdapterControlBlock
370 unsigned long vir2phy_offset; 507 unsigned long vir2phy_offset;
371 /* Offset is used in making arc cdb physical to virtual calculations */ 508 /* Offset is used in making arc cdb physical to virtual calculations */
372 uint32_t outbound_int_enable; 509 uint32_t outbound_int_enable;
373 510 uint32_t cdb_phyaddr_hi32;
511 uint32_t reg_mu_acc_handle0;
512 spinlock_t eh_lock;
513 spinlock_t ccblist_lock;
374 union { 514 union {
375 struct MessageUnit_A __iomem * pmuA; 515 struct MessageUnit_A __iomem *pmuA;
376 struct MessageUnit_B * pmuB; 516 struct MessageUnit_B *pmuB;
517 struct MessageUnit_C __iomem *pmuC;
377 }; 518 };
378 /* message unit ATU inbound base address0 */ 519 /* message unit ATU inbound base address0 */
379 520 void __iomem *mem_base0;
521 void __iomem *mem_base1;
380 uint32_t acb_flags; 522 uint32_t acb_flags;
523 u16 dev_id;
381 uint8_t adapter_index; 524 uint8_t adapter_index;
382 #define ACB_F_SCSISTOPADAPTER 0x0001 525 #define ACB_F_SCSISTOPADAPTER 0x0001
383 #define ACB_F_MSG_STOP_BGRB 0x0002 526 #define ACB_F_MSG_STOP_BGRB 0x0002
@@ -392,8 +535,11 @@ struct AdapterControlBlock
392 /* message clear rqbuffer */ 535 /* message clear rqbuffer */
393 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040 536 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
394 #define ACB_F_BUS_RESET 0x0080 537 #define ACB_F_BUS_RESET 0x0080
538 #define ACB_F_BUS_HANG_ON 0x0800/* need hardware reset bus */
539
395 #define ACB_F_IOP_INITED 0x0100 540 #define ACB_F_IOP_INITED 0x0100
396 /* iop init */ 541 /* iop init */
542 #define ACB_F_ABORT 0x0200
397 #define ACB_F_FIRMWARE_TRAP 0x0400 543 #define ACB_F_FIRMWARE_TRAP 0x0400
398 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM]; 544 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM];
399 /* used for memory free */ 545 /* used for memory free */
@@ -408,7 +554,8 @@ struct AdapterControlBlock
408 /* dma_coherent used for memory free */ 554 /* dma_coherent used for memory free */
409 dma_addr_t dma_coherent_handle; 555 dma_addr_t dma_coherent_handle;
410 /* dma_coherent_handle used for memory free */ 556 /* dma_coherent_handle used for memory free */
411 557 dma_addr_t dma_coherent_handle_hbb_mu;
558 unsigned int uncache_size;
412 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER]; 559 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER];
413 /* data collection buffer for read from 80331 */ 560 /* data collection buffer for read from 80331 */
414 int32_t rqbuf_firstindex; 561 int32_t rqbuf_firstindex;
@@ -432,14 +579,18 @@ struct AdapterControlBlock
432 uint32_t firm_numbers_queue; 579 uint32_t firm_numbers_queue;
433 uint32_t firm_sdram_size; 580 uint32_t firm_sdram_size;
434 uint32_t firm_hd_channels; 581 uint32_t firm_hd_channels;
435 char firm_model[12]; 582 uint32_t firm_cfg_version;
436 char firm_version[20]; 583 char firm_model[12];
584 char firm_version[20];
437 char device_map[20]; /*21,84-99*/ 585 char device_map[20]; /*21,84-99*/
438 struct work_struct arcmsr_do_message_isr_bh; 586 struct work_struct arcmsr_do_message_isr_bh;
439 struct timer_list eternal_timer; 587 struct timer_list eternal_timer;
440 unsigned short fw_state; 588 unsigned short fw_flag;
589 #define FW_NORMAL 0x0000
590 #define FW_BOG 0x0001
591 #define FW_DEADLOCK 0x0010
441 atomic_t rq_map_token; 592 atomic_t rq_map_token;
442 int ante_token_value; 593 atomic_t ante_token_value;
443};/* HW_DEVICE_EXTENSION */ 594};/* HW_DEVICE_EXTENSION */
444/* 595/*
445******************************************************************************* 596*******************************************************************************
@@ -447,67 +598,33 @@ struct AdapterControlBlock
447** this CCB length must be 32 bytes boundary 598** this CCB length must be 32 bytes boundary
448******************************************************************************* 599*******************************************************************************
449*/ 600*/
450struct CommandControlBlock 601struct CommandControlBlock{
451{ 602 /*x32:sizeof struct_CCB=(32+60)byte, x64:sizeof struct_CCB=(64+60)byte*/
452 struct ARCMSR_CDB arcmsr_cdb; 603 struct list_head list; /*x32: 8byte, x64: 16byte*/
453 /* 604 struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */
454 ** 0-503 (size of CDB = 504): 605 struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/
455 ** arcmsr messenger scsi command descriptor size 504 bytes 606 uint32_t cdb_phyaddr_pattern; /*x32: 4byte, x64: 4byte*/
456 */ 607 uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/
457 uint32_t cdb_shifted_phyaddr; 608 uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/
458 /* 504-507 */ 609 #define CCB_FLAG_READ 0x0000
459 uint32_t reserved1; 610 #define CCB_FLAG_WRITE 0x0001
460 /* 508-511 */ 611 #define CCB_FLAG_ERROR 0x0002
461#if BITS_PER_LONG == 64 612 #define CCB_FLAG_FLUSHCACHE 0x0004
613 #define CCB_FLAG_MASTER_ABORTED 0x0008
614 uint16_t startdone; /*x32:2byte,x32:2byte*/
615 #define ARCMSR_CCB_DONE 0x0000
616 #define ARCMSR_CCB_START 0x55AA
617 #define ARCMSR_CCB_ABORTED 0xAA55
618 #define ARCMSR_CCB_ILLEGAL 0xFFFF
619 #if BITS_PER_LONG == 64
462 /* ======================512+64 bytes======================== */ 620 /* ======================512+64 bytes======================== */
463 struct list_head list; 621 uint32_t reserved[5]; /*24 byte*/
464 /* 512-527 16 bytes next/prev ptrs for ccb lists */ 622 #else
465 struct scsi_cmnd * pcmd;
466 /* 528-535 8 bytes pointer of linux scsi command */
467 struct AdapterControlBlock * acb;
468 /* 536-543 8 bytes pointer of acb */
469
470 uint16_t ccb_flags;
471 /* 544-545 */
472 #define CCB_FLAG_READ 0x0000
473 #define CCB_FLAG_WRITE 0x0001
474 #define CCB_FLAG_ERROR 0x0002
475 #define CCB_FLAG_FLUSHCACHE 0x0004
476 #define CCB_FLAG_MASTER_ABORTED 0x0008
477 uint16_t startdone;
478 /* 546-547 */
479 #define ARCMSR_CCB_DONE 0x0000
480 #define ARCMSR_CCB_START 0x55AA
481 #define ARCMSR_CCB_ABORTED 0xAA55
482 #define ARCMSR_CCB_ILLEGAL 0xFFFF
483 uint32_t reserved2[7];
484 /* 548-551 552-555 556-559 560-563 564-567 568-571 572-575 */
485#else
486 /* ======================512+32 bytes======================== */ 623 /* ======================512+32 bytes======================== */
487 struct list_head list; 624 uint32_t reserved; /*8 byte*/
488 /* 512-519 8 bytes next/prev ptrs for ccb lists */ 625 #endif
489 struct scsi_cmnd * pcmd; 626 /* ======================================================= */
490 /* 520-523 4 bytes pointer of linux scsi command */ 627 struct ARCMSR_CDB arcmsr_cdb;
491 struct AdapterControlBlock * acb;
492 /* 524-527 4 bytes pointer of acb */
493
494 uint16_t ccb_flags;
495 /* 528-529 */
496 #define CCB_FLAG_READ 0x0000
497 #define CCB_FLAG_WRITE 0x0001
498 #define CCB_FLAG_ERROR 0x0002
499 #define CCB_FLAG_FLUSHCACHE 0x0004
500 #define CCB_FLAG_MASTER_ABORTED 0x0008
501 uint16_t startdone;
502 /* 530-531 */
503 #define ARCMSR_CCB_DONE 0x0000
504 #define ARCMSR_CCB_START 0x55AA
505 #define ARCMSR_CCB_ABORTED 0xAA55
506 #define ARCMSR_CCB_ILLEGAL 0xFFFF
507 uint32_t reserved2[3];
508 /* 532-535 536-539 540-543 */
509#endif
510 /* ========================================================== */
511}; 628};
512/* 629/*
513******************************************************************************* 630*******************************************************************************
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 20:34:09 -0500