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-rw-r--r--drivers/scsi/aic7xxx_old/aic7xxx.h28
-rw-r--r--drivers/scsi/aic7xxx_old/aic7xxx.reg1401
-rw-r--r--drivers/scsi/aic7xxx_old/aic7xxx.seq1539
-rw-r--r--drivers/scsi/aic7xxx_old/aic7xxx_proc.c374
-rw-r--r--drivers/scsi/aic7xxx_old/aic7xxx_reg.h629
-rw-r--r--drivers/scsi/aic7xxx_old/aic7xxx_seq.c817
-rw-r--r--drivers/scsi/aic7xxx_old/scsi_message.h49
-rw-r--r--drivers/scsi/aic7xxx_old/sequencer.h135
8 files changed, 4972 insertions, 0 deletions
diff --git a/drivers/scsi/aic7xxx_old/aic7xxx.h b/drivers/scsi/aic7xxx_old/aic7xxx.h
new file mode 100644
index 000000000000..0116c8128a6b
--- /dev/null
+++ b/drivers/scsi/aic7xxx_old/aic7xxx.h
@@ -0,0 +1,28 @@
1/*+M*************************************************************************
2 * Adaptec AIC7xxx device driver for Linux.
3 *
4 * Copyright (c) 1994 John Aycock
5 * The University of Calgary Department of Computer Science.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; see the file COPYING. If not, write to
19 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 * $Id: aic7xxx.h,v 3.2 1996/07/23 03:37:26 deang Exp $
22 *-M*************************************************************************/
23#ifndef _aic7xxx_h
24#define _aic7xxx_h
25
26#define AIC7XXX_H_VERSION "5.2.0"
27
28#endif /* _aic7xxx_h */
diff --git a/drivers/scsi/aic7xxx_old/aic7xxx.reg b/drivers/scsi/aic7xxx_old/aic7xxx.reg
new file mode 100644
index 000000000000..f67b4bced01c
--- /dev/null
+++ b/drivers/scsi/aic7xxx_old/aic7xxx.reg
@@ -0,0 +1,1401 @@
1/*
2 * Aic7xxx register and scratch ram definitions.
3 *
4 * Copyright (c) 1994-1998 Justin Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * Where this Software is combined with software released under the terms of
17 * the GNU General Public License ("GPL") and the terms of the GPL would require the
18 * combined work to also be released under the terms of the GPL, the terms
19 * and conditions of this License will apply in addition to those of the
20 * GPL with the exception of any terms or conditions of this License that
21 * conflict with, or are expressly prohibited by, the GPL.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * $Id: aic7xxx.reg,v 1.4 1997/06/27 19:38:39 gibbs Exp $
36 */
37
38/*
39 * This file is processed by the aic7xxx_asm utility for use in assembling
40 * firmware for the aic7xxx family of SCSI host adapters as well as to generate
41 * a C header file for use in the kernel portion of the Aic7xxx driver.
42 *
43 * All page numbers refer to the Adaptec AIC-7770 Data Book available from
44 * Adaptec's Technical Documents Department 1-800-934-2766
45 */
46
47/*
48 * SCSI Sequence Control (p. 3-11).
49 * Each bit, when set starts a specific SCSI sequence on the bus
50 */
51register SCSISEQ {
52 address 0x000
53 access_mode RW
54 bit TEMODE 0x80
55 bit ENSELO 0x40
56 bit ENSELI 0x20
57 bit ENRSELI 0x10
58 bit ENAUTOATNO 0x08
59 bit ENAUTOATNI 0x04
60 bit ENAUTOATNP 0x02
61 bit SCSIRSTO 0x01
62}
63
64/*
65 * SCSI Transfer Control 0 Register (pp. 3-13).
66 * Controls the SCSI module data path.
67 */
68register SXFRCTL0 {
69 address 0x001
70 access_mode RW
71 bit DFON 0x80
72 bit DFPEXP 0x40
73 bit FAST20 0x20
74 bit CLRSTCNT 0x10
75 bit SPIOEN 0x08
76 bit SCAMEN 0x04
77 bit CLRCHN 0x02
78}
79
80/*
81 * SCSI Transfer Control 1 Register (pp. 3-14,15).
82 * Controls the SCSI module data path.
83 */
84register SXFRCTL1 {
85 address 0x002
86 access_mode RW
87 bit BITBUCKET 0x80
88 bit SWRAPEN 0x40
89 bit ENSPCHK 0x20
90 mask STIMESEL 0x18
91 bit ENSTIMER 0x04
92 bit ACTNEGEN 0x02
93 bit STPWEN 0x01 /* Powered Termination */
94}
95
96/*
97 * SCSI Control Signal Read Register (p. 3-15).
98 * Reads the actual state of the SCSI bus pins
99 */
100register SCSISIGI {
101 address 0x003
102 access_mode RO
103 bit CDI 0x80
104 bit IOI 0x40
105 bit MSGI 0x20
106 bit ATNI 0x10
107 bit SELI 0x08
108 bit BSYI 0x04
109 bit REQI 0x02
110 bit ACKI 0x01
111/*
112 * Possible phases in SCSISIGI
113 */
114 mask PHASE_MASK CDI|IOI|MSGI
115 mask P_DATAOUT 0x00
116 mask P_DATAIN IOI
117 mask P_COMMAND CDI
118 mask P_MESGOUT CDI|MSGI
119 mask P_STATUS CDI|IOI
120 mask P_MESGIN CDI|IOI|MSGI
121}
122
123/*
124 * SCSI Control Signal Write Register (p. 3-16).
125 * Writing to this register modifies the control signals on the bus. Only
126 * those signals that are allowed in the current mode (Initiator/Target) are
127 * asserted.
128 */
129register SCSISIGO {
130 address 0x003
131 access_mode WO
132 bit CDO 0x80
133 bit IOO 0x40
134 bit MSGO 0x20
135 bit ATNO 0x10
136 bit SELO 0x08
137 bit BSYO 0x04
138 bit REQO 0x02
139 bit ACKO 0x01
140/*
141 * Possible phases to write into SCSISIG0
142 */
143 mask PHASE_MASK CDI|IOI|MSGI
144 mask P_DATAOUT 0x00
145 mask P_DATAIN IOI
146 mask P_COMMAND CDI
147 mask P_MESGOUT CDI|MSGI
148 mask P_STATUS CDI|IOI
149 mask P_MESGIN CDI|IOI|MSGI
150}
151
152/*
153 * SCSI Rate Control (p. 3-17).
154 * Contents of this register determine the Synchronous SCSI data transfer
155 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the
156 * SOFS (3:0) bits disables synchronous data transfers. Any offset value
157 * greater than 0 enables synchronous transfers.
158 */
159register SCSIRATE {
160 address 0x004
161 access_mode RW
162 bit WIDEXFER 0x80 /* Wide transfer control */
163 mask SXFR 0x70 /* Sync transfer rate */
164 mask SXFR_ULTRA2 0x7f /* Sync transfer rate */
165 mask SOFS 0x0f /* Sync offset */
166}
167
168/*
169 * SCSI ID (p. 3-18).
170 * Contains the ID of the board and the current target on the
171 * selected channel.
172 */
173register SCSIID {
174 address 0x005
175 access_mode RW
176 mask TID 0xf0 /* Target ID mask */
177 mask OID 0x0f /* Our ID mask */
178 /*
179 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)
180 * The aic7890/91 allow an offset of up to 127 transfers in both wide
181 * and narrow mode.
182 */
183 alias SCSIOFFSET
184 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */
185}
186
187/*
188 * SCSI Latched Data (p. 3-19).
189 * Read/Write latches used to transfer data on the SCSI bus during
190 * Automatic or Manual PIO mode. SCSIDATH can be used for the
191 * upper byte of a 16bit wide asynchronouse data phase transfer.
192 */
193register SCSIDATL {
194 address 0x006
195 access_mode RW
196}
197
198register SCSIDATH {
199 address 0x007
200 access_mode RW
201}
202
203/*
204 * SCSI Transfer Count (pp. 3-19,20)
205 * These registers count down the number of bytes transferred
206 * across the SCSI bus. The counter is decremented only once
207 * the data has been safely transferred. SDONE in SSTAT0 is
208 * set when STCNT goes to 0
209 */
210register STCNT {
211 address 0x008
212 size 3
213 access_mode RW
214}
215
216/*
217 * Option Mode Register (Alternate Mode) (p. 5-198)
218 * This register is used to set certain options on Ultra3 based chips.
219 * The chip must be in alternate mode (bit ALT_MODE in SFUNCT must be set)
220 */
221register OPTIONMODE {
222 address 0x008
223 access_mode RW
224 bit AUTORATEEN 0x80
225 bit AUTOACKEN 0x40
226 bit ATNMGMNTEN 0x20
227 bit BUSFREEREV 0x10
228 bit EXPPHASEDIS 0x08
229 bit SCSIDATL_IMGEN 0x04
230 bit AUTO_MSGOUT_DE 0x02
231 bit DIS_MSGIN_DUALEDGE 0x01
232}
233
234
235/*
236 * Clear SCSI Interrupt 0 (p. 3-20)
237 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
238 */
239register CLRSINT0 {
240 address 0x00b
241 access_mode WO
242 bit CLRSELDO 0x40
243 bit CLRSELDI 0x20
244 bit CLRSELINGO 0x10
245 bit CLRSWRAP 0x08
246 bit CLRSPIORDY 0x02
247}
248
249/*
250 * SCSI Status 0 (p. 3-21)
251 * Contains one set of SCSI Interrupt codes
252 * These are most likely of interest to the sequencer
253 */
254register SSTAT0 {
255 address 0x00b
256 access_mode RO
257 bit TARGET 0x80 /* Board acting as target */
258 bit SELDO 0x40 /* Selection Done */
259 bit SELDI 0x20 /* Board has been selected */
260 bit SELINGO 0x10 /* Selection In Progress */
261 bit SWRAP 0x08 /* 24bit counter wrap */
262 bit IOERR 0x08 /* LVD Tranceiver mode changed */
263 bit SDONE 0x04 /* STCNT = 0x000000 */
264 bit SPIORDY 0x02 /* SCSI PIO Ready */
265 bit DMADONE 0x01 /* DMA transfer completed */
266}
267
268/*
269 * Clear SCSI Interrupt 1 (p. 3-23)
270 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
271 */
272register CLRSINT1 {
273 address 0x00c
274 access_mode WO
275 bit CLRSELTIMEO 0x80
276 bit CLRATNO 0x40
277 bit CLRSCSIRSTI 0x20
278 bit CLRBUSFREE 0x08
279 bit CLRSCSIPERR 0x04
280 bit CLRPHASECHG 0x02
281 bit CLRREQINIT 0x01
282}
283
284/*
285 * SCSI Status 1 (p. 3-24)
286 */
287register SSTAT1 {
288 address 0x00c
289 access_mode RO
290 bit SELTO 0x80
291 bit ATNTARG 0x40
292 bit SCSIRSTI 0x20
293 bit PHASEMIS 0x10
294 bit BUSFREE 0x08
295 bit SCSIPERR 0x04
296 bit PHASECHG 0x02
297 bit REQINIT 0x01
298}
299
300/*
301 * SCSI Status 2 (pp. 3-25,26)
302 */
303register SSTAT2 {
304 address 0x00d
305 access_mode RO
306 bit OVERRUN 0x80
307 bit SHVALID 0x40
308 bit WIDE_RES 0x20
309 bit EXP_ACTIVE 0x10 /* SCSI Expander Active */
310 bit CRCVALERR 0x08 /* CRC Value Error */
311 bit CRCENDERR 0x04 /* CRC End Error */
312 bit CRCREQERR 0x02 /* CRC REQ Error */
313 bit DUAL_EDGE_ERROR 0x01 /* Invalid pins for Dual Edge phase */
314 mask SFCNT 0x1f
315}
316
317/*
318 * SCSI Status 3 (p. 3-26)
319 */
320register SSTAT3 {
321 address 0x00e
322 access_mode RO
323 mask SCSICNT 0xf0
324 mask OFFCNT 0x0f
325}
326
327/*
328 * SCSI ID for the aic7890/91 chips
329 */
330register SCSIID_ULTRA2 {
331 address 0x00f
332 access_mode RW
333 mask TID 0xf0 /* Target ID mask */
334 mask OID 0x0f /* Our ID mask */
335}
336
337/*
338 * SCSI Interrupt Mode 1 (p. 3-28)
339 * Setting any bit will enable the corresponding function
340 * in SIMODE0 to interrupt via the IRQ pin.
341 */
342register SIMODE0 {
343 address 0x010
344 access_mode RW
345 bit ENSELDO 0x40
346 bit ENSELDI 0x20
347 bit ENSELINGO 0x10
348 bit ENSWRAP 0x08
349 bit ENIOERR 0x08 /* LVD Tranceiver mode changes */
350 bit ENSDONE 0x04
351 bit ENSPIORDY 0x02
352 bit ENDMADONE 0x01
353}
354
355/*
356 * SCSI Interrupt Mode 1 (pp. 3-28,29)
357 * Setting any bit will enable the corresponding function
358 * in SIMODE1 to interrupt via the IRQ pin.
359 */
360register SIMODE1 {
361 address 0x011
362 access_mode RW
363 bit ENSELTIMO 0x80
364 bit ENATNTARG 0x40
365 bit ENSCSIRST 0x20
366 bit ENPHASEMIS 0x10
367 bit ENBUSFREE 0x08
368 bit ENSCSIPERR 0x04
369 bit ENPHASECHG 0x02
370 bit ENREQINIT 0x01
371}
372
373/*
374 * SCSI Data Bus (High) (p. 3-29)
375 * This register reads data on the SCSI Data bus directly.
376 */
377register SCSIBUSL {
378 address 0x012
379 access_mode RO
380}
381
382register SCSIBUSH {
383 address 0x013
384 access_mode RO
385}
386
387/*
388 * SCSI/Host Address (p. 3-30)
389 * These registers hold the host address for the byte about to be
390 * transferred on the SCSI bus. They are counted up in the same
391 * manner as STCNT is counted down. SHADDR should always be used
392 * to determine the address of the last byte transferred since HADDR
393 * can be skewed by write ahead.
394 */
395register SHADDR {
396 address 0x014
397 size 4
398 access_mode RO
399}
400
401/*
402 * Selection Timeout Timer (p. 3-30)
403 */
404register SELTIMER {
405 address 0x018
406 access_mode RW
407 bit STAGE6 0x20
408 bit STAGE5 0x10
409 bit STAGE4 0x08
410 bit STAGE3 0x04
411 bit STAGE2 0x02
412 bit STAGE1 0x01
413}
414
415/*
416 * Selection/Reselection ID (p. 3-31)
417 * Upper four bits are the device id. The ONEBIT is set when the re/selecting
418 * device did not set its own ID.
419 */
420register SELID {
421 address 0x019
422 access_mode RW
423 mask SELID_MASK 0xf0
424 bit ONEBIT 0x08
425}
426
427/*
428 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book)
429 * Indicates if external logic has been attached to the chip to
430 * perform the tasks of accessing a serial eeprom, testing termination
431 * strength, and performing cable detection. On the aic7860, most of
432 * these features are handled on chip, but on the aic7855 an attached
433 * aic3800 does the grunt work.
434 */
435register SPIOCAP {
436 address 0x01b
437 access_mode RW
438 bit SOFT1 0x80
439 bit SOFT0 0x40
440 bit SOFTCMDEN 0x20
441 bit HAS_BRDCTL 0x10 /* External Board control */
442 bit SEEPROM 0x08 /* External serial eeprom logic */
443 bit EEPROM 0x04 /* Writable external BIOS ROM */
444 bit ROM 0x02 /* Logic for accessing external ROM */
445 bit SSPIOCPS 0x01 /* Termination and cable detection */
446}
447
448/*
449 * SCSI Block Control (p. 3-32)
450 * Controls Bus type and channel selection. In a twin channel configuration
451 * addresses 0x00-0x1e are gated to the appropriate channel based on this
452 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
453 * on a wide bus.
454 */
455register SBLKCTL {
456 address 0x01f
457 access_mode RW
458 bit DIAGLEDEN 0x80 /* Aic78X0 only */
459 bit DIAGLEDON 0x40 /* Aic78X0 only */
460 bit AUTOFLUSHDIS 0x20
461 bit SELBUSB 0x08
462 bit ENAB40 0x08 /* LVD transceiver active */
463 bit ENAB20 0x04 /* SE/HVD transceiver active */
464 bit SELWIDE 0x02
465 bit XCVR 0x01 /* External transceiver active */
466}
467
468/*
469 * Sequencer Control (p. 3-33)
470 * Error detection mode and speed configuration
471 */
472register SEQCTL {
473 address 0x060
474 access_mode RW
475 bit PERRORDIS 0x80
476 bit PAUSEDIS 0x40
477 bit FAILDIS 0x20
478 bit FASTMODE 0x10
479 bit BRKADRINTEN 0x08
480 bit STEP 0x04
481 bit SEQRESET 0x02
482 bit LOADRAM 0x01
483}
484
485/*
486 * Sequencer RAM Data (p. 3-34)
487 * Single byte window into the Scratch Ram area starting at the address
488 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
489 * four bytes in succession. The SEQADDRs will increment after the most
490 * significant byte is written
491 */
492register SEQRAM {
493 address 0x061
494 access_mode RW
495}
496
497/*
498 * Sequencer Address Registers (p. 3-35)
499 * Only the first bit of SEQADDR1 holds addressing information
500 */
501register SEQADDR0 {
502 address 0x062
503 access_mode RW
504}
505
506register SEQADDR1 {
507 address 0x063
508 access_mode RW
509 mask SEQADDR1_MASK 0x01
510}
511
512/*
513 * Accumulator
514 * We cheat by passing arguments in the Accumulator up to the kernel driver
515 */
516register ACCUM {
517 address 0x064
518 access_mode RW
519 accumulator
520}
521
522register SINDEX {
523 address 0x065
524 access_mode RW
525 sindex
526}
527
528register DINDEX {
529 address 0x066
530 access_mode RW
531}
532
533register ALLONES {
534 address 0x069
535 access_mode RO
536 allones
537}
538
539register ALLZEROS {
540 address 0x06a
541 access_mode RO
542 allzeros
543}
544
545register NONE {
546 address 0x06a
547 access_mode WO
548 none
549}
550
551register FLAGS {
552 address 0x06b
553 access_mode RO
554 bit ZERO 0x02
555 bit CARRY 0x01
556}
557
558register SINDIR {
559 address 0x06c
560 access_mode RO
561}
562
563register DINDIR {
564 address 0x06d
565 access_mode WO
566}
567
568register FUNCTION1 {
569 address 0x06e
570 access_mode RW
571}
572
573register STACK {
574 address 0x06f
575 access_mode RO
576}
577
578/*
579 * Board Control (p. 3-43)
580 */
581register BCTL {
582 address 0x084
583 access_mode RW
584 bit ACE 0x08
585 bit ENABLE 0x01
586}
587
588register DSCOMMAND0 {
589 address 0x084
590 access_mode RW
591 bit CACHETHEN 0x80
592 bit DPARCKEN 0x40
593 bit MPARCKEN 0x20
594 bit EXTREQLCK 0x10
595 bit INTSCBRAMSEL 0x08
596 bit RAMPS 0x04
597 bit USCBSIZE32 0x02
598 bit CIOPARCKEN 0x01
599}
600
601/*
602 * On the aic78X0 chips, Board Control is replaced by the DSCommand
603 * register (p. 4-64)
604 */
605register DSCOMMAND {
606 address 0x084
607 access_mode RW
608 bit CACHETHEN 0x80 /* Cache Threshold enable */
609 bit DPARCKEN 0x40 /* Data Parity Check Enable */
610 bit MPARCKEN 0x20 /* Memory Parity Check Enable */
611 bit EXTREQLCK 0x10 /* External Request Lock */
612}
613
614/*
615 * Bus On/Off Time (p. 3-44)
616 */
617register BUSTIME {
618 address 0x085
619 access_mode RW
620 mask BOFF 0xf0
621 mask BON 0x0f
622}
623
624/*
625 * Bus Speed (p. 3-45)
626 */
627register BUSSPD {
628 address 0x086
629 access_mode RW
630 mask DFTHRSH 0xc0
631 mask STBOFF 0x38
632 mask STBON 0x07
633 mask DFTHRSH_100 0xc0
634}
635
636/*
637 * Host Control (p. 3-47) R/W
638 * Overall host control of the device.
639 */
640register HCNTRL {
641 address 0x087
642 access_mode RW
643 bit POWRDN 0x40
644 bit SWINT 0x10
645 bit IRQMS 0x08
646 bit PAUSE 0x04
647 bit INTEN 0x02
648 bit CHIPRST 0x01
649 bit CHIPRSTACK 0x01
650}
651
652/*
653 * Host Address (p. 3-48)
654 * This register contains the address of the byte about
655 * to be transferred across the host bus.
656 */
657register HADDR {
658 address 0x088
659 size 4
660 access_mode RW
661}
662
663register HCNT {
664 address 0x08c
665 size 3
666 access_mode RW
667}
668
669/*
670 * SCB Pointer (p. 3-49)
671 * Gate one of the four SCBs into the SCBARRAY window.
672 */
673register SCBPTR {
674 address 0x090
675 access_mode RW
676}
677
678/*
679 * Interrupt Status (p. 3-50)
680 * Status for system interrupts
681 */
682register INTSTAT {
683 address 0x091
684 access_mode RW
685 bit BRKADRINT 0x08
686 bit SCSIINT 0x04
687 bit CMDCMPLT 0x02
688 bit SEQINT 0x01
689 mask BAD_PHASE SEQINT /* unknown scsi bus phase */
690 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */
691 mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/
692 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */
693 mask EXTENDED_MSG 0x40|SEQINT /* Extended message received */
694 mask WIDE_RESIDUE 0x50|SEQINT /* need kernel to back up */
695 /* the SG array for us */
696 mask REJECT_MSG 0x60|SEQINT /* Reject message received */
697 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */
698 mask RESIDUAL 0x80|SEQINT /* Residual byte count != 0 */
699 mask AWAITING_MSG 0xa0|SEQINT /*
700 * Kernel requested to specify
701 * a message to this target
702 * (command was null), so tell
703 * it that it can fill the
704 * message buffer.
705 */
706 mask SEQ_SG_FIXUP 0xb0|SEQINT /* need help with fixing up
707 * the sg array pointer after
708 * a phasemis with no valid
709 * sg elements in the shadow
710 * pipeline.
711 */
712 mask TRACEPOINT2 0xc0|SEQINT
713 mask MSGIN_PHASEMIS 0xd0|SEQINT /*
714 * Target changed phase on us
715 * when we were expecting
716 * another msgin byte.
717 */
718 mask DATA_OVERRUN 0xe0|SEQINT /*
719 * Target attempted to write
720 * beyond the bounds of its
721 * command.
722 */
723
724 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */
725 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
726}
727
728/*
729 * Hard Error (p. 3-53)
730 * Reporting of catastrophic errors. You usually cannot recover from
731 * these without a full board reset.
732 */
733register ERROR {
734 address 0x092
735 access_mode RO
736 bit CIOPARERR 0x80 /* Ultra2 only */
737 bit PCIERRSTAT 0x40 /* PCI only */
738 bit MPARERR 0x20 /* PCI only */
739 bit DPARERR 0x10 /* PCI only */
740 bit SQPARERR 0x08
741 bit ILLOPCODE 0x04
742 bit ILLSADDR 0x02
743 bit DSCTMOUT 0x02 /* Ultra3 only */
744 bit ILLHADDR 0x01
745}
746
747/*
748 * Clear Interrupt Status (p. 3-52)
749 */
750register CLRINT {
751 address 0x092
752 access_mode WO
753 bit CLRPARERR 0x10 /* PCI only */
754 bit CLRBRKADRINT 0x08
755 bit CLRSCSIINT 0x04
756 bit CLRCMDINT 0x02
757 bit CLRSEQINT 0x01
758}
759
760register DFCNTRL {
761 address 0x093
762 access_mode RW
763 bit PRELOADEN 0x80 /* aic7890 only */
764 bit WIDEODD 0x40
765 bit SCSIEN 0x20
766 bit SDMAEN 0x10
767 bit SDMAENACK 0x10
768 bit HDMAEN 0x08
769 bit HDMAENACK 0x08
770 bit DIRECTION 0x04
771 bit FIFOFLUSH 0x02
772 bit FIFORESET 0x01
773}
774
775register DFSTATUS {
776 address 0x094
777 access_mode RO
778 bit PRELOAD_AVAIL 0x80
779 bit DWORDEMP 0x20
780 bit MREQPEND 0x10
781 bit HDONE 0x08
782 bit DFTHRESH 0x04
783 bit FIFOFULL 0x02
784 bit FIFOEMP 0x01
785}
786
787register DFDAT {
788 address 0x099
789 access_mode RW
790}
791
792/*
793 * SCB Auto Increment (p. 3-59)
794 * Byte offset into the SCB Array and an optional bit to allow auto
795 * incrementing of the address during download and upload operations
796 */
797register SCBCNT {
798 address 0x09a
799 access_mode RW
800 bit SCBAUTO 0x80
801 mask SCBCNT_MASK 0x1f
802}
803
804/*
805 * Queue In FIFO (p. 3-60)
806 * Input queue for queued SCBs (commands that the seqencer has yet to start)
807 */
808register QINFIFO {
809 address 0x09b
810 access_mode RW
811}
812
813/*
814 * Queue In Count (p. 3-60)
815 * Number of queued SCBs
816 */
817register QINCNT {
818 address 0x09c
819 access_mode RO
820}
821
822/*
823 * SCSIDATL IMAGE Register (p. 5-104)
824 * Write to this register also go to SCSIDATL but this register will preserve
825 * the data for later reading as long as the SCSIDATL_IMGEN bit in the
826 * OPTIONMODE register is set.
827 */
828register SCSIDATL_IMG {
829 address 0x09c
830 access_mode RW
831}
832
833/*
834 * Queue Out FIFO (p. 3-61)
835 * Queue of SCBs that have completed and await the host
836 */
837register QOUTFIFO {
838 address 0x09d
839 access_mode WO
840}
841
842/*
843 * CRC Control 1 Register (p. 5-105)
844 * Control bits for the Ultra 160/m CRC facilities
845 */
846register CRCCONTROL1 {
847 address 0x09d
848 access_mode RW
849 bit CRCONSEEN 0x80 /* CRC ON Single Edge ENable */
850 bit CRCVALCHKEN 0x40 /* CRC Value Check Enable */
851 bit CRCENDCHKEN 0x20 /* CRC End Check Enable */
852 bit CRCREQCHKEN 0x10
853 bit TARGCRCENDEN 0x08 /* Enable End CRC transfer when target */
854 bit TARGCRCCNTEN 0x04 /* Enable CRC transfer when target */
855}
856
857/*
858 * Queue Out Count (p. 3-61)
859 * Number of queued SCBs in the Out FIFO
860 */
861register QOUTCNT {
862 address 0x09e
863 access_mode RO
864}
865
866/*
867 * SCSI Phase Register (p. 5-106)
868 * Current bus phase
869 */
870register SCSIPHASE {
871 address 0x09e
872 access_mode RO
873 bit SP_STATUS 0x20
874 bit SP_COMMAND 0x10
875 bit SP_MSG_IN 0x08
876 bit SP_MSG_OUT 0x04
877 bit SP_DATA_IN 0x02
878 bit SP_DATA_OUT 0x01
879}
880
881/*
882 * Special Function
883 */
884register SFUNCT {
885 address 0x09f
886 access_mode RW
887 bit ALT_MODE 0x80
888}
889
890/*
891 * SCB Definition (p. 5-4)
892 */
893scb {
894 address 0x0a0
895 SCB_CONTROL {
896 size 1
897 bit MK_MESSAGE 0x80
898 bit DISCENB 0x40
899 bit TAG_ENB 0x20
900 bit DISCONNECTED 0x04
901 mask SCB_TAG_TYPE 0x03
902 }
903 SCB_TCL {
904 size 1
905 bit SELBUSB 0x08
906 mask TID 0xf0
907 mask LID 0x07
908 }
909 SCB_TARGET_STATUS {
910 size 1
911 }
912 SCB_SGCOUNT {
913 size 1
914 }
915 SCB_SGPTR {
916 size 4
917 }
918 SCB_RESID_SGCNT {
919 size 1
920 }
921 SCB_RESID_DCNT {
922 size 3
923 }
924 SCB_DATAPTR {
925 size 4
926 }
927 SCB_DATACNT {
928 /*
929 * Really only 3 bytes, but padded to make
930 * the kernel's job easier.
931 */
932 size 4
933 }
934 SCB_CMDPTR {
935 size 4
936 }
937 SCB_CMDLEN {
938 size 1
939 }
940 SCB_TAG {
941 size 1
942 }
943 SCB_NEXT {
944 size 1
945 }
946 SCB_PREV {
947 size 1
948 }
949 SCB_BUSYTARGETS {
950 size 4
951 }
952}
953
954const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */
955
956/* --------------------- AHA-2840-only definitions -------------------- */
957
958register SEECTL_2840 {
959 address 0x0c0
960 access_mode RW
961 bit CS_2840 0x04
962 bit CK_2840 0x02
963 bit DO_2840 0x01
964}
965
966register STATUS_2840 {
967 address 0x0c1
968 access_mode RW
969 bit EEPROM_TF 0x80
970 mask BIOS_SEL 0x60
971 mask ADSEL 0x1e
972 bit DI_2840 0x01
973}
974
975/* --------------------- AIC-7870-only definitions -------------------- */
976
977register DSPCISTATUS {
978 address 0x086
979 mask DFTHRSH_100 0xc0
980}
981
982register CCHADDR {
983 address 0x0E0
984 size 8
985}
986
987register CCHCNT {
988 address 0x0E8
989}
990
991register CCSGRAM {
992 address 0x0E9
993}
994
995register CCSGADDR {
996 address 0x0EA
997}
998
999register CCSGCTL {
1000 address 0x0EB
1001 bit CCSGDONE 0x80
1002 bit CCSGEN 0x08
1003 bit FLAG 0x02
1004 bit CCSGRESET 0x01
1005}
1006
1007register CCSCBCNT {
1008 address 0xEF
1009}
1010
1011register CCSCBCTL {
1012 address 0x0EE
1013 bit CCSCBDONE 0x80
1014 bit ARRDONE 0x40 /* SCB Array prefetch done */
1015 bit CCARREN 0x10
1016 bit CCSCBEN 0x08
1017 bit CCSCBDIR 0x04
1018 bit CCSCBRESET 0x01
1019}
1020
1021register CCSCBADDR {
1022 address 0x0ED
1023}
1024
1025register CCSCBRAM {
1026 address 0xEC
1027}
1028
1029register CCSCBPTR {
1030 address 0x0F1
1031}
1032
1033register HNSCB_QOFF {
1034 address 0x0F4
1035}
1036
1037register HESCB_QOFF {
1038 address 0x0F5
1039}
1040
1041register SNSCB_QOFF {
1042 address 0x0F6
1043}
1044
1045register SESCB_QOFF {
1046 address 0x0F7
1047}
1048
1049register SDSCB_QOFF {
1050 address 0x0F8
1051}
1052
1053register QOFF_CTLSTA {
1054 address 0x0FA
1055 bit ESTABLISH_SCB_AVAIL 0x80
1056 bit SCB_AVAIL 0x40
1057 bit SNSCB_ROLLOVER 0x20
1058 bit SDSCB_ROLLOVER 0x10
1059 bit SESCB_ROLLOVER 0x08
1060 mask SCB_QSIZE 0x07
1061 mask SCB_QSIZE_256 0x06
1062}
1063
1064register DFF_THRSH {
1065 address 0x0FB
1066 mask WR_DFTHRSH 0x70
1067 mask RD_DFTHRSH 0x07
1068 mask RD_DFTHRSH_MIN 0x00
1069 mask RD_DFTHRSH_25 0x01
1070 mask RD_DFTHRSH_50 0x02
1071 mask RD_DFTHRSH_63 0x03
1072 mask RD_DFTHRSH_75 0x04
1073 mask RD_DFTHRSH_85 0x05
1074 mask RD_DFTHRSH_90 0x06
1075 mask RD_DFTHRSH_MAX 0x07
1076 mask WR_DFTHRSH_MIN 0x00
1077 mask WR_DFTHRSH_25 0x10
1078 mask WR_DFTHRSH_50 0x20
1079 mask WR_DFTHRSH_63 0x30
1080 mask WR_DFTHRSH_75 0x40
1081 mask WR_DFTHRSH_85 0x50
1082 mask WR_DFTHRSH_90 0x60
1083 mask WR_DFTHRSH_MAX 0x70
1084}
1085
1086register SG_CACHEPTR {
1087 access_mode RW
1088 address 0x0fc
1089 mask SG_USER_DATA 0xfc
1090 bit LAST_SEG 0x02
1091 bit LAST_SEG_DONE 0x01
1092}
1093
1094register BRDCTL {
1095 address 0x01d
1096 bit BRDDAT7 0x80
1097 bit BRDDAT6 0x40
1098 bit BRDDAT5 0x20
1099 bit BRDSTB 0x10
1100 bit BRDCS 0x08
1101 bit BRDRW 0x04
1102 bit BRDCTL1 0x02
1103 bit BRDCTL0 0x01
1104 /* 7890 Definitions */
1105 bit BRDDAT4 0x10
1106 bit BRDDAT3 0x08
1107 bit BRDDAT2 0x04
1108 bit BRDRW_ULTRA2 0x02
1109 bit BRDSTB_ULTRA2 0x01
1110}
1111
1112/*
1113 * Serial EEPROM Control (p. 4-92 in 7870 Databook)
1114 * Controls the reading and writing of an external serial 1-bit
1115 * EEPROM Device. In order to access the serial EEPROM, you must
1116 * first set the SEEMS bit that generates a request to the memory
1117 * port for access to the serial EEPROM device. When the memory
1118 * port is not busy servicing another request, it reconfigures
1119 * to allow access to the serial EEPROM. When this happens, SEERDY
1120 * gets set high to verify that the memory port access has been
1121 * granted.
1122 *
1123 * After successful arbitration for the memory port, the SEECS bit of
1124 * the SEECTL register is connected to the chip select. The SEECK,
1125 * SEEDO, and SEEDI are connected to the clock, data out, and data in
1126 * lines respectively. The SEERDY bit of SEECTL is useful in that it
1127 * gives us an 800 nsec timer. After a write to the SEECTL register,
1128 * the SEERDY goes high 800 nsec later. The one exception to this is
1129 * when we first request access to the memory port. The SEERDY goes
1130 * high to signify that access has been granted and, for this case, has
1131 * no implied timing.
1132 *
1133 * See 93cx6.c for detailed information on the protocol necessary to
1134 * read the serial EEPROM.
1135 */
1136register SEECTL {
1137 address 0x01e
1138 bit EXTARBACK 0x80
1139 bit EXTARBREQ 0x40
1140 bit SEEMS 0x20
1141 bit SEERDY 0x10
1142 bit SEECS 0x08
1143 bit SEECK 0x04
1144 bit SEEDO 0x02
1145 bit SEEDI 0x01
1146}
1147/* ---------------------- Scratch RAM Offsets ------------------------- */
1148/* These offsets are either to values that are initialized by the board's
1149 * BIOS or are specified by the sequencer code.
1150 *
1151 * The host adapter card (at least the BIOS) uses 20-2f for SCSI
1152 * device information, 32-33 and 5a-5f as well. As it turns out, the
1153 * BIOS trashes 20-2f, writing the synchronous negotiation results
1154 * on top of the BIOS values, so we re-use those for our per-target
1155 * scratchspace (actually a value that can be copied directly into
1156 * SCSIRATE). The kernel driver will enable synchronous negotiation
1157 * for all targets that have a value other than 0 in the lower four
1158 * bits of the target scratch space. This should work regardless of
1159 * whether the bios has been installed.
1160 */
1161
1162scratch_ram {
1163 address 0x020
1164
1165 /*
1166 * 1 byte per target starting at this address for configuration values
1167 */
1168 TARG_SCSIRATE {
1169 size 16
1170 }
1171 /*
1172 * Bit vector of targets that have ULTRA enabled.
1173 */
1174 ULTRA_ENB {
1175 size 2
1176 }
1177 /*
1178 * Bit vector of targets that have disconnection disabled.
1179 */
1180 DISC_DSB {
1181 size 2
1182 }
1183 /*
1184 * Single byte buffer used to designate the type or message
1185 * to send to a target.
1186 */
1187 MSG_OUT {
1188 size 1
1189 }
1190 /* Parameters for DMA Logic */
1191 DMAPARAMS {
1192 size 1
1193 bit PRELOADEN 0x80
1194 bit WIDEODD 0x40
1195 bit SCSIEN 0x20
1196 bit SDMAEN 0x10
1197 bit SDMAENACK 0x10
1198 bit HDMAEN 0x08
1199 bit HDMAENACK 0x08
1200 bit DIRECTION 0x04
1201 bit FIFOFLUSH 0x02
1202 bit FIFORESET 0x01
1203 }
1204 SEQ_FLAGS {
1205 size 1
1206 bit IDENTIFY_SEEN 0x80
1207 bit SCBPTR_VALID 0x20
1208 bit DPHASE 0x10
1209 bit AMTARGET 0x08
1210 bit WIDE_BUS 0x02
1211 bit TWIN_BUS 0x01
1212 }
1213 /*
1214 * Temporary storage for the
1215 * target/channel/lun of a
1216 * reconnecting target
1217 */
1218 SAVED_TCL {
1219 size 1
1220 }
1221 /* Working value of the number of SG segments left */
1222 SG_COUNT {
1223 size 1
1224 }
1225 /* Working value of SG pointer */
1226 SG_NEXT {
1227 size 4
1228 }
1229 /*
1230 * The last bus phase as seen by the sequencer.
1231 */
1232 LASTPHASE {
1233 size 1
1234 bit CDI 0x80
1235 bit IOI 0x40
1236 bit MSGI 0x20
1237 mask PHASE_MASK CDI|IOI|MSGI
1238 mask P_DATAOUT 0x00
1239 mask P_DATAIN IOI
1240 mask P_COMMAND CDI
1241 mask P_MESGOUT CDI|MSGI
1242 mask P_STATUS CDI|IOI
1243 mask P_MESGIN CDI|IOI|MSGI
1244 mask P_BUSFREE 0x01
1245 }
1246 /*
1247 * head of list of SCBs awaiting
1248 * selection
1249 */
1250 WAITING_SCBH {
1251 size 1
1252 }
1253 /*
1254 * head of list of SCBs that are
1255 * disconnected. Used for SCB
1256 * paging.
1257 */
1258 DISCONNECTED_SCBH {
1259 size 1
1260 }
1261 /*
1262 * head of list of SCBs that are
1263 * not in use. Used for SCB paging.
1264 */
1265 FREE_SCBH {
1266 size 1
1267 }
1268 /*
1269 * Address of the hardware scb array in the host.
1270 */
1271 HSCB_ADDR {
1272 size 4
1273 }
1274 /*
1275 * Address of the 256 byte array storing the SCBID of outstanding
1276 * untagged SCBs indexed by TCL.
1277 */
1278 SCBID_ADDR {
1279 size 4
1280 }
1281 /*
1282 * Address of the array of command descriptors used to store
1283 * information about incoming selections.
1284 */
1285 TMODE_CMDADDR {
1286 size 4
1287 }
1288 KERNEL_QINPOS {
1289 size 1
1290 }
1291 QINPOS {
1292 size 1
1293 }
1294 QOUTPOS {
1295 size 1
1296 }
1297 /*
1298 * Offset into the command descriptor array for the next
1299 * available desciptor to use.
1300 */
1301 TMODE_CMDADDR_NEXT {
1302 size 1
1303 }
1304 ARG_1 {
1305 size 1
1306 mask SEND_MSG 0x80
1307 mask SEND_SENSE 0x40
1308 mask SEND_REJ 0x20
1309 mask MSGOUT_PHASEMIS 0x10
1310 alias RETURN_1
1311 }
1312 ARG_2 {
1313 size 1
1314 alias RETURN_2
1315 }
1316
1317 /*
1318 * Snapshot of MSG_OUT taken after each message is sent.
1319 */
1320 LAST_MSG {
1321 size 1
1322 }
1323
1324 /*
1325 * Number of times we have filled the CCSGRAM with prefetched
1326 * SG elements.
1327 */
1328 PREFETCH_CNT {
1329 size 1
1330 }
1331
1332
1333 /*
1334 * These are reserved registers in the card's scratch ram. Some of
1335 * the values are specified in the AHA2742 technical reference manual
1336 * and are initialized by the BIOS at boot time.
1337 */
1338 SCSICONF {
1339 address 0x05a
1340 size 1
1341 bit TERM_ENB 0x80
1342 bit RESET_SCSI 0x40
1343 mask HSCSIID 0x07 /* our SCSI ID */
1344 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */
1345 }
1346 HOSTCONF {
1347 address 0x05d
1348 size 1
1349 }
1350 HA_274_BIOSCTRL {
1351 address 0x05f
1352 size 1
1353 mask BIOSMODE 0x30
1354 mask BIOSDISABLED 0x30
1355 bit CHANNEL_B_PRIMARY 0x08
1356 }
1357 /*
1358 * Per target SCSI offset values for Ultra2 controllers.
1359 */
1360 TARG_OFFSET {
1361 address 0x070
1362 size 16
1363 }
1364}
1365
1366const SCB_LIST_NULL 0xff
1367
1368const CCSGADDR_MAX 0x80
1369const CCSGRAM_MAXSEGS 16
1370
1371/* Offsets into the SCBID array where different data is stored */
1372const UNTAGGEDSCB_OFFSET 0
1373const QOUTFIFO_OFFSET 1
1374const QINFIFO_OFFSET 2
1375
1376/* WDTR Message values */
1377const BUS_8_BIT 0x00
1378const BUS_16_BIT 0x01
1379const BUS_32_BIT 0x02
1380
1381/* Offset maximums */
1382const MAX_OFFSET_8BIT 0x0f
1383const MAX_OFFSET_16BIT 0x08
1384const MAX_OFFSET_ULTRA2 0x7f
1385const HOST_MSG 0xff
1386
1387/* Target mode command processing constants */
1388const CMD_GROUP_CODE_SHIFT 0x05
1389const CMD_GROUP0_BYTE_DELTA -4
1390const CMD_GROUP2_BYTE_DELTA -6
1391const CMD_GROUP4_BYTE_DELTA 4
1392const CMD_GROUP5_BYTE_DELTA 11
1393
1394/*
1395 * Downloaded (kernel inserted) constants
1396 */
1397
1398/*
1399 * Number of command descriptors in the command descriptor array.
1400 */
1401const TMODE_NUMCMDS download
diff --git a/drivers/scsi/aic7xxx_old/aic7xxx.seq b/drivers/scsi/aic7xxx_old/aic7xxx.seq
new file mode 100644
index 000000000000..f6fc4b75b5a5
--- /dev/null
+++ b/drivers/scsi/aic7xxx_old/aic7xxx.seq
@@ -0,0 +1,1539 @@
1/*
2 * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD.
3 *
4 * Copyright (c) 1994-1999 Justin Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * Where this Software is combined with software released under the terms of
17 * the GNU General Public License (GPL) and the terms of the GPL would require the
18 * combined work to also be released under the terms of the GPL, the terms
19 * and conditions of this License will apply in addition to those of the
20 * GPL with the exception of any terms or conditions of this License that
21 * conflict with, or are expressly prohibited by, the GPL.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * $Id: aic7xxx.seq,v 1.77 1998/06/28 02:58:57 gibbs Exp $
36 */
37
38#include "aic7xxx.reg"
39#include "scsi_message.h"
40
41/*
42 * A few words on the waiting SCB list:
43 * After starting the selection hardware, we check for reconnecting targets
44 * as well as for our selection to complete just in case the reselection wins
45 * bus arbitration. The problem with this is that we must keep track of the
46 * SCB that we've already pulled from the QINFIFO and started the selection
47 * on just in case the reselection wins so that we can retry the selection at
48 * a later time. This problem cannot be resolved by holding a single entry
49 * in scratch ram since a reconnecting target can request sense and this will
50 * create yet another SCB waiting for selection. The solution used here is to
51 * use byte 27 of the SCB as a pseudo-next pointer and to thread a list
52 * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes,
53 * SCB_LIST_NULL is 0xff which is out of range. An entry is also added to
54 * this list everytime a request sense occurs or after completing a non-tagged
55 * command for which a second SCB has been queued. The sequencer will
56 * automatically consume the entries.
57 */
58
59reset:
60 clr SCSISIGO; /* De-assert BSY */
61 and SXFRCTL1, ~BITBUCKET;
62 /* Always allow reselection */
63 mvi SCSISEQ, ENRSELI|ENAUTOATNP;
64
65 if ((p->features & AHC_CMD_CHAN) != 0) {
66 /* Ensure that no DMA operations are in progress */
67 clr CCSGCTL;
68 clr CCSCBCTL;
69 }
70
71 call clear_target_state;
72poll_for_work:
73 and SXFRCTL0, ~SPIOEN;
74 if ((p->features & AHC_QUEUE_REGS) == 0) {
75 mov A, QINPOS;
76 }
77poll_for_work_loop:
78 if ((p->features & AHC_QUEUE_REGS) == 0) {
79 and SEQCTL, ~PAUSEDIS;
80 }
81 test SSTAT0, SELDO|SELDI jnz selection;
82 test SCSISEQ, ENSELO jnz poll_for_work;
83 if ((p->features & AHC_TWIN) != 0) {
84 /*
85 * Twin channel devices cannot handle things like SELTO
86 * interrupts on the "background" channel. So, if we
87 * are selecting, keep polling the current channel util
88 * either a selection or reselection occurs.
89 */
90 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */
91 test SSTAT0, SELDO|SELDI jnz selection;
92 test SCSISEQ, ENSELO jnz poll_for_work;
93 xor SBLKCTL,SELBUSB; /* Toggle back */
94 }
95 cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting;
96test_queue:
97 /* Has the driver posted any work for us? */
98 if ((p->features & AHC_QUEUE_REGS) != 0) {
99 test QOFF_CTLSTA, SCB_AVAIL jz poll_for_work_loop;
100 mov NONE, SNSCB_QOFF;
101 inc QINPOS;
102 } else {
103 or SEQCTL, PAUSEDIS;
104 cmp KERNEL_QINPOS, A je poll_for_work_loop;
105 inc QINPOS;
106 and SEQCTL, ~PAUSEDIS;
107 }
108
109/*
110 * We have at least one queued SCB now and we don't have any
111 * SCBs in the list of SCBs awaiting selection. If we have
112 * any SCBs available for use, pull the tag from the QINFIFO
113 * and get to work on it.
114 */
115 if ((p->flags & AHC_PAGESCBS) != 0) {
116 mov ALLZEROS call get_free_or_disc_scb;
117 }
118
119dequeue_scb:
120 add A, -1, QINPOS;
121 mvi QINFIFO_OFFSET call fetch_byte;
122
123 if ((p->flags & AHC_PAGESCBS) == 0) {
124 /* In the non-paging case, the SCBID == hardware SCB index */
125 mov SCBPTR, RETURN_2;
126 }
127dma_queued_scb:
128/*
129 * DMA the SCB from host ram into the current SCB location.
130 */
131 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
132 mov RETURN_2 call dma_scb;
133
134/*
135 * Preset the residual fields in case we never go through a data phase.
136 * This isn't done by the host so we can avoid a DMA to clear these
137 * fields for the normal case of I/O that completes without underrun
138 * or overrun conditions.
139 */
140 if ((p->features & AHC_CMD_CHAN) != 0) {
141 bmov SCB_RESID_DCNT, SCB_DATACNT, 3;
142 } else {
143 mov SCB_RESID_DCNT[0],SCB_DATACNT[0];
144 mov SCB_RESID_DCNT[1],SCB_DATACNT[1];
145 mov SCB_RESID_DCNT[2],SCB_DATACNT[2];
146 }
147 mov SCB_RESID_SGCNT, SCB_SGCOUNT;
148
149start_scb:
150 /*
151 * Place us on the waiting list in case our selection
152 * doesn't win during bus arbitration.
153 */
154 mov SCB_NEXT,WAITING_SCBH;
155 mov WAITING_SCBH, SCBPTR;
156start_waiting:
157 /*
158 * Pull the first entry off of the waiting SCB list.
159 */
160 mov SCBPTR, WAITING_SCBH;
161 call start_selection;
162 jmp poll_for_work;
163
164start_selection:
165 if ((p->features & AHC_TWIN) != 0) {
166 and SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */
167 and A,SELBUSB,SCB_TCL; /* Get new channel bit */
168 or SINDEX,A;
169 mov SBLKCTL,SINDEX; /* select channel */
170 }
171initialize_scsiid:
172 if ((p->features & AHC_ULTRA2) != 0) {
173 and A, TID, SCB_TCL; /* Get target ID */
174 and SCSIID_ULTRA2, OID; /* Clear old target */
175 or SCSIID_ULTRA2, A;
176 } else {
177 and A, TID, SCB_TCL; /* Get target ID */
178 and SCSIID, OID; /* Clear old target */
179 or SCSIID, A;
180 }
181 mov SCSIDATL, ALLZEROS; /* clear out the latched */
182 /* data register, this */
183 /* fixes a bug on some */
184 /* controllers where the */
185 /* last byte written to */
186 /* this register can leak */
187 /* onto the data bus at */
188 /* bad times, such as during */
189 /* selection timeouts */
190 mvi SCSISEQ, ENSELO|ENAUTOATNO|ENRSELI|ENAUTOATNP ret;
191
192/*
193 * Initialize Ultra mode setting and clear the SCSI channel.
194 * SINDEX should contain any additional bit's the client wants
195 * set in SXFRCTL0.
196 */
197initialize_channel:
198 or SXFRCTL0, CLRSTCNT|CLRCHN, SINDEX;
199 if ((p->features & AHC_ULTRA) != 0) {
200ultra:
201 mvi SINDEX, ULTRA_ENB+1;
202 test SAVED_TCL, 0x80 jnz ultra_2; /* Target ID > 7 */
203 dec SINDEX;
204ultra_2:
205 mov FUNCTION1,SAVED_TCL;
206 mov A,FUNCTION1;
207 test SINDIR, A jz ndx_dtr;
208 or SXFRCTL0, FAST20;
209 }
210/*
211 * Initialize SCSIRATE with the appropriate value for this target.
212 * The SCSIRATE settings for each target are stored in an array
213 * based at TARG_SCSIRATE.
214 */
215ndx_dtr:
216 shr A,4,SAVED_TCL;
217 if ((p->features & AHC_TWIN) != 0) {
218 test SBLKCTL,SELBUSB jz ndx_dtr_2;
219 or SAVED_TCL, SELBUSB;
220 or A,0x08; /* Channel B entries add 8 */
221ndx_dtr_2:
222 }
223
224 if ((p->features & AHC_ULTRA2) != 0) {
225 add SINDEX, TARG_OFFSET, A;
226 mov SCSIOFFSET, SINDIR;
227 }
228
229 add SINDEX,TARG_SCSIRATE,A;
230 mov SCSIRATE,SINDIR ret;
231
232
233selection:
234 test SSTAT0,SELDO jnz select_out;
235/*
236 * Reselection has been initiated by a target. Make a note that we've been
237 * reselected, but haven't seen an IDENTIFY message from the target yet.
238 */
239initiator_reselect:
240 mvi CLRSINT0, CLRSELDI;
241 /* XXX test for and handle ONE BIT condition */
242 and SAVED_TCL, SELID_MASK, SELID;
243 mvi CLRSINT1,CLRBUSFREE;
244 or SIMODE1, ENBUSFREE; /*
245 * We aren't expecting a
246 * bus free, so interrupt
247 * the kernel driver if it
248 * happens.
249 */
250 mvi SPIOEN call initialize_channel;
251 mvi MSG_OUT, MSG_NOOP; /* No message to send */
252 jmp ITloop;
253
254/*
255 * After the selection, remove this SCB from the "waiting SCB"
256 * list. This is achieved by simply moving our "next" pointer into
257 * WAITING_SCBH. Our next pointer will be set to null the next time this
258 * SCB is used, so don't bother with it now.
259 */
260select_out:
261 /* Turn off the selection hardware */
262 mvi SCSISEQ, ENRSELI|ENAUTOATNP; /*
263 * ATN on parity errors
264 * for "in" phases
265 */
266 mvi CLRSINT0, CLRSELDO;
267 mov SCBPTR, WAITING_SCBH;
268 mov WAITING_SCBH,SCB_NEXT;
269 mov SAVED_TCL, SCB_TCL;
270 mvi CLRSINT1,CLRBUSFREE;
271 or SIMODE1, ENBUSFREE; /*
272 * We aren't expecting a
273 * bus free, so interrupt
274 * the kernel driver if it
275 * happens.
276 */
277 mvi SPIOEN call initialize_channel;
278/*
279 * As soon as we get a successful selection, the target should go
280 * into the message out phase since we have ATN asserted.
281 */
282 mvi MSG_OUT, MSG_IDENTIFYFLAG;
283 or SEQ_FLAGS, IDENTIFY_SEEN;
284
285/*
286 * Main loop for information transfer phases. Wait for the target
287 * to assert REQ before checking MSG, C/D and I/O for the bus phase.
288 */
289ITloop:
290 call phase_lock;
291
292 mov A, LASTPHASE;
293
294 test A, ~P_DATAIN jz p_data;
295 cmp A,P_COMMAND je p_command;
296 cmp A,P_MESGOUT je p_mesgout;
297 cmp A,P_STATUS je p_status;
298 cmp A,P_MESGIN je p_mesgin;
299
300 mvi INTSTAT,BAD_PHASE; /* unknown phase - signal driver */
301 jmp ITloop; /* Try reading the bus again. */
302
303await_busfree:
304 and SIMODE1, ~ENBUSFREE;
305 call clear_target_state;
306 mov NONE, SCSIDATL; /* Ack the last byte */
307 and SXFRCTL0, ~SPIOEN;
308 test SSTAT1,REQINIT|BUSFREE jz .;
309 test SSTAT1, BUSFREE jnz poll_for_work;
310 mvi INTSTAT, BAD_PHASE;
311
312clear_target_state:
313 /*
314 * We assume that the kernel driver may reset us
315 * at any time, even in the middle of a DMA, so
316 * clear DFCNTRL too.
317 */
318 clr DFCNTRL;
319
320 /*
321 * We don't know the target we will connect to,
322 * so default to narrow transfers to avoid
323 * parity problems.
324 */
325 if ((p->features & AHC_ULTRA2) != 0) {
326 bmov SCSIRATE, ALLZEROS, 2;
327 } else {
328 clr SCSIRATE;
329 and SXFRCTL0, ~(FAST20);
330 }
331 mvi LASTPHASE, P_BUSFREE;
332 /* clear target specific flags */
333 clr SEQ_FLAGS ret;
334
335
336data_phase_reinit:
337/*
338 * If we re-enter the data phase after going through another phase, the
339 * STCNT may have been cleared, so restore it from the residual field.
340 * On Ultra2, we have to put it into the HCNT field because we have to
341 * drop the data down into the shadow layer via the preload ability.
342 */
343 if ((p->features & AHC_ULTRA2) != 0) {
344 bmov HADDR, SHADDR, 4;
345 bmov HCNT, SCB_RESID_DCNT, 3;
346 }
347 if ((p->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
348 bmov STCNT, SCB_RESID_DCNT, 3;
349 }
350 if ((p->features & AHC_CMD_CHAN) == 0) {
351 mvi DINDEX, STCNT;
352 mvi SCB_RESID_DCNT call bcopy_3;
353 }
354 jmp data_phase_loop;
355p_data:
356 if ((p->features & AHC_ULTRA2) != 0) {
357 mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN;
358 } else {
359 mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET;
360 }
361 test LASTPHASE, IOI jnz . + 2;
362 or DMAPARAMS, DIRECTION;
363 call assert; /*
364 * Ensure entering a data
365 * phase is okay - seen identify, etc.
366 */
367 if ((p->features & AHC_CMD_CHAN) != 0) {
368 mvi CCSGADDR, CCSGADDR_MAX;
369 }
370
371 test SEQ_FLAGS, DPHASE jnz data_phase_reinit;
372 or SEQ_FLAGS, DPHASE; /* we've seen a data phase */
373 /*
374 * Initialize the DMA address and counter from the SCB.
375 * Also set SG_COUNT and SG_NEXT in memory since we cannot
376 * modify the values in the SCB itself until we see a
377 * save data pointers message.
378 */
379 if ((p->features & AHC_CMD_CHAN) != 0) {
380 bmov HADDR, SCB_DATAPTR, 7;
381 bmov SG_COUNT, SCB_SGCOUNT, 5;
382 if ((p->features & AHC_ULTRA2) == 0) {
383 bmov STCNT, HCNT, 3;
384 }
385 } else {
386 mvi DINDEX, HADDR;
387 mvi SCB_DATAPTR call bcopy_7;
388 call set_stcnt_from_hcnt;
389 mvi DINDEX, SG_COUNT;
390 mvi SCB_SGCOUNT call bcopy_5;
391 }
392data_phase_loop:
393 /* Guard against overruns */
394 test SG_COUNT, 0xff jnz data_phase_inbounds;
395/*
396 * Turn on 'Bit Bucket' mode, set the transfer count to
397 * 16meg and let the target run until it changes phase.
398 * When the transfer completes, notify the host that we
399 * had an overrun.
400 */
401 or SXFRCTL1,BITBUCKET;
402 and DMAPARAMS, ~(HDMAEN|SDMAEN);
403 if ((p->features & AHC_ULTRA2) != 0) {
404 bmov HCNT, ALLONES, 3;
405 }
406 if ((p->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
407 bmov STCNT, ALLONES, 3;
408 }
409 if ((p->features & AHC_CMD_CHAN) == 0) {
410 mvi STCNT[0], 0xFF;
411 mvi STCNT[1], 0xFF;
412 mvi STCNT[2], 0xFF;
413 }
414
415data_phase_inbounds:
416/* If we are the last SG block, tell the hardware. */
417 if ((p->features & AHC_ULTRA2) != 0) {
418 shl A, 2, SG_COUNT;
419 cmp SG_COUNT,0x01 jne data_phase_wideodd;
420 or A, LAST_SEG;
421 } else {
422 cmp SG_COUNT,0x01 jne data_phase_wideodd;
423 and DMAPARAMS, ~WIDEODD;
424 }
425data_phase_wideodd:
426 if ((p->features & AHC_ULTRA2) != 0) {
427 mov SG_CACHEPTR, A;
428 mov DFCNTRL, DMAPARAMS; /* start the operation */
429 test SXFRCTL1, BITBUCKET jnz data_phase_overrun;
430u2_preload_wait:
431 test SSTAT1, PHASEMIS jnz u2_phasemis;
432 test DFSTATUS, PRELOAD_AVAIL jz u2_preload_wait;
433 } else {
434 mov DMAPARAMS call dma;
435data_phase_dma_done:
436/* Go tell the host about any overruns */
437 test SXFRCTL1,BITBUCKET jnz data_phase_overrun;
438
439/* Exit if we had an underrun. dma clears SINDEX in this case. */
440 test SINDEX,0xff jz data_phase_finish;
441 }
442/*
443 * Advance the scatter-gather pointers
444 */
445sg_advance:
446 if ((p->features & AHC_ULTRA2) != 0) {
447 cmp SG_COUNT, 0x01 je u2_data_phase_finish;
448 } else {
449 dec SG_COUNT;
450 test SG_COUNT, 0xff jz data_phase_finish;
451 }
452
453 if ((p->features & AHC_CMD_CHAN) != 0) {
454
455 /*
456 * Do we have any prefetch left???
457 */
458 cmp CCSGADDR, CCSGADDR_MAX jne prefetch_avail;
459
460 /*
461 * Fetch MIN(CCSGADDR_MAX, (SG_COUNT * 8)) bytes.
462 */
463 add A, -(CCSGRAM_MAXSEGS + 1), SG_COUNT;
464 mvi A, CCSGADDR_MAX;
465 jc . + 2;
466 shl A, 3, SG_COUNT;
467 mov CCHCNT, A;
468 bmov CCHADDR, SG_NEXT, 4;
469 mvi CCSGCTL, CCSGEN|CCSGRESET;
470 test CCSGCTL, CCSGDONE jz .;
471 and CCSGCTL, ~CCSGEN;
472 test CCSGCTL, CCSGEN jnz .;
473 mvi CCSGCTL, CCSGRESET;
474prefetch_avail:
475 bmov HADDR, CCSGRAM, 8;
476 if ((p->features & AHC_ULTRA2) == 0) {
477 bmov STCNT, HCNT, 3;
478 } else {
479 dec SG_COUNT;
480 }
481 } else {
482 mvi DINDEX, HADDR;
483 mvi SG_NEXT call bcopy_4;
484
485 mvi HCNT[0],SG_SIZEOF;
486 clr HCNT[1];
487 clr HCNT[2];
488
489 or DFCNTRL, HDMAEN|DIRECTION|FIFORESET;
490
491 call dma_finish;
492
493/*
494 * Copy data from FIFO into SCB data pointer and data count.
495 * This assumes that the SG segments are of the form:
496 * struct ahc_dma_seg {
497 * u_int32_t addr; four bytes, little-endian order
498 * u_int32_t len; four bytes, little endian order
499 * };
500 */
501 mvi DINDEX, HADDR;
502 call dfdat_in_7;
503 call set_stcnt_from_hcnt;
504 }
505/* Advance the SG pointer */
506 clr A; /* add sizeof(struct scatter) */
507 add SG_NEXT[0],SG_SIZEOF;
508 adc SG_NEXT[1],A;
509
510 if ((p->features & AHC_ULTRA2) != 0) {
511 jmp data_phase_loop;
512 } else {
513 test SSTAT1, REQINIT jz .;
514 test SSTAT1,PHASEMIS jz data_phase_loop;
515 }
516
517
518/*
519 * We've loaded all of our segments into the preload layer. Now, we simply
520 * have to wait for it to finish or for us to get a phasemis. And, since
521 * we'll get a phasemis if we do finish, all we really need to do is wait
522 * for a phasemis then check if we did actually complete all the segments.
523 */
524 if ((p->features & AHC_ULTRA2) != 0) {
525u2_data_phase_finish:
526 test SSTAT1, PHASEMIS jnz u2_phasemis;
527 test SG_CACHEPTR, LAST_SEG_DONE jz u2_data_phase_finish;
528 clr SG_COUNT;
529 test SSTAT1, REQINIT jz .;
530 test SSTAT1, PHASEMIS jz data_phase_loop;
531u2_phasemis:
532 call ultra2_dmafinish;
533 test SG_CACHEPTR, LAST_SEG_DONE jnz data_phase_finish;
534 test SSTAT2, SHVALID jnz u2_fixup_residual;
535 mvi INTSTAT, SEQ_SG_FIXUP;
536 jmp data_phase_finish;
537u2_fixup_residual:
538 shr ARG_1, 2, SG_CACHEPTR;
539u2_phasemis_loop:
540 and A, 0x3f, SG_COUNT;
541 cmp ARG_1, A je data_phase_finish;
542/*
543 * Subtract SG_SIZEOF from the SG_NEXT pointer and add 1 to the SG_COUNT
544 */
545 clr A;
546 add SG_NEXT[0], -SG_SIZEOF;
547 adc SG_NEXT[1], 0xff;
548 inc SG_COUNT;
549 jmp u2_phasemis_loop;
550 }
551
552data_phase_finish:
553/*
554 * After a DMA finishes, save the SG and STCNT residuals back into the SCB
555 * We use STCNT instead of HCNT, since it's a reflection of how many bytes
556 * were transferred on the SCSI (as opposed to the host) bus.
557 */
558 if ((p->features & AHC_CMD_CHAN) != 0) {
559 bmov SCB_RESID_DCNT, STCNT, 3;
560 mov SCB_RESID_SGCNT, SG_COUNT;
561 if ((p->features & AHC_ULTRA2) != 0) {
562 or SXFRCTL0, CLRSTCNT|CLRCHN;
563 }
564 } else {
565 mov SCB_RESID_DCNT[0],STCNT[0];
566 mov SCB_RESID_DCNT[1],STCNT[1];
567 mov SCB_RESID_DCNT[2],STCNT[2];
568 mov SCB_RESID_SGCNT, SG_COUNT;
569 }
570
571 jmp ITloop;
572
573data_phase_overrun:
574/*
575 * Turn off BITBUCKET mode and notify the host
576 */
577 if ((p->features & AHC_ULTRA2) != 0) {
578/*
579 * Wait for the target to quit transferring data on the SCSI bus
580 */
581 test SSTAT1, PHASEMIS jz .;
582 call ultra2_dmafinish;
583 }
584 and SXFRCTL1, ~BITBUCKET;
585 mvi INTSTAT,DATA_OVERRUN;
586 jmp ITloop;
587
588
589
590
591/*
592 * Actually turn off the DMA hardware, save our current position into the
593 * proper residual variables, wait for the next REQ signal, then jump to
594 * the ITloop. Jumping to the ITloop ensures that if we happen to get
595 * brought into the data phase again (or are still in it after our last
596 * segment) that we will properly signal an overrun to the kernel.
597 */
598 if ((p->features & AHC_ULTRA2) != 0) {
599ultra2_dmafinish:
600 test DFCNTRL, DIRECTION jnz ultra2_dmahalt;
601 and DFCNTRL, ~SCSIEN;
602 test DFCNTRL, SCSIEN jnz .;
603 if ((p->bugs & AHC_BUG_AUTOFLUSH) != 0) {
604 or DFCNTRL, FIFOFLUSH;
605 }
606ultra2_dmafifoflush:
607 if ((p->bugs & AHC_BUG_AUTOFLUSH) != 0) {
608 /*
609 * hardware bug alert! This needless set of jumps
610 * works around a glitch in the silicon. When the
611 * PCI DMA fifo goes empty, but there is still SCSI
612 * data to be flushed into the PCI DMA fifo (and from
613 * there on into main memory), the FIFOEMP bit will
614 * come on between the time when the PCI DMA buffer
615 * went empty and the next bit of data is copied from
616 * the SCSI fifo into the PCI fifo. It should only
617 * come on when both FIFOs (meaning the entire FIFO
618 * chain) are emtpy. Since it can take up to 4 cycles
619 * for new data to be copied from the SCSI fifo into
620 * the PCI fifo, testing for FIFOEMP status for 4
621 * extra times gives the needed time for any
622 * remaining SCSI fifo data to be put in the PCI fifo
623 * before we declare it *truly* empty.
624 */
625 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
626 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
627 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
628 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
629 }
630 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
631 test DFSTATUS, MREQPEND jnz .;
632ultra2_dmahalt:
633 and DFCNTRL, ~(HDMAEN|SCSIEN);
634 test DFCNTRL, (HDMAEN|SCSIEN) jnz .;
635 ret;
636 }
637
638/*
639 * Command phase. Set up the DMA registers and let 'er rip.
640 */
641p_command:
642 call assert;
643
644/*
645 * Load HADDR and HCNT.
646 */
647 if ((p->features & AHC_CMD_CHAN) != 0) {
648 bmov HADDR, SCB_CMDPTR, 5;
649 bmov HCNT[1], ALLZEROS, 2;
650 if ((p->features & AHC_ULTRA2) == 0) {
651 bmov STCNT, HCNT, 3;
652 }
653 } else {
654 mvi DINDEX, HADDR;
655 mvi SCB_CMDPTR call bcopy_5;
656 clr HCNT[1];
657 clr HCNT[2];
658 call set_stcnt_from_hcnt;
659 }
660
661 if ((p->features & AHC_ULTRA2) == 0) {
662 mvi (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET) call dma;
663 } else {
664 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION);
665 test SSTAT0, SDONE jnz .;
666p_command_dma_loop:
667 test SSTAT0, SDONE jnz p_command_ultra2_dma_done;
668 test SSTAT1,PHASEMIS jz p_command_dma_loop; /* ie. underrun */
669p_command_ultra2_dma_done:
670 test SCSISIGI, REQI jz p_command_ultra2_shutdown;
671 test SSTAT1, (PHASEMIS|REQINIT) jz p_command_ultra2_dma_done;
672p_command_ultra2_shutdown:
673 and DFCNTRL, ~(HDMAEN|SCSIEN);
674 test DFCNTRL, (HDMAEN|SCSIEN) jnz .;
675 or SXFRCTL0, CLRSTCNT|CLRCHN;
676 }
677 jmp ITloop;
678
679/*
680 * Status phase. Wait for the data byte to appear, then read it
681 * and store it into the SCB.
682 */
683p_status:
684 call assert;
685
686 mov SCB_TARGET_STATUS, SCSIDATL;
687 jmp ITloop;
688
689/*
690 * Message out phase. If MSG_OUT is 0x80, build I full indentify message
691 * sequence and send it to the target. In addition, if the MK_MESSAGE bit
692 * is set in the SCB_CONTROL byte, interrupt the host and allow it to send
693 * it's own message.
694 *
695 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
696 * This is done to allow the hsot to send messages outside of an identify
697 * sequence while protecting the seqencer from testing the MK_MESSAGE bit
698 * on an SCB that might not be for the current nexus. (For example, a
699 * BDR message in responce to a bad reselection would leave us pointed to
700 * an SCB that doesn't have anything to do with the current target).
701 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
702 * bus device reset).
703 *
704 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
705 * in case the target decides to put us in this phase for some strange
706 * reason.
707 */
708p_mesgout_retry:
709 or SCSISIGO,ATNO,LASTPHASE;/* turn on ATN for the retry */
710p_mesgout:
711 mov SINDEX, MSG_OUT;
712 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
713p_mesgout_identify:
714 if ((p->features & AHC_WIDE) != 0) {
715 and SINDEX,0xf,SCB_TCL; /* lun */
716 } else {
717 and SINDEX,0x7,SCB_TCL; /* lun */
718 }
719 and A,DISCENB,SCB_CONTROL; /* mask off disconnect privledge */
720 or SINDEX,A; /* or in disconnect privledge */
721 or SINDEX,MSG_IDENTIFYFLAG;
722p_mesgout_mk_message:
723 test SCB_CONTROL,MK_MESSAGE jz p_mesgout_tag;
724 mov SCSIDATL, SINDEX; /* Send the last byte */
725 jmp p_mesgout_from_host + 1;/* Skip HOST_MSG test */
726/*
727 * Send a tag message if TAG_ENB is set in the SCB control block.
728 * Use SCB_TAG (the position in the kernel's SCB array) as the tag value.
729 */
730p_mesgout_tag:
731 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
732 mov SCSIDATL, SINDEX; /* Send the identify message */
733 call phase_lock;
734 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
735 and SCSIDATL,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
736 call phase_lock;
737 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
738 mov SCB_TAG jmp p_mesgout_onebyte;
739/*
740 * Interrupt the driver, and allow it to send a message
741 * if it asks.
742 */
743p_mesgout_from_host:
744 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
745 mvi INTSTAT,AWAITING_MSG;
746 nop;
747 /*
748 * Did the host detect a phase change?
749 */
750 cmp RETURN_1, MSGOUT_PHASEMIS je p_mesgout_done;
751
752p_mesgout_onebyte:
753 mvi CLRSINT1, CLRATNO;
754 mov SCSIDATL, SINDEX;
755
756/*
757 * If the next bus phase after ATN drops is a message out, it means
758 * that the target is requesting that the last message(s) be resent.
759 */
760 call phase_lock;
761 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
762
763p_mesgout_done:
764 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
765 mov LAST_MSG, MSG_OUT;
766 cmp MSG_OUT, MSG_IDENTIFYFLAG jne . + 2;
767 and SCB_CONTROL, ~MK_MESSAGE;
768 mvi MSG_OUT, MSG_NOOP; /* No message left */
769 jmp ITloop;
770
771/*
772 * Message in phase. Bytes are read using Automatic PIO mode.
773 */
774p_mesgin:
775 mvi ACCUM call inb_first; /* read the 1st message byte */
776
777 test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
778 cmp A,MSG_DISCONNECT je mesgin_disconnect;
779 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
780 cmp ALLZEROS,A je mesgin_complete;
781 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
782 cmp A,MSG_EXTENDED je mesgin_extended;
783 cmp A,MSG_MESSAGE_REJECT je mesgin_reject;
784 cmp A,MSG_NOOP je mesgin_done;
785 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_wide_residue;
786
787rej_mesgin:
788/*
789 * We have no idea what this message in is, so we issue a message reject
790 * and hope for the best. In any case, rejection should be a rare
791 * occurrence - signal the driver when it happens.
792 */
793 mvi INTSTAT,SEND_REJECT; /* let driver know */
794
795 mvi MSG_MESSAGE_REJECT call mk_mesg;
796
797mesgin_done:
798 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
799 jmp ITloop;
800
801
802mesgin_complete:
803/*
804 * We got a "command complete" message, so put the SCB_TAG into the QOUTFIFO,
805 * and trigger a completion interrupt. Before doing so, check to see if there
806 * is a residual or the status byte is something other than STATUS_GOOD (0).
807 * In either of these conditions, we upload the SCB back to the host so it can
808 * process this information. In the case of a non zero status byte, we
809 * additionally interrupt the kernel driver synchronously, allowing it to
810 * decide if sense should be retrieved. If the kernel driver wishes to request
811 * sense, it will fill the kernel SCB with a request sense command and set
812 * RETURN_1 to SEND_SENSE. If RETURN_1 is set to SEND_SENSE we redownload
813 * the SCB, and process it as the next command by adding it to the waiting list.
814 * If the kernel driver does not wish to request sense, it need only clear
815 * RETURN_1, and the command is allowed to complete normally. We don't bother
816 * to post to the QOUTFIFO in the error cases since it would require extra
817 * work in the kernel driver to ensure that the entry was removed before the
818 * command complete code tried processing it.
819 */
820
821/*
822 * First check for residuals
823 */
824 test SCB_RESID_SGCNT,0xff jnz upload_scb;
825 test SCB_TARGET_STATUS,0xff jz complete; /* Good Status? */
826upload_scb:
827 mvi DMAPARAMS, FIFORESET;
828 mov SCB_TAG call dma_scb;
829check_status:
830 test SCB_TARGET_STATUS,0xff jz complete; /* Just a residual? */
831 mvi INTSTAT,BAD_STATUS; /* let driver know */
832 nop;
833 cmp RETURN_1, SEND_SENSE jne complete;
834 /* This SCB becomes the next to execute as it will retrieve sense */
835 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
836 mov SCB_TAG call dma_scb;
837add_to_waiting_list:
838 mov SCB_NEXT,WAITING_SCBH;
839 mov WAITING_SCBH, SCBPTR;
840 /*
841 * Prepare our selection hardware before the busfree so we have a
842 * high probability of winning arbitration.
843 */
844 call start_selection;
845 jmp await_busfree;
846
847complete:
848 /* If we are untagged, clear our address up in host ram */
849 test SCB_CONTROL, TAG_ENB jnz complete_post;
850 mov A, SAVED_TCL;
851 mvi UNTAGGEDSCB_OFFSET call post_byte_setup;
852 mvi SCB_LIST_NULL call post_byte;
853
854complete_post:
855 /* Post the SCB and issue an interrupt */
856 if ((p->features & AHC_QUEUE_REGS) != 0) {
857 mov A, SDSCB_QOFF;
858 } else {
859 mov A, QOUTPOS;
860 }
861 mvi QOUTFIFO_OFFSET call post_byte_setup;
862 mov SCB_TAG call post_byte;
863 if ((p->features & AHC_QUEUE_REGS) == 0) {
864 inc QOUTPOS;
865 }
866 mvi INTSTAT,CMDCMPLT;
867
868add_to_free_list:
869 call add_scb_to_free_list;
870 jmp await_busfree;
871
872/*
873 * Is it an extended message? Copy the message to our message buffer and
874 * notify the host. The host will tell us whether to reject this message,
875 * respond to it with the message that the host placed in our message buffer,
876 * or simply to do nothing.
877 */
878mesgin_extended:
879 mvi INTSTAT,EXTENDED_MSG; /* let driver know */
880 jmp ITloop;
881
882/*
883 * Is it a disconnect message? Set a flag in the SCB to remind us
884 * and await the bus going free.
885 */
886mesgin_disconnect:
887 or SCB_CONTROL,DISCONNECTED;
888 call add_scb_to_disc_list;
889 jmp await_busfree;
890
891/*
892 * Save data pointers message:
893 * Copying RAM values back to SCB, for Save Data Pointers message, but
894 * only if we've actually been into a data phase to change them. This
895 * protects against bogus data in scratch ram and the residual counts
896 * since they are only initialized when we go into data_in or data_out.
897 */
898mesgin_sdptrs:
899 test SEQ_FLAGS, DPHASE jz mesgin_done;
900 /*
901 * The SCB SGPTR becomes the next one we'll download,
902 * and the SCB DATAPTR becomes the current SHADDR.
903 * Use the residual number since STCNT is corrupted by
904 * any message transfer.
905 */
906 if ((p->features & AHC_CMD_CHAN) != 0) {
907 bmov SCB_SGCOUNT, SG_COUNT, 5;
908 bmov SCB_DATAPTR, SHADDR, 4;
909 bmov SCB_DATACNT, SCB_RESID_DCNT, 3;
910 } else {
911 mvi DINDEX, SCB_SGCOUNT;
912 mvi SG_COUNT call bcopy_5;
913 mvi DINDEX, SCB_DATAPTR;
914 mvi SHADDR call bcopy_4;
915 mvi SCB_RESID_DCNT call bcopy_3;
916 }
917 jmp mesgin_done;
918
919/*
920 * Restore pointers message? Data pointers are recopied from the
921 * SCB anytime we enter a data phase for the first time, so all
922 * we need to do is clear the DPHASE flag and let the data phase
923 * code do the rest.
924 */
925mesgin_rdptrs:
926 and SEQ_FLAGS, ~DPHASE; /*
927 * We'll reload them
928 * the next time through
929 * the dataphase.
930 */
931 jmp mesgin_done;
932
933/*
934 * Identify message? For a reconnecting target, this tells us the lun
935 * that the reconnection is for - find the correct SCB and switch to it,
936 * clearing the "disconnected" bit so we don't "find" it by accident later.
937 */
938mesgin_identify:
939
940 if ((p->features & AHC_WIDE) != 0) {
941 and A,0x0f; /* lun in lower four bits */
942 } else {
943 and A,0x07; /* lun in lower three bits */
944 }
945 or SAVED_TCL,A; /* SAVED_TCL should be complete now */
946
947 mvi ARG_2, SCB_LIST_NULL; /* SCBID of prev SCB in disc List */
948 call get_untagged_SCBID;
949 cmp ARG_1, SCB_LIST_NULL je snoop_tag;
950 if ((p->flags & AHC_PAGESCBS) != 0) {
951 test SEQ_FLAGS, SCBPTR_VALID jz use_retrieveSCB;
952 }
953 /*
954 * If the SCB was found in the disconnected list (as is
955 * always the case in non-paging scenarios), SCBPTR is already
956 * set to the correct SCB. So, simply setup the SCB and get
957 * on with things.
958 */
959 mov SCBPTR call rem_scb_from_disc_list;
960 jmp setup_SCB;
961/*
962 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
963 * If we get one, we use the tag returned to find the proper
964 * SCB. With SCB paging, this requires using search for both tagged
965 * and non-tagged transactions since the SCB may exist in any slot.
966 * If we're not using SCB paging, we can use the tag as the direct
967 * index to the SCB.
968 */
969snoop_tag:
970 mov NONE,SCSIDATL; /* ACK Identify MSG */
971snoop_tag_loop:
972 call phase_lock;
973 cmp LASTPHASE, P_MESGIN jne not_found;
974 cmp SCSIBUSL,MSG_SIMPLE_Q_TAG jne not_found;
975get_tag:
976 mvi ARG_1 call inb_next; /* tag value */
977
978use_retrieveSCB:
979 call retrieveSCB;
980setup_SCB:
981 mov A, SAVED_TCL;
982 cmp SCB_TCL, A jne not_found_cleanup_scb;
983 test SCB_CONTROL,DISCONNECTED jz not_found_cleanup_scb;
984 and SCB_CONTROL,~DISCONNECTED;
985 or SEQ_FLAGS,IDENTIFY_SEEN; /* make note of IDENTIFY */
986 /* See if the host wants to send a message upon reconnection */
987 test SCB_CONTROL, MK_MESSAGE jz mesgin_done;
988 and SCB_CONTROL, ~MK_MESSAGE;
989 mvi HOST_MSG call mk_mesg;
990 jmp mesgin_done;
991
992not_found_cleanup_scb:
993 test SCB_CONTROL, DISCONNECTED jz . + 3;
994 call add_scb_to_disc_list;
995 jmp not_found;
996 call add_scb_to_free_list;
997not_found:
998 mvi INTSTAT, NO_MATCH;
999 mvi MSG_BUS_DEV_RESET call mk_mesg;
1000 jmp mesgin_done;
1001
1002/*
1003 * Message reject? Let the kernel driver handle this. If we have an
1004 * outstanding WDTR or SDTR negotiation, assume that it's a response from
1005 * the target selecting 8bit or asynchronous transfer, otherwise just ignore
1006 * it since we have no clue what it pertains to.
1007 */
1008mesgin_reject:
1009 mvi INTSTAT, REJECT_MSG;
1010 jmp mesgin_done;
1011
1012/*
1013 * Wide Residue. We handle the simple cases, but pass of the one hard case
1014 * to the kernel (when the residue byte happened to cause us to advance our
1015 * sg element array, so we know have to back that advance out).
1016 */
1017mesgin_wide_residue:
1018 mvi ARG_1 call inb_next; /* ACK the wide_residue and get */
1019 /* the size byte */
1020/*
1021 * In order for this to be reliable, we have to do all sorts of horrible
1022 * magic in terms of resetting the datafifo and reloading the shadow layer
1023 * with the correct new values (so that a subsequent save data pointers
1024 * message will do the right thing). We let the kernel do that work.
1025 */
1026 mvi INTSTAT, WIDE_RESIDUE;
1027 jmp mesgin_done;
1028
1029/*
1030 * [ ADD MORE MESSAGE HANDLING HERE ]
1031 */
1032
1033/*
1034 * Locking the driver out, build a one-byte message passed in SINDEX
1035 * if there is no active message already. SINDEX is returned intact.
1036 */
1037mk_mesg:
1038 or SCSISIGO,ATNO,LASTPHASE;/* turn on ATNO */
1039 mov MSG_OUT,SINDEX ret;
1040
1041/*
1042 * Functions to read data in Automatic PIO mode.
1043 *
1044 * According to Adaptec's documentation, an ACK is not sent on input from
1045 * the target until SCSIDATL is read from. So we wait until SCSIDATL is
1046 * latched (the usual way), then read the data byte directly off the bus
1047 * using SCSIBUSL. When we have pulled the ATN line, or we just want to
1048 * acknowledge the byte, then we do a dummy read from SCISDATL. The SCSI
1049 * spec guarantees that the target will hold the data byte on the bus until
1050 * we send our ACK.
1051 *
1052 * The assumption here is that these are called in a particular sequence,
1053 * and that REQ is already set when inb_first is called. inb_{first,next}
1054 * use the same calling convention as inb.
1055 */
1056
1057inb_next:
1058 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1059inb_next_wait:
1060 /*
1061 * If there is a parity error, wait for the kernel to
1062 * see the interrupt and prepare our message response
1063 * before continuing.
1064 */
1065 test SSTAT1, REQINIT jz inb_next_wait;
1066 test SSTAT1, SCSIPERR jnz .;
1067 and LASTPHASE, PHASE_MASK, SCSISIGI;
1068 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis;
1069inb_first:
1070 mov DINDEX,SINDEX;
1071 mov DINDIR,SCSIBUSL ret; /*read byte directly from bus*/
1072inb_last:
1073 mov NONE,SCSIDATL ret; /*dummy read from latch to ACK*/
1074
1075
1076mesgin_phasemis:
1077/*
1078 * We expected to receive another byte, but the target changed phase
1079 */
1080 mvi INTSTAT, MSGIN_PHASEMIS;
1081 jmp ITloop;
1082
1083/*
1084 * DMA data transfer. HADDR and HCNT must be loaded first, and
1085 * SINDEX should contain the value to load DFCNTRL with - 0x3d for
1086 * host->scsi, or 0x39 for scsi->host. The SCSI channel is cleared
1087 * during initialization.
1088 */
1089if ((p->features & AHC_ULTRA2) == 0) {
1090dma:
1091 mov DFCNTRL,SINDEX;
1092dma_loop:
1093 test SSTAT0,DMADONE jnz dma_dmadone;
1094 test SSTAT1,PHASEMIS jz dma_loop; /* ie. underrun */
1095dma_phasemis:
1096 test SSTAT0,SDONE jnz dma_checkfifo;
1097 mov SINDEX,ALLZEROS; /* Notify caller of phasemiss */
1098
1099/*
1100 * We will be "done" DMAing when the transfer count goes to zero, or
1101 * the target changes the phase (in light of this, it makes sense that
1102 * the DMA circuitry doesn't ACK when PHASEMIS is active). If we are
1103 * doing a SCSI->Host transfer, the data FIFO should be flushed auto-
1104 * magically on STCNT=0 or a phase change, so just wait for FIFO empty
1105 * status.
1106 */
1107dma_checkfifo:
1108 test DFCNTRL,DIRECTION jnz dma_fifoempty;
1109dma_fifoflush:
1110 test DFSTATUS,FIFOEMP jz dma_fifoflush;
1111
1112dma_fifoempty:
1113 /* Don't clobber an inprogress host data transfer */
1114 test DFSTATUS, MREQPEND jnz dma_fifoempty;
1115/*
1116 * Now shut the DMA enables off and make sure that the DMA enables are
1117 * actually off first lest we get an ILLSADDR.
1118 */
1119dma_dmadone:
1120 cmp LASTPHASE, P_COMMAND je dma_await_nreq;
1121 test SCSIRATE, 0x0f jnz dma_shutdown;
1122dma_await_nreq:
1123 test SCSISIGI, REQI jz dma_shutdown;
1124 test SSTAT1, (PHASEMIS|REQINIT) jz dma_await_nreq;
1125dma_shutdown:
1126 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
1127dma_halt:
1128 /*
1129 * Some revisions of the aic7880 have a problem where, if the
1130 * data fifo is full, but the PCI input latch is not empty,
1131 * HDMAEN cannot be cleared. The fix used here is to attempt
1132 * to drain the data fifo until there is space for the input
1133 * latch to drain and HDMAEN de-asserts.
1134 */
1135 if ((p->bugs & AHC_BUG_PCI_2_1_RETRY) != 0) {
1136 mov NONE, DFDAT;
1137 }
1138 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt;
1139}
1140return:
1141 ret;
1142
1143/*
1144 * Assert that if we've been reselected, then we've seen an IDENTIFY
1145 * message.
1146 */
1147assert:
1148 test SEQ_FLAGS,IDENTIFY_SEEN jnz return; /* seen IDENTIFY? */
1149
1150 mvi INTSTAT,NO_IDENT ret; /* no - tell the kernel */
1151
1152/*
1153 * Locate a disconnected SCB either by SAVED_TCL (ARG_1 is SCB_LIST_NULL)
1154 * or by the SCBID ARG_1. The search begins at the SCB index passed in
1155 * via SINDEX which is an SCB that must be on the disconnected list. If
1156 * the SCB cannot be found, SINDEX will be SCB_LIST_NULL, otherwise, SCBPTR
1157 * is set to the proper SCB.
1158 */
1159findSCB:
1160 mov SCBPTR,SINDEX; /* Initialize SCBPTR */
1161 cmp ARG_1, SCB_LIST_NULL jne findSCB_by_SCBID;
1162 mov A, SAVED_TCL;
1163 mvi SCB_TCL jmp findSCB_loop; /* &SCB_TCL -> SINDEX */
1164findSCB_by_SCBID:
1165 mov A, ARG_1; /* Tag passed in ARG_1 */
1166 mvi SCB_TAG jmp findSCB_loop; /* &SCB_TAG -> SINDEX */
1167findSCB_next:
1168 mov ARG_2, SCBPTR;
1169 cmp SCB_NEXT, SCB_LIST_NULL je notFound;
1170 mov SCBPTR,SCB_NEXT;
1171 dec SINDEX; /* Last comparison moved us too far */
1172findSCB_loop:
1173 cmp SINDIR, A jne findSCB_next;
1174 mov SINDEX, SCBPTR ret;
1175notFound:
1176 mvi SINDEX, SCB_LIST_NULL ret;
1177
1178/*
1179 * Retrieve an SCB by SCBID first searching the disconnected list falling
1180 * back to DMA'ing the SCB down from the host. This routine assumes that
1181 * ARG_1 is the SCBID of interrest and that SINDEX is the position in the
1182 * disconnected list to start the search from. If SINDEX is SCB_LIST_NULL,
1183 * we go directly to the host for the SCB.
1184 */
1185retrieveSCB:
1186 test SEQ_FLAGS, SCBPTR_VALID jz retrieve_from_host;
1187 mov SCBPTR call findSCB; /* Continue the search */
1188 cmp SINDEX, SCB_LIST_NULL je retrieve_from_host;
1189
1190/*
1191 * This routine expects SINDEX to contain the index of the SCB to be
1192 * removed, SCBPTR to be pointing to that SCB, and ARG_2 to be the
1193 * SCBID of the SCB just previous to this one in the list or SCB_LIST_NULL
1194 * if it is at the head.
1195 */
1196rem_scb_from_disc_list:
1197/* Remove this SCB from the disconnection list */
1198 cmp ARG_2, SCB_LIST_NULL je rHead;
1199 mov DINDEX, SCB_NEXT;
1200 mov SCBPTR, ARG_2;
1201 mov SCB_NEXT, DINDEX;
1202 mov SCBPTR, SINDEX ret;
1203rHead:
1204 mov DISCONNECTED_SCBH,SCB_NEXT ret;
1205
1206retrieve_from_host:
1207/*
1208 * We didn't find it. Pull an SCB and DMA down the one we want.
1209 * We should never get here in the non-paging case.
1210 */
1211 mov ALLZEROS call get_free_or_disc_scb;
1212 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
1213 /* Jump instead of call as we want to return anyway */
1214 mov ARG_1 jmp dma_scb;
1215
1216/*
1217 * Determine whether a target is using tagged or non-tagged transactions
1218 * by first looking for a matching transaction based on the TCL and if
1219 * that fails, looking up this device in the host's untagged SCB array.
1220 * The TCL to search for is assumed to be in SAVED_TCL. The value is
1221 * returned in ARG_1 (SCB_LIST_NULL for tagged, SCBID for non-tagged).
1222 * The SCBPTR_VALID bit is set in SEQ_FLAGS if we found the information
1223 * in an SCB instead of having to go to the host.
1224 */
1225get_untagged_SCBID:
1226 cmp DISCONNECTED_SCBH, SCB_LIST_NULL je get_SCBID_from_host;
1227 mvi ARG_1, SCB_LIST_NULL;
1228 mov DISCONNECTED_SCBH call findSCB;
1229 cmp SINDEX, SCB_LIST_NULL je get_SCBID_from_host;
1230 or SEQ_FLAGS, SCBPTR_VALID;/* Was in disconnected list */
1231 test SCB_CONTROL, TAG_ENB jnz . + 2;
1232 mov ARG_1, SCB_TAG ret;
1233 mvi ARG_1, SCB_LIST_NULL ret;
1234
1235/*
1236 * Fetch a byte from host memory given an index of (A + (256 * SINDEX))
1237 * and a base address of SCBID_ADDR. The byte is returned in RETURN_2.
1238 */
1239fetch_byte:
1240 mov ARG_2, SINDEX;
1241 if ((p->features & AHC_CMD_CHAN) != 0) {
1242 mvi DINDEX, CCHADDR;
1243 mvi SCBID_ADDR call set_1byte_addr;
1244 mvi CCHCNT, 1;
1245 mvi CCSGCTL, CCSGEN|CCSGRESET;
1246 test CCSGCTL, CCSGDONE jz .;
1247 mvi CCSGCTL, CCSGRESET;
1248 bmov RETURN_2, CCSGRAM, 1 ret;
1249 } else {
1250 mvi DINDEX, HADDR;
1251 mvi SCBID_ADDR call set_1byte_addr;
1252 mvi HCNT[0], 1;
1253 clr HCNT[1];
1254 clr HCNT[2];
1255 mvi DFCNTRL, HDMAEN|DIRECTION|FIFORESET;
1256 call dma_finish;
1257 mov RETURN_2, DFDAT ret;
1258 }
1259
1260/*
1261 * Prepare the hardware to post a byte to host memory given an
1262 * index of (A + (256 * SINDEX)) and a base address of SCBID_ADDR.
1263 */
1264post_byte_setup:
1265 mov ARG_2, SINDEX;
1266 if ((p->features & AHC_CMD_CHAN) != 0) {
1267 mvi DINDEX, CCHADDR;
1268 mvi SCBID_ADDR call set_1byte_addr;
1269 mvi CCHCNT, 1;
1270 mvi CCSCBCTL, CCSCBRESET ret;
1271 } else {
1272 mvi DINDEX, HADDR;
1273 mvi SCBID_ADDR call set_1byte_addr;
1274 mvi HCNT[0], 1;
1275 clr HCNT[1];
1276 clr HCNT[2];
1277 mvi DFCNTRL, FIFORESET ret;
1278 }
1279
1280post_byte:
1281 if ((p->features & AHC_CMD_CHAN) != 0) {
1282 bmov CCSCBRAM, SINDEX, 1;
1283 or CCSCBCTL, CCSCBEN|CCSCBRESET;
1284 test CCSCBCTL, CCSCBDONE jz .;
1285 clr CCSCBCTL ret;
1286 } else {
1287 mov DFDAT, SINDEX;
1288 or DFCNTRL, HDMAEN|FIFOFLUSH;
1289 jmp dma_finish;
1290 }
1291
1292get_SCBID_from_host:
1293 mov A, SAVED_TCL;
1294 mvi UNTAGGEDSCB_OFFSET call fetch_byte;
1295 mov RETURN_1, RETURN_2 ret;
1296
1297phase_lock:
1298 test SSTAT1, REQINIT jz phase_lock;
1299 test SSTAT1, SCSIPERR jnz phase_lock;
1300 and SCSISIGO, PHASE_MASK, SCSISIGI;
1301 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
1302
1303if ((p->features & AHC_CMD_CHAN) == 0) {
1304set_stcnt_from_hcnt:
1305 mov STCNT[0], HCNT[0];
1306 mov STCNT[1], HCNT[1];
1307 mov STCNT[2], HCNT[2] ret;
1308
1309bcopy_7:
1310 mov DINDIR, SINDIR;
1311 mov DINDIR, SINDIR;
1312bcopy_5:
1313 mov DINDIR, SINDIR;
1314bcopy_4:
1315 mov DINDIR, SINDIR;
1316bcopy_3:
1317 mov DINDIR, SINDIR;
1318 mov DINDIR, SINDIR;
1319 mov DINDIR, SINDIR ret;
1320}
1321
1322/*
1323 * Setup addr assuming that A is an index into
1324 * an array of 32byte objects, SINDEX contains
1325 * the base address of that array, and DINDEX
1326 * contains the base address of the location
1327 * to store the indexed address.
1328 */
1329set_32byte_addr:
1330 shr ARG_2, 3, A;
1331 shl A, 5;
1332/*
1333 * Setup addr assuming that A + (ARG_1 * 256) is an
1334 * index into an array of 1byte objects, SINDEX contains
1335 * the base address of that array, and DINDEX contains
1336 * the base address of the location to store the computed
1337 * address.
1338 */
1339set_1byte_addr:
1340 add DINDIR, A, SINDIR;
1341 mov A, ARG_2;
1342 adc DINDIR, A, SINDIR;
1343 clr A;
1344 adc DINDIR, A, SINDIR;
1345 adc DINDIR, A, SINDIR ret;
1346
1347/*
1348 * Either post or fetch and SCB from host memory based on the
1349 * DIRECTION bit in DMAPARAMS. The host SCB index is in SINDEX.
1350 */
1351dma_scb:
1352 mov A, SINDEX;
1353 if ((p->features & AHC_CMD_CHAN) != 0) {
1354 mvi DINDEX, CCHADDR;
1355 mvi HSCB_ADDR call set_32byte_addr;
1356 mov CCSCBPTR, SCBPTR;
1357 mvi CCHCNT, 32;
1358 test DMAPARAMS, DIRECTION jz dma_scb_tohost;
1359 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET;
1360 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN|CCSCBDIR jne .;
1361 jmp dma_scb_finish;
1362dma_scb_tohost:
1363 if ((p->features & AHC_ULTRA2) == 0) {
1364 mvi CCSCBCTL, CCSCBRESET;
1365 bmov CCSCBRAM, SCB_CONTROL, 32;
1366 or CCSCBCTL, CCSCBEN|CCSCBRESET;
1367 test CCSCBCTL, CCSCBDONE jz .;
1368 }
1369 if ((p->features & AHC_ULTRA2) != 0) {
1370 if ((p->bugs & AHC_BUG_SCBCHAN_UPLOAD) != 0) {
1371 mvi CCSCBCTL, CCARREN|CCSCBRESET;
1372 cmp CCSCBCTL, ARRDONE|CCARREN jne .;
1373 mvi CCHCNT, 32;
1374 mvi CCSCBCTL, CCSCBEN|CCSCBRESET;
1375 cmp CCSCBCTL, CCSCBDONE|CCSCBEN jne .;
1376 } else {
1377 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET;
1378 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .;
1379 }
1380 }
1381dma_scb_finish:
1382 clr CCSCBCTL;
1383 test CCSCBCTL, CCARREN|CCSCBEN jnz .;
1384 ret;
1385 }
1386 if ((p->features & AHC_CMD_CHAN) == 0) {
1387 mvi DINDEX, HADDR;
1388 mvi HSCB_ADDR call set_32byte_addr;
1389 mvi HCNT[0], 32;
1390 clr HCNT[1];
1391 clr HCNT[2];
1392 mov DFCNTRL, DMAPARAMS;
1393 test DMAPARAMS, DIRECTION jnz dma_scb_fromhost;
1394 /* Fill it with the SCB data */
1395copy_scb_tofifo:
1396 mvi SINDEX, SCB_CONTROL;
1397 add A, 32, SINDEX;
1398copy_scb_tofifo_loop:
1399 mov DFDAT,SINDIR;
1400 mov DFDAT,SINDIR;
1401 mov DFDAT,SINDIR;
1402 mov DFDAT,SINDIR;
1403 mov DFDAT,SINDIR;
1404 mov DFDAT,SINDIR;
1405 mov DFDAT,SINDIR;
1406 mov DFDAT,SINDIR;
1407 cmp SINDEX, A jne copy_scb_tofifo_loop;
1408 or DFCNTRL, HDMAEN|FIFOFLUSH;
1409 jmp dma_finish;
1410dma_scb_fromhost:
1411 mvi DINDEX, SCB_CONTROL;
1412 if ((p->bugs & AHC_BUG_PCI_2_1_RETRY) != 0) {
1413 /*
1414 * Set the A to -24. It it hits 0, then we let
1415 * our code fall through to dfdat_in_8 to complete
1416 * the last of the copy.
1417 *
1418 * Also, things happen 8 bytes at a time in this
1419 * case, so we may need to drain the fifo at most
1420 * 3 times to keep things flowing
1421 */
1422 mvi A, -24;
1423dma_scb_hang_fifo:
1424 /* Wait for the first bit of data to hit the fifo */
1425 test DFSTATUS, FIFOEMP jnz .;
1426dma_scb_hang_wait:
1427 /* OK, now they've started to transfer into the fifo,
1428 * so wait for them to stop trying to transfer any
1429 * more data.
1430 */
1431 test DFSTATUS, MREQPEND jnz .;
1432 /*
1433 * OK, they started, then they stopped, now see if they
1434 * managed to complete the job before stopping. Try
1435 * it multiple times to give the chip a few cycles to
1436 * set the flag if it did complete.
1437 */
1438 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
1439 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
1440 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
1441 /*
1442 * Too bad, the chip didn't complete the DMA, but there
1443 * aren't any more memory requests pending, so that
1444 * means it stopped part way through and hung. That's
1445 * our bug, so now we drain what data there is in the
1446 * fifo in order to get things going again.
1447 */
1448dma_scb_hang_empty_fifo:
1449 call dfdat_in_8;
1450 add A, 8;
1451 add SINDEX, A, HCNT;
1452 /*
1453 * If there are another 8 bytes of data waiting in the
1454 * fifo, then the carry bit will be set as a result
1455 * of the above add command (unless A is non-negative,
1456 * in which case the carry bit won't be set).
1457 */
1458 jc dma_scb_hang_empty_fifo;
1459 /*
1460 * We've emptied the fifo now, but we wouldn't have got
1461 * here if the memory transfer hadn't stopped part way
1462 * through, so go back up to the beginning of the
1463 * loop and start over. When it succeeds in getting
1464 * all the data down, HDONE will be set and we'll
1465 * jump to the code just below here.
1466 */
1467 jmp dma_scb_hang_fifo;
1468dma_scb_hang_dma_done:
1469 and DFCNTRL, ~HDMAEN;
1470 test DFCNTRL, HDMAEN jnz .;
1471 call dfdat_in_8;
1472 add A, 8;
1473 cmp A, 8 jne . - 2;
1474 ret;
1475 } else {
1476 call dma_finish;
1477 call dfdat_in_8;
1478 call dfdat_in_8;
1479 call dfdat_in_8;
1480 }
1481dfdat_in_8:
1482 mov DINDIR,DFDAT;
1483dfdat_in_7:
1484 mov DINDIR,DFDAT;
1485 mov DINDIR,DFDAT;
1486 mov DINDIR,DFDAT;
1487 mov DINDIR,DFDAT;
1488 mov DINDIR,DFDAT;
1489 mov DINDIR,DFDAT;
1490 mov DINDIR,DFDAT ret;
1491 }
1492
1493
1494/*
1495 * Wait for DMA from host memory to data FIFO to complete, then disable
1496 * DMA and wait for it to acknowledge that it's off.
1497 */
1498if ((p->features & AHC_CMD_CHAN) == 0) {
1499dma_finish:
1500 test DFSTATUS,HDONE jz dma_finish;
1501 /* Turn off DMA */
1502 and DFCNTRL, ~HDMAEN;
1503 test DFCNTRL, HDMAEN jnz .;
1504 ret;
1505}
1506
1507add_scb_to_free_list:
1508 if ((p->flags & AHC_PAGESCBS) != 0) {
1509 mov SCB_NEXT, FREE_SCBH;
1510 mov FREE_SCBH, SCBPTR;
1511 }
1512 mvi SCB_TAG, SCB_LIST_NULL ret;
1513
1514if ((p->flags & AHC_PAGESCBS) != 0) {
1515get_free_or_disc_scb:
1516 cmp FREE_SCBH, SCB_LIST_NULL jne dequeue_free_scb;
1517 cmp DISCONNECTED_SCBH, SCB_LIST_NULL jne dequeue_disc_scb;
1518return_error:
1519 mvi SINDEX, SCB_LIST_NULL ret;
1520dequeue_disc_scb:
1521 mov SCBPTR, DISCONNECTED_SCBH;
1522dma_up_scb:
1523 mvi DMAPARAMS, FIFORESET;
1524 mov SCB_TAG call dma_scb;
1525unlink_disc_scb:
1526 mov DISCONNECTED_SCBH, SCB_NEXT ret;
1527dequeue_free_scb:
1528 mov SCBPTR, FREE_SCBH;
1529 mov FREE_SCBH, SCB_NEXT ret;
1530}
1531
1532add_scb_to_disc_list:
1533/*
1534 * Link this SCB into the DISCONNECTED list. This list holds the
1535 * candidates for paging out an SCB if one is needed for a new command.
1536 * Modifying the disconnected list is a critical(pause dissabled) section.
1537 */
1538 mov SCB_NEXT, DISCONNECTED_SCBH;
1539 mov DISCONNECTED_SCBH, SCBPTR ret;
diff --git a/drivers/scsi/aic7xxx_old/aic7xxx_proc.c b/drivers/scsi/aic7xxx_old/aic7xxx_proc.c
new file mode 100644
index 000000000000..3bf334931a8a
--- /dev/null
+++ b/drivers/scsi/aic7xxx_old/aic7xxx_proc.c
@@ -0,0 +1,374 @@
1/*+M*************************************************************************
2 * Adaptec AIC7xxx device driver proc support for Linux.
3 *
4 * Copyright (c) 1995, 1996 Dean W. Gehnert
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; see the file COPYING. If not, write to
18 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 * ----------------------------------------------------------------
21 * o Modified from the EATA-DMA /proc support.
22 * o Additional support for device block statistics provided by
23 * Matthew Jacob.
24 * o Correction of overflow by Heinz Mauelshagen
25 * o Adittional corrections by Doug Ledford
26 *
27 * Dean W. Gehnert, deang@teleport.com, 05/01/96
28 *
29 * $Id: aic7xxx_proc.c,v 4.1 1997/06/97 08:23:42 deang Exp $
30 *-M*************************************************************************/
31
32#include <linux/config.h>
33
34#define BLS (&aic7xxx_buffer[size])
35#define HDRB \
36" 0 - 4K 4 - 16K 16 - 64K 64 - 256K 256K - 1M 1M+"
37
38#ifdef PROC_DEBUG
39extern int vsprintf(char *, const char *, va_list);
40
41static void
42proc_debug(const char *fmt, ...)
43{
44 va_list ap;
45 char buf[256];
46
47 va_start(ap, fmt);
48 vsprintf(buf, fmt, ap);
49 printk(buf);
50 va_end(ap);
51}
52#else /* PROC_DEBUG */
53# define proc_debug(fmt, args...)
54#endif /* PROC_DEBUG */
55
56static int aic7xxx_buffer_size = 0;
57static char *aic7xxx_buffer = NULL;
58
59
60/*+F*************************************************************************
61 * Function:
62 * aic7xxx_set_info
63 *
64 * Description:
65 * Set parameters for the driver from the /proc filesystem.
66 *-F*************************************************************************/
67static int
68aic7xxx_set_info(char *buffer, int length, struct Scsi_Host *HBAptr)
69{
70 proc_debug("aic7xxx_set_info(): %s\n", buffer);
71 return (-ENOSYS); /* Currently this is a no-op */
72}
73
74
75/*+F*************************************************************************
76 * Function:
77 * aic7xxx_proc_info
78 *
79 * Description:
80 * Return information to handle /proc support for the driver.
81 *-F*************************************************************************/
82int
83aic7xxx_proc_info ( struct Scsi_Host *HBAptr, char *buffer, char **start, off_t offset, int length,
84 int inout)
85{
86 struct aic7xxx_host *p;
87 struct aic_dev_data *aic_dev;
88 struct scsi_device *sdptr;
89 int size = 0;
90 unsigned char i;
91 unsigned char tindex;
92
93 for(p=first_aic7xxx; p && p->host != HBAptr; p=p->next)
94 ;
95
96 if (!p)
97 {
98 size += sprintf(buffer, "Can't find adapter for host number %d\n", HBAptr->host_no);
99 if (size > length)
100 {
101 return (size);
102 }
103 else
104 {
105 return (length);
106 }
107 }
108
109 if (inout == TRUE) /* Has data been written to the file? */
110 {
111 return (aic7xxx_set_info(buffer, length, HBAptr));
112 }
113
114 p = (struct aic7xxx_host *) HBAptr->hostdata;
115
116 /*
117 * It takes roughly 1K of space to hold all relevant card info, not
118 * counting any proc stats, so we start out with a 1.5k buffer size and
119 * if proc_stats is defined, then we sweep the stats structure to see
120 * how many drives we will be printing out for and add 384 bytes per
121 * device with active stats.
122 *
123 * Hmmmm...that 1.5k seems to keep growing as items get added so they
124 * can be easily viewed for debugging purposes. So, we bumped that
125 * 1.5k to 4k so we can quit having to bump it all the time.
126 */
127
128 size = 4096;
129 list_for_each_entry(aic_dev, &p->aic_devs, list)
130 size += 512;
131 if (aic7xxx_buffer_size != size)
132 {
133 if (aic7xxx_buffer != NULL)
134 {
135 kfree(aic7xxx_buffer);
136 aic7xxx_buffer_size = 0;
137 }
138 aic7xxx_buffer = kmalloc(size, GFP_KERNEL);
139 }
140 if (aic7xxx_buffer == NULL)
141 {
142 size = sprintf(buffer, "AIC7xxx - kmalloc error at line %d\n",
143 __LINE__);
144 return size;
145 }
146 aic7xxx_buffer_size = size;
147
148 size = 0;
149 size += sprintf(BLS, "Adaptec AIC7xxx driver version: ");
150 size += sprintf(BLS, "%s/", AIC7XXX_C_VERSION);
151 size += sprintf(BLS, "%s", AIC7XXX_H_VERSION);
152 size += sprintf(BLS, "\n");
153 size += sprintf(BLS, "Adapter Configuration:\n");
154 size += sprintf(BLS, " SCSI Adapter: %s\n",
155 board_names[p->board_name_index]);
156 if (p->flags & AHC_TWIN)
157 size += sprintf(BLS, " Twin Channel Controller ");
158 else
159 {
160 char *channel = "";
161 char *ultra = "";
162 char *wide = "Narrow ";
163 if (p->flags & AHC_MULTI_CHANNEL)
164 {
165 channel = " Channel A";
166 if (p->flags & (AHC_CHNLB|AHC_CHNLC))
167 channel = (p->flags & AHC_CHNLB) ? " Channel B" : " Channel C";
168 }
169 if (p->features & AHC_WIDE)
170 wide = "Wide ";
171 if (p->features & AHC_ULTRA3)
172 {
173 switch(p->chip & AHC_CHIPID_MASK)
174 {
175 case AHC_AIC7892:
176 case AHC_AIC7899:
177 ultra = "Ultra-160/m LVD/SE ";
178 break;
179 default:
180 ultra = "Ultra-3 LVD/SE ";
181 break;
182 }
183 }
184 else if (p->features & AHC_ULTRA2)
185 ultra = "Ultra-2 LVD/SE ";
186 else if (p->features & AHC_ULTRA)
187 ultra = "Ultra ";
188 size += sprintf(BLS, " %s%sController%s ",
189 ultra, wide, channel);
190 }
191 switch(p->chip & ~AHC_CHIPID_MASK)
192 {
193 case AHC_VL:
194 size += sprintf(BLS, "at VLB slot %d\n", p->pci_device_fn);
195 break;
196 case AHC_EISA:
197 size += sprintf(BLS, "at EISA slot %d\n", p->pci_device_fn);
198 break;
199 default:
200 size += sprintf(BLS, "at PCI %d/%d/%d\n", p->pci_bus,
201 PCI_SLOT(p->pci_device_fn), PCI_FUNC(p->pci_device_fn));
202 break;
203 }
204 if( !(p->maddr) )
205 {
206 size += sprintf(BLS, " Programmed I/O Base: %lx\n", p->base);
207 }
208 else
209 {
210 size += sprintf(BLS, " PCI MMAPed I/O Base: 0x%lx\n", p->mbase);
211 }
212 if( (p->chip & (AHC_VL | AHC_EISA)) )
213 {
214 size += sprintf(BLS, " BIOS Memory Address: 0x%08x\n", p->bios_address);
215 }
216 size += sprintf(BLS, " Adapter SEEPROM Config: %s\n",
217 (p->flags & AHC_SEEPROM_FOUND) ? "SEEPROM found and used." :
218 ((p->flags & AHC_USEDEFAULTS) ? "SEEPROM not found, using defaults." :
219 "SEEPROM not found, using leftover BIOS values.") );
220 size += sprintf(BLS, " Adaptec SCSI BIOS: %s\n",
221 (p->flags & AHC_BIOS_ENABLED) ? "Enabled" : "Disabled");
222 size += sprintf(BLS, " IRQ: %d\n", HBAptr->irq);
223 size += sprintf(BLS, " SCBs: Active %d, Max Active %d,\n",
224 p->activescbs, p->max_activescbs);
225 size += sprintf(BLS, " Allocated %d, HW %d, "
226 "Page %d\n", p->scb_data->numscbs, p->scb_data->maxhscbs,
227 p->scb_data->maxscbs);
228 if (p->flags & AHC_EXTERNAL_SRAM)
229 size += sprintf(BLS, " Using External SCB SRAM\n");
230 size += sprintf(BLS, " Interrupts: %ld", p->isr_count);
231 if (p->chip & AHC_EISA)
232 {
233 size += sprintf(BLS, " %s\n",
234 (p->pause & IRQMS) ? "(Level Sensitive)" : "(Edge Triggered)");
235 }
236 else
237 {
238 size += sprintf(BLS, "\n");
239 }
240 size += sprintf(BLS, " BIOS Control Word: 0x%04x\n",
241 p->bios_control);
242 size += sprintf(BLS, " Adapter Control Word: 0x%04x\n",
243 p->adapter_control);
244 size += sprintf(BLS, " Extended Translation: %sabled\n",
245 (p->flags & AHC_EXTEND_TRANS_A) ? "En" : "Dis");
246 size += sprintf(BLS, "Disconnect Enable Flags: 0x%04x\n", p->discenable);
247 if (p->features & (AHC_ULTRA | AHC_ULTRA2))
248 {
249 size += sprintf(BLS, " Ultra Enable Flags: 0x%04x\n", p->ultraenb);
250 }
251 size += sprintf(BLS, "Default Tag Queue Depth: %d\n", aic7xxx_default_queue_depth);
252 size += sprintf(BLS, " Tagged Queue By Device array for aic7xxx host "
253 "instance %d:\n", p->instance);
254 size += sprintf(BLS, " {");
255 for(i=0; i < (MAX_TARGETS - 1); i++)
256 size += sprintf(BLS, "%d,",aic7xxx_tag_info[p->instance].tag_commands[i]);
257 size += sprintf(BLS, "%d}\n",aic7xxx_tag_info[p->instance].tag_commands[i]);
258
259 size += sprintf(BLS, "\n");
260 size += sprintf(BLS, "Statistics:\n\n");
261 list_for_each_entry(aic_dev, &p->aic_devs, list)
262 {
263 sdptr = aic_dev->SDptr;
264 tindex = sdptr->channel << 3 | sdptr->id;
265 size += sprintf(BLS, "(scsi%d:%d:%d:%d)\n",
266 p->host_no, sdptr->channel, sdptr->id, sdptr->lun);
267 size += sprintf(BLS, " Device using %s/%s",
268 (aic_dev->cur.width == MSG_EXT_WDTR_BUS_16_BIT) ?
269 "Wide" : "Narrow",
270 (aic_dev->cur.offset != 0) ?
271 "Sync transfers at " : "Async transfers.\n" );
272 if (aic_dev->cur.offset != 0)
273 {
274 struct aic7xxx_syncrate *sync_rate;
275 unsigned char options = aic_dev->cur.options;
276 int period = aic_dev->cur.period;
277 int rate = (aic_dev->cur.width ==
278 MSG_EXT_WDTR_BUS_16_BIT) ? 1 : 0;
279
280 sync_rate = aic7xxx_find_syncrate(p, &period, 0, &options);
281 if (sync_rate != NULL)
282 {
283 size += sprintf(BLS, "%s MByte/sec, offset %d\n",
284 sync_rate->rate[rate],
285 aic_dev->cur.offset );
286 }
287 else
288 {
289 size += sprintf(BLS, "3.3 MByte/sec, offset %d\n",
290 aic_dev->cur.offset );
291 }
292 }
293 size += sprintf(BLS, " Transinfo settings: ");
294 size += sprintf(BLS, "current(%d/%d/%d/%d), ",
295 aic_dev->cur.period,
296 aic_dev->cur.offset,
297 aic_dev->cur.width,
298 aic_dev->cur.options);
299 size += sprintf(BLS, "goal(%d/%d/%d/%d), ",
300 aic_dev->goal.period,
301 aic_dev->goal.offset,
302 aic_dev->goal.width,
303 aic_dev->goal.options);
304 size += sprintf(BLS, "user(%d/%d/%d/%d)\n",
305 p->user[tindex].period,
306 p->user[tindex].offset,
307 p->user[tindex].width,
308 p->user[tindex].options);
309 if(sdptr->simple_tags)
310 {
311 size += sprintf(BLS, " Tagged Command Queueing Enabled, Ordered Tags %s, Depth %d/%d\n", sdptr->ordered_tags ? "Enabled" : "Disabled", sdptr->queue_depth, aic_dev->max_q_depth);
312 }
313 if(aic_dev->barrier_total)
314 size += sprintf(BLS, " Total transfers %ld:\n (%ld/%ld/%ld/%ld reads/writes/REQ_BARRIER/Ordered Tags)\n",
315 aic_dev->r_total+aic_dev->w_total, aic_dev->r_total, aic_dev->w_total,
316 aic_dev->barrier_total, aic_dev->ordered_total);
317 else
318 size += sprintf(BLS, " Total transfers %ld:\n (%ld/%ld reads/writes)\n",
319 aic_dev->r_total+aic_dev->w_total, aic_dev->r_total, aic_dev->w_total);
320 size += sprintf(BLS, "%s\n", HDRB);
321 size += sprintf(BLS, " Reads:");
322 for (i = 0; i < ARRAY_SIZE(aic_dev->r_bins); i++)
323 {
324 size += sprintf(BLS, " %10ld", aic_dev->r_bins[i]);
325 }
326 size += sprintf(BLS, "\n");
327 size += sprintf(BLS, " Writes:");
328 for (i = 0; i < ARRAY_SIZE(aic_dev->w_bins); i++)
329 {
330 size += sprintf(BLS, " %10ld", aic_dev->w_bins[i]);
331 }
332 size += sprintf(BLS, "\n");
333 size += sprintf(BLS, "\n\n");
334 }
335 if (size >= aic7xxx_buffer_size)
336 {
337 printk(KERN_WARNING "aic7xxx: Overflow in aic7xxx_proc.c\n");
338 }
339
340 if (offset > size - 1)
341 {
342 kfree(aic7xxx_buffer);
343 aic7xxx_buffer = NULL;
344 aic7xxx_buffer_size = length = 0;
345 *start = NULL;
346 }
347 else
348 {
349 *start = buffer;
350 length = min_t(int, length, size - offset);
351 memcpy(buffer, &aic7xxx_buffer[offset], length);
352 }
353
354 return (length);
355}
356
357/*
358 * Overrides for Emacs so that we follow Linus's tabbing style.
359 * Emacs will notice this stuff at the end of the file and automatically
360 * adjust the settings for this buffer only. This must remain at the end
361 * of the file.
362 * ---------------------------------------------------------------------------
363 * Local variables:
364 * c-indent-level: 2
365 * c-brace-imaginary-offset: 0
366 * c-brace-offset: -2
367 * c-argdecl-indent: 2
368 * c-label-offset: -2
369 * c-continued-statement-offset: 2
370 * c-continued-brace-offset: 0
371 * indent-tabs-mode: nil
372 * tab-width: 8
373 * End:
374 */
diff --git a/drivers/scsi/aic7xxx_old/aic7xxx_reg.h b/drivers/scsi/aic7xxx_old/aic7xxx_reg.h
new file mode 100644
index 000000000000..27f2334abc71
--- /dev/null
+++ b/drivers/scsi/aic7xxx_old/aic7xxx_reg.h
@@ -0,0 +1,629 @@
1/*
2 * DO NOT EDIT - This file is automatically generated.
3 */
4
5#define SCSISEQ 0x00
6#define TEMODE 0x80
7#define ENSELO 0x40
8#define ENSELI 0x20
9#define ENRSELI 0x10
10#define ENAUTOATNO 0x08
11#define ENAUTOATNI 0x04
12#define ENAUTOATNP 0x02
13#define SCSIRSTO 0x01
14
15#define SXFRCTL0 0x01
16#define DFON 0x80
17#define DFPEXP 0x40
18#define FAST20 0x20
19#define CLRSTCNT 0x10
20#define SPIOEN 0x08
21#define SCAMEN 0x04
22#define CLRCHN 0x02
23
24#define SXFRCTL1 0x02
25#define BITBUCKET 0x80
26#define SWRAPEN 0x40
27#define ENSPCHK 0x20
28#define STIMESEL 0x18
29#define ENSTIMER 0x04
30#define ACTNEGEN 0x02
31#define STPWEN 0x01
32
33#define SCSISIGO 0x03
34#define CDO 0x80
35#define IOO 0x40
36#define MSGO 0x20
37#define ATNO 0x10
38#define SELO 0x08
39#define BSYO 0x04
40#define REQO 0x02
41#define ACKO 0x01
42
43#define SCSISIGI 0x03
44#define ATNI 0x10
45#define SELI 0x08
46#define BSYI 0x04
47#define REQI 0x02
48#define ACKI 0x01
49
50#define SCSIRATE 0x04
51#define WIDEXFER 0x80
52#define SXFR_ULTRA2 0x7f
53#define SXFR 0x70
54#define SOFS 0x0f
55
56#define SCSIID 0x05
57#define SCSIOFFSET 0x05
58#define SOFS_ULTRA2 0x7f
59
60#define SCSIDATL 0x06
61
62#define SCSIDATH 0x07
63
64#define STCNT 0x08
65
66#define OPTIONMODE 0x08
67#define AUTORATEEN 0x80
68#define AUTOACKEN 0x40
69#define ATNMGMNTEN 0x20
70#define BUSFREEREV 0x10
71#define EXPPHASEDIS 0x08
72#define SCSIDATL_IMGEN 0x04
73#define AUTO_MSGOUT_DE 0x02
74#define DIS_MSGIN_DUALEDGE 0x01
75
76#define CLRSINT0 0x0b
77#define CLRSELDO 0x40
78#define CLRSELDI 0x20
79#define CLRSELINGO 0x10
80#define CLRSWRAP 0x08
81#define CLRSPIORDY 0x02
82
83#define SSTAT0 0x0b
84#define TARGET 0x80
85#define SELDO 0x40
86#define SELDI 0x20
87#define SELINGO 0x10
88#define IOERR 0x08
89#define SWRAP 0x08
90#define SDONE 0x04
91#define SPIORDY 0x02
92#define DMADONE 0x01
93
94#define CLRSINT1 0x0c
95#define CLRSELTIMEO 0x80
96#define CLRATNO 0x40
97#define CLRSCSIRSTI 0x20
98#define CLRBUSFREE 0x08
99#define CLRSCSIPERR 0x04
100#define CLRPHASECHG 0x02
101#define CLRREQINIT 0x01
102
103#define SSTAT1 0x0c
104#define SELTO 0x80
105#define ATNTARG 0x40
106#define SCSIRSTI 0x20
107#define PHASEMIS 0x10
108#define BUSFREE 0x08
109#define SCSIPERR 0x04
110#define PHASECHG 0x02
111#define REQINIT 0x01
112
113#define SSTAT2 0x0d
114#define OVERRUN 0x80
115#define SHVALID 0x40
116#define WIDE_RES 0x20
117#define SFCNT 0x1f
118#define EXP_ACTIVE 0x10
119#define CRCVALERR 0x08
120#define CRCENDERR 0x04
121#define CRCREQERR 0x02
122#define DUAL_EDGE_ERROR 0x01
123
124#define SSTAT3 0x0e
125#define SCSICNT 0xf0
126#define OFFCNT 0x0f
127
128#define SCSIID_ULTRA2 0x0f
129#define OID 0x0f
130
131#define SIMODE0 0x10
132#define ENSELDO 0x40
133#define ENSELDI 0x20
134#define ENSELINGO 0x10
135#define ENIOERR 0x08
136#define ENSWRAP 0x08
137#define ENSDONE 0x04
138#define ENSPIORDY 0x02
139#define ENDMADONE 0x01
140
141#define SIMODE1 0x11
142#define ENSELTIMO 0x80
143#define ENATNTARG 0x40
144#define ENSCSIRST 0x20
145#define ENPHASEMIS 0x10
146#define ENBUSFREE 0x08
147#define ENSCSIPERR 0x04
148#define ENPHASECHG 0x02
149#define ENREQINIT 0x01
150
151#define SCSIBUSL 0x12
152
153#define SCSIBUSH 0x13
154
155#define SHADDR 0x14
156
157#define SELTIMER 0x18
158#define STAGE6 0x20
159#define STAGE5 0x10
160#define STAGE4 0x08
161#define STAGE3 0x04
162#define STAGE2 0x02
163#define STAGE1 0x01
164
165#define SELID 0x19
166#define SELID_MASK 0xf0
167#define ONEBIT 0x08
168
169#define SPIOCAP 0x1b
170#define SOFT1 0x80
171#define SOFT0 0x40
172#define SOFTCMDEN 0x20
173#define HAS_BRDCTL 0x10
174#define SEEPROM 0x08
175#define EEPROM 0x04
176#define ROM 0x02
177#define SSPIOCPS 0x01
178
179#define BRDCTL 0x1d
180#define BRDDAT7 0x80
181#define BRDDAT6 0x40
182#define BRDDAT5 0x20
183#define BRDDAT4 0x10
184#define BRDSTB 0x10
185#define BRDCS 0x08
186#define BRDDAT3 0x08
187#define BRDDAT2 0x04
188#define BRDRW 0x04
189#define BRDRW_ULTRA2 0x02
190#define BRDCTL1 0x02
191#define BRDSTB_ULTRA2 0x01
192#define BRDCTL0 0x01
193
194#define SEECTL 0x1e
195#define EXTARBACK 0x80
196#define EXTARBREQ 0x40
197#define SEEMS 0x20
198#define SEERDY 0x10
199#define SEECS 0x08
200#define SEECK 0x04
201#define SEEDO 0x02
202#define SEEDI 0x01
203
204#define SBLKCTL 0x1f
205#define DIAGLEDEN 0x80
206#define DIAGLEDON 0x40
207#define AUTOFLUSHDIS 0x20
208#define ENAB40 0x08
209#define ENAB20 0x04
210#define SELWIDE 0x02
211#define XCVR 0x01
212
213#define SRAM_BASE 0x20
214
215#define TARG_SCSIRATE 0x20
216
217#define ULTRA_ENB 0x30
218
219#define DISC_DSB 0x32
220
221#define MSG_OUT 0x34
222
223#define DMAPARAMS 0x35
224#define PRELOADEN 0x80
225#define WIDEODD 0x40
226#define SCSIEN 0x20
227#define SDMAENACK 0x10
228#define SDMAEN 0x10
229#define HDMAEN 0x08
230#define HDMAENACK 0x08
231#define DIRECTION 0x04
232#define FIFOFLUSH 0x02
233#define FIFORESET 0x01
234
235#define SEQ_FLAGS 0x36
236#define IDENTIFY_SEEN 0x80
237#define SCBPTR_VALID 0x20
238#define DPHASE 0x10
239#define AMTARGET 0x08
240#define WIDE_BUS 0x02
241#define TWIN_BUS 0x01
242
243#define SAVED_TCL 0x37
244
245#define SG_COUNT 0x38
246
247#define SG_NEXT 0x39
248
249#define LASTPHASE 0x3d
250#define P_MESGIN 0xe0
251#define PHASE_MASK 0xe0
252#define P_STATUS 0xc0
253#define P_MESGOUT 0xa0
254#define P_COMMAND 0x80
255#define CDI 0x80
256#define IOI 0x40
257#define P_DATAIN 0x40
258#define MSGI 0x20
259#define P_BUSFREE 0x01
260#define P_DATAOUT 0x00
261
262#define WAITING_SCBH 0x3e
263
264#define DISCONNECTED_SCBH 0x3f
265
266#define FREE_SCBH 0x40
267
268#define HSCB_ADDR 0x41
269
270#define SCBID_ADDR 0x45
271
272#define TMODE_CMDADDR 0x49
273
274#define KERNEL_QINPOS 0x4d
275
276#define QINPOS 0x4e
277
278#define QOUTPOS 0x4f
279
280#define TMODE_CMDADDR_NEXT 0x50
281
282#define ARG_1 0x51
283#define RETURN_1 0x51
284#define SEND_MSG 0x80
285#define SEND_SENSE 0x40
286#define SEND_REJ 0x20
287#define MSGOUT_PHASEMIS 0x10
288
289#define ARG_2 0x52
290#define RETURN_2 0x52
291
292#define LAST_MSG 0x53
293
294#define PREFETCH_CNT 0x54
295
296#define SCSICONF 0x5a
297#define TERM_ENB 0x80
298#define RESET_SCSI 0x40
299#define HWSCSIID 0x0f
300#define HSCSIID 0x07
301
302#define HOSTCONF 0x5d
303
304#define HA_274_BIOSCTRL 0x5f
305#define BIOSMODE 0x30
306#define BIOSDISABLED 0x30
307#define CHANNEL_B_PRIMARY 0x08
308
309#define SEQCTL 0x60
310#define PERRORDIS 0x80
311#define PAUSEDIS 0x40
312#define FAILDIS 0x20
313#define FASTMODE 0x10
314#define BRKADRINTEN 0x08
315#define STEP 0x04
316#define SEQRESET 0x02
317#define LOADRAM 0x01
318
319#define SEQRAM 0x61
320
321#define SEQADDR0 0x62
322
323#define SEQADDR1 0x63
324#define SEQADDR1_MASK 0x01
325
326#define ACCUM 0x64
327
328#define SINDEX 0x65
329
330#define DINDEX 0x66
331
332#define ALLONES 0x69
333
334#define ALLZEROS 0x6a
335
336#define NONE 0x6a
337
338#define FLAGS 0x6b
339#define ZERO 0x02
340#define CARRY 0x01
341
342#define SINDIR 0x6c
343
344#define DINDIR 0x6d
345
346#define FUNCTION1 0x6e
347
348#define STACK 0x6f
349
350#define TARG_OFFSET 0x70
351
352#define BCTL 0x84
353#define ACE 0x08
354#define ENABLE 0x01
355
356#define DSCOMMAND0 0x84
357#define INTSCBRAMSEL 0x08
358#define RAMPS 0x04
359#define USCBSIZE32 0x02
360#define CIOPARCKEN 0x01
361
362#define DSCOMMAND 0x84
363#define CACHETHEN 0x80
364#define DPARCKEN 0x40
365#define MPARCKEN 0x20
366#define EXTREQLCK 0x10
367
368#define BUSTIME 0x85
369#define BOFF 0xf0
370#define BON 0x0f
371
372#define BUSSPD 0x86
373#define DFTHRSH 0xc0
374#define STBOFF 0x38
375#define STBON 0x07
376
377#define DSPCISTATUS 0x86
378#define DFTHRSH_100 0xc0
379
380#define HCNTRL 0x87
381#define POWRDN 0x40
382#define SWINT 0x10
383#define IRQMS 0x08
384#define PAUSE 0x04
385#define INTEN 0x02
386#define CHIPRST 0x01
387#define CHIPRSTACK 0x01
388
389#define HADDR 0x88
390
391#define HCNT 0x8c
392
393#define SCBPTR 0x90
394
395#define INTSTAT 0x91
396#define SEQINT_MASK 0xf1
397#define DATA_OVERRUN 0xe1
398#define MSGIN_PHASEMIS 0xd1
399#define TRACEPOINT2 0xc1
400#define SEQ_SG_FIXUP 0xb1
401#define AWAITING_MSG 0xa1
402#define RESIDUAL 0x81
403#define BAD_STATUS 0x71
404#define REJECT_MSG 0x61
405#define WIDE_RESIDUE 0x51
406#define EXTENDED_MSG 0x41
407#define NO_MATCH 0x31
408#define NO_IDENT 0x21
409#define SEND_REJECT 0x11
410#define INT_PEND 0x0f
411#define BRKADRINT 0x08
412#define SCSIINT 0x04
413#define CMDCMPLT 0x02
414#define BAD_PHASE 0x01
415#define SEQINT 0x01
416
417#define CLRINT 0x92
418#define CLRPARERR 0x10
419#define CLRBRKADRINT 0x08
420#define CLRSCSIINT 0x04
421#define CLRCMDINT 0x02
422#define CLRSEQINT 0x01
423
424#define ERROR 0x92
425#define CIOPARERR 0x80
426#define PCIERRSTAT 0x40
427#define MPARERR 0x20
428#define DPARERR 0x10
429#define SQPARERR 0x08
430#define ILLOPCODE 0x04
431#define DSCTMOUT 0x02
432#define ILLSADDR 0x02
433#define ILLHADDR 0x01
434
435#define DFCNTRL 0x93
436
437#define DFSTATUS 0x94
438#define PRELOAD_AVAIL 0x80
439#define DWORDEMP 0x20
440#define MREQPEND 0x10
441#define HDONE 0x08
442#define DFTHRESH 0x04
443#define FIFOFULL 0x02
444#define FIFOEMP 0x01
445
446#define DFDAT 0x99
447
448#define SCBCNT 0x9a
449#define SCBAUTO 0x80
450#define SCBCNT_MASK 0x1f
451
452#define QINFIFO 0x9b
453
454#define QINCNT 0x9c
455
456#define SCSIDATL_IMG 0x9c
457
458#define QOUTFIFO 0x9d
459
460#define CRCCONTROL1 0x9d
461#define CRCONSEEN 0x80
462#define CRCVALCHKEN 0x40
463#define CRCENDCHKEN 0x20
464#define CRCREQCHKEN 0x10
465#define TARGCRCENDEN 0x08
466#define TARGCRCCNTEN 0x04
467
468#define SCSIPHASE 0x9e
469#define SP_STATUS 0x20
470#define SP_COMMAND 0x10
471#define SP_MSG_IN 0x08
472#define SP_MSG_OUT 0x04
473#define SP_DATA_IN 0x02
474#define SP_DATA_OUT 0x01
475
476#define QOUTCNT 0x9e
477
478#define SFUNCT 0x9f
479#define ALT_MODE 0x80
480
481#define SCB_CONTROL 0xa0
482#define MK_MESSAGE 0x80
483#define DISCENB 0x40
484#define TAG_ENB 0x20
485#define DISCONNECTED 0x04
486#define SCB_TAG_TYPE 0x03
487
488#define SCB_BASE 0xa0
489
490#define SCB_TCL 0xa1
491#define TID 0xf0
492#define SELBUSB 0x08
493#define LID 0x07
494
495#define SCB_TARGET_STATUS 0xa2
496
497#define SCB_SGCOUNT 0xa3
498
499#define SCB_SGPTR 0xa4
500
501#define SCB_RESID_SGCNT 0xa8
502
503#define SCB_RESID_DCNT 0xa9
504
505#define SCB_DATAPTR 0xac
506
507#define SCB_DATACNT 0xb0
508
509#define SCB_CMDPTR 0xb4
510
511#define SCB_CMDLEN 0xb8
512
513#define SCB_TAG 0xb9
514
515#define SCB_NEXT 0xba
516
517#define SCB_PREV 0xbb
518
519#define SCB_BUSYTARGETS 0xbc
520
521#define SEECTL_2840 0xc0
522#define CS_2840 0x04
523#define CK_2840 0x02
524#define DO_2840 0x01
525
526#define STATUS_2840 0xc1
527#define EEPROM_TF 0x80
528#define BIOS_SEL 0x60
529#define ADSEL 0x1e
530#define DI_2840 0x01
531
532#define CCHADDR 0xe0
533
534#define CCHCNT 0xe8
535
536#define CCSGRAM 0xe9
537
538#define CCSGADDR 0xea
539
540#define CCSGCTL 0xeb
541#define CCSGDONE 0x80
542#define CCSGEN 0x08
543#define FLAG 0x02
544#define CCSGRESET 0x01
545
546#define CCSCBRAM 0xec
547
548#define CCSCBADDR 0xed
549
550#define CCSCBCTL 0xee
551#define CCSCBDONE 0x80
552#define ARRDONE 0x40
553#define CCARREN 0x10
554#define CCSCBEN 0x08
555#define CCSCBDIR 0x04
556#define CCSCBRESET 0x01
557
558#define CCSCBCNT 0xef
559
560#define CCSCBPTR 0xf1
561
562#define HNSCB_QOFF 0xf4
563
564#define HESCB_QOFF 0xf5
565
566#define SNSCB_QOFF 0xf6
567
568#define SESCB_QOFF 0xf7
569
570#define SDSCB_QOFF 0xf8
571
572#define QOFF_CTLSTA 0xfa
573#define ESTABLISH_SCB_AVAIL 0x80
574#define SCB_AVAIL 0x40
575#define SNSCB_ROLLOVER 0x20
576#define SDSCB_ROLLOVER 0x10
577#define SESCB_ROLLOVER 0x08
578#define SCB_QSIZE 0x07
579#define SCB_QSIZE_256 0x06
580
581#define DFF_THRSH 0xfb
582#define WR_DFTHRSH 0x70
583#define WR_DFTHRSH_MAX 0x70
584#define WR_DFTHRSH_90 0x60
585#define WR_DFTHRSH_85 0x50
586#define WR_DFTHRSH_75 0x40
587#define WR_DFTHRSH_63 0x30
588#define WR_DFTHRSH_50 0x20
589#define WR_DFTHRSH_25 0x10
590#define RD_DFTHRSH_MAX 0x07
591#define RD_DFTHRSH 0x07
592#define RD_DFTHRSH_90 0x06
593#define RD_DFTHRSH_85 0x05
594#define RD_DFTHRSH_75 0x04
595#define RD_DFTHRSH_63 0x03
596#define RD_DFTHRSH_50 0x02
597#define RD_DFTHRSH_25 0x01
598#define WR_DFTHRSH_MIN 0x00
599#define RD_DFTHRSH_MIN 0x00
600
601#define SG_CACHEPTR 0xfc
602#define SG_USER_DATA 0xfc
603#define LAST_SEG 0x02
604#define LAST_SEG_DONE 0x01
605
606
607#define CMD_GROUP2_BYTE_DELTA 0xfa
608#define MAX_OFFSET_8BIT 0x0f
609#define BUS_16_BIT 0x01
610#define QINFIFO_OFFSET 0x02
611#define CMD_GROUP5_BYTE_DELTA 0x0b
612#define CMD_GROUP_CODE_SHIFT 0x05
613#define MAX_OFFSET_ULTRA2 0x7f
614#define MAX_OFFSET_16BIT 0x08
615#define BUS_8_BIT 0x00
616#define QOUTFIFO_OFFSET 0x01
617#define UNTAGGEDSCB_OFFSET 0x00
618#define CCSGRAM_MAXSEGS 0x10
619#define SCB_LIST_NULL 0xff
620#define SG_SIZEOF 0x08
621#define CMD_GROUP4_BYTE_DELTA 0x04
622#define CMD_GROUP0_BYTE_DELTA 0xfc
623#define HOST_MSG 0xff
624#define BUS_32_BIT 0x02
625#define CCSGADDR_MAX 0x80
626
627
628/* Downloaded Constant Definitions */
629#define TMODE_NUMCMDS 0x00
diff --git a/drivers/scsi/aic7xxx_old/aic7xxx_seq.c b/drivers/scsi/aic7xxx_old/aic7xxx_seq.c
new file mode 100644
index 000000000000..e1bc140e9735
--- /dev/null
+++ b/drivers/scsi/aic7xxx_old/aic7xxx_seq.c
@@ -0,0 +1,817 @@
1/*
2 * DO NOT EDIT - This file is automatically generated.
3 */
4static unsigned char seqprog[] = {
5 0xff, 0x6a, 0x06, 0x08,
6 0x7f, 0x02, 0x04, 0x08,
7 0x12, 0x6a, 0x00, 0x00,
8 0xff, 0x6a, 0xd6, 0x09,
9 0xff, 0x6a, 0xdc, 0x09,
10 0x00, 0x65, 0xca, 0x58,
11 0xf7, 0x01, 0x02, 0x08,
12 0xff, 0x4e, 0xc8, 0x08,
13 0xbf, 0x60, 0xc0, 0x08,
14 0x60, 0x0b, 0x86, 0x68,
15 0x40, 0x00, 0x0c, 0x68,
16 0x08, 0x1f, 0x3e, 0x10,
17 0x60, 0x0b, 0x86, 0x68,
18 0x40, 0x00, 0x0c, 0x68,
19 0x08, 0x1f, 0x3e, 0x10,
20 0xff, 0x3e, 0x48, 0x60,
21 0x40, 0xfa, 0x10, 0x78,
22 0xff, 0xf6, 0xd4, 0x08,
23 0x01, 0x4e, 0x9c, 0x18,
24 0x40, 0x60, 0xc0, 0x00,
25 0x00, 0x4d, 0x10, 0x70,
26 0x01, 0x4e, 0x9c, 0x18,
27 0xbf, 0x60, 0xc0, 0x08,
28 0x00, 0x6a, 0x86, 0x5c,
29 0xff, 0x4e, 0xc8, 0x18,
30 0x02, 0x6a, 0x70, 0x5b,
31 0xff, 0x52, 0x20, 0x09,
32 0x0d, 0x6a, 0x6a, 0x00,
33 0x00, 0x52, 0xe6, 0x5b,
34 0x03, 0xb0, 0x52, 0x31,
35 0xff, 0xb0, 0x52, 0x09,
36 0xff, 0xb1, 0x54, 0x09,
37 0xff, 0xb2, 0x56, 0x09,
38 0xff, 0xa3, 0x50, 0x09,
39 0xff, 0x3e, 0x74, 0x09,
40 0xff, 0x90, 0x7c, 0x08,
41 0xff, 0x3e, 0x20, 0x09,
42 0x00, 0x65, 0x4e, 0x58,
43 0x00, 0x65, 0x0c, 0x40,
44 0xf7, 0x1f, 0xca, 0x08,
45 0x08, 0xa1, 0xc8, 0x08,
46 0x00, 0x65, 0xca, 0x00,
47 0xff, 0x65, 0x3e, 0x08,
48 0xf0, 0xa1, 0xc8, 0x08,
49 0x0f, 0x0f, 0x1e, 0x08,
50 0x00, 0x0f, 0x1e, 0x00,
51 0xf0, 0xa1, 0xc8, 0x08,
52 0x0f, 0x05, 0x0a, 0x08,
53 0x00, 0x05, 0x0a, 0x00,
54 0xff, 0x6a, 0x0c, 0x08,
55 0x5a, 0x6a, 0x00, 0x04,
56 0x12, 0x65, 0x02, 0x00,
57 0x31, 0x6a, 0xca, 0x00,
58 0x80, 0x37, 0x6e, 0x68,
59 0xff, 0x65, 0xca, 0x18,
60 0xff, 0x37, 0xdc, 0x08,
61 0xff, 0x6e, 0xc8, 0x08,
62 0x00, 0x6c, 0x76, 0x78,
63 0x20, 0x01, 0x02, 0x00,
64 0x4c, 0x37, 0xc8, 0x28,
65 0x08, 0x1f, 0x7e, 0x78,
66 0x08, 0x37, 0x6e, 0x00,
67 0x08, 0x64, 0xc8, 0x00,
68 0x70, 0x64, 0xca, 0x18,
69 0xff, 0x6c, 0x0a, 0x08,
70 0x20, 0x64, 0xca, 0x18,
71 0xff, 0x6c, 0x08, 0x0c,
72 0x40, 0x0b, 0x96, 0x68,
73 0x20, 0x6a, 0x16, 0x00,
74 0xf0, 0x19, 0x6e, 0x08,
75 0x08, 0x6a, 0x18, 0x00,
76 0x08, 0x11, 0x22, 0x00,
77 0x08, 0x6a, 0x66, 0x58,
78 0x08, 0x6a, 0x68, 0x00,
79 0x00, 0x65, 0xaa, 0x40,
80 0x12, 0x6a, 0x00, 0x00,
81 0x40, 0x6a, 0x16, 0x00,
82 0xff, 0x3e, 0x20, 0x09,
83 0xff, 0xba, 0x7c, 0x08,
84 0xff, 0xa1, 0x6e, 0x08,
85 0x08, 0x6a, 0x18, 0x00,
86 0x08, 0x11, 0x22, 0x00,
87 0x08, 0x6a, 0x66, 0x58,
88 0x80, 0x6a, 0x68, 0x00,
89 0x80, 0x36, 0x6c, 0x00,
90 0x00, 0x65, 0xba, 0x5b,
91 0xff, 0x3d, 0xc8, 0x08,
92 0xbf, 0x64, 0xe2, 0x78,
93 0x80, 0x64, 0xc8, 0x71,
94 0xa0, 0x64, 0xf8, 0x71,
95 0xc0, 0x64, 0xf0, 0x71,
96 0xe0, 0x64, 0x38, 0x72,
97 0x01, 0x6a, 0x22, 0x01,
98 0x00, 0x65, 0xaa, 0x40,
99 0xf7, 0x11, 0x22, 0x08,
100 0x00, 0x65, 0xca, 0x58,
101 0xff, 0x06, 0xd4, 0x08,
102 0xf7, 0x01, 0x02, 0x08,
103 0x09, 0x0c, 0xc4, 0x78,
104 0x08, 0x0c, 0x0c, 0x68,
105 0x01, 0x6a, 0x22, 0x01,
106 0xff, 0x6a, 0x26, 0x09,
107 0x02, 0x6a, 0x08, 0x30,
108 0xff, 0x6a, 0x08, 0x08,
109 0xdf, 0x01, 0x02, 0x08,
110 0x01, 0x6a, 0x7a, 0x00,
111 0xff, 0x6a, 0x6c, 0x0c,
112 0x04, 0x14, 0x10, 0x31,
113 0x03, 0xa9, 0x18, 0x31,
114 0x03, 0xa9, 0x10, 0x30,
115 0x08, 0x6a, 0xcc, 0x00,
116 0xa9, 0x6a, 0xd0, 0x5b,
117 0x00, 0x65, 0x02, 0x41,
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530 0xff, 0x6a, 0x1a, 0x09,
531 0xff, 0x6a, 0x1c, 0x09,
532 0xff, 0x35, 0x26, 0x09,
533 0x04, 0x35, 0x3c, 0x6c,
534 0xa0, 0x6a, 0xca, 0x00,
535 0x20, 0x65, 0xc8, 0x18,
536 0xff, 0x6c, 0x32, 0x09,
537 0xff, 0x6c, 0x32, 0x09,
538 0xff, 0x6c, 0x32, 0x09,
539 0xff, 0x6c, 0x32, 0x09,
540 0xff, 0x6c, 0x32, 0x09,
541 0xff, 0x6c, 0x32, 0x09,
542 0xff, 0x6c, 0x32, 0x09,
543 0xff, 0x6c, 0x32, 0x09,
544 0x00, 0x65, 0x26, 0x64,
545 0x0a, 0x93, 0x26, 0x01,
546 0x00, 0x65, 0x78, 0x44,
547 0xa0, 0x6a, 0xcc, 0x00,
548 0xe8, 0x6a, 0xc8, 0x00,
549 0x01, 0x94, 0x40, 0x6c,
550 0x10, 0x94, 0x42, 0x6c,
551 0x08, 0x94, 0x54, 0x6c,
552 0x08, 0x94, 0x54, 0x6c,
553 0x08, 0x94, 0x54, 0x6c,
554 0x00, 0x65, 0x68, 0x5c,
555 0x08, 0x64, 0xc8, 0x18,
556 0x00, 0x8c, 0xca, 0x18,
557 0x00, 0x65, 0x4a, 0x4c,
558 0x00, 0x65, 0x40, 0x44,
559 0xf7, 0x93, 0x26, 0x09,
560 0x08, 0x93, 0x56, 0x6c,
561 0x00, 0x65, 0x68, 0x5c,
562 0x08, 0x64, 0xc8, 0x18,
563 0x08, 0x64, 0x58, 0x64,
564 0xff, 0x6a, 0xd4, 0x0c,
565 0x00, 0x65, 0x78, 0x5c,
566 0x00, 0x65, 0x68, 0x5c,
567 0x00, 0x65, 0x68, 0x5c,
568 0x00, 0x65, 0x68, 0x5c,
569 0xff, 0x99, 0xda, 0x08,
570 0xff, 0x99, 0xda, 0x08,
571 0xff, 0x99, 0xda, 0x08,
572 0xff, 0x99, 0xda, 0x08,
573 0xff, 0x99, 0xda, 0x08,
574 0xff, 0x99, 0xda, 0x08,
575 0xff, 0x99, 0xda, 0x08,
576 0xff, 0x99, 0xda, 0x0c,
577 0x08, 0x94, 0x78, 0x7c,
578 0xf7, 0x93, 0x26, 0x09,
579 0x08, 0x93, 0x7c, 0x6c,
580 0xff, 0x6a, 0xd4, 0x0c,
581 0xff, 0x40, 0x74, 0x09,
582 0xff, 0x90, 0x80, 0x08,
583 0xff, 0x6a, 0x72, 0x05,
584 0xff, 0x40, 0x94, 0x64,
585 0xff, 0x3f, 0x8c, 0x64,
586 0xff, 0x6a, 0xca, 0x04,
587 0xff, 0x3f, 0x20, 0x09,
588 0x01, 0x6a, 0x6a, 0x00,
589 0x00, 0xb9, 0xe6, 0x5b,
590 0xff, 0xba, 0x7e, 0x0c,
591 0xff, 0x40, 0x20, 0x09,
592 0xff, 0xba, 0x80, 0x0c,
593 0xff, 0x3f, 0x74, 0x09,
594 0xff, 0x90, 0x7e, 0x0c,
595};
596
597static int aic7xxx_patch15_func(struct aic7xxx_host *p);
598
599static int
600aic7xxx_patch15_func(struct aic7xxx_host *p)
601{
602 return ((p->bugs & AHC_BUG_SCBCHAN_UPLOAD) != 0);
603}
604
605static int aic7xxx_patch14_func(struct aic7xxx_host *p);
606
607static int
608aic7xxx_patch14_func(struct aic7xxx_host *p)
609{
610 return ((p->bugs & AHC_BUG_PCI_2_1_RETRY) != 0);
611}
612
613static int aic7xxx_patch13_func(struct aic7xxx_host *p);
614
615static int
616aic7xxx_patch13_func(struct aic7xxx_host *p)
617{
618 return ((p->features & AHC_WIDE) != 0);
619}
620
621static int aic7xxx_patch12_func(struct aic7xxx_host *p);
622
623static int
624aic7xxx_patch12_func(struct aic7xxx_host *p)
625{
626 return ((p->bugs & AHC_BUG_AUTOFLUSH) != 0);
627}
628
629static int aic7xxx_patch11_func(struct aic7xxx_host *p);
630
631static int
632aic7xxx_patch11_func(struct aic7xxx_host *p)
633{
634 return ((p->features & AHC_ULTRA2) == 0);
635}
636
637static int aic7xxx_patch10_func(struct aic7xxx_host *p);
638
639static int
640aic7xxx_patch10_func(struct aic7xxx_host *p)
641{
642 return ((p->features & AHC_CMD_CHAN) == 0);
643}
644
645static int aic7xxx_patch9_func(struct aic7xxx_host *p);
646
647static int
648aic7xxx_patch9_func(struct aic7xxx_host *p)
649{
650 return ((p->chip & AHC_CHIPID_MASK) == AHC_AIC7895);
651}
652
653static int aic7xxx_patch8_func(struct aic7xxx_host *p);
654
655static int
656aic7xxx_patch8_func(struct aic7xxx_host *p)
657{
658 return ((p->features & AHC_ULTRA) != 0);
659}
660
661static int aic7xxx_patch7_func(struct aic7xxx_host *p);
662
663static int
664aic7xxx_patch7_func(struct aic7xxx_host *p)
665{
666 return ((p->features & AHC_ULTRA2) != 0);
667}
668
669static int aic7xxx_patch6_func(struct aic7xxx_host *p);
670
671static int
672aic7xxx_patch6_func(struct aic7xxx_host *p)
673{
674 return ((p->flags & AHC_PAGESCBS) == 0);
675}
676
677static int aic7xxx_patch5_func(struct aic7xxx_host *p);
678
679static int
680aic7xxx_patch5_func(struct aic7xxx_host *p)
681{
682 return ((p->flags & AHC_PAGESCBS) != 0);
683}
684
685static int aic7xxx_patch4_func(struct aic7xxx_host *p);
686
687static int
688aic7xxx_patch4_func(struct aic7xxx_host *p)
689{
690 return ((p->features & AHC_QUEUE_REGS) != 0);
691}
692
693static int aic7xxx_patch3_func(struct aic7xxx_host *p);
694
695static int
696aic7xxx_patch3_func(struct aic7xxx_host *p)
697{
698 return ((p->features & AHC_TWIN) != 0);
699}
700
701static int aic7xxx_patch2_func(struct aic7xxx_host *p);
702
703static int
704aic7xxx_patch2_func(struct aic7xxx_host *p)
705{
706 return ((p->features & AHC_QUEUE_REGS) == 0);
707}
708
709static int aic7xxx_patch1_func(struct aic7xxx_host *p);
710
711static int
712aic7xxx_patch1_func(struct aic7xxx_host *p)
713{
714 return ((p->features & AHC_CMD_CHAN) != 0);
715}
716
717static int aic7xxx_patch0_func(struct aic7xxx_host *p);
718
719static int
720aic7xxx_patch0_func(struct aic7xxx_host *p)
721{
722 return (0);
723}
724
725struct sequencer_patch {
726 int (*patch_func)(struct aic7xxx_host *);
727 unsigned int begin :10,
728 skip_instr :10,
729 skip_patch :12;
730} sequencer_patches[] = {
731 { aic7xxx_patch1_func, 3, 2, 1 },
732 { aic7xxx_patch2_func, 7, 1, 1 },
733 { aic7xxx_patch2_func, 8, 1, 1 },
734 { aic7xxx_patch3_func, 11, 4, 1 },
735 { aic7xxx_patch4_func, 16, 3, 2 },
736 { aic7xxx_patch0_func, 19, 4, 1 },
737 { aic7xxx_patch5_func, 23, 1, 1 },
738 { aic7xxx_patch6_func, 26, 1, 1 },
739 { aic7xxx_patch1_func, 29, 1, 2 },
740 { aic7xxx_patch0_func, 30, 3, 1 },
741 { aic7xxx_patch3_func, 39, 4, 1 },
742 { aic7xxx_patch7_func, 43, 3, 2 },
743 { aic7xxx_patch0_func, 46, 3, 1 },
744 { aic7xxx_patch8_func, 52, 7, 1 },
745 { aic7xxx_patch3_func, 60, 3, 1 },
746 { aic7xxx_patch7_func, 63, 2, 1 },
747 { aic7xxx_patch7_func, 102, 1, 2 },
748 { aic7xxx_patch0_func, 103, 2, 1 },
749 { aic7xxx_patch7_func, 107, 2, 1 },
750 { aic7xxx_patch9_func, 109, 1, 1 },
751 { aic7xxx_patch10_func, 110, 2, 1 },
752 { aic7xxx_patch7_func, 113, 1, 2 },
753 { aic7xxx_patch0_func, 114, 1, 1 },
754 { aic7xxx_patch1_func, 118, 1, 1 },
755 { aic7xxx_patch1_func, 121, 3, 3 },
756 { aic7xxx_patch11_func, 123, 1, 1 },
757 { aic7xxx_patch0_func, 124, 5, 1 },
758 { aic7xxx_patch7_func, 132, 1, 1 },
759 { aic7xxx_patch9_func, 133, 1, 1 },
760 { aic7xxx_patch10_func, 134, 3, 1 },
761 { aic7xxx_patch7_func, 137, 3, 2 },
762 { aic7xxx_patch0_func, 140, 2, 1 },
763 { aic7xxx_patch7_func, 142, 5, 2 },
764 { aic7xxx_patch0_func, 147, 3, 1 },
765 { aic7xxx_patch7_func, 150, 1, 2 },
766 { aic7xxx_patch0_func, 151, 2, 1 },
767 { aic7xxx_patch1_func, 153, 15, 4 },
768 { aic7xxx_patch11_func, 166, 1, 2 },
769 { aic7xxx_patch0_func, 167, 1, 1 },
770 { aic7xxx_patch0_func, 168, 10, 1 },
771 { aic7xxx_patch7_func, 181, 1, 2 },
772 { aic7xxx_patch0_func, 182, 2, 1 },
773 { aic7xxx_patch7_func, 184, 18, 1 },
774 { aic7xxx_patch1_func, 202, 3, 3 },
775 { aic7xxx_patch7_func, 204, 1, 1 },
776 { aic7xxx_patch0_func, 205, 4, 1 },
777 { aic7xxx_patch7_func, 210, 2, 1 },
778 { aic7xxx_patch7_func, 215, 13, 3 },
779 { aic7xxx_patch12_func, 218, 1, 1 },
780 { aic7xxx_patch12_func, 219, 4, 1 },
781 { aic7xxx_patch1_func, 229, 3, 3 },
782 { aic7xxx_patch11_func, 231, 1, 1 },
783 { aic7xxx_patch0_func, 232, 5, 1 },
784 { aic7xxx_patch11_func, 237, 1, 2 },
785 { aic7xxx_patch0_func, 238, 9, 1 },
786 { aic7xxx_patch13_func, 254, 1, 2 },
787 { aic7xxx_patch0_func, 255, 1, 1 },
788 { aic7xxx_patch4_func, 316, 1, 2 },
789 { aic7xxx_patch0_func, 317, 1, 1 },
790 { aic7xxx_patch2_func, 320, 1, 1 },
791 { aic7xxx_patch1_func, 330, 3, 2 },
792 { aic7xxx_patch0_func, 333, 5, 1 },
793 { aic7xxx_patch13_func, 341, 1, 2 },
794 { aic7xxx_patch0_func, 342, 1, 1 },
795 { aic7xxx_patch5_func, 347, 1, 1 },
796 { aic7xxx_patch11_func, 389, 15, 2 },
797 { aic7xxx_patch14_func, 402, 1, 1 },
798 { aic7xxx_patch1_func, 441, 7, 2 },
799 { aic7xxx_patch0_func, 448, 8, 1 },
800 { aic7xxx_patch1_func, 457, 4, 2 },
801 { aic7xxx_patch0_func, 461, 6, 1 },
802 { aic7xxx_patch1_func, 467, 4, 2 },
803 { aic7xxx_patch0_func, 471, 3, 1 },
804 { aic7xxx_patch10_func, 481, 10, 1 },
805 { aic7xxx_patch1_func, 500, 22, 5 },
806 { aic7xxx_patch11_func, 508, 4, 1 },
807 { aic7xxx_patch7_func, 512, 7, 3 },
808 { aic7xxx_patch15_func, 512, 5, 2 },
809 { aic7xxx_patch0_func, 517, 2, 1 },
810 { aic7xxx_patch10_func, 522, 50, 3 },
811 { aic7xxx_patch14_func, 543, 17, 2 },
812 { aic7xxx_patch0_func, 560, 4, 1 },
813 { aic7xxx_patch10_func, 572, 4, 1 },
814 { aic7xxx_patch5_func, 576, 2, 1 },
815 { aic7xxx_patch5_func, 579, 9, 1 },
816
817};
diff --git a/drivers/scsi/aic7xxx_old/scsi_message.h b/drivers/scsi/aic7xxx_old/scsi_message.h
new file mode 100644
index 000000000000..a79f89c65173
--- /dev/null
+++ b/drivers/scsi/aic7xxx_old/scsi_message.h
@@ -0,0 +1,49 @@
1/* Messages (1 byte) */ /* I/T (M)andatory or (O)ptional */
2#define MSG_CMDCOMPLETE 0x00 /* M/M */
3#define MSG_EXTENDED 0x01 /* O/O */
4#define MSG_SAVEDATAPOINTER 0x02 /* O/O */
5#define MSG_RESTOREPOINTERS 0x03 /* O/O */
6#define MSG_DISCONNECT 0x04 /* O/O */
7#define MSG_INITIATOR_DET_ERR 0x05 /* M/M */
8#define MSG_ABORT 0x06 /* O/M */
9#define MSG_MESSAGE_REJECT 0x07 /* M/M */
10#define MSG_NOOP 0x08 /* M/M */
11#define MSG_PARITY_ERROR 0x09 /* M/M */
12#define MSG_LINK_CMD_COMPLETE 0x0a /* O/O */
13#define MSG_LINK_CMD_COMPLETEF 0x0b /* O/O */
14#define MSG_BUS_DEV_RESET 0x0c /* O/M */
15#define MSG_ABORT_TAG 0x0d /* O/O */
16#define MSG_CLEAR_QUEUE 0x0e /* O/O */
17#define MSG_INIT_RECOVERY 0x0f /* O/O */
18#define MSG_REL_RECOVERY 0x10 /* O/O */
19#define MSG_TERM_IO_PROC 0x11 /* O/O */
20
21/* Messages (2 byte) */
22#define MSG_SIMPLE_Q_TAG 0x20 /* O/O */
23#define MSG_HEAD_OF_Q_TAG 0x21 /* O/O */
24#define MSG_ORDERED_Q_TAG 0x22 /* O/O */
25#define MSG_IGN_WIDE_RESIDUE 0x23 /* O/O */
26
27/* Identify message */ /* M/M */
28#define MSG_IDENTIFYFLAG 0x80
29#define MSG_IDENTIFY_DISCFLAG 0x40
30#define MSG_IDENTIFY(lun, disc) (((disc) ? 0xc0 : MSG_IDENTIFYFLAG) | (lun))
31#define MSG_ISIDENTIFY(m) ((m) & MSG_IDENTIFYFLAG)
32
33/* Extended messages (opcode and length) */
34#define MSG_EXT_SDTR 0x01
35#define MSG_EXT_SDTR_LEN 0x03
36
37#define MSG_EXT_WDTR 0x03
38#define MSG_EXT_WDTR_LEN 0x02
39#define MSG_EXT_WDTR_BUS_8_BIT 0x00
40#define MSG_EXT_WDTR_BUS_16_BIT 0x01
41#define MSG_EXT_WDTR_BUS_32_BIT 0x02
42
43#define MSG_EXT_PPR 0x04
44#define MSG_EXT_PPR_LEN 0x06
45#define MSG_EXT_PPR_OPTION_ST 0x00
46#define MSG_EXT_PPR_OPTION_DT_CRC 0x02
47#define MSG_EXT_PPR_OPTION_DT_UNITS 0x03
48#define MSG_EXT_PPR_OPTION_DT_CRC_QUICK 0x04
49#define MSG_EXT_PPR_OPTION_DT_UNITS_QUICK 0x05
diff --git a/drivers/scsi/aic7xxx_old/sequencer.h b/drivers/scsi/aic7xxx_old/sequencer.h
new file mode 100644
index 000000000000..ee66855222b1
--- /dev/null
+++ b/drivers/scsi/aic7xxx_old/sequencer.h
@@ -0,0 +1,135 @@
1/*
2 * Instruction formats for the sequencer program downloaded to
3 * Aic7xxx SCSI host adapters
4 *
5 * Copyright (c) 1997, 1998 Justin T. Gibbs.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification, immediately at the beginning of the file.
14 * 2. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * Where this Software is combined with software released under the terms of
18 * the GNU General Public License ("GPL") and the terms of the GPL would require the
19 * combined work to also be released under the terms of the GPL, the terms
20 * and conditions of this License will apply in addition to those of the
21 * GPL with the exception of any terms or conditions of this License that
22 * conflict with, or are expressly prohibited by, the GPL.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * $Id: sequencer.h,v 1.3 1997/09/27 19:37:31 gibbs Exp $
37 */
38
39#ifdef __LITTLE_ENDIAN_BITFIELD
40struct ins_format1 {
41 unsigned int
42 immediate : 8,
43 source : 9,
44 destination : 9,
45 ret : 1,
46 opcode : 4,
47 parity : 1;
48};
49
50struct ins_format2 {
51 unsigned int
52 shift_control : 8,
53 source : 9,
54 destination : 9,
55 ret : 1,
56 opcode : 4,
57 parity : 1;
58};
59
60struct ins_format3 {
61 unsigned int
62 immediate : 8,
63 source : 9,
64 address : 10,
65 opcode : 4,
66 parity : 1;
67};
68#elif defined(__BIG_ENDIAN_BITFIELD)
69struct ins_format1 {
70 unsigned int
71 parity : 1,
72 opcode : 4,
73 ret : 1,
74 destination : 9,
75 source : 9,
76 immediate : 8;
77};
78
79struct ins_format2 {
80 unsigned int
81 parity : 1,
82 opcode : 4,
83 ret : 1,
84 destination : 9,
85 source : 9,
86 shift_control : 8;
87};
88
89struct ins_format3 {
90 unsigned int
91 parity : 1,
92 opcode : 4,
93 address : 10,
94 source : 9,
95 immediate : 8;
96};
97#endif
98
99union ins_formats {
100 struct ins_format1 format1;
101 struct ins_format2 format2;
102 struct ins_format3 format3;
103 unsigned char bytes[4];
104 unsigned int integer;
105};
106struct instruction {
107 union ins_formats format;
108 unsigned int srcline;
109 struct symbol *patch_label;
110 struct {
111 struct instruction *stqe_next;
112 } links;
113};
114
115#define AIC_OP_OR 0x0
116#define AIC_OP_AND 0x1
117#define AIC_OP_XOR 0x2
118#define AIC_OP_ADD 0x3
119#define AIC_OP_ADC 0x4
120#define AIC_OP_ROL 0x5
121#define AIC_OP_BMOV 0x6
122
123#define AIC_OP_JMP 0x8
124#define AIC_OP_JC 0x9
125#define AIC_OP_JNC 0xa
126#define AIC_OP_CALL 0xb
127#define AIC_OP_JNE 0xc
128#define AIC_OP_JNZ 0xd
129#define AIC_OP_JE 0xe
130#define AIC_OP_JZ 0xf
131
132/* Pseudo Ops */
133#define AIC_OP_SHL 0x10
134#define AIC_OP_SHR 0x20
135#define AIC_OP_ROR 0x30
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 11:32:28 -0500