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diff --git a/drivers/scsi/aic7xxx/aic7xxx.seq b/drivers/scsi/aic7xxx/aic7xxx.seq
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1/*
2 * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $FreeBSD$
41 */
42
43VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#56 $"
44PATCH_ARG_LIST = "struct ahc_softc *ahc"
45PREFIX = "ahc_"
46
47#include "aic7xxx.reg"
48#include "scsi_message.h"
49
50/*
51 * A few words on the waiting SCB list:
52 * After starting the selection hardware, we check for reconnecting targets
53 * as well as for our selection to complete just in case the reselection wins
54 * bus arbitration. The problem with this is that we must keep track of the
55 * SCB that we've already pulled from the QINFIFO and started the selection
56 * on just in case the reselection wins so that we can retry the selection at
57 * a later time. This problem cannot be resolved by holding a single entry
58 * in scratch ram since a reconnecting target can request sense and this will
59 * create yet another SCB waiting for selection. The solution used here is to
60 * use byte 27 of the SCB as a psuedo-next pointer and to thread a list
61 * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes,
62 * SCB_LIST_NULL is 0xff which is out of range. An entry is also added to
63 * this list everytime a request sense occurs or after completing a non-tagged
64 * command for which a second SCB has been queued. The sequencer will
65 * automatically consume the entries.
66 */
67
68bus_free_sel:
69 /*
70 * Turn off the selection hardware. We need to reset the
71 * selection request in order to perform a new selection.
72 */
73 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP;
74 and SIMODE1, ~ENBUSFREE;
75poll_for_work:
76 call clear_target_state;
77 and SXFRCTL0, ~SPIOEN;
78 if ((ahc->features & AHC_ULTRA2) != 0) {
79 clr SCSIBUSL;
80 }
81 test SCSISEQ, ENSELO jnz poll_for_selection;
82 if ((ahc->features & AHC_TWIN) != 0) {
83 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */
84 test SCSISEQ, ENSELO jnz poll_for_selection;
85 }
86 cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting;
87poll_for_work_loop:
88 if ((ahc->features & AHC_TWIN) != 0) {
89 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */
90 }
91 test SSTAT0, SELDO|SELDI jnz selection;
92test_queue:
93 /* Has the driver posted any work for us? */
94BEGIN_CRITICAL;
95 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
96 test QOFF_CTLSTA, SCB_AVAIL jz poll_for_work_loop;
97 } else {
98 mov A, QINPOS;
99 cmp KERNEL_QINPOS, A je poll_for_work_loop;
100 }
101 mov ARG_1, NEXT_QUEUED_SCB;
102
103 /*
104 * We have at least one queued SCB now and we don't have any
105 * SCBs in the list of SCBs awaiting selection. Allocate a
106 * card SCB for the host's SCB and get to work on it.
107 */
108 if ((ahc->flags & AHC_PAGESCBS) != 0) {
109 mov ALLZEROS call get_free_or_disc_scb;
110 } else {
111 /* In the non-paging case, the SCBID == hardware SCB index */
112 mov SCBPTR, ARG_1;
113 }
114 or SEQ_FLAGS2, SCB_DMA;
115END_CRITICAL;
116dma_queued_scb:
117 /*
118 * DMA the SCB from host ram into the current SCB location.
119 */
120 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
121 mov ARG_1 call dma_scb;
122 /*
123 * Check one last time to see if this SCB was canceled
124 * before we completed the DMA operation. If it was,
125 * the QINFIFO next pointer will not match our saved
126 * value.
127 */
128 mov A, ARG_1;
129BEGIN_CRITICAL;
130 cmp NEXT_QUEUED_SCB, A jne abort_qinscb;
131 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
132 cmp SCB_TAG, A je . + 2;
133 mvi SCB_MISMATCH call set_seqint;
134 }
135 mov NEXT_QUEUED_SCB, SCB_NEXT;
136 mov SCB_NEXT,WAITING_SCBH;
137 mov WAITING_SCBH, SCBPTR;
138 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
139 mov NONE, SNSCB_QOFF;
140 } else {
141 inc QINPOS;
142 }
143 and SEQ_FLAGS2, ~SCB_DMA;
144END_CRITICAL;
145start_waiting:
146 /*
147 * Start the first entry on the waiting SCB list.
148 */
149 mov SCBPTR, WAITING_SCBH;
150 call start_selection;
151
152poll_for_selection:
153 /*
154 * Twin channel devices cannot handle things like SELTO
155 * interrupts on the "background" channel. So, while
156 * selecting, keep polling the current channel until
157 * either a selection or reselection occurs.
158 */
159 test SSTAT0, SELDO|SELDI jz poll_for_selection;
160
161selection:
162 /*
163 * We aren't expecting a bus free, so interrupt
164 * the kernel driver if it happens.
165 */
166 mvi CLRSINT1,CLRBUSFREE;
167 if ((ahc->features & AHC_DT) == 0) {
168 or SIMODE1, ENBUSFREE;
169 }
170
171 /*
172 * Guard against a bus free after (re)selection
173 * but prior to enabling the busfree interrupt. SELDI
174 * and SELDO will be cleared in that case.
175 */
176 test SSTAT0, SELDI|SELDO jz bus_free_sel;
177 test SSTAT0,SELDO jnz select_out;
178select_in:
179 if ((ahc->flags & AHC_TARGETROLE) != 0) {
180 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
181 test SSTAT0, TARGET jz initiator_reselect;
182 }
183 mvi CLRSINT0, CLRSELDI;
184
185 /*
186 * We've just been selected. Assert BSY and
187 * setup the phase for receiving messages
188 * from the target.
189 */
190 mvi SCSISIGO, P_MESGOUT|BSYO;
191
192 /*
193 * Setup the DMA for sending the identify and
194 * command information.
195 */
196 mvi SEQ_FLAGS, CMDPHASE_PENDING;
197
198 mov A, TQINPOS;
199 if ((ahc->features & AHC_CMD_CHAN) != 0) {
200 mvi DINDEX, CCHADDR;
201 mvi SHARED_DATA_ADDR call set_32byte_addr;
202 mvi CCSCBCTL, CCSCBRESET;
203 } else {
204 mvi DINDEX, HADDR;
205 mvi SHARED_DATA_ADDR call set_32byte_addr;
206 mvi DFCNTRL, FIFORESET;
207 }
208
209 /* Initiator that selected us */
210 and SAVED_SCSIID, SELID_MASK, SELID;
211 /* The Target ID we were selected at */
212 if ((ahc->features & AHC_MULTI_TID) != 0) {
213 and A, OID, TARGIDIN;
214 } else if ((ahc->features & AHC_ULTRA2) != 0) {
215 and A, OID, SCSIID_ULTRA2;
216 } else {
217 and A, OID, SCSIID;
218 }
219 or SAVED_SCSIID, A;
220 if ((ahc->features & AHC_TWIN) != 0) {
221 test SBLKCTL, SELBUSB jz . + 2;
222 or SAVED_SCSIID, TWIN_CHNLB;
223 }
224 if ((ahc->features & AHC_CMD_CHAN) != 0) {
225 mov CCSCBRAM, SAVED_SCSIID;
226 } else {
227 mov DFDAT, SAVED_SCSIID;
228 }
229
230 /*
231 * If ATN isn't asserted, the target isn't interested
232 * in talking to us. Go directly to bus free.
233 * XXX SCSI-1 may require us to assume lun 0 if
234 * ATN is false.
235 */
236 test SCSISIGI, ATNI jz target_busfree;
237
238 /*
239 * Watch ATN closely now as we pull in messages from the
240 * initiator. We follow the guidlines from section 6.5
241 * of the SCSI-2 spec for what messages are allowed when.
242 */
243 call target_inb;
244
245 /*
246 * Our first message must be one of IDENTIFY, ABORT, or
247 * BUS_DEVICE_RESET.
248 */
249 test DINDEX, MSG_IDENTIFYFLAG jz host_target_message_loop;
250 /* Store for host */
251 if ((ahc->features & AHC_CMD_CHAN) != 0) {
252 mov CCSCBRAM, DINDEX;
253 } else {
254 mov DFDAT, DINDEX;
255 }
256 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, DINDEX;
257
258 /* Remember for disconnection decision */
259 test DINDEX, MSG_IDENTIFY_DISCFLAG jnz . + 2;
260 /* XXX Honor per target settings too */
261 or SEQ_FLAGS, NO_DISCONNECT;
262
263 test SCSISIGI, ATNI jz ident_messages_done;
264 call target_inb;
265 /*
266 * If this is a tagged request, the tagged message must
267 * immediately follow the identify. We test for a valid
268 * tag message by seeing if it is >= MSG_SIMPLE_Q_TAG and
269 * < MSG_IGN_WIDE_RESIDUE.
270 */
271 add A, -MSG_SIMPLE_Q_TAG, DINDEX;
272 jnc ident_messages_done_msg_pending;
273 add A, -MSG_IGN_WIDE_RESIDUE, DINDEX;
274 jc ident_messages_done_msg_pending;
275
276 /* Store for host */
277 if ((ahc->features & AHC_CMD_CHAN) != 0) {
278 mov CCSCBRAM, DINDEX;
279 } else {
280 mov DFDAT, DINDEX;
281 }
282
283 /*
284 * If the initiator doesn't feel like providing a tag number,
285 * we've got a failed selection and must transition to bus
286 * free.
287 */
288 test SCSISIGI, ATNI jz target_busfree;
289
290 /*
291 * Store the tag for the host.
292 */
293 call target_inb;
294 if ((ahc->features & AHC_CMD_CHAN) != 0) {
295 mov CCSCBRAM, DINDEX;
296 } else {
297 mov DFDAT, DINDEX;
298 }
299 mov INITIATOR_TAG, DINDEX;
300 or SEQ_FLAGS, TARGET_CMD_IS_TAGGED;
301
302ident_messages_done:
303 /* Terminate the ident list */
304 if ((ahc->features & AHC_CMD_CHAN) != 0) {
305 mvi CCSCBRAM, SCB_LIST_NULL;
306 } else {
307 mvi DFDAT, SCB_LIST_NULL;
308 }
309 or SEQ_FLAGS, TARG_CMD_PENDING;
310 test SEQ_FLAGS2, TARGET_MSG_PENDING
311 jnz target_mesgout_pending;
312 test SCSISIGI, ATNI jnz target_mesgout_continue;
313 jmp target_ITloop;
314
315
316ident_messages_done_msg_pending:
317 or SEQ_FLAGS2, TARGET_MSG_PENDING;
318 jmp ident_messages_done;
319
320 /*
321 * Pushed message loop to allow the kernel to
322 * run it's own target mode message state engine.
323 */
324host_target_message_loop:
325 mvi HOST_MSG_LOOP call set_seqint;
326 cmp RETURN_1, EXIT_MSG_LOOP je target_ITloop;
327 test SSTAT0, SPIORDY jz .;
328 jmp host_target_message_loop;
329 }
330
331if ((ahc->flags & AHC_INITIATORROLE) != 0) {
332/*
333 * Reselection has been initiated by a target. Make a note that we've been
334 * reselected, but haven't seen an IDENTIFY message from the target yet.
335 */
336initiator_reselect:
337 /* XXX test for and handle ONE BIT condition */
338 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
339 and SAVED_SCSIID, SELID_MASK, SELID;
340 if ((ahc->features & AHC_ULTRA2) != 0) {
341 and A, OID, SCSIID_ULTRA2;
342 } else {
343 and A, OID, SCSIID;
344 }
345 or SAVED_SCSIID, A;
346 if ((ahc->features & AHC_TWIN) != 0) {
347 test SBLKCTL, SELBUSB jz . + 2;
348 or SAVED_SCSIID, TWIN_CHNLB;
349 }
350 mvi CLRSINT0, CLRSELDI;
351 jmp ITloop;
352}
353
354abort_qinscb:
355 call add_scb_to_free_list;
356 jmp poll_for_work_loop;
357
358start_selection:
359 /*
360 * If bus reset interrupts have been disabled (from a previous
361 * reset), re-enable them now. Resets are only of interest
362 * when we have outstanding transactions, so we can safely
363 * defer re-enabling the interrupt until, as an initiator,
364 * we start sending out transactions again.
365 */
366 test SIMODE1, ENSCSIRST jnz . + 3;
367 mvi CLRSINT1, CLRSCSIRSTI;
368 or SIMODE1, ENSCSIRST;
369 if ((ahc->features & AHC_TWIN) != 0) {
370 and SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */
371 test SCB_SCSIID, TWIN_CHNLB jz . + 2;
372 or SINDEX, SELBUSB;
373 mov SBLKCTL,SINDEX; /* select channel */
374 }
375initialize_scsiid:
376 if ((ahc->features & AHC_ULTRA2) != 0) {
377 mov SCSIID_ULTRA2, SCB_SCSIID;
378 } else if ((ahc->features & AHC_TWIN) != 0) {
379 and SCSIID, TWIN_TID|OID, SCB_SCSIID;
380 } else {
381 mov SCSIID, SCB_SCSIID;
382 }
383 if ((ahc->flags & AHC_TARGETROLE) != 0) {
384 mov SINDEX, SCSISEQ_TEMPLATE;
385 test SCB_CONTROL, TARGET_SCB jz . + 2;
386 or SINDEX, TEMODE;
387 mov SCSISEQ, SINDEX ret;
388 } else {
389 mov SCSISEQ, SCSISEQ_TEMPLATE ret;
390 }
391
392/*
393 * Initialize transfer settings with SCB provided settings.
394 */
395set_transfer_settings:
396 if ((ahc->features & AHC_ULTRA) != 0) {
397 test SCB_CONTROL, ULTRAENB jz . + 2;
398 or SXFRCTL0, FAST20;
399 }
400 /*
401 * Initialize SCSIRATE with the appropriate value for this target.
402 */
403 if ((ahc->features & AHC_ULTRA2) != 0) {
404 bmov SCSIRATE, SCB_SCSIRATE, 2 ret;
405 } else {
406 mov SCSIRATE, SCB_SCSIRATE ret;
407 }
408
409if ((ahc->flags & AHC_TARGETROLE) != 0) {
410/*
411 * We carefully toggle SPIOEN to allow us to return the
412 * message byte we receive so it can be checked prior to
413 * driving REQ on the bus for the next byte.
414 */
415target_inb:
416 /*
417 * Drive REQ on the bus by enabling SCSI PIO.
418 */
419 or SXFRCTL0, SPIOEN;
420 /* Wait for the byte */
421 test SSTAT0, SPIORDY jz .;
422 /* Prevent our read from triggering another REQ */
423 and SXFRCTL0, ~SPIOEN;
424 /* Save latched contents */
425 mov DINDEX, SCSIDATL ret;
426}
427
428/*
429 * After the selection, remove this SCB from the "waiting SCB"
430 * list. This is achieved by simply moving our "next" pointer into
431 * WAITING_SCBH. Our next pointer will be set to null the next time this
432 * SCB is used, so don't bother with it now.
433 */
434select_out:
435 /* Turn off the selection hardware */
436 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ;
437 mov SCBPTR, WAITING_SCBH;
438 mov WAITING_SCBH,SCB_NEXT;
439 mov SAVED_SCSIID, SCB_SCSIID;
440 and SAVED_LUN, LID, SCB_LUN;
441 call set_transfer_settings;
442 if ((ahc->flags & AHC_TARGETROLE) != 0) {
443 test SSTAT0, TARGET jz initiator_select;
444
445 or SXFRCTL0, CLRSTCNT|CLRCHN;
446
447 /*
448 * Put tag in connonical location since not
449 * all connections have an SCB.
450 */
451 mov INITIATOR_TAG, SCB_TARGET_ITAG;
452
453 /*
454 * We've just re-selected an initiator.
455 * Assert BSY and setup the phase for
456 * sending our identify messages.
457 */
458 mvi P_MESGIN|BSYO call change_phase;
459 mvi CLRSINT0, CLRSELDO;
460
461 /*
462 * Start out with a simple identify message.
463 */
464 or SAVED_LUN, MSG_IDENTIFYFLAG call target_outb;
465
466 /*
467 * If we are the result of a tagged command, send
468 * a simple Q tag and the tag id.
469 */
470 test SCB_CONTROL, TAG_ENB jz . + 3;
471 mvi MSG_SIMPLE_Q_TAG call target_outb;
472 mov SCB_TARGET_ITAG call target_outb;
473target_synccmd:
474 /*
475 * Now determine what phases the host wants us
476 * to go through.
477 */
478 mov SEQ_FLAGS, SCB_TARGET_PHASES;
479
480 test SCB_CONTROL, MK_MESSAGE jz target_ITloop;
481 mvi P_MESGIN|BSYO call change_phase;
482 jmp host_target_message_loop;
483target_ITloop:
484 /*
485 * Start honoring ATN signals now that
486 * we properly identified ourselves.
487 */
488 test SCSISIGI, ATNI jnz target_mesgout;
489 test SEQ_FLAGS, CMDPHASE_PENDING jnz target_cmdphase;
490 test SEQ_FLAGS, DPHASE_PENDING jnz target_dphase;
491 test SEQ_FLAGS, SPHASE_PENDING jnz target_sphase;
492
493 /*
494 * No more work to do. Either disconnect or not depending
495 * on the state of NO_DISCONNECT.
496 */
497 test SEQ_FLAGS, NO_DISCONNECT jz target_disconnect;
498 mvi TARG_IMMEDIATE_SCB, SCB_LIST_NULL;
499 call complete_target_cmd;
500 if ((ahc->flags & AHC_PAGESCBS) != 0) {
501 mov ALLZEROS call get_free_or_disc_scb;
502 }
503 cmp TARG_IMMEDIATE_SCB, SCB_LIST_NULL je .;
504 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
505 mov TARG_IMMEDIATE_SCB call dma_scb;
506 call set_transfer_settings;
507 or SXFRCTL0, CLRSTCNT|CLRCHN;
508 jmp target_synccmd;
509
510target_mesgout:
511 mvi SCSISIGO, P_MESGOUT|BSYO;
512target_mesgout_continue:
513 call target_inb;
514target_mesgout_pending:
515 and SEQ_FLAGS2, ~TARGET_MSG_PENDING;
516 /* Local Processing goes here... */
517 jmp host_target_message_loop;
518
519target_disconnect:
520 mvi P_MESGIN|BSYO call change_phase;
521 test SEQ_FLAGS, DPHASE jz . + 2;
522 mvi MSG_SAVEDATAPOINTER call target_outb;
523 mvi MSG_DISCONNECT call target_outb;
524
525target_busfree_wait:
526 /* Wait for preceding I/O session to complete. */
527 test SCSISIGI, ACKI jnz .;
528target_busfree:
529 and SIMODE1, ~ENBUSFREE;
530 if ((ahc->features & AHC_ULTRA2) != 0) {
531 clr SCSIBUSL;
532 }
533 clr SCSISIGO;
534 mvi LASTPHASE, P_BUSFREE;
535 call complete_target_cmd;
536 jmp poll_for_work;
537
538target_cmdphase:
539 /*
540 * The target has dropped ATN (doesn't want to abort or BDR)
541 * and we believe this selection to be valid. If the ring
542 * buffer for new commands is full, return busy or queue full.
543 */
544 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
545 and A, HOST_TQINPOS, HS_MAILBOX;
546 } else {
547 mov A, KERNEL_TQINPOS;
548 }
549 cmp TQINPOS, A jne tqinfifo_has_space;
550 mvi P_STATUS|BSYO call change_phase;
551 test SEQ_FLAGS, TARGET_CMD_IS_TAGGED jz . + 3;
552 mvi STATUS_QUEUE_FULL call target_outb;
553 jmp target_busfree_wait;
554 mvi STATUS_BUSY call target_outb;
555 jmp target_busfree_wait;
556tqinfifo_has_space:
557 mvi P_COMMAND|BSYO call change_phase;
558 call target_inb;
559 mov A, DINDEX;
560 /* Store for host */
561 if ((ahc->features & AHC_CMD_CHAN) != 0) {
562 mov CCSCBRAM, A;
563 } else {
564 mov DFDAT, A;
565 }
566
567 /*
568 * Determine the number of bytes to read
569 * based on the command group code via table lookup.
570 * We reuse the first 8 bytes of the TARG_SCSIRATE
571 * BIOS array for this table. Count is one less than
572 * the total for the command since we've already fetched
573 * the first byte.
574 */
575 shr A, CMD_GROUP_CODE_SHIFT;
576 add SINDEX, CMDSIZE_TABLE, A;
577 mov A, SINDIR;
578
579 test A, 0xFF jz command_phase_done;
580 or SXFRCTL0, SPIOEN;
581command_loop:
582 test SSTAT0, SPIORDY jz .;
583 cmp A, 1 jne . + 2;
584 and SXFRCTL0, ~SPIOEN; /* Last Byte */
585 if ((ahc->features & AHC_CMD_CHAN) != 0) {
586 mov CCSCBRAM, SCSIDATL;
587 } else {
588 mov DFDAT, SCSIDATL;
589 }
590 dec A;
591 test A, 0xFF jnz command_loop;
592
593command_phase_done:
594 and SEQ_FLAGS, ~CMDPHASE_PENDING;
595 jmp target_ITloop;
596
597target_dphase:
598 /*
599 * Data phases on the bus are from the
600 * perspective of the initiator. The dma
601 * code looks at LASTPHASE to determine the
602 * data direction of the DMA. Toggle it for
603 * target transfers.
604 */
605 xor LASTPHASE, IOI, SCB_TARGET_DATA_DIR;
606 or SCB_TARGET_DATA_DIR, BSYO call change_phase;
607 jmp p_data;
608
609target_sphase:
610 mvi P_STATUS|BSYO call change_phase;
611 mvi LASTPHASE, P_STATUS;
612 mov SCB_SCSI_STATUS call target_outb;
613 /* XXX Watch for ATN or parity errors??? */
614 mvi SCSISIGO, P_MESGIN|BSYO;
615 /* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */
616 mov ALLZEROS call target_outb;
617 jmp target_busfree_wait;
618
619complete_target_cmd:
620 test SEQ_FLAGS, TARG_CMD_PENDING jnz . + 2;
621 mov SCB_TAG jmp complete_post;
622 if ((ahc->features & AHC_CMD_CHAN) != 0) {
623 /* Set the valid byte */
624 mvi CCSCBADDR, 24;
625 mov CCSCBRAM, ALLONES;
626 mvi CCHCNT, 28;
627 or CCSCBCTL, CCSCBEN|CCSCBRESET;
628 test CCSCBCTL, CCSCBDONE jz .;
629 clr CCSCBCTL;
630 } else {
631 /* Set the valid byte */
632 or DFCNTRL, FIFORESET;
633 mvi DFWADDR, 3; /* Third 64bit word or byte 24 */
634 mov DFDAT, ALLONES;
635 mvi 28 call set_hcnt;
636 or DFCNTRL, HDMAEN|FIFOFLUSH;
637 call dma_finish;
638 }
639 inc TQINPOS;
640 mvi INTSTAT,CMDCMPLT ret;
641 }
642
643if ((ahc->flags & AHC_INITIATORROLE) != 0) {
644initiator_select:
645 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
646 /*
647 * As soon as we get a successful selection, the target
648 * should go into the message out phase since we have ATN
649 * asserted.
650 */
651 mvi MSG_OUT, MSG_IDENTIFYFLAG;
652 mvi SEQ_FLAGS, NO_CDB_SENT;
653 mvi CLRSINT0, CLRSELDO;
654
655 /*
656 * Main loop for information transfer phases. Wait for the
657 * target to assert REQ before checking MSG, C/D and I/O for
658 * the bus phase.
659 */
660mesgin_phasemis:
661ITloop:
662 call phase_lock;
663
664 mov A, LASTPHASE;
665
666 test A, ~P_DATAIN jz p_data;
667 cmp A,P_COMMAND je p_command;
668 cmp A,P_MESGOUT je p_mesgout;
669 cmp A,P_STATUS je p_status;
670 cmp A,P_MESGIN je p_mesgin;
671
672 mvi BAD_PHASE call set_seqint;
673 jmp ITloop; /* Try reading the bus again. */
674
675await_busfree:
676 and SIMODE1, ~ENBUSFREE;
677 mov NONE, SCSIDATL; /* Ack the last byte */
678 if ((ahc->features & AHC_ULTRA2) != 0) {
679 clr SCSIBUSL; /* Prevent bit leakage durint SELTO */
680 }
681 and SXFRCTL0, ~SPIOEN;
682 test SSTAT1,REQINIT|BUSFREE jz .;
683 test SSTAT1, BUSFREE jnz poll_for_work;
684 mvi MISSED_BUSFREE call set_seqint;
685}
686
687clear_target_state:
688 /*
689 * We assume that the kernel driver may reset us
690 * at any time, even in the middle of a DMA, so
691 * clear DFCNTRL too.
692 */
693 clr DFCNTRL;
694 or SXFRCTL0, CLRSTCNT|CLRCHN;
695
696 /*
697 * We don't know the target we will connect to,
698 * so default to narrow transfers to avoid
699 * parity problems.
700 */
701 if ((ahc->features & AHC_ULTRA2) != 0) {
702 bmov SCSIRATE, ALLZEROS, 2;
703 } else {
704 clr SCSIRATE;
705 if ((ahc->features & AHC_ULTRA) != 0) {
706 and SXFRCTL0, ~(FAST20);
707 }
708 }
709 mvi LASTPHASE, P_BUSFREE;
710 /* clear target specific flags */
711 mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT ret;
712
713sg_advance:
714 clr A; /* add sizeof(struct scatter) */
715 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
716 adc SCB_RESIDUAL_SGPTR[1],A;
717 adc SCB_RESIDUAL_SGPTR[2],A;
718 adc SCB_RESIDUAL_SGPTR[3],A ret;
719
720if ((ahc->features & AHC_CMD_CHAN) != 0) {
721disable_ccsgen:
722 test CCSGCTL, CCSGEN jz return;
723 test CCSGCTL, CCSGDONE jz .;
724disable_ccsgen_fetch_done:
725 clr CCSGCTL;
726 test CCSGCTL, CCSGEN jnz .;
727 ret;
728idle_loop:
729 /*
730 * Do we need any more segments for this transfer?
731 */
732 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz return;
733
734 /* Did we just finish fetching segs? */
735 cmp CCSGCTL, CCSGEN|CCSGDONE je idle_sgfetch_complete;
736
737 /* Are we actively fetching segments? */
738 test CCSGCTL, CCSGEN jnz return;
739
740 /*
741 * Do we have any prefetch left???
742 */
743 cmp CCSGADDR, SG_PREFETCH_CNT jne idle_sg_avail;
744
745 /*
746 * Need to fetch segments, but we can only do that
747 * if the command channel is completely idle. Make
748 * sure we don't have an SCB prefetch going on.
749 */
750 test CCSCBCTL, CCSCBEN jnz return;
751
752 /*
753 * We fetch a "cacheline aligned" and sized amount of data
754 * so we don't end up referencing a non-existant page.
755 * Cacheline aligned is in quotes because the kernel will
756 * set the prefetch amount to a reasonable level if the
757 * cacheline size is unknown.
758 */
759 mvi CCHCNT, SG_PREFETCH_CNT;
760 and CCHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
761 bmov CCHADDR[1], SCB_RESIDUAL_SGPTR[1], 3;
762 mvi CCSGCTL, CCSGEN|CCSGRESET ret;
763idle_sgfetch_complete:
764 call disable_ccsgen_fetch_done;
765 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
766idle_sg_avail:
767 if ((ahc->features & AHC_ULTRA2) != 0) {
768 /* Does the hardware have space for another SG entry? */
769 test DFSTATUS, PRELOAD_AVAIL jz return;
770 bmov HADDR, CCSGRAM, 7;
771 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
772 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
773 mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
774 }
775 call sg_advance;
776 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
777 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
778 or SINDEX, LAST_SEG;
779 mov SG_CACHE_PRE, SINDEX;
780 /* Load the segment */
781 or DFCNTRL, PRELOADEN;
782 }
783 ret;
784}
785
786if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
787/*
788 * Calculate the trailing portion of this S/G segment that cannot
789 * be transferred using memory write and invalidate PCI transactions.
790 * XXX Can we optimize this for PCI writes only???
791 */
792calc_mwi_residual:
793 /*
794 * If the ending address is on a cacheline boundary,
795 * there is no need for an extra segment.
796 */
797 mov A, HCNT[0];
798 add A, A, HADDR[0];
799 and A, CACHESIZE_MASK;
800 test A, 0xFF jz return;
801
802 /*
803 * If the transfer is less than a cachline,
804 * there is no need for an extra segment.
805 */
806 test HCNT[1], 0xFF jnz calc_mwi_residual_final;
807 test HCNT[2], 0xFF jnz calc_mwi_residual_final;
808 add NONE, INVERTED_CACHESIZE_MASK, HCNT[0];
809 jnc return;
810
811calc_mwi_residual_final:
812 mov MWI_RESIDUAL, A;
813 not A;
814 inc A;
815 add HCNT[0], A;
816 adc HCNT[1], -1;
817 adc HCNT[2], -1 ret;
818}
819
820p_data:
821 test SEQ_FLAGS,NOT_IDENTIFIED|NO_CDB_SENT jz p_data_allowed;
822 mvi PROTO_VIOLATION call set_seqint;
823p_data_allowed:
824 if ((ahc->features & AHC_ULTRA2) != 0) {
825 mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN;
826 } else {
827 mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET;
828 }
829 test LASTPHASE, IOI jnz . + 2;
830 or DMAPARAMS, DIRECTION;
831 if ((ahc->features & AHC_CMD_CHAN) != 0) {
832 /* We don't have any valid S/G elements */
833 mvi CCSGADDR, SG_PREFETCH_CNT;
834 }
835 test SEQ_FLAGS, DPHASE jz data_phase_initialize;
836
837 /*
838 * If we re-enter the data phase after going through another
839 * phase, our transfer location has almost certainly been
840 * corrupted by the interveining, non-data, transfers. Ask
841 * the host driver to fix us up based on the transfer residual.
842 */
843 mvi PDATA_REINIT call set_seqint;
844 jmp data_phase_loop;
845
846data_phase_initialize:
847 /* We have seen a data phase for the first time */
848 or SEQ_FLAGS, DPHASE;
849
850 /*
851 * Initialize the DMA address and counter from the SCB.
852 * Also set SCB_RESIDUAL_SGPTR, including the LAST_SEG
853 * flag in the highest byte of the data count. We cannot
854 * modify the saved values in the SCB until we see a save
855 * data pointers message.
856 */
857 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
858 /* The lowest address byte must be loaded last. */
859 mov SCB_DATACNT[3] call set_hhaddr;
860 }
861 if ((ahc->features & AHC_CMD_CHAN) != 0) {
862 bmov HADDR, SCB_DATAPTR, 7;
863 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
864 } else {
865 mvi DINDEX, HADDR;
866 mvi SCB_DATAPTR call bcopy_7;
867 mvi DINDEX, SCB_RESIDUAL_DATACNT + 3;
868 mvi SCB_DATACNT + 3 call bcopy_5;
869 }
870 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
871 call calc_mwi_residual;
872 }
873 and SCB_RESIDUAL_SGPTR[0], ~SG_FULL_RESID;
874
875 if ((ahc->features & AHC_ULTRA2) == 0) {
876 if ((ahc->features & AHC_CMD_CHAN) != 0) {
877 bmov STCNT, HCNT, 3;
878 } else {
879 call set_stcnt_from_hcnt;
880 }
881 }
882
883data_phase_loop:
884 /* Guard against overruns */
885 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_inbounds;
886
887 /*
888 * Turn on `Bit Bucket' mode, wait until the target takes
889 * us to another phase, and then notify the host.
890 */
891 and DMAPARAMS, DIRECTION;
892 mov DFCNTRL, DMAPARAMS;
893 or SXFRCTL1,BITBUCKET;
894 if ((ahc->features & AHC_DT) == 0) {
895 test SSTAT1,PHASEMIS jz .;
896 } else {
897 test SCSIPHASE, DATA_PHASE_MASK jnz .;
898 }
899 and SXFRCTL1, ~BITBUCKET;
900 mvi DATA_OVERRUN call set_seqint;
901 jmp ITloop;
902
903data_phase_inbounds:
904 if ((ahc->features & AHC_ULTRA2) != 0) {
905 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
906 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
907 or SINDEX, LAST_SEG;
908 mov SG_CACHE_PRE, SINDEX;
909 mov DFCNTRL, DMAPARAMS;
910ultra2_dma_loop:
911 call idle_loop;
912 /*
913 * The transfer is complete if either the last segment
914 * completes or the target changes phase.
915 */
916 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz ultra2_dmafinish;
917 if ((ahc->features & AHC_DT) == 0) {
918 if ((ahc->flags & AHC_TARGETROLE) != 0) {
919 /*
920 * As a target, we control the phases,
921 * so ignore PHASEMIS.
922 */
923 test SSTAT0, TARGET jnz ultra2_dma_loop;
924 }
925 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
926 test SSTAT1,PHASEMIS jz ultra2_dma_loop;
927 }
928 } else {
929 test DFCNTRL, SCSIEN jnz ultra2_dma_loop;
930 }
931
932ultra2_dmafinish:
933 /*
934 * The transfer has terminated either due to a phase
935 * change, and/or the completion of the last segment.
936 * We have two goals here. Do as much other work
937 * as possible while the data fifo drains on a read
938 * and respond as quickly as possible to the standard
939 * messages (save data pointers/disconnect and command
940 * complete) that usually follow a data phase.
941 */
942 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
943 /*
944 * On chips with broken auto-flush, start
945 * the flushing process now. We'll poke
946 * the chip from time to time to keep the
947 * flush process going as we complete the
948 * data phase.
949 */
950 or DFCNTRL, FIFOFLUSH;
951 }
952 /*
953 * We assume that, even though data may still be
954 * transferring to the host, that the SCSI side of
955 * the DMA engine is now in a static state. This
956 * allows us to update our notion of where we are
957 * in this transfer.
958 *
959 * If, by chance, we stopped before being able
960 * to fetch additional segments for this transfer,
961 * yet the last S/G was completely exhausted,
962 * call our idle loop until it is able to load
963 * another segment. This will allow us to immediately
964 * pickup on the next segment on the next data phase.
965 *
966 * If we happened to stop on the last segment, then
967 * our residual information is still correct from
968 * the idle loop and there is no need to perform
969 * any fixups.
970 */
971ultra2_ensure_sg:
972 test SG_CACHE_SHADOW, LAST_SEG jz ultra2_shvalid;
973 /* Record if we've consumed all S/G entries */
974 test SSTAT2, SHVALID jnz residuals_correct;
975 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL;
976 jmp residuals_correct;
977
978ultra2_shvalid:
979 test SSTAT2, SHVALID jnz sgptr_fixup;
980 call idle_loop;
981 jmp ultra2_ensure_sg;
982
983sgptr_fixup:
984 /*
985 * Fixup the residual next S/G pointer. The S/G preload
986 * feature of the chip allows us to load two elements
987 * in addition to the currently active element. We
988 * store the bottom byte of the next S/G pointer in
989 * the SG_CACEPTR register so we can restore the
990 * correct value when the DMA completes. If the next
991 * sg ptr value has advanced to the point where higher
992 * bytes in the address have been affected, fix them
993 * too.
994 */
995 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
996 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
997 add SCB_RESIDUAL_SGPTR[1], -1;
998 adc SCB_RESIDUAL_SGPTR[2], -1;
999 adc SCB_RESIDUAL_SGPTR[3], -1;
1000sgptr_fixup_done:
1001 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
1002 /* We are not the last seg */
1003 and SCB_RESIDUAL_DATACNT[3], ~SG_LAST_SEG;
1004residuals_correct:
1005 /*
1006 * Go ahead and shut down the DMA engine now.
1007 * In the future, we'll want to handle end of
1008 * transfer messages prior to doing this, but this
1009 * requires similar restructuring for pre-ULTRA2
1010 * controllers.
1011 */
1012 test DMAPARAMS, DIRECTION jnz ultra2_fifoempty;
1013ultra2_fifoflush:
1014 if ((ahc->features & AHC_DT) == 0) {
1015 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
1016 /*
1017 * On Rev A of the aic7890, the autoflush
1018 * feature doesn't function correctly.
1019 * Perform an explicit manual flush. During
1020 * a manual flush, the FIFOEMP bit becomes
1021 * true every time the PCI FIFO empties
1022 * regardless of the state of the SCSI FIFO.
1023 * It can take up to 4 clock cycles for the
1024 * SCSI FIFO to get data into the PCI FIFO
1025 * and for FIFOEMP to de-assert. Here we
1026 * guard against this condition by making
1027 * sure the FIFOEMP bit stays on for 5 full
1028 * clock cycles.
1029 */
1030 or DFCNTRL, FIFOFLUSH;
1031 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1032 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1033 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1034 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1035 }
1036 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1037 } else {
1038 /*
1039 * We enable the auto-ack feature on DT capable
1040 * controllers. This means that the controller may
1041 * have already transferred some overrun bytes into
1042 * the data FIFO and acked them on the bus. The only
1043 * way to detect this situation is to wait for
1044 * LAST_SEG_DONE to come true on a completed transfer
1045 * and then test to see if the data FIFO is non-empty.
1046 */
1047 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL
1048 jz ultra2_wait_fifoemp;
1049 test SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
1050 /*
1051 * FIFOEMP can lag LAST_SEG_DONE. Wait a few
1052 * clocks before calling this an overrun.
1053 */
1054 test DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
1055 test DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
1056 test DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
1057 /* Overrun */
1058 jmp data_phase_loop;
1059ultra2_wait_fifoemp:
1060 test DFSTATUS, FIFOEMP jz .;
1061 }
1062ultra2_fifoempty:
1063 /* Don't clobber an inprogress host data transfer */
1064 test DFSTATUS, MREQPEND jnz ultra2_fifoempty;
1065ultra2_dmahalt:
1066 and DFCNTRL, ~(SCSIEN|HDMAEN);
1067 test DFCNTRL, SCSIEN|HDMAEN jnz .;
1068 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1069 /*
1070 * Keep HHADDR cleared for future, 32bit addressed
1071 * only, DMA operations.
1072 *
1073 * Due to bayonette style S/G handling, our residual
1074 * data must be "fixed up" once the transfer is halted.
1075 * Here we fixup the HSHADDR stored in the high byte
1076 * of the residual data cnt. By postponing the fixup,
1077 * we can batch the clearing of HADDR with the fixup.
1078 * If we halted on the last segment, the residual is
1079 * already correct. If we are not on the last
1080 * segment, copy the high address directly from HSHADDR.
1081 * We don't need to worry about maintaining the
1082 * SG_LAST_SEG flag as it will always be false in the
1083 * case where an update is required.
1084 */
1085 or DSCOMMAND1, HADDLDSEL0;
1086 test SG_CACHE_SHADOW, LAST_SEG jnz . + 2;
1087 mov SCB_RESIDUAL_DATACNT[3], SHADDR;
1088 clr HADDR;
1089 and DSCOMMAND1, ~HADDLDSEL0;
1090 }
1091 } else {
1092 /* If we are the last SG block, tell the hardware. */
1093 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1094 && ahc->pci_cachesize != 0) {
1095 test MWI_RESIDUAL, 0xFF jnz dma_mid_sg;
1096 }
1097 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg;
1098 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1099 test SSTAT0, TARGET jz dma_last_sg;
1100 if ((ahc->flags & AHC_TMODE_WIDEODD_BUG) != 0) {
1101 test DMAPARAMS, DIRECTION jz dma_mid_sg;
1102 }
1103 }
1104dma_last_sg:
1105 and DMAPARAMS, ~WIDEODD;
1106dma_mid_sg:
1107 /* Start DMA data transfer. */
1108 mov DFCNTRL, DMAPARAMS;
1109dma_loop:
1110 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1111 call idle_loop;
1112 }
1113 test SSTAT0,DMADONE jnz dma_dmadone;
1114 test SSTAT1,PHASEMIS jz dma_loop; /* ie. underrun */
1115dma_phasemis:
1116 /*
1117 * We will be "done" DMAing when the transfer count goes to
1118 * zero, or the target changes the phase (in light of this,
1119 * it makes sense that the DMA circuitry doesn't ACK when
1120 * PHASEMIS is active). If we are doing a SCSI->Host transfer,
1121 * the data FIFO should be flushed auto-magically on STCNT=0
1122 * or a phase change, so just wait for FIFO empty status.
1123 */
1124dma_checkfifo:
1125 test DFCNTRL,DIRECTION jnz dma_fifoempty;
1126dma_fifoflush:
1127 test DFSTATUS,FIFOEMP jz dma_fifoflush;
1128dma_fifoempty:
1129 /* Don't clobber an inprogress host data transfer */
1130 test DFSTATUS, MREQPEND jnz dma_fifoempty;
1131
1132 /*
1133 * Now shut off the DMA and make sure that the DMA
1134 * hardware has actually stopped. Touching the DMA
1135 * counters, etc. while a DMA is active will result
1136 * in an ILLSADDR exception.
1137 */
1138dma_dmadone:
1139 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
1140dma_halt:
1141 /*
1142 * Some revisions of the aic78XX have a problem where, if the
1143 * data fifo is full, but the PCI input latch is not empty,
1144 * HDMAEN cannot be cleared. The fix used here is to drain
1145 * the prefetched but unused data from the data fifo until
1146 * there is space for the input latch to drain.
1147 */
1148 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
1149 mov NONE, DFDAT;
1150 }
1151 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt;
1152
1153 /* See if we have completed this last segment */
1154 test STCNT[0], 0xff jnz data_phase_finish;
1155 test STCNT[1], 0xff jnz data_phase_finish;
1156 test STCNT[2], 0xff jnz data_phase_finish;
1157
1158 /*
1159 * Advance the scatter-gather pointers if needed
1160 */
1161 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1162 && ahc->pci_cachesize != 0) {
1163 test MWI_RESIDUAL, 0xFF jz no_mwi_resid;
1164 /*
1165 * Reload HADDR from SHADDR and setup the
1166 * count to be the size of our residual.
1167 */
1168 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1169 bmov HADDR, SHADDR, 4;
1170 mov HCNT, MWI_RESIDUAL;
1171 bmov HCNT[1], ALLZEROS, 2;
1172 } else {
1173 mvi DINDEX, HADDR;
1174 mvi SHADDR call bcopy_4;
1175 mov MWI_RESIDUAL call set_hcnt;
1176 }
1177 clr MWI_RESIDUAL;
1178 jmp sg_load_done;
1179no_mwi_resid:
1180 }
1181 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz sg_load;
1182 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL;
1183 jmp data_phase_finish;
1184sg_load:
1185 /*
1186 * Load the next SG element's data address and length
1187 * into the DMA engine. If we don't have hardware
1188 * to perform a prefetch, we'll have to fetch the
1189 * segment from host memory first.
1190 */
1191 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1192 /* Wait for the idle loop to complete */
1193 test CCSGCTL, CCSGEN jz . + 3;
1194 call idle_loop;
1195 test CCSGCTL, CCSGEN jnz . - 1;
1196 bmov HADDR, CCSGRAM, 7;
1197 /*
1198 * Workaround for flaky external SCB RAM
1199 * on certain aic7895 setups. It seems
1200 * unable to handle direct transfers from
1201 * S/G ram to certain SCB locations.
1202 */
1203 mov SINDEX, CCSGRAM;
1204 mov SCB_RESIDUAL_DATACNT[3], SINDEX;
1205 } else {
1206 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1207 mov ALLZEROS call set_hhaddr;
1208 }
1209 mvi DINDEX, HADDR;
1210 mvi SCB_RESIDUAL_SGPTR call bcopy_4;
1211
1212 mvi SG_SIZEOF call set_hcnt;
1213
1214 or DFCNTRL, HDMAEN|DIRECTION|FIFORESET;
1215
1216 call dma_finish;
1217
1218 mvi DINDEX, HADDR;
1219 call dfdat_in_7;
1220 mov SCB_RESIDUAL_DATACNT[3], DFDAT;
1221 }
1222
1223 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1224 mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
1225
1226 /*
1227 * The lowest address byte must be loaded
1228 * last as it triggers the computation of
1229 * some items in the PCI block. The ULTRA2
1230 * chips do this on PRELOAD.
1231 */
1232 mov HADDR, HADDR;
1233 }
1234 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1235 && ahc->pci_cachesize != 0) {
1236 call calc_mwi_residual;
1237 }
1238
1239 /* Point to the new next sg in memory */
1240 call sg_advance;
1241
1242sg_load_done:
1243 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1244 bmov STCNT, HCNT, 3;
1245 } else {
1246 call set_stcnt_from_hcnt;
1247 }
1248
1249 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1250 test SSTAT0, TARGET jnz data_phase_loop;
1251 }
1252 }
1253data_phase_finish:
1254 /*
1255 * If the target has left us in data phase, loop through
1256 * the dma code again. In the case of ULTRA2 adapters,
1257 * we should only loop if there is a data overrun. For
1258 * all other adapters, we'll loop after each S/G element
1259 * is loaded as well as if there is an overrun.
1260 */
1261 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1262 test SSTAT0, TARGET jnz data_phase_done;
1263 }
1264 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1265 test SSTAT1, REQINIT jz .;
1266 if ((ahc->features & AHC_DT) == 0) {
1267 test SSTAT1,PHASEMIS jz data_phase_loop;
1268 } else {
1269 test SCSIPHASE, DATA_PHASE_MASK jnz data_phase_loop;
1270 }
1271 }
1272
1273data_phase_done:
1274 /*
1275 * After a DMA finishes, save the SG and STCNT residuals back into
1276 * the SCB. We use STCNT instead of HCNT, since it's a reflection
1277 * of how many bytes were transferred on the SCSI (as opposed to the
1278 * host) bus.
1279 */
1280 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1281 /* Kill off any pending prefetch */
1282 call disable_ccsgen;
1283 }
1284
1285 if ((ahc->features & AHC_ULTRA2) == 0) {
1286 /*
1287 * Clear the high address byte so that all other DMA
1288 * operations, which use 32bit addressing, can assume
1289 * HHADDR is 0.
1290 */
1291 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1292 mov ALLZEROS call set_hhaddr;
1293 }
1294 }
1295
1296 /*
1297 * Update our residual information before the information is
1298 * lost by some other type of SCSI I/O (e.g. PIO). If we have
1299 * transferred all data, no update is needed.
1300 *
1301 */
1302 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jnz residual_update_done;
1303 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1304 && ahc->pci_cachesize != 0) {
1305 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1306 test MWI_RESIDUAL, 0xFF jz bmov_resid;
1307 }
1308 mov A, MWI_RESIDUAL;
1309 add SCB_RESIDUAL_DATACNT[0], A, STCNT[0];
1310 clr A;
1311 adc SCB_RESIDUAL_DATACNT[1], A, STCNT[1];
1312 adc SCB_RESIDUAL_DATACNT[2], A, STCNT[2];
1313 clr MWI_RESIDUAL;
1314 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1315 jmp . + 2;
1316bmov_resid:
1317 bmov SCB_RESIDUAL_DATACNT, STCNT, 3;
1318 }
1319 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1320 bmov SCB_RESIDUAL_DATACNT, STCNT, 3;
1321 } else {
1322 mov SCB_RESIDUAL_DATACNT[0], STCNT[0];
1323 mov SCB_RESIDUAL_DATACNT[1], STCNT[1];
1324 mov SCB_RESIDUAL_DATACNT[2], STCNT[2];
1325 }
1326residual_update_done:
1327 /*
1328 * Since we've been through a data phase, the SCB_RESID* fields
1329 * are now initialized. Clear the full residual flag.
1330 */
1331 and SCB_SGPTR[0], ~SG_FULL_RESID;
1332
1333 if ((ahc->features & AHC_ULTRA2) != 0) {
1334 /* Clear the channel in case we return to data phase later */
1335 or SXFRCTL0, CLRSTCNT|CLRCHN;
1336 or SXFRCTL0, CLRSTCNT|CLRCHN;
1337 }
1338
1339 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1340 test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
1341 and SEQ_FLAGS, ~DPHASE_PENDING;
1342 /*
1343 * For data-in phases, wait for any pending acks from the
1344 * initiator before changing phase. We only need to
1345 * send Ignore Wide Residue messages for data-in phases.
1346 */
1347 test DFCNTRL, DIRECTION jz target_ITloop;
1348 test SSTAT1, REQINIT jnz .;
1349 test SCB_LUN, SCB_XFERLEN_ODD jz target_ITloop;
1350 test SCSIRATE, WIDEXFER jz target_ITloop;
1351 /*
1352 * Issue an Ignore Wide Residue Message.
1353 */
1354 mvi P_MESGIN|BSYO call change_phase;
1355 mvi MSG_IGN_WIDE_RESIDUE call target_outb;
1356 mvi 1 call target_outb;
1357 jmp target_ITloop;
1358 } else {
1359 jmp ITloop;
1360 }
1361
1362if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1363/*
1364 * Command phase. Set up the DMA registers and let 'er rip.
1365 */
1366p_command:
1367 test SEQ_FLAGS, NOT_IDENTIFIED jz p_command_okay;
1368 mvi PROTO_VIOLATION call set_seqint;
1369p_command_okay:
1370
1371 if ((ahc->features & AHC_ULTRA2) != 0) {
1372 bmov HCNT[0], SCB_CDB_LEN, 1;
1373 bmov HCNT[1], ALLZEROS, 2;
1374 mvi SG_CACHE_PRE, LAST_SEG;
1375 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1376 bmov STCNT[0], SCB_CDB_LEN, 1;
1377 bmov STCNT[1], ALLZEROS, 2;
1378 } else {
1379 mov STCNT[0], SCB_CDB_LEN;
1380 clr STCNT[1];
1381 clr STCNT[2];
1382 }
1383 add NONE, -13, SCB_CDB_LEN;
1384 mvi SCB_CDB_STORE jnc p_command_embedded;
1385p_command_from_host:
1386 if ((ahc->features & AHC_ULTRA2) != 0) {
1387 bmov HADDR[0], SCB_CDB_PTR, 4;
1388 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION);
1389 } else {
1390 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1391 bmov HADDR[0], SCB_CDB_PTR, 4;
1392 bmov HCNT, STCNT, 3;
1393 } else {
1394 mvi DINDEX, HADDR;
1395 mvi SCB_CDB_PTR call bcopy_4;
1396 mov SCB_CDB_LEN call set_hcnt;
1397 }
1398 mvi DFCNTRL, (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET);
1399 }
1400 jmp p_command_xfer;
1401p_command_embedded:
1402 /*
1403 * The data fifo seems to require 4 byte aligned
1404 * transfers from the sequencer. Force this to
1405 * be the case by clearing HADDR[0] even though
1406 * we aren't going to touch host memory.
1407 */
1408 clr HADDR[0];
1409 if ((ahc->features & AHC_ULTRA2) != 0) {
1410 mvi DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION);
1411 bmov DFDAT, SCB_CDB_STORE, 12;
1412 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1413 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1414 /*
1415 * On the 7895 the data FIFO will
1416 * get corrupted if you try to dump
1417 * data from external SCB memory into
1418 * the FIFO while it is enabled. So,
1419 * fill the fifo and then enable SCSI
1420 * transfers.
1421 */
1422 mvi DFCNTRL, (DIRECTION|FIFORESET);
1423 } else {
1424 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET);
1425 }
1426 bmov DFDAT, SCB_CDB_STORE, 12;
1427 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1428 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFOFLUSH);
1429 } else {
1430 or DFCNTRL, FIFOFLUSH;
1431 }
1432 } else {
1433 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET);
1434 call copy_to_fifo_6;
1435 call copy_to_fifo_6;
1436 or DFCNTRL, FIFOFLUSH;
1437 }
1438p_command_xfer:
1439 and SEQ_FLAGS, ~NO_CDB_SENT;
1440 if ((ahc->features & AHC_DT) == 0) {
1441 test SSTAT0, SDONE jnz . + 2;
1442 test SSTAT1, PHASEMIS jz . - 1;
1443 /*
1444 * Wait for our ACK to go-away on it's own
1445 * instead of being killed by SCSIEN getting cleared.
1446 */
1447 test SCSISIGI, ACKI jnz .;
1448 } else {
1449 test DFCNTRL, SCSIEN jnz .;
1450 }
1451 test SSTAT0, SDONE jnz p_command_successful;
1452 /*
1453 * Don't allow a data phase if the command
1454 * was not fully transferred.
1455 */
1456 or SEQ_FLAGS, NO_CDB_SENT;
1457p_command_successful:
1458 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
1459 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz .;
1460 jmp ITloop;
1461
1462/*
1463 * Status phase. Wait for the data byte to appear, then read it
1464 * and store it into the SCB.
1465 */
1466p_status:
1467 test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation;
1468p_status_okay:
1469 mov SCB_SCSI_STATUS, SCSIDATL;
1470 or SCB_CONTROL, STATUS_RCVD;
1471 jmp ITloop;
1472
1473/*
1474 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
1475 * indentify message sequence and send it to the target. The host may
1476 * override this behavior by setting the MK_MESSAGE bit in the SCB
1477 * control byte. This will cause us to interrupt the host and allow
1478 * it to handle the message phase completely on its own. If the bit
1479 * associated with this target is set, we will also interrupt the host,
1480 * thereby allowing it to send a message on the next selection regardless
1481 * of the transaction being sent.
1482 *
1483 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
1484 * This is done to allow the host to send messages outside of an identify
1485 * sequence while protecting the seqencer from testing the MK_MESSAGE bit
1486 * on an SCB that might not be for the current nexus. (For example, a
1487 * BDR message in responce to a bad reselection would leave us pointed to
1488 * an SCB that doesn't have anything to do with the current target).
1489 *
1490 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
1491 * bus device reset).
1492 *
1493 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
1494 * in case the target decides to put us in this phase for some strange
1495 * reason.
1496 */
1497p_mesgout_retry:
1498 /* Turn on ATN for the retry */
1499 if ((ahc->features & AHC_DT) == 0) {
1500 or SCSISIGO, ATNO, LASTPHASE;
1501 } else {
1502 mvi SCSISIGO, ATNO;
1503 }
1504p_mesgout:
1505 mov SINDEX, MSG_OUT;
1506 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
1507 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
1508p_mesgout_identify:
1509 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SAVED_LUN;
1510 test SCB_CONTROL, DISCENB jnz . + 2;
1511 and SINDEX, ~DISCENB;
1512/*
1513 * Send a tag message if TAG_ENB is set in the SCB control block.
1514 * Use SCB_TAG (the position in the kernel's SCB array) as the tag value.
1515 */
1516p_mesgout_tag:
1517 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
1518 mov SCSIDATL, SINDEX; /* Send the identify message */
1519 call phase_lock;
1520 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
1521 and SCSIDATL,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
1522 call phase_lock;
1523 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
1524 mov SCB_TAG jmp p_mesgout_onebyte;
1525/*
1526 * Interrupt the driver, and allow it to handle this message
1527 * phase and any required retries.
1528 */
1529p_mesgout_from_host:
1530 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
1531 jmp host_message_loop;
1532
1533p_mesgout_onebyte:
1534 mvi CLRSINT1, CLRATNO;
1535 mov SCSIDATL, SINDEX;
1536
1537/*
1538 * If the next bus phase after ATN drops is message out, it means
1539 * that the target is requesting that the last message(s) be resent.
1540 */
1541 call phase_lock;
1542 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
1543
1544p_mesgout_done:
1545 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
1546 mov LAST_MSG, MSG_OUT;
1547 mvi MSG_OUT, MSG_NOOP; /* No message left */
1548 jmp ITloop;
1549
1550/*
1551 * Message in phase. Bytes are read using Automatic PIO mode.
1552 */
1553p_mesgin:
1554 mvi ACCUM call inb_first; /* read the 1st message byte */
1555
1556 test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
1557 cmp A,MSG_DISCONNECT je mesgin_disconnect;
1558 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
1559 cmp ALLZEROS,A je mesgin_complete;
1560 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
1561 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue;
1562 cmp A,MSG_NOOP je mesgin_done;
1563
1564/*
1565 * Pushed message loop to allow the kernel to
1566 * run it's own message state engine. To avoid an
1567 * extra nop instruction after signaling the kernel,
1568 * we perform the phase_lock before checking to see
1569 * if we should exit the loop and skip the phase_lock
1570 * in the ITloop. Performing back to back phase_locks
1571 * shouldn't hurt, but why do it twice...
1572 */
1573host_message_loop:
1574 mvi HOST_MSG_LOOP call set_seqint;
1575 call phase_lock;
1576 cmp RETURN_1, EXIT_MSG_LOOP je ITloop + 1;
1577 jmp host_message_loop;
1578
1579mesgin_ign_wide_residue:
1580if ((ahc->features & AHC_WIDE) != 0) {
1581 test SCSIRATE, WIDEXFER jz mesgin_reject;
1582 /* Pull the residue byte */
1583 mvi ARG_1 call inb_next;
1584 cmp ARG_1, 0x01 jne mesgin_reject;
1585 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
1586 test SCB_LUN, SCB_XFERLEN_ODD jnz mesgin_done;
1587 mvi IGN_WIDE_RES call set_seqint;
1588 jmp mesgin_done;
1589}
1590
1591mesgin_proto_violation:
1592 mvi PROTO_VIOLATION call set_seqint;
1593 jmp mesgin_done;
1594mesgin_reject:
1595 mvi MSG_MESSAGE_REJECT call mk_mesg;
1596mesgin_done:
1597 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1598 jmp ITloop;
1599
1600/*
1601 * We received a "command complete" message. Put the SCB_TAG into the QOUTFIFO,
1602 * and trigger a completion interrupt. Before doing so, check to see if there
1603 * is a residual or the status byte is something other than STATUS_GOOD (0).
1604 * In either of these conditions, we upload the SCB back to the host so it can
1605 * process this information. In the case of a non zero status byte, we
1606 * additionally interrupt the kernel driver synchronously, allowing it to
1607 * decide if sense should be retrieved. If the kernel driver wishes to request
1608 * sense, it will fill the kernel SCB with a request sense command, requeue
1609 * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting
1610 * RETURN_1 to SEND_SENSE.
1611 */
1612mesgin_complete:
1613
1614 /*
1615 * If ATN is raised, we still want to give the target a message.
1616 * Perhaps there was a parity error on this last message byte.
1617 * Either way, the target should take us to message out phase
1618 * and then attempt to complete the command again. We should use a
1619 * critical section here to guard against a timeout triggering
1620 * for this command and setting ATN while we are still processing
1621 * the completion.
1622 test SCSISIGI, ATNI jnz mesgin_done;
1623 */
1624
1625 /*
1626 * If we are identified and have successfully sent the CDB,
1627 * any status will do. Optimize this fast path.
1628 */
1629 test SCB_CONTROL, STATUS_RCVD jz mesgin_proto_violation;
1630 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz complete_accepted;
1631
1632 /*
1633 * If the target never sent an identify message but instead went
1634 * to mesgin to give an invalid message, let the host abort us.
1635 */
1636 test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation;
1637
1638 /*
1639 * If we recevied good status but never successfully sent the
1640 * cdb, abort the command.
1641 */
1642 test SCB_SCSI_STATUS,0xff jnz complete_accepted;
1643 test SEQ_FLAGS, NO_CDB_SENT jnz mesgin_proto_violation;
1644
1645complete_accepted:
1646 /*
1647 * See if we attempted to deliver a message but the target ingnored us.
1648 */
1649 test SCB_CONTROL, MK_MESSAGE jz . + 2;
1650 mvi MKMSG_FAILED call set_seqint;
1651
1652 /*
1653 * Check for residuals
1654 */
1655 test SCB_SGPTR, SG_LIST_NULL jnz check_status;/* No xfer */
1656 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
1657 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
1658check_status:
1659 test SCB_SCSI_STATUS,0xff jz complete; /* Good Status? */
1660upload_scb:
1661 or SCB_SGPTR, SG_RESID_VALID;
1662 mvi DMAPARAMS, FIFORESET;
1663 mov SCB_TAG call dma_scb;
1664 test SCB_SCSI_STATUS, 0xff jz complete; /* Just a residual? */
1665 mvi BAD_STATUS call set_seqint; /* let driver know */
1666 cmp RETURN_1, SEND_SENSE jne complete;
1667 call add_scb_to_free_list;
1668 jmp await_busfree;
1669complete:
1670 mov SCB_TAG call complete_post;
1671 jmp await_busfree;
1672}
1673
1674complete_post:
1675 /* Post the SCBID in SINDEX and issue an interrupt */
1676 call add_scb_to_free_list;
1677 mov ARG_1, SINDEX;
1678 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
1679 mov A, SDSCB_QOFF;
1680 } else {
1681 mov A, QOUTPOS;
1682 }
1683 mvi QOUTFIFO_OFFSET call post_byte_setup;
1684 mov ARG_1 call post_byte;
1685 if ((ahc->features & AHC_QUEUE_REGS) == 0) {
1686 inc QOUTPOS;
1687 }
1688 mvi INTSTAT,CMDCMPLT ret;
1689
1690if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1691/*
1692 * Is it a disconnect message? Set a flag in the SCB to remind us
1693 * and await the bus going free. If this is an untagged transaction
1694 * store the SCB id for it in our untagged target table for lookup on
1695 * a reselction.
1696 */
1697mesgin_disconnect:
1698 /*
1699 * If ATN is raised, we still want to give the target a message.
1700 * Perhaps there was a parity error on this last message byte
1701 * or we want to abort this command. Either way, the target
1702 * should take us to message out phase and then attempt to
1703 * disconnect again.
1704 * XXX - Wait for more testing.
1705 test SCSISIGI, ATNI jnz mesgin_done;
1706 */
1707 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT
1708 jnz mesgin_proto_violation;
1709 or SCB_CONTROL,DISCONNECTED;
1710 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1711 call add_scb_to_disc_list;
1712 }
1713 test SCB_CONTROL, TAG_ENB jnz await_busfree;
1714 mov ARG_1, SCB_TAG;
1715 and SAVED_LUN, LID, SCB_LUN;
1716 mov SCB_SCSIID call set_busy_target;
1717 jmp await_busfree;
1718
1719/*
1720 * Save data pointers message:
1721 * Copying RAM values back to SCB, for Save Data Pointers message, but
1722 * only if we've actually been into a data phase to change them. This
1723 * protects against bogus data in scratch ram and the residual counts
1724 * since they are only initialized when we go into data_in or data_out.
1725 * Ack the message as soon as possible. For chips without S/G pipelining,
1726 * we can only ack the message after SHADDR has been saved. On these
1727 * chips, SHADDR increments with every bus transaction, even PIO.
1728 */
1729mesgin_sdptrs:
1730 if ((ahc->features & AHC_ULTRA2) != 0) {
1731 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1732 test SEQ_FLAGS, DPHASE jz ITloop;
1733 } else {
1734 test SEQ_FLAGS, DPHASE jz mesgin_done;
1735 }
1736
1737 /*
1738 * If we are asked to save our position at the end of the
1739 * transfer, just mark us at the end rather than perform a
1740 * full save.
1741 */
1742 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz mesgin_sdptrs_full;
1743 or SCB_SGPTR, SG_LIST_NULL;
1744 if ((ahc->features & AHC_ULTRA2) != 0) {
1745 jmp ITloop;
1746 } else {
1747 jmp mesgin_done;
1748 }
1749
1750mesgin_sdptrs_full:
1751
1752 /*
1753 * The SCB_SGPTR becomes the next one we'll download,
1754 * and the SCB_DATAPTR becomes the current SHADDR.
1755 * Use the residual number since STCNT is corrupted by
1756 * any message transfer.
1757 */
1758 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1759 bmov SCB_DATAPTR, SHADDR, 4;
1760 if ((ahc->features & AHC_ULTRA2) == 0) {
1761 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1762 }
1763 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8;
1764 } else {
1765 mvi DINDEX, SCB_DATAPTR;
1766 mvi SHADDR call bcopy_4;
1767 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1768 mvi SCB_RESIDUAL_DATACNT call bcopy_8;
1769 }
1770 jmp ITloop;
1771
1772/*
1773 * Restore pointers message? Data pointers are recopied from the
1774 * SCB anytime we enter a data phase for the first time, so all
1775 * we need to do is clear the DPHASE flag and let the data phase
1776 * code do the rest. We also reset/reallocate the FIFO to make
1777 * sure we have a clean start for the next data or command phase.
1778 */
1779mesgin_rdptrs:
1780 and SEQ_FLAGS, ~DPHASE; /*
1781 * We'll reload them
1782 * the next time through
1783 * the dataphase.
1784 */
1785 or SXFRCTL0, CLRSTCNT|CLRCHN;
1786 jmp mesgin_done;
1787
1788/*
1789 * Index into our Busy Target table. SINDEX and DINDEX are modified
1790 * upon return. SCBPTR may be modified by this action.
1791 */
1792set_busy_target:
1793 shr DINDEX, 4, SINDEX;
1794 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1795 mov SCBPTR, SAVED_LUN;
1796 add DINDEX, SCB_64_BTT;
1797 } else {
1798 add DINDEX, BUSY_TARGETS;
1799 }
1800 mov DINDIR, ARG_1 ret;
1801
1802/*
1803 * Identify message? For a reconnecting target, this tells us the lun
1804 * that the reconnection is for - find the correct SCB and switch to it,
1805 * clearing the "disconnected" bit so we don't "find" it by accident later.
1806 */
1807mesgin_identify:
1808 /*
1809 * Determine whether a target is using tagged or non-tagged
1810 * transactions by first looking at the transaction stored in
1811 * the busy target array. If there is no untagged transaction
1812 * for this target or the transaction is for a different lun, then
1813 * this must be a tagged transaction.
1814 */
1815 shr SINDEX, 4, SAVED_SCSIID;
1816 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A;
1817 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1818 add SINDEX, SCB_64_BTT;
1819 mov SCBPTR, SAVED_LUN;
1820 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1821 add NONE, -SCB_64_BTT, SINDEX;
1822 jc . + 2;
1823 mvi INTSTAT, OUT_OF_RANGE;
1824 nop;
1825 add NONE, -(SCB_64_BTT + 16), SINDEX;
1826 jnc . + 2;
1827 mvi INTSTAT, OUT_OF_RANGE;
1828 nop;
1829 }
1830 } else {
1831 add SINDEX, BUSY_TARGETS;
1832 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1833 add NONE, -BUSY_TARGETS, SINDEX;
1834 jc . + 2;
1835 mvi INTSTAT, OUT_OF_RANGE;
1836 nop;
1837 add NONE, -(BUSY_TARGETS + 16), SINDEX;
1838 jnc . + 2;
1839 mvi INTSTAT, OUT_OF_RANGE;
1840 nop;
1841 }
1842 }
1843 mov ARG_1, SINDIR;
1844 cmp ARG_1, SCB_LIST_NULL je snoop_tag;
1845 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1846 mov ARG_1 call findSCB;
1847 } else {
1848 mov SCBPTR, ARG_1;
1849 }
1850 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1851 jmp setup_SCB_id_lun_okay;
1852 } else {
1853 /*
1854 * We only allow one untagged command per-target
1855 * at a time. So, if the lun doesn't match, look
1856 * for a tag message.
1857 */
1858 and A, LID, SCB_LUN;
1859 cmp SAVED_LUN, A je setup_SCB_id_lun_okay;
1860 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1861 /*
1862 * findSCB removes the SCB from the
1863 * disconnected list, so we must replace
1864 * it there should this SCB be for another
1865 * lun.
1866 */
1867 call cleanup_scb;
1868 }
1869 }
1870
1871/*
1872 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
1873 * If we get one, we use the tag returned to find the proper
1874 * SCB. With SCB paging, we must search for non-tagged
1875 * transactions since the SCB may exist in any slot. If we're not
1876 * using SCB paging, we can use the tag as the direct index to the
1877 * SCB.
1878 */
1879snoop_tag:
1880 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1881 or SEQ_FLAGS, 0x80;
1882 }
1883 mov NONE,SCSIDATL; /* ACK Identify MSG */
1884 call phase_lock;
1885 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1886 or SEQ_FLAGS, 0x1;
1887 }
1888 cmp LASTPHASE, P_MESGIN jne not_found;
1889 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1890 or SEQ_FLAGS, 0x2;
1891 }
1892 cmp SCSIBUSL,MSG_SIMPLE_Q_TAG jne not_found;
1893get_tag:
1894 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1895 mvi ARG_1 call inb_next; /* tag value */
1896 mov ARG_1 call findSCB;
1897 } else {
1898 mvi ARG_1 call inb_next; /* tag value */
1899 mov SCBPTR, ARG_1;
1900 }
1901
1902/*
1903 * Ensure that the SCB the tag points to is for
1904 * an SCB transaction to the reconnecting target.
1905 */
1906setup_SCB:
1907 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1908 or SEQ_FLAGS, 0x4;
1909 }
1910 mov A, SCB_SCSIID;
1911 cmp SAVED_SCSIID, A jne not_found_cleanup_scb;
1912 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1913 or SEQ_FLAGS, 0x8;
1914 }
1915setup_SCB_id_okay:
1916 and A, LID, SCB_LUN;
1917 cmp SAVED_LUN, A jne not_found_cleanup_scb;
1918setup_SCB_id_lun_okay:
1919 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1920 or SEQ_FLAGS, 0x10;
1921 }
1922 test SCB_CONTROL,DISCONNECTED jz not_found_cleanup_scb;
1923 and SCB_CONTROL,~DISCONNECTED;
1924 test SCB_CONTROL, TAG_ENB jnz setup_SCB_tagged;
1925 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1926 mov A, SCBPTR;
1927 }
1928 mvi ARG_1, SCB_LIST_NULL;
1929 mov SAVED_SCSIID call set_busy_target;
1930 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1931 mov SCBPTR, A;
1932 }
1933setup_SCB_tagged:
1934 clr SEQ_FLAGS; /* make note of IDENTIFY */
1935 call set_transfer_settings;
1936 /* See if the host wants to send a message upon reconnection */
1937 test SCB_CONTROL, MK_MESSAGE jz mesgin_done;
1938 mvi HOST_MSG call mk_mesg;
1939 jmp mesgin_done;
1940
1941not_found_cleanup_scb:
1942 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1943 call cleanup_scb;
1944 }
1945not_found:
1946 mvi NO_MATCH call set_seqint;
1947 jmp mesgin_done;
1948
1949mk_mesg:
1950 if ((ahc->features & AHC_DT) == 0) {
1951 or SCSISIGO, ATNO, LASTPHASE;
1952 } else {
1953 mvi SCSISIGO, ATNO;
1954 }
1955 mov MSG_OUT,SINDEX ret;
1956
1957/*
1958 * Functions to read data in Automatic PIO mode.
1959 *
1960 * According to Adaptec's documentation, an ACK is not sent on input from
1961 * the target until SCSIDATL is read from. So we wait until SCSIDATL is
1962 * latched (the usual way), then read the data byte directly off the bus
1963 * using SCSIBUSL. When we have pulled the ATN line, or we just want to
1964 * acknowledge the byte, then we do a dummy read from SCISDATL. The SCSI
1965 * spec guarantees that the target will hold the data byte on the bus until
1966 * we send our ACK.
1967 *
1968 * The assumption here is that these are called in a particular sequence,
1969 * and that REQ is already set when inb_first is called. inb_{first,next}
1970 * use the same calling convention as inb.
1971 */
1972inb_next_wait_perr:
1973 mvi PERR_DETECTED call set_seqint;
1974 jmp inb_next_wait;
1975inb_next:
1976 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1977inb_next_wait:
1978 /*
1979 * If there is a parity error, wait for the kernel to
1980 * see the interrupt and prepare our message response
1981 * before continuing.
1982 */
1983 test SSTAT1, REQINIT jz inb_next_wait;
1984 test SSTAT1, SCSIPERR jnz inb_next_wait_perr;
1985inb_next_check_phase:
1986 and LASTPHASE, PHASE_MASK, SCSISIGI;
1987 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis;
1988inb_first:
1989 mov DINDEX,SINDEX;
1990 mov DINDIR,SCSIBUSL ret; /*read byte directly from bus*/
1991inb_last:
1992 mov NONE,SCSIDATL ret; /*dummy read from latch to ACK*/
1993}
1994
1995if ((ahc->flags & AHC_TARGETROLE) != 0) {
1996/*
1997 * Change to a new phase. If we are changing the state of the I/O signal,
1998 * from out to in, wait an additional data release delay before continuing.
1999 */
2000change_phase:
2001 /* Wait for preceeding I/O session to complete. */
2002 test SCSISIGI, ACKI jnz .;
2003
2004 /* Change the phase */
2005 and DINDEX, IOI, SCSISIGI;
2006 mov SCSISIGO, SINDEX;
2007 and A, IOI, SINDEX;
2008
2009 /*
2010 * If the data direction has changed, from
2011 * out (initiator driving) to in (target driving),
2012 * we must wait at least a data release delay plus
2013 * the normal bus settle delay. [SCSI III SPI 10.11.0]
2014 */
2015 cmp DINDEX, A je change_phase_wait;
2016 test SINDEX, IOI jz change_phase_wait;
2017 call change_phase_wait;
2018change_phase_wait:
2019 nop;
2020 nop;
2021 nop;
2022 nop ret;
2023
2024/*
2025 * Send a byte to an initiator in Automatic PIO mode.
2026 */
2027target_outb:
2028 or SXFRCTL0, SPIOEN;
2029 test SSTAT0, SPIORDY jz .;
2030 mov SCSIDATL, SINDEX;
2031 test SSTAT0, SPIORDY jz .;
2032 and SXFRCTL0, ~SPIOEN ret;
2033}
2034
2035/*
2036 * Locate a disconnected SCB by SCBID. Upon return, SCBPTR and SINDEX will
2037 * be set to the position of the SCB. If the SCB cannot be found locally,
2038 * it will be paged in from host memory. RETURN_2 stores the address of the
2039 * preceding SCB in the disconnected list which can be used to speed up
2040 * removal of the found SCB from the disconnected list.
2041 */
2042if ((ahc->flags & AHC_PAGESCBS) != 0) {
2043BEGIN_CRITICAL;
2044findSCB:
2045 mov A, SINDEX; /* Tag passed in SINDEX */
2046 cmp DISCONNECTED_SCBH, SCB_LIST_NULL je findSCB_notFound;
2047 mov SCBPTR, DISCONNECTED_SCBH; /* Initialize SCBPTR */
2048 mvi ARG_2, SCB_LIST_NULL; /* Head of list */
2049 jmp findSCB_loop;
2050findSCB_next:
2051 cmp SCB_NEXT, SCB_LIST_NULL je findSCB_notFound;
2052 mov ARG_2, SCBPTR;
2053 mov SCBPTR,SCB_NEXT;
2054findSCB_loop:
2055 cmp SCB_TAG, A jne findSCB_next;
2056rem_scb_from_disc_list:
2057 cmp ARG_2, SCB_LIST_NULL je rHead;
2058 mov DINDEX, SCB_NEXT;
2059 mov SINDEX, SCBPTR;
2060 mov SCBPTR, ARG_2;
2061 mov SCB_NEXT, DINDEX;
2062 mov SCBPTR, SINDEX ret;
2063rHead:
2064 mov DISCONNECTED_SCBH,SCB_NEXT ret;
2065END_CRITICAL;
2066findSCB_notFound:
2067 /*
2068 * We didn't find it. Page in the SCB.
2069 */
2070 mov ARG_1, A; /* Save tag */
2071 mov ALLZEROS call get_free_or_disc_scb;
2072 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
2073 mov ARG_1 jmp dma_scb;
2074}
2075
2076/*
2077 * Prepare the hardware to post a byte to host memory given an
2078 * index of (A + (256 * SINDEX)) and a base address of SHARED_DATA_ADDR.
2079 */
2080post_byte_setup:
2081 mov ARG_2, SINDEX;
2082 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2083 mvi DINDEX, CCHADDR;
2084 mvi SHARED_DATA_ADDR call set_1byte_addr;
2085 mvi CCHCNT, 1;
2086 mvi CCSCBCTL, CCSCBRESET ret;
2087 } else {
2088 mvi DINDEX, HADDR;
2089 mvi SHARED_DATA_ADDR call set_1byte_addr;
2090 mvi 1 call set_hcnt;
2091 mvi DFCNTRL, FIFORESET ret;
2092 }
2093
2094post_byte:
2095 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2096 bmov CCSCBRAM, SINDEX, 1;
2097 or CCSCBCTL, CCSCBEN|CCSCBRESET;
2098 test CCSCBCTL, CCSCBDONE jz .;
2099 clr CCSCBCTL ret;
2100 } else {
2101 mov DFDAT, SINDEX;
2102 or DFCNTRL, HDMAEN|FIFOFLUSH;
2103 jmp dma_finish;
2104 }
2105
2106phase_lock_perr:
2107 mvi PERR_DETECTED call set_seqint;
2108phase_lock:
2109 /*
2110 * If there is a parity error, wait for the kernel to
2111 * see the interrupt and prepare our message response
2112 * before continuing.
2113 */
2114 test SSTAT1, REQINIT jz phase_lock;
2115 test SSTAT1, SCSIPERR jnz phase_lock_perr;
2116phase_lock_latch_phase:
2117 if ((ahc->features & AHC_DT) == 0) {
2118 and SCSISIGO, PHASE_MASK, SCSISIGI;
2119 }
2120 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
2121
2122if ((ahc->features & AHC_CMD_CHAN) == 0) {
2123set_hcnt:
2124 mov HCNT[0], SINDEX;
2125clear_hcnt:
2126 clr HCNT[1];
2127 clr HCNT[2] ret;
2128
2129set_stcnt_from_hcnt:
2130 mov STCNT[0], HCNT[0];
2131 mov STCNT[1], HCNT[1];
2132 mov STCNT[2], HCNT[2] ret;
2133
2134bcopy_8:
2135 mov DINDIR, SINDIR;
2136bcopy_7:
2137 mov DINDIR, SINDIR;
2138 mov DINDIR, SINDIR;
2139bcopy_5:
2140 mov DINDIR, SINDIR;
2141bcopy_4:
2142 mov DINDIR, SINDIR;
2143bcopy_3:
2144 mov DINDIR, SINDIR;
2145 mov DINDIR, SINDIR;
2146 mov DINDIR, SINDIR ret;
2147}
2148
2149if ((ahc->flags & AHC_TARGETROLE) != 0) {
2150/*
2151 * Setup addr assuming that A is an index into
2152 * an array of 32byte objects, SINDEX contains
2153 * the base address of that array, and DINDEX
2154 * contains the base address of the location
2155 * to store the indexed address.
2156 */
2157set_32byte_addr:
2158 shr ARG_2, 3, A;
2159 shl A, 5;
2160 jmp set_1byte_addr;
2161}
2162
2163/*
2164 * Setup addr assuming that A is an index into
2165 * an array of 64byte objects, SINDEX contains
2166 * the base address of that array, and DINDEX
2167 * contains the base address of the location
2168 * to store the indexed address.
2169 */
2170set_64byte_addr:
2171 shr ARG_2, 2, A;
2172 shl A, 6;
2173
2174/*
2175 * Setup addr assuming that A + (ARG_2 * 256) is an
2176 * index into an array of 1byte objects, SINDEX contains
2177 * the base address of that array, and DINDEX contains
2178 * the base address of the location to store the computed
2179 * address.
2180 */
2181set_1byte_addr:
2182 add DINDIR, A, SINDIR;
2183 mov A, ARG_2;
2184 adc DINDIR, A, SINDIR;
2185 clr A;
2186 adc DINDIR, A, SINDIR;
2187 adc DINDIR, A, SINDIR ret;
2188
2189/*
2190 * Either post or fetch an SCB from host memory based on the
2191 * DIRECTION bit in DMAPARAMS. The host SCB index is in SINDEX.
2192 */
2193dma_scb:
2194 mov A, SINDEX;
2195 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2196 mvi DINDEX, CCHADDR;
2197 mvi HSCB_ADDR call set_64byte_addr;
2198 mov CCSCBPTR, SCBPTR;
2199 test DMAPARAMS, DIRECTION jz dma_scb_tohost;
2200 if ((ahc->flags & AHC_SCB_BTT) != 0) {
2201 mvi CCHCNT, SCB_DOWNLOAD_SIZE_64;
2202 } else {
2203 mvi CCHCNT, SCB_DOWNLOAD_SIZE;
2204 }
2205 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET;
2206 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN|CCSCBDIR jne .;
2207 jmp dma_scb_finish;
2208dma_scb_tohost:
2209 mvi CCHCNT, SCB_UPLOAD_SIZE;
2210 if ((ahc->features & AHC_ULTRA2) == 0) {
2211 mvi CCSCBCTL, CCSCBRESET;
2212 bmov CCSCBRAM, SCB_BASE, SCB_UPLOAD_SIZE;
2213 or CCSCBCTL, CCSCBEN|CCSCBRESET;
2214 test CCSCBCTL, CCSCBDONE jz .;
2215 } else if ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0) {
2216 mvi CCSCBCTL, CCARREN|CCSCBRESET;
2217 cmp CCSCBCTL, ARRDONE|CCARREN jne .;
2218 mvi CCHCNT, SCB_UPLOAD_SIZE;
2219 mvi CCSCBCTL, CCSCBEN|CCSCBRESET;
2220 cmp CCSCBCTL, CCSCBDONE|CCSCBEN jne .;
2221 } else {
2222 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET;
2223 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .;
2224 }
2225dma_scb_finish:
2226 clr CCSCBCTL;
2227 test CCSCBCTL, CCARREN|CCSCBEN jnz .;
2228 ret;
2229 } else {
2230 mvi DINDEX, HADDR;
2231 mvi HSCB_ADDR call set_64byte_addr;
2232 mvi SCB_DOWNLOAD_SIZE call set_hcnt;
2233 mov DFCNTRL, DMAPARAMS;
2234 test DMAPARAMS, DIRECTION jnz dma_scb_fromhost;
2235 /* Fill it with the SCB data */
2236copy_scb_tofifo:
2237 mvi SINDEX, SCB_BASE;
2238 add A, SCB_DOWNLOAD_SIZE, SINDEX;
2239copy_scb_tofifo_loop:
2240 call copy_to_fifo_8;
2241 cmp SINDEX, A jne copy_scb_tofifo_loop;
2242 or DFCNTRL, HDMAEN|FIFOFLUSH;
2243 jmp dma_finish;
2244dma_scb_fromhost:
2245 mvi DINDEX, SCB_BASE;
2246 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
2247 /*
2248 * The PCI module will only issue a PCI
2249 * retry if the data FIFO is empty. If the
2250 * host disconnects in the middle of a
2251 * transfer, we must empty the fifo of all
2252 * available data to force the chip to
2253 * continue the transfer. This does not
2254 * happen for SCSI transfers as the SCSI module
2255 * will drain the FIFO as data are made available.
2256 * When the hang occurs, we know that a multiple
2257 * of 8 bytes is in the FIFO because the PCI
2258 * module has an 8 byte input latch that only
2259 * dumps to the FIFO when HCNT == 0 or the
2260 * latch is full.
2261 */
2262 clr A;
2263 /* Wait for at least 8 bytes of data to arrive. */
2264dma_scb_hang_fifo:
2265 test DFSTATUS, FIFOQWDEMP jnz dma_scb_hang_fifo;
2266dma_scb_hang_wait:
2267 test DFSTATUS, MREQPEND jnz dma_scb_hang_wait;
2268 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2269 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2270 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2271 /*
2272 * The PCI module no longer intends to perform
2273 * a PCI transaction. Drain the fifo.
2274 */
2275dma_scb_hang_dma_drain_fifo:
2276 not A, HCNT;
2277 add A, SCB_DOWNLOAD_SIZE+SCB_BASE+1;
2278 and A, ~0x7;
2279 mov DINDIR,DFDAT;
2280 cmp DINDEX, A jne . - 1;
2281 cmp DINDEX, SCB_DOWNLOAD_SIZE+SCB_BASE
2282 je dma_finish_nowait;
2283 /* Restore A as the lines left to transfer. */
2284 add A, -SCB_BASE, DINDEX;
2285 shr A, 3;
2286 jmp dma_scb_hang_fifo;
2287dma_scb_hang_dma_done:
2288 and DFCNTRL, ~HDMAEN;
2289 test DFCNTRL, HDMAEN jnz .;
2290 add SEQADDR0, A;
2291 } else {
2292 call dma_finish;
2293 }
2294 call dfdat_in_8;
2295 call dfdat_in_8;
2296 call dfdat_in_8;
2297dfdat_in_8:
2298 mov DINDIR,DFDAT;
2299dfdat_in_7:
2300 mov DINDIR,DFDAT;
2301 mov DINDIR,DFDAT;
2302 mov DINDIR,DFDAT;
2303 mov DINDIR,DFDAT;
2304 mov DINDIR,DFDAT;
2305dfdat_in_2:
2306 mov DINDIR,DFDAT;
2307 mov DINDIR,DFDAT ret;
2308 }
2309
2310copy_to_fifo_8:
2311 mov DFDAT,SINDIR;
2312 mov DFDAT,SINDIR;
2313copy_to_fifo_6:
2314 mov DFDAT,SINDIR;
2315copy_to_fifo_5:
2316 mov DFDAT,SINDIR;
2317copy_to_fifo_4:
2318 mov DFDAT,SINDIR;
2319 mov DFDAT,SINDIR;
2320 mov DFDAT,SINDIR;
2321 mov DFDAT,SINDIR ret;
2322
2323/*
2324 * Wait for DMA from host memory to data FIFO to complete, then disable
2325 * DMA and wait for it to acknowledge that it's off.
2326 */
2327dma_finish:
2328 test DFSTATUS,HDONE jz dma_finish;
2329dma_finish_nowait:
2330 /* Turn off DMA */
2331 and DFCNTRL, ~HDMAEN;
2332 test DFCNTRL, HDMAEN jnz .;
2333 ret;
2334
2335/*
2336 * Restore an SCB that failed to match an incoming reselection
2337 * to the correct/safe state. If the SCB is for a disconnected
2338 * transaction, it must be returned to the disconnected list.
2339 * If it is not in the disconnected state, it must be free.
2340 */
2341cleanup_scb:
2342 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2343 test SCB_CONTROL,DISCONNECTED jnz add_scb_to_disc_list;
2344 }
2345add_scb_to_free_list:
2346 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2347BEGIN_CRITICAL;
2348 mov SCB_NEXT, FREE_SCBH;
2349 mvi SCB_TAG, SCB_LIST_NULL;
2350 mov FREE_SCBH, SCBPTR ret;
2351END_CRITICAL;
2352 } else {
2353 mvi SCB_TAG, SCB_LIST_NULL ret;
2354 }
2355
2356if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
2357set_hhaddr:
2358 or DSCOMMAND1, HADDLDSEL0;
2359 and HADDR, SG_HIGH_ADDR_BITS, SINDEX;
2360 and DSCOMMAND1, ~HADDLDSEL0 ret;
2361}
2362
2363if ((ahc->flags & AHC_PAGESCBS) != 0) {
2364get_free_or_disc_scb:
2365BEGIN_CRITICAL;
2366 cmp FREE_SCBH, SCB_LIST_NULL jne dequeue_free_scb;
2367 cmp DISCONNECTED_SCBH, SCB_LIST_NULL jne dequeue_disc_scb;
2368return_error:
2369 mvi NO_FREE_SCB call set_seqint;
2370 mvi SINDEX, SCB_LIST_NULL ret;
2371dequeue_disc_scb:
2372 mov SCBPTR, DISCONNECTED_SCBH;
2373 mov DISCONNECTED_SCBH, SCB_NEXT;
2374END_CRITICAL;
2375 mvi DMAPARAMS, FIFORESET;
2376 mov SCB_TAG jmp dma_scb;
2377BEGIN_CRITICAL;
2378dequeue_free_scb:
2379 mov SCBPTR, FREE_SCBH;
2380 mov FREE_SCBH, SCB_NEXT ret;
2381END_CRITICAL;
2382
2383add_scb_to_disc_list:
2384/*
2385 * Link this SCB into the DISCONNECTED list. This list holds the
2386 * candidates for paging out an SCB if one is needed for a new command.
2387 * Modifying the disconnected list is a critical(pause dissabled) section.
2388 */
2389BEGIN_CRITICAL;
2390 mov SCB_NEXT, DISCONNECTED_SCBH;
2391 mov DISCONNECTED_SCBH, SCBPTR ret;
2392END_CRITICAL;
2393}
2394set_seqint:
2395 mov INTSTAT, SINDEX;
2396 nop;
2397return:
2398 ret;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 00:26:20 -0500